A single-wire debugging system and method based on the ARM SWD debugging protocol

Abstract

The present invention provides a single-wire debugging system and method based on the ARM SWD debugging protocol, including a debugger and a debugging target; data interaction is carried out between the debugger and the debugging target based on the single-wire debugging protocol. The single-wire debugging system and method based on the ARM SWD debugging protocol of the present invention can achieve single-wire communication between the debugger and the debugging target, thereby reducing the occupation of I / O resources during debugging and greatly improving the convenience of debugging.

Description

Technical Field

[0001] The present invention relates to a debugging system and method, and particularly to a single-wire debugging system and method based on the ARM SWD debugging protocol. Background Art

[0002] The ARM SWD (Serial Wire Debug) debugging protocol is based on a two-wire serial interface, namely the communication clock SWCLK and the bidirectional data SWDIO. In the prior art, as Figure 1 shown, a debugging system based on the ARM SWD protocol usually consists of a debugging target, a debugger, and a host computer loaded with an Integrated Development Environment (IDE). Usually, the debugging target is a Microcontroller Unit (MCU); the debugger uses a general debugger, such as JLINK, ULINK, etc.; and the IDE of the host computer uses KEIL, IAR, etc. During debugging, the debugger converts the modulation instructions of the host computer into the SWD protocol, and performs operations such as debugging control, status monitoring, and program downloading on the debugging target MCU through SWCLK and SWDIO. Specifically, the basic operations of the SWD protocol are shown in Table 1.

[0003] Table 1. Explanation of the Basic Operations of the SWD Protocol

[0004]

[0005] Based on the SWD protocol, the debugger realizes the debugging control of the debugging target MCU through a series of read and write operations. The debugger is set as the host side Host, and the debugging target is set as the slave side Target. As Figure 2 shown, when the debugger performs a write operation on the debugging target, the host side initiates an 8-bit data packet request. After the data packet request, there is a default 1-bit conversion bit, waits for 3-bit ACK from the slave side, then adds 1-bit conversion bit, and the host side sends 32-bit write data and 1-bit check bit. As Figure 3 shown, when the debugger performs a read operation on the debugging target, the host side initiates an 8-bit data packet request. After the data packet request, there is a default 1-bit conversion bit, waits for 3-bit ACK from the slave side, the slave side continues to send 32-bit read data and 1-bit check bit, and finally adds 1-bit conversion bit.

[0006] However, during the debugging based on the ARM SWD protocol, the debugging function will always occupy the general I / O resources of the MCU, thus squeezing the I / O resources available to the user and bringing inconvenience to the debugging. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a single-wire debugging system and method based on the ARM SWD debugging protocol, which can realize single-wire communication between the debugger and the debugging target, thereby reducing the occupation of I / O resources during debugging and greatly improving the convenience of debugging.

[0008] To achieve the above object and other related objects, the present invention provides a single-wire debugging system based on the ARM SWD debugging protocol, including a debugger and a debugging target; the transmission frames of the debugger and the debugging target both sequentially include 1 start bit, 2 control bits, N data bits, and 1 stop bit; where N is a natural number; when the debugger performs a write operation, the debugger encodes 2 control bits representing a data packet request and N data packet requests for SWD write data into a first frame and sends it to the debugging target; the debugging target encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into a second frame and returns it to the debugger, where N = a + b, and a and b are natural numbers; after the debugger judges ACK, it encodes 2 control bits representing write data, N data of SWD write data into one frame to encode 4N data of SWD write data into four frames in sequence, and then encodes 2 control bits representing write data, c check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debugging target, where N = c + d, and c and d are natural numbers.

[0009] In an embodiment of the present invention, when the debugger performs a read operation, the debugger encodes 2 control bits representing a data packet request and N data packet requests for SWD read data into a first frame and sends it to the debugging target; after the debugging target receives the read request, it encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into a second frame and returns it to the debugger; after the debugger judges ACK, it continues to receive data from the debugging target; the debugging target encodes 2 control bits representing read data, N data of SWD read data into one frame to encode 4N data of SWD read data into four frames in sequence; encodes 2 control bits representing read data, c check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debugger.

[0010] In an embodiment of the present invention, in the transmission frame of the debugger, the control bit 00 indicates that the N data bits are write data, and the control bit 11 indicates that the N data bits are a data packet request; the control bit 01 indicates that the first three bits of the N data bits are ACK, and the control bit 10 indicates that the N data bits are read data.

[0011] In an embodiment of the present invention, the debugger is further configured to send a synchronization frame for synchronization before each write operation and read operation.

[0012] In an embodiment of the present invention, the debugging target includes a debugging kernel and a debugging control module; the debugging kernel performs data reading and writing based on the ARM SWD protocol;

[0013] When the control bit of the data frame received by the debugging control module indicates a JTAG to SWD switch, the debugging control module sends the timing of the JTAG to SWD switch to the debugging kernel;

[0014] When the control bit of the data frame received by the debugging control module indicates a reset, the debugging control module sends the reset timing to the debugging kernel;

[0015] When the control bit of the data frame received by the debugging control module indicates a data packet request, the debugging control module extracts N data bits of the data frame and sends them to the debugging kernel, and then packs the ACK of the debugging kernel into a frame and sends it to the debugger;

[0016] When the debugging control module finishes receiving the data packet request, it judges whether to perform a write operation or a read operation according to the data packet request; when it judges to perform a write operation, it receives the subsequent five frames of data, converts them into 4N-bit data and c-bit parity bits of SWD write data, and sends them to the debugging kernel; when it judges to perform a read operation, it converts the 4N-bit data and c-bit parity bits of the SWD read data sent by the debugging kernel into five frames of data and sends them to the debugger.

[0017] In an embodiment of the present invention, the debugging target is an MCU, and the debugging control module is integrated in the MCU.

[0018] In an embodiment of the present invention, it further includes a host computer, which is connected to the debugger and is used to send debugging commands to the debugger; the debugger performs data reading and writing with the debugging target according to the debugging commands.

[0019] The present invention provides a single-wire debugging method based on the ARM SWD debugging protocol, including:

[0020] Setting that the sending frames of the debugger and the debugging target both sequentially include 1 start bit, 2 control bits, N data bits and 1 stop bit; where N is a natural number;

[0021] When the debugger performs a write operation, the debugger encodes 2 control bits representing a data packet request and an N-bit data packet request of SWD write data into a first frame and sends it to the debug target; the debug target encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into a second frame and returns it to the debugger, where N = a + b, and a and b are natural numbers; after the debugger determines the ACK, it encodes 2 control bits representing write data, the N-bit data of SWD write data into one frame, sequentially encodes the 4N-bit data of SWD write data into four frames, and then encodes 2 control bits representing write data, c bits of check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debug target, where N = c + d, and c and d are natural numbers.

[0022] In an embodiment of the present invention, when the debugger performs a read operation, the debugger encodes 2 control bits representing a data packet request and an N-bit data packet request of SWD read data into a first frame and sends it to the debug target; after the debug target receives the read request, it encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into a second frame and returns it to the debugger; after the debugger determines the ACK, it continues to receive data from the debug target; the debug target encodes 2 control bits representing read data, the N-bit data of SWD read data into one frame, sequentially encodes the 4N-bit data of SWD read data into four frames; encodes 2 control bits representing read data, c bits of check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debugger.

[0023] In an embodiment of the present invention, the debug target includes a debug kernel and a debug control module; the debug kernel performs data reading and writing based on the ARM SWD protocol;

[0024] When the control bit of the data frame received by the debug control module represents the JTAG to SWD switch, the debug control module sends the timing of JTAG switching to SWD to the debug kernel;

[0025] When the control bit of the data frame received by the debug control module represents reset, the debug control module sends the reset timing to the debug kernel;

[0026] When the control bit of the data frame received by the debug control module represents a data packet request, the debug control module extracts N data bits of the data frame and sends them to the debug kernel, and then packs the ACK of the debug kernel into a frame and sends it to the debugger;

[0027] When the debug control module finishes receiving the data packet request, it determines whether to perform a write operation or a read operation according to the data packet request; when it determines to perform a write operation, it receives the subsequent five frames of data, converts them into 4N-bit data of SWD write data and c-bit parity bits, and sends them to the debug kernel; when it determines to perform a read operation, it converts the 4N-bit data of the SWD read data and the c-bit parity bits sent by the debug kernel into five frames of data and sends them to the debugger.

[0028] As described above, the single-wire debugging system and method based on the ARM SWD debugging protocol of the present invention have the following beneficial effects:

[0029] (1) It realizes single-wire communication between the debugger and the debug target, thereby reducing the occupation of I / O resources during debugging;

[0030] (2) It improves the utilization rate of I / O resources during debugging and facilitates debugging. Description of the Drawings

[0031] Figure 1 It is a schematic structural diagram of a debugging system based on the ARM SWD protocol in an embodiment of the prior art;

[0032] Figure 2 It is a write operation timing diagram of a write operation based on the ARM SWD protocol in an embodiment of the prior art;

[0033] Figure 3 It is a read operation timing diagram of a read operation based on the ARM SWD protocol in an embodiment of the prior art;

[0034] Figure 4 It is a schematic structural diagram of a transmission frame of the debugger of the present invention in an embodiment;

[0035] Figure 5 It is a schematic structural diagram of a transmission frame of the debug target of the present invention in an embodiment;

[0036] Figure 6 It is a schematic structural diagram of a synchronization frame of the present invention in an embodiment;

[0037] Figure 7 It is a schematic diagram of a write protocol in the single-wire debugging protocol of the present invention in an embodiment;

[0038] Figure 8 It is a schematic diagram of a read protocol in the single-wire debugging protocol of the present invention in an embodiment;

[0039] Figure 9 It is a schematic diagram of JTAG to SWD timing conversion of the present invention;

[0040] Figure 10Schematic diagram of the reset timing conversion of the present invention;

[0041] Figure 11 Schematic diagram of the data packet request timing conversion of the present invention;

[0042] Figure 12 Schematic diagram of the write data timing conversion of the present invention;

[0043] Figure 13 Schematic diagram of the read data timing conversion of the present invention;

[0044] Figure 14 Schematic diagram of the debugging process of the single - wire debugging system based on the ARM SWD debugging protocol of the present invention in an embodiment. Detailed implementation manners

[0045] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0046] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] Based on the ARM SWD debugging protocol, the single - wire debugging system and method of the present invention can achieve single - wire communication between the debugger and the debugging target, reduce the occupation of I / O resources during debugging, greatly improve the convenience of debugging, and are highly practical. In the present invention, the debugger serves as the host side, and the debugging target serves as the slave side, which can be an MCU.

[0048] In one embodiment, the single-wire debugging system based on the ARM SWD debugging protocol of the present invention includes a debugger and a debugging target. In the single-wire debugging system, the data bits of the SWD data are set to 4N bits, the data bits of the transmission frames of the debugger and the debugging target are N bits, ACK is a bits, and the parity bit is c bits, where N, a, and c are all natural numbers. When the transmission frame sends ACK or the parity bit, b bits of "0" are padded after ACK to make up N data bits, and d bits of "0" are padded after the parity bit to make up N data bits. Therefore, a + b = N, and c + d = N. For the convenience of description, in the following embodiments, N is taken as 8, a is taken as 3, and c is taken as 1 as an example for illustration.

[0049] As Figure 4 shown, the transmission frame of the debugger sequentially includes 1 start bit (Start), 2 control bits (Cmd[0:1]), 8 data bits (Data[0:7]), and 1 stop bit (Stop). Among them, the start bit Start must be 0. The control bits Cmd[0:1] take the value of 00 representing that Data[0:7] is for writing data, take the value of 01 representing the JTAG to SWD switch, take the value of 10 representing reset, and take the value of 11 representing that Data[0:7] is for packet request. The data bits Data[0:7] represent writing data or packet request. The stop bit Stop must be 1. Among them, it should be noted that the number of data bits of the transmission frame can be limited according to requirements, and preferably 8 data bits are adopted.

[0050] As Figure 5 shown, the transmission frame of the debugging target sequentially includes 1 start bit (Start), 2 control bits (Cmd[0:1]), 8 data bits (Data[0:7]), and 1 stop bit (Stop). Among them, the start bit Start must be 0. The control bits Cmd[0:1] take the value of 00 representing invalid, take the value of 01 representing that the first three bits of Data[0:7] are ACK, take the value of 10 representing that Data[0:7] is for reading data, and take the value of 11 representing invalid. The data bits Data[0:7] represent writing data or packet request. The stop bit Stop must be 1.

[0051] In one embodiment of the present invention, before each write operation and read operation, the debugger sends a synchronization frame for synchronization. When the debugging target receives the synchronization frame, it adjusts the baud rate counter by calculating the edge interval of the synchronization data to achieve the purpose of synchronization. The synchronization frame is as Figure 6 shown, including 14 consecutive 0s and 8 01010101s. Preferably, the communication baud rate between the debugger and the debugging target is 115200 bps.

[0052] When the debugger performs a write operation on the debugging target, asFigure 7 As shown, the debugger acting as the host end encodes the start bit, 2 control bits representing the data packet request, 8-bit data packet request for SWD write data, and stop bit into the first frame and sends it to the debug target acting as the slave end. The debug target encodes the start bit, 2 control bits representing ACK, 3-bit ACK, 5-bit 0, and stop bit into the second frame and returns it to the debugger. After the debugger determines the ACK, it encodes the start bit, 2 control bits representing write data, 8-bit data of 1 byte of SWD write data, and stop bit into one frame. After repeating this four times, the 32-bit data of SWD write data is encoded into four frames in total. Finally, it encodes the start bit, 2 control bits representing write data, 1-bit parity bit of SWD write data, 7-bit 0, and stop bit into one frame, and sends a total of five frames to the debug target, thereby completing the write operation of the debugger to the debug target.

[0053] When the debugger performs a read operation on the debug target, as Figure 8 shown, the debugger encodes the start bit, 2 control bits representing the data packet request, 8-bit data packet request for SWD read data, and stop bit into the first frame and sends it to the debug target. After the debug target receives the read request represented by the data packet request, it encodes the start bit, 2 control bits representing ACK, 3-bit ACK, 5-bit 0, and stop bit into the second frame and returns it to the debugger. After the debugger determines the ACK, it continues to receive the data from the debug target. The debug target encodes the start bit, 2 control bits representing read data, 8-bit data of 1 byte of SWD read data, and stop bit into one frame. After repeating this four times, the 32-bit data of SWD read data is encoded into four frames in total. Finally, it encodes the start bit, 2 control bits representing read data, 1-bit parity bit of SWD write data, 7-bit 0, and stop bit into one frame, and sends a total of five frames to the debugger, thereby completing the data reading of the debugger to the debug target.

[0054] To implement the single-wire debugging based on the ARM SWD debugging protocol of the present invention, in an embodiment of the present invention, the debug target includes a debug core and a debug control module HCDP. The debug core performs data reading and writing based on the ARM SWD protocol; the debug control module HCDP is used to implement data exchange between the debug core based on the ARM SWD protocol and a debugger using the single-wire debugging protocol.

[0055] Specifically, the debug control module HCDP receives the data frame sent by the debugger and determines the operation to be performed according to the information of the control bit in the data frame.

[0056] (1) When the control bit of the data frame received by the debug control module HCDP is 01, it indicates a JTAG to SWD switch. Then the debug control module HCDP sends asFigure 9 The timing of switching JTAG to SWD as shown is sent to the debug kernel so that the debug kernel performs corresponding operations. At this time, the data bits Data[0:7] of the received data frame will be ignored.

[0057] (2) When the control bit of the data frame received by the debug control module HCDP is 10, it indicates a reset. Then, the debug control module HCDP sends the reset timing as shown Figure 10 to the debug kernel so that the debug kernel is reset. At this time, the data bits Data[0:7] of the received data frame will be ignored.

[0058] (3) When the control bit of the data frame received by the debug control module HCDP is 11, it indicates a data packet request. Then, as shown Figure 11 , the debug control module HCDP extracts 8 data bits of the data frame and sends them to the debug kernel. The debug kernel reads the 8 data bits and generates an ACK. The debug control module HCDP then packs the ACK of the debug kernel into a frame and sends it to the debugger. Among them, the frame includes a start bit, 2 control bits representing ACK, 3 bits of ACK, 5 bits of 0, and a stop bit.

[0059] (4) When the debug control module HCDP finishes receiving the data packet request, it determines whether to perform a write operation or a read operation according to the data packet request.

[0060] As shown Figure 12 , when it is determined to perform a write operation, the debug control module HCDP receives the subsequent five frames of data sent by the debugger and converts them into 32-bit data and 1-bit parity bit of SWD write data and sends them to the debug kernel. Among them, the five frames of data are four frames composed of a start bit, 2 control bits representing write data, 8-bit data of one byte of SWD write data, and a stop bit, and one frame composed of a start bit, 2 control bits representing write data, 1-bit parity bit of SWD write data, 7 bits of 0, and a stop bit.

[0061] As shown Figure 13 , when it is determined to perform a read operation, the debug control module HCDP converts the 32-bit data and 1-bit parity bit of SWD read data sent by the debug kernel into five frames of data and sends them to the debugger. The five frames of data are four frames composed of a start bit, 2 control bits representing read data, 8-bit data of one byte of SWD read data, and a stop bit, and one frame composed of a start bit, 2 control bits representing read data, 1-bit parity bit of SWD write data, 7 bits of 0, and a stop bit.

[0062] In an embodiment of the present invention, the debugging target is an MCU, and the debugging control module HCDP is integrated with the MCU core within the MCU. The MCU core performs operations such as reset, clock synchronization, data transmission, and data reception through the debugging control module HCDP. Among them,

[0063] In an embodiment of the present invention, the single-wire debugging system based on the ARM SWD debugging protocol of the present invention further includes a host computer, which is connected to the debugger and is used to send debugging commands to the debugger; the debugger performs data reading and writing with the debugging target according to the debugging commands, and the debugging process is as Figure 14 shown.

[0064] In the single-wire debugging method, the data bits of the SWD data are set to 4N bits, the data bits of the sending frames of the debugger and the debugging target are N bits, the ACK is a bits, and the parity bit is c bits, where N, a, and c are all natural numbers. When the sending frame sends the ACK or the parity bit, b bits of "0" are filled after the ACK to make up N data bits, and d bits of "0" are filled after the parity bit to make up N data bits. Therefore, a + b = N, and c + d = N. For the convenience of description, in the following embodiments, N is taken as 8, a is taken as 3, and c is taken as 1 as an example for illustration.

[0065] In an embodiment of the present invention, the single-wire debugging method based on the ARM SWD debugging protocol of the present invention includes:

[0066] a) Set the sending frames of the debugger and the debugging target to sequentially include 1 start bit, 2 control bits, 8 data bits, and 1 stop bit.

[0067] b) When the debugger performs a write operation, the debugger encodes the 2 control bits representing the data packet request and the 8-bit data packet request of the SWD write data into the first frame and sends it to the debugging target; the debugging target encodes the 2 control bits representing the ACK, 3 bits of ACK, and 5 bits of 0 into the second frame and returns it to the debugger; after the debugger judges the ACK, it encodes the 2 control bits representing the write data, the 8-bit data of the SWD write data into one frame, and sequentially encodes the 32-bit data of the SWD write data into four frames, and then encodes the 2 control bits representing the write data, 1 parity bit of the SWD write data, and 7 bits of 0 into one frame, and sends a total of five frames to the debugging target.

[0068] c) When the debugger performs a read operation, the debugger encodes 2 control bits representing a data packet request and an 8-bit data packet request for SWD read data into a first frame and sends it to the debug target; after receiving the read request, the debug target encodes 2 control bits representing ACK, 3 bits of ACK, and 5 bits of 0 into a second frame and returns it to the debugger; after the debugger determines the ACK, it continues to receive data from the debug target; the debug target encodes 2 control bits representing read data, 8 bits of data for SWD read data into one frame, and sequentially encodes 32 bits of data for SWD read data into four frames; encodes 2 control bits representing read data, 1 parity bit for SWD write data, and 7 bits of 0 into one frame, and sends a total of five frames to the debugger.

[0069] In an embodiment of the present invention, the debug target includes a debug kernel and a debug control module; the debug kernel performs data reading and writing based on the ARM SWD protocol; when the control bit of the data frame received by the debug control module represents a JTAG to SWD switch, the debug control module sends the timing of the JTAG switch to SWD to the debug kernel; when the control bit of the data frame received by the debug control module represents a reset, the debug control module sends the reset timing to the debug kernel; when the control bit of the data frame received by the debug control module represents a data packet request, the debug control module extracts 8 data bits of the data frame and sends them to the debug kernel, and then packs the ACK of the debug kernel into a frame and sends it to the debugger; when the debug control module finishes receiving the data packet request, it determines whether to perform a write operation or a read operation according to the data packet request; when it is determined to perform a write operation, it receives the subsequent five frames of data and converts them into 32 bits of data for SWD write data and 1 parity bit and sends them to the debug kernel; when it is determined to perform a read operation, it converts 32 bits of data for SWD read data and 1 parity bit sent by the debug kernel into five frames of data and sends them to the debugger.

[0070] Preferably, the debug target is an MCU, and the debug control module is integrated in the MCU.

[0071] In summary, the single-wire debugging system and method based on the ARM SWD debugging protocol of the present invention realize single-wire communication between the debugger and the debug target, thereby reducing the occupation of I / O resources during debugging; improving the utilization rate of I / O resources during debugging and facilitating debugging. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0072] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A single-wire debugging system based on the ARM SWD debugging protocol, characterized in that: It includes a debugger and a debug target; The transmission frames of the debugger and the debug target both sequentially include 1 start bit, 2 control bits, N data bits, and 1 stop bit; where N is a natural number; When the debugger performs a write operation, the debugger encodes 2 control bits representing a data packet request and N data packet requests of SWD write data into the first frame and sends it to the debug target; the debug target encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into the second frame and returns it to the debugger, where N = a + b, and a and b are natural numbers; after the debugger determines the ACK, it encodes 2 control bits representing write data, N bits of data of SWD write data into one frame to sequentially encode 4N bits of data of SWD write data into four frames, and then encodes 2 control bits representing write data, c bits of check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debug target, where N = c + d, and c and d are natural numbers; When the debugger performs a read operation, the debugger encodes 2 control bits representing a data packet request and N data packet requests of SWD read data into the first frame and sends it to the debug target; after the debug target receives the read request, it encodes 2 control bits representing ACK, a bits of ACK, and b bits of 0 into the second frame and returns it to the debugger; after the debugger determines the ACK, it continues to receive data from the debug target; the debug target encodes 2 control bits representing read data, N bits of data of SWD read data into one frame to sequentially encode 4N bits of data of SWD read data into four frames; encodes 2 control bits representing read data, c bits of check bits of SWD write data, and d bits of 0 into one frame, and sends a total of five frames to the debugger.

2. The single-wire debugging system based on the ARM SWD debugging protocol according to claim 1, wherein: In the transmission frame of the debugger, control bit 00 indicates that the N data bits are write data, and control bit 11 indicates that the N data bits are a data packet request; in the transmission frame of the debug target, control bit 01 indicates that the first three of the N data bits are ACK, and control bit 10 indicates that the N data bits are read data.

3. The single-wire debugging system based on the ARM SWD debugging protocol according to claim 1, characterized in that: The debugger is also used to send a synchronization frame for synchronization before each write operation and read operation.

4. The single-wire debugging system based on the ARM SWD debugging protocol according to claim 1, characterized in that: The debug target includes a debug core and a debug control module; The debug core performs data reading and writing based on the ARM SWD protocol; When the control bit of the data frame received by the debug control module indicates a JTAG to SWD switch, the debug control module sends the timing of JTAG switching to SWD to the debug core; When the control bit of the data frame received by the debug control module indicates a reset, the debug control module sends the reset timing to the debug core; When the control bit of the data frame received by the debug control module indicates a data packet request, the debug control module extracts N data bits of the data frame and sends them to the debug core, and then packs the ACK of the debug core into a frame and sends it to the debugger; When the debug control module finishes receiving the data packet request, it determines whether to perform a write operation or a read operation according to the data packet request; when it determines to perform a write operation, it receives the subsequent five frames of data, converts them into 4N-bit data of SWD write data and c-bit parity bits, and sends them to the debug kernel; when it determines to perform a read operation, it converts the 4N-bit data of SWD read data and c-bit parity bits sent by the debug kernel into five frames of data and sends them to the debugger.

5. The single-wire debugging system based on the ARM SWD debugging protocol according to claim 4, wherein: The debug target is an MCU, and the debug control module is integrated in the MCU.

6. The single-wire debugging system based on the ARM SWD debugging protocol according to claim 1, characterized in that: It further includes a host computer, which is connected to the debugger and is used to send debug commands to the debugger; the debugger performs data reading and writing with the debug target according to the debug commands.

7. A single-wire debugging method based on the ARM SWD debugging protocol, characterized in that: It includes: It is set that the transmission frames of the debugger and the debug target both sequentially include 1 start bit, 2 control bits, N data bits and 1 stop bit, where N is a natural number. When the debugger performs a write operation, the debugger encodes the 2 control bits representing the data packet request and the N-bit data packet request of the SWD write data into the first frame and sends it to the debug target; the debug target encodes the 2 control bits representing ACK, a-bit ACK and b-bit 0 into the second frame and returns it to the debugger, where N = a + b, and a and b are natural numbers; after the debugger determines ACK, it encodes the 2 control bits representing write data and the N-bit data of the SWD write data into one frame to sequentially encode the 4N-bit data of the SWD write data into four frames, and then encodes the 2 control bits representing write data, the c-bit parity bits of the SWD write data and d-bit 0 into one frame, and sends a total of five frames to the debug target, where N = c + d, and c and d are natural numbers. When the debugger performs a read operation, the debugger encodes the 2 control bits representing the data packet request and the N-bit data packet request of the SWD read data into the first frame and sends it to the debug target; after the debug target receives the read request, it encodes the 2 control bits representing ACK, a-bit ACK and b-bit 0 into the second frame and returns it to the debugger; after the debugger determines ACK, it continues to receive the data from the debug target; the debug target encodes the 2 control bits representing read data and the N-bit data of the SWD read data into one frame to sequentially encode the 4N-bit data of the SWD read data into four frames; it encodes the 2 control bits representing read data, the c-bit parity bits of the SWD write data and d-bit 0 into one frame, and sends a total of five frames to the debugger.

8. The single-wire debugging method based on the ARM SWD debugging protocol according to claim 7, characterized in that: The debug target includes a debug kernel and a debug control module; The debug kernel performs data reading and writing based on the ARM SWD protocol; When the control bit of the data frame received by the debug control module represents the JTAG to SWD switch, the debug control module sends the timing of JTAG switching to SWD to the debug kernel; When the control bit of the data frame received by the debug control module represents reset, the debug control module sends the reset timing to the debug kernel; When the control bit of the data frame received by the debug control module indicates a data packet request, the debug control module extracts N data bits of the data frame and sends them to the debug kernel, and then packs the ACK of the debug kernel into a frame and sends it to the debugger; When the debug control module finishes receiving the data packet request, it determines whether to perform a write operation or a read operation according to the data packet request; when it determines to perform a write operation, it receives the subsequent five frames of data and converts them into 4N-bit data of SWD write data and c-bit parity bits and sends them to the debug kernel; when it determines to perform a read operation, it converts the 4N-bit data of SWD read data and c-bit parity bits sent by the debug kernel into five frames of data and sends them to the debugger.

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