Dynamic logical page size of memory devices

Abstract

This application relates to dynamic logical page sizes in memory devices. A memory device may use an initial set of logical pages, each of the same size, and one or more logical-to-physical (L2P) tables for mapping the logical addresses of the logical pages to the physical addresses of corresponding physical pages. When a command is received from a host device, the memory device may dynamically segment logical pages to introduce smaller logical pages, provided that the block size of the data accessed by the host device is smaller than the size of the segmented logical pages. The memory device may maintain one or more additional L2P tables for each introduced smaller logical page size, and one or more pointer tables for mapping between the L2P tables and entries for larger logical page sizes and the L2P tables and entries associated with smaller logical page sizes.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 117,907, filed December 10, 2020, entitled “Dynamic Logical Page Sizes for Memory Devices”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to the dynamic logical page size of memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller for the memory device and configured to cause the apparatus to: receive a write command to write a first amount of data to the memory device, the write command being associated with a logical address; read a first entry of a first logical-to-physical (L2P) table at least partially based on the logical address, wherein the first L2P table is used to map a plurality of logical addresses to physical addresses of corresponding first plurality of logical pages, each having a first logical page size, and wherein the first entry of the first L2P table includes a first physical address of a first logical page among the first plurality of logical pages; identify a second logical page size at least partially based on the size of the first data amount; write at least a portion of the first data amount to a second logical page of the memory device having the second logical page size, the first logical page including the second logical page, at least partially based on the first physical address; and store a first entry of a second L2P table for mapping a second plurality of logical addresses to physical addresses of corresponding second plurality of logical pages of the memory device, each of the second plurality of logical pages having the second logical page size, wherein the first entry of the second L2P table includes a second physical address of the second logical page, at least partially based on the identified second logical page size.

[0007] Describing another device. The device may include: a memory device; and a controller for the memory device and configured to cause the device to: receive a read command associated with a logical address of the starting location of data stored in the memory device; read a first entry of a first L2P table, at least partially based on the logical address, wherein the first entry includes a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of memory containing the data, the first logical page including the second logical page; determine, at least partially based on the value of the first portion of the first physical address, whether the second logical page size is different from the first logical page size; determine, at least partially based on the determination of whether the second logical page size is different from the first logical page size, a second physical address pointing to the starting location of the data within the second logical page; read the data from the starting location of the data within the second logical page, at least partially based on the second physical address; and transfer the data to a host device of the memory device.

[0008] Describes a non-transitory computer-readable medium. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a write command to write a first amount of data to a memory device, the write command being associated with a logical address; read a first entry of a first L2P table, at least partially based on the logical address, wherein the first L2P table is used to map a plurality of logical addresses to physical addresses corresponding to a first plurality of logical pages of the memory device, each logical page having a first logical page size, and wherein the first entry of the first L2P table includes a first physical address of the first logical page among the first plurality of logical pages; identify a second logical page size, at least partially based on the size of the first data amount; write at least a portion of the first data amount to a second logical page of the memory device having the second logical page size, the first logical page including the second logical page, at least partially based on the first physical address; and store a first entry of a second L2P table, at least partially based on the identified second logical page size, for mapping a second plurality of logical addresses to physical addresses corresponding to a second plurality of logical pages of the memory device, each logical page among the second plurality of logical pages having the second logical page size, wherein the first entry of the second L2P table includes a second physical address of the second logical page.

[0009] Another non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a read command associated with a logical address of the starting location of data stored in a memory device; read, at least partially based on the logical address, a first entry of a first L2P table, wherein the first entry includes a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of memory containing the data, the first logical page including the second logical page; determine, at least partially based on the value of the first portion of the first physical address, whether the second logical page size is different from the first logical page size; determine, at least partially based on the determination of whether the second logical page size is different from the first logical page size, a second physical address pointing to the starting location of the data within the second logical page; read the data from the starting location of the data within the second logical page, at least partially based on the second physical address; and transfer the data to a host device of the memory device. Attached Figure Description

[0010] Figure 1Examples of systems supporting dynamic logical page sizes for memory devices, based on the examples disclosed herein, are shown.

[0011] Figure 2 An example of an L2P table architecture supporting dynamic logical page size for memory devices is shown, based on the examples disclosed herein.

[0012] Figure 3 An example of a process flow that supports dynamic logical page size of a memory device, based on the examples disclosed herein, is shown.

[0013] Figure 4 An example of an operation flow supporting dynamic logical page size of a memory device is shown, based on the examples disclosed herein.

[0014] Figure 5 An example of a process flow that supports dynamic logical page size of a memory device, based on the examples disclosed herein, is shown.

[0015] Figure 6 A block diagram of a memory system supporting dynamic logical page sizes of memory devices according to various aspects of this disclosure is shown.

[0016] Figure 7 and 8 A flowchart illustrating one or more methods for supporting dynamic logical page sizes of memory devices, based on examples disclosed herein. Detailed Implementation

[0017] Each memory cell within a memory device can be associated with a corresponding physical address, where the physical address identifies the physical location of the corresponding memory cell within the memory device. The physical location of data within the memory device can change over time because the memory device accommodates the writing of additional data, maintenance operations performed by the memory device, or for any other reason. The host device of the memory device can use logical addresses (which may be alternatively referred to as virtual addresses or system addresses, and others) to reference data (e.g., when a read, write, or other command associated with the data is issued), and the memory device can maintain a mapping between the logical addresses associated with the data stored in the memory device and the physical addresses of the memory cells where the data is stored. This allows the memory device to change physical addresses over time, as described herein.

[0018] For example, a host device may refer to a data location stored in a memory device using logical block addresses (LBAs), which can map to the physical address of a memory page in the memory device where the data is stored. A page can refer to a group of memory cells, as further explained herein. Although examples can be found herein with reference to the LBA description, it should be understood that the teachings herein can be extended to other types of logical addresses. Because the physical address of data can change, some memory devices can maintain one or more logical-to-physical (L2P) tables that map LBAs referenced by the host device to the corresponding physical addresses of pages in the memory device. In this way, a host device can request to read data from the memory device using the same LBA used to write the data, even if the data has been moved to a different physical address during this time.

[0019] Some memory devices divide physical pages into logical pages with a page size different from the physical page size. For example, a memory device may have a physical page size of 16KB, and these physical pages may be divided into logical pages, each with a logical page size of 4KB. In this case, an L2P table can be used to map host-provided LBAs to the physical addresses of the logical pages, thereby enabling the host device to read and write data to pages smaller than the physical page size. However, because there are more logical pages than physical pages, such an L2P table may require more entries than an L2P table used to map LBAs to physical addresses.

[0020] The length of an L2P table (in terms of the number of entries) can impact the performance of a memory device. For example, a memory device may incur more overhead when creating, storing, maintaining, and traversing a longer L2P table compared to a shorter one. Therefore, reducing the number of entries in an L2P table can improve performance. Furthermore, querying an L2P table can introduce latency in response to commands issued by a host device (e.g., read or write commands). For example, an L2P table may be stored within the memory device and read by a controller used for (e.g., coupled to) the memory device, and in some cases, L2P tables may be organized as a hierarchy of L2P tables. Therefore, aspects of the teachings herein, including reducing the number of tables that can be traversed or read from the memory device to identify the physical address corresponding to the data associated with the LBA, can further provide latency benefits, as well as other benefits that will be appreciated by those skilled in the art.

[0021] As described herein, a memory device can reduce the number of entries in an L2P table by using multiple dynamic logical page sizes, wherein the logical page sizes available to the memory device can be dynamic and can range from a maximum logical page size (which may be the same as or larger than the physical page size of the memory device) to a minimum logical page size (which may be smaller than the physical page size of the memory device). This differs, for example, from using only a single logical page size, using only logical pages each of a fixed size, or both. The memory device can select the logical page size for storing data associated with a write command based on the size (e.g., quantity, length) of the data to be written and can maintain multiple L2P tables, each associated with a specific logical page size among the multiple logical page sizes available to the memory device.

[0022] For example, the memory device may first generate or otherwise store L2P tables, each containing entries pointing to a logical page with the maximum page size, thereby reducing the number of entries in these L2P tables. If the amount of data requested by the host to be written would occupy the maximum page size, the memory device can use these L2P tables to locate the logical page with the maximum page size to write the data. However, if the data requested by the host to be written can be accommodated by a smaller logical page size, the memory device can divide the larger logical page into a group of two or more smaller logical pages and store the data in the smaller logical pages within the previously larger logical page.

[0023] To enable subsequent retrieval of data from smaller logical pages, the memory device can update the original L2P entry pointing to the larger logical page to indicate that the page has been partitioned. The memory device can create a new L2P table containing entries pointing to the smaller logical pages, and can add or update entries in the L2P pointer table that point to the new L2P table and indicate the length of the new L2P table.

[0024] When the host device subsequently requests to read data, the memory device can traverse two levels of L2P tables to locate the data based on LBAs. For example, the memory device can read the entry in the original L2P table corresponding to the requested LBA to determine that a larger logical page has been partitioned, read the entry in the L2P pointer table to identify the location and length of the new L2P table, and read the entry in the new L2P table to locate the data.

[0025] As described herein, this method enables a memory device to use a smaller or shorter L2P table when the host requests to read or write large data streams (e.g., for streaming audio or video), and allows the memory device to segment larger logical pages into smaller logical pages when the host device requests to write smaller amounts of data. Therefore, the size and classification of logical pages used by the memory device, as well as the size and number of L2P tables, can be dynamically changed in response to commands issued by the host device, wherein the memory device initially uses a small and short L2P table and larger logical pages, and during operation, the count and length of the L2P table are increased, and smaller logical page sizes are dynamically (e.g., "as needed") introduced. These and other techniques described herein allow the memory device to use an "appropriately sized" L2P table and a number and length of logical addresses for the host device's data access patterns, thereby providing latency, overhead, and other benefits that can be understood by those skilled in the art.

[0026] The features of this disclosure are firstly in reference to Figure 1 The system described herein is described in the context of the system described. Features of this disclosure are described in reference to... Figure 2-5 The described operation flow and process flow are presented within the context of the description. These and other features of this disclosure are further supported by references. Figure 6-8 The device diagrams and flowcharts describing the dynamic logical page size of the memory device are shown and referenced in their description.

[0027] Figure 1 This is an example of a system 100 that supports dynamic logical page sizes for memory devices, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0028] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0029] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0030] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to examples described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 A memory system 110 is shown, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0031] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0032] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but it should be understood that the memory system 110 may contain any number of memory devices 130. Furthermore, in cases where the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0033] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. Furthermore, in some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0034] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0035] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0036] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, when data is read from or written to memory device 130, data may be stored in local memory 120 and may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updates) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a cache strategy.

[0037] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions described herein as belonging to memory system controller 115. Generally, one or more functions described herein as belonging to memory system controller 115 may actually be performed in some cases by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, bridged-conducting RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells.

[0039] In some instances, memory device 130 may include local controllers 135 (e.g., on the same die or within the same package) that can operate on one or more memory cells of memory device 130. Local controllers 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein.

[0040] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0041] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information. If each cell is configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if each cell is configured to store three bits of information, it may be referred to as a three-level cell (TLC); if each cell is configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in supporting circuitry.

[0042] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0043] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0044] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0045] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to the remaining one or more pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data remaining in the old block 170 as invalid or obsolete and update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be preferred, for example, for latency or wear considerations, to erase and rewrite the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0046] In some cases, L2P tables can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0047] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in block 170 containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0048] The number and length of L2P tables (e.g., in terms of the number of entries) can affect the performance of memory device 130. For example, memory device 130 may incur more overhead when generating, maintaining, and traversing longer L2P tables than with shorter L2P tables. Therefore, reducing the number, length, or both of the L2P tables may improve performance.

[0049] Memory system 110 can reduce the number, length, or both of the L2P tables by using multiple dynamic logical page sizes as described herein. For example, memory device 130 can first generate an L2P table with entries pointing to logical pages with the largest page size, thereby reducing the number of entries in the L2P table of each respective memory device 130. Memory system controller 115 can first generate a primary L2P table with entries mapping LBAs to the first generated L2P table of memory device 130. If the amount of data requested by host system 105 to write, for example, to memory device 130 would occupy the largest page size, then memory system controller 115 can use the primary L2P table and the L2P tables of memory device 130 to locate the logical page with the largest page size to write the data. However, if the amount of data requested by host system 105 to write can be accommodated by a smaller logical page size, then memory device 130 can divide the larger logical page into a group of two or more smaller logical pages and store the data in the smaller logical pages within the larger logical page.

[0050] In order to subsequently retrieve data from smaller logical pages, memory device 130 can update the original L2P entry pointing to the larger logical page to indicate that the page has been partitioned. Memory device 130 can create a new L2P table containing entries pointing to the smaller logical pages, and memory system controller 115 can add or update entries pointing to the new L2P table and indicating the length of the new L2P table in the L2P pointer table stored in local memory 120.

[0051] When host system 105 subsequently requests to read data, memory system controller 115 can traverse two levels of L2P tables to locate the data based on LBA. For example, memory system controller 115 can read the entry in the original L2P table of memory device 130 corresponding to the requested LBA to determine that a larger logical page has been partitioned, read the entry in the L2P pointer table of local memory 120 to identify the location and length of the new L2P table, and read the entry in the new L2P table of memory device 130 to locate the data.

[0052] As described herein, this method enables the memory system 110 to use a shorter L2P table when the host system 105 requests to read or write a large data stream (e.g., for streaming audio or video), and allows the memory device 130 to split a larger logical page into smaller logical pages when the host system 105 requests to write a smaller amount of data.

[0053] System 100 may include any number of non-transitory computer-readable media supporting dynamic logical page sizes of memory devices. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0054] Figure 2 An example of an L2P table architecture 200 supporting dynamic logical page sizes for memory devices, according to the examples disclosed herein, is shown. In some instances, the L2P table architecture 200 may be derived from, for example, references to... Figure 1 The memory system implementation of the described memory system 110. For example, the L2P table architecture 200 may be implemented by the controller 205 and the memory device 210, which may be references. Figure 1Examples of the described memory system controller 115 and memory device 130 or 140. In some instances, the L2P architecture 200 may be implemented in response to one or more commands (e.g., one or more write commands, read commands, or other commands).

[0055] Controller 205 can access the controller 205's local memory (e.g., reference). Figure 1 The described local memory 120 stores and maintains one or more tables for mapping LBAs to corresponding L2P tables located in memory device 210. For example, controller 205 may maintain a main L2P table 215. The main L2P table 215 may contain a number of entries 225 (e.g., 8 entries 225, or some other number of entries 225), each entry mapping an LBA to a corresponding L2P table 220 in memory device 210. For example, entry 225-a may map an LBA to L2P table 220-a. In some cases, entry 225 may contain the physical address of the corresponding L2P table 220. For example, entry 225-a may contain the physical address of L2P table 220-a. In some cases, entry 225 may be a 4-byte (B) physical address.

[0056] Memory device 210 may include one or more tables for mapping LBAs to physical addresses of corresponding logical pages stored in memory device 210. For example, memory device 210 may first generate a set of L2P tables 220, each containing a certain number of entries 230 (e.g., 128,000 entries 230, or some other number of entries 230). Entries 230 may contain the physical addresses of logical pages stored in memory device 210. In some instances, each L2P table 220 may be associated with a maximum logical page size x supported by memory device 210. For example, each entry 230 of L2P table 220 may contain the physical address of a logical page of size x stored in memory device 210. In some cases, entry 230 may be a 4-byte physical address.

[0057] Memory device 210 may generate lower-level L2P tables associated with logical page sizes smaller than the maximum logical page size x. For example, if the amount of data requested for writing by the host device can be accommodated by logical pages smaller than x, then memory device 210 may partition one or more logical pages of size x into a group of two or more logical pages of smaller size. Memory device 210 may create a new L2P table containing the group of smaller logical pages. For example, if the amount of data requested for writing by the host device is likely closest to size x / 2, then memory device 210 may partition a logical page of size x (e.g., the logical page pointed to by entry 230-a) into two logical pages, each of size x / 2. Memory device 210 may generate an L2P table 245 associated with logical pages of size x / 2. For example, memory device 210 may create an L2P table 245 with two entries 250. First entry 250 may contain the physical address of one of the two logical pages of size x / 2, and second entry 250 may contain the physical address of the other logical page of size x / 2. Memory device 210 may write data to one or both of the logical pages of size x / 2 (e.g., if the size of the data to be written is greater than x / 2). To enable subsequent retrieval of the data, memory device 210 may update at least a portion of the physical address of entry 230-a to indicate that the logical page pointed to by entry 230-a has been partitioned. Although the above example is described with respect to logical pages of size x / 2, memory device 210 may generate any number of additional lower-level L2P tables associated with logical page sizes less than x and supported by memory device 210. For example, memory device 210 may generate an L2P table 255 with a number of entries 260 containing the physical addresses of logical pages of size x / 4 in response to receiving a write command from a host device.

[0058] Memory device 210 may maintain lower-level L2P tables associated with logical page sizes smaller than the maximum logical page size x. For example, memory device 210 may have one or more previously generated lower-level L2P tables in response to receiving a write command from a host device. If memory device 210 determines that a logical page of size x will be split into two or more logical pages of smaller sizes and an L2P table associated with the smaller sizes already exists, then memory device 210 may add entries to the existing L2P tables pointing to the new logical pages instead of generating an additional L2P table associated with the smaller sizes. For example, if L2P table 245 exists in memory device 210 and memory device determines that a logical page of size x will be split into two logical pages of size x / 2, then memory device may add two entries 250, each associated with one of the two logical pages of size x / 2, instead of generating an additional L2P table 245. In this way, the additional L2P table can be associated with multiple logical pages of size x that have already been split.

[0059] The controller 205 may generate and maintain an L2P pointer table 235 in its local memory. The controller 205 may use the L2P pointer table 235 to track and locate additional L2P tables stored in the memory device 210. For example, the L2P pointer table 235 may contain a number of entries 240 (e.g., eight entries 240, or some other number of entries 240), each entry mapping the physical address of the corresponding entry 230 from the L2P table 220 to the physical address of the corresponding L2P table 245 in the memory device 210 associated with a logical page size less than the maximum logical page size x. In some instances, each entry 240 may be associated with a specific (e.g., corresponding) L2P table 245, and information about that specific L2P table 245 may be tracked. For example, entry 240-a may be associated with L2P table 245. The first part of entry 240-a may contain the physical address of L2P table 245, and the second part of entry 240-a may track the length of L2P table 245. For example, when memory device 210 generates L2P table 245, controller 205 may create entry 240-a, wherein the first part of entry 240-a contains the physical address of L2P table 245, and the second part of entry 240-a contains the length of L2P table 245 (e.g., the number of entries 250). If L2P table 245 is subsequently updated (e.g., entry 250 is added to or removed from L2P table 245), then controller 205 may update entry 240-a to specify the new length of L2P table 245. Controller 205 may create and update additional entries 240 in response to memory device 210 generating and maintaining L2P tables associated with logical page sizes less than the maximum logical page size x. In some cases, entry 240 may be 8 bytes.

[0060] The controller 205 may store a primary L2P table 215 and an L2P pointer table 235 in a first type of memory, and the memory device 210 may store L2P tables (e.g., L2P tables 220, 245, and 250) in a second type of memory. In some cases, the first type of memory may be SRAM, and the second type of memory may be NAND memory. In other cases, the first type of memory and the second type of memory may be the same type of memory.

[0061] In some instances, data previously written to a logical page may become invalid or obsolete. Controller 205 may mark or otherwise delimit the data on those other logical pages as invalid or obsolete (e.g., via an unmap (UNMAP) command). Therefore, those other logical pages can be freely written with new data without losing previously stored data.

[0062] The memory device can merge two or more free logical pages in a lower-level L2P table. For example, if writing data frees up four 128KB logical pages, the memory device can merge these four 128KB logical pages into a single 512KB logical page. The memory device can adjust the corresponding entry in this 512KB L2P table to indicate that the logical page has not yet been split, and the controller 205 can update the corresponding entry 240 in the L2P pointer table 235 with the new, reduced-length L2P table associated with the 128KB logical page. Alternatively, the memory device can remove entries in the L2P table corresponding to the four 128KB logical pages and offset any remaining entries in the L2P table up to occupy the gap created by removing the entries corresponding to the four 128KB logical pages. The memory device can update the offset of any entry in the corresponding 512KB L2P table to indicate the new position in the L2P table. In this way, the entries in the L2P table can remain contiguous.

[0063] Figure 3 An example of a process flow 300 supporting dynamic logical page sizes of a memory device, according to the examples disclosed herein, is shown. Process flow 300 can be executed by components of the memory system, such as those described in reference to... Figure 1 The memory system 110 is described. For example, process flow 300 can be executed by a controller and a memory device, for example, referring to [references to...]. Figure 1 and 2 The memory system controllers 115 and 205, and memory devices 130, 140, and 210 are described. Process flow 300 can depict the generation and maintenance of L2P tables (e.g., in response to receiving a write command from the host device). Figure 2The process described in the L2P table is as follows. For clarity, process flow 300 uses a specific instance of a memory device with a maximum logical page size of 512KB, but similar processes are also applicable to memory devices with different maximum logical page sizes, which are also covered within the scope of this disclosure.

[0064] At 305, the controller may receive a write command from the host device. The write command may contain data to be written to the memory device and an LBA assigned by the host device to the data and subsequently available for reading.

[0065] In some instances, the controller may store virtual block information associated with the memory device and may allocate physical addresses for data to be written based on the virtual block information. For example, the memory device may contain one or more dies (e.g., die 160), each containing one or more planes (e.g., plane 165). In some cases, a virtual block may be defined as a set of blocks with the same block number across all planes of the memory device. For example, if the memory device contains four dies and each die contains four planes, then virtual block 0 may be the block set {die 0 plane 0 block 0, die 0 plane 1 block 0, die 0 plane 2 block 0, ..., die 2 plane 0 block 0, ..., die 3 plane 2 block 0, die 3 plane 3 block 0}. In some other cases, a virtual block may be defined as a subset of memory cells contained in a block (e.g., block 170) within the memory device. The controller may track which virtual blocks in the memory device are free, allocate physical addresses for data based on the free virtual blocks, and write the data to the allocated physical addresses in the memory device.

[0066] In some instances, the controller may create a mapping between the LBA assigned to the data and the physical address of the data stored in the memory device, and may store the mapping in a change log stored in the controller. The controller can then use the mapping stored in the change log to read the data. In some cases, the controller may determine to erase the mapping stored in the change log (e.g., due to change log size limitations, entering low-power mode). To avoid losing the mapping, the controller may determine to store the mapping in one or more L2P tables stored in the memory device. In some cases, steps 310 to 380 may be implemented in response to the controller determining to store the mapping in the one or more L2P tables. In some other cases, steps 310 to 380 may be implemented in response to receiving a write command from the host device at 305.

[0067] At 310, the controller can use the LBA as an index to read entries in the primary L2P table associated with the LBA (e.g., entry 225-a in primary L2P table 215). For example, the primary L2P table may be stored in the SRAM of a memory device. An entry may contain a physical address pointing to a 512KB L2P table (e.g., L2P table 220-a).

[0068] At 315, the controller may determine (e.g., identify) the offset associated with the LBA to determine a specific entry in the 512KB L2P table. For example, a physical address may point to the 512KB L2P table, and the controller may add the offset to this physical address to determine the physical address of the specific entry in the 512KB L2P table. As an example, the controller may determine the offset at 315 based on a portion of the bits contained in the LBA; for example, a certain number of the most significant bits of the LBA may identify entry 225 associated with the LBA (e.g., entry 225-a in the main L2P table 215), and a certain other number of bits (e.g., the remaining bits or another portion of the less significant bits) may identify the offset determined at 315. Or, as another example, entry 225 in the main L2P table 215 may be stored as an indication of the offset determined at 315.

[0069] The 512KB L2P table may contain the following entries: (1) an entry that directly points to a 512KB logical page (if the 512KB logical page has not yet been partitioned into smaller logical pages), or (2) an entry containing an indication that the 512KB has been partitioned into smaller logical page sizes; and an offset value that can subsequently be used to locate data within the smaller logical pages. For example, the 512KB L2P table and the corresponding 512KB logical page may be stored in the NAND memory of a memory device.

[0070] At position 320, the controller can read the entry in the 512KB L2P table located at the physical address determined at position 315. This entry can contain the physical address of the data to be written to the host within a 512KB logical page.

[0071] At 325, the controller may identify the logical page size based on the size of the data that the host has requested to be written in the write command. (Although process flow 300 describes 325 as occurring after 320, in some instances, 325 may occur before, or in parallel with, 310, 315, or 320.) The controller may identify the logical page size by selecting a logical page size from a set of logical page sizes supported by the memory device. For example, the memory device may support logical page sizes of 512KB, 256KB, 128KB, 64KB, 32KB, 16KB, 8KB, and 4KB. The controller may select the logical page size that is closest to the size of the data requested to be written by the host. The selected logical page size may be larger or smaller than the data size and may be selected to optimize various aspects (e.g., minimizing the total number of logical pages, minimizing the number of L2P table entries, or optimizing some other aspect). For example, if the host requests to write 400KB of data, the controller can select a logical page size of 512KB and write the data into a single 512KB logical page. If the host device requests to write 5KB of data, the controller can select a logical page size of 4KB and write the data into two 4KB logical pages. That is, the controller can write the first part of the data into the first 4KB logical page and the second part of the data into the second 4KB logical page.

[0072] At 330, the controller can determine whether the selected logical page size is 512KB (e.g., the maximum logical page size associated with the memory device).

[0073] If the selected logical page size is 512KB, then at position 335, the controller can write data to the 512KB logical page pointed to by the physical address read from the 512KB L2P table at position 320. In this case, the entries in the lower-level L2P table continue to point to the 512KB logical page containing the data and are therefore not updated.

[0074] If the selected logical page size is not 512KB, then at position 340, the controller can determine whether a logical page pool already exists with the selected logical page size within the 512KB page pointed to by the second-level L2P table. For example, if the selected logical page size is 128KB, then the controller can determine whether the pointed-to 512KB logical page has already been partitioned into 128KB logical pages.

[0075] If the 512KB page has not yet been partitioned into a logical page pool with the selected logical page size, then the controller and / or memory device may perform steps 345 to 360 as follows. In this case, the memory device may not have yet created a lower-level L2P table pointing to the logical pages within the pool (e.g., relative to the 512KB L2P table), and therefore such an L2P table can be created.

[0076] At position 345, the memory device may divide the 512KB logical page into a pool of logical pages with a selected logical page size, and write data into one or more logical pages within the pool. Further details regarding the division of the 512KB logical page are provided below. Figure 4 describe.

[0077] At 350, the memory device can create a new second-level L2P table (e.g., L2P table 255) for a selected logical page size containing entries containing data physical addresses.

[0078] At 355, the controller can update the L2P pointer table (e.g., L2P pointer table 235) by adding an entry to the L2P pointer table containing: (1) the physical address of the new lower-level L2P table associated with the selected logical page size, and (2) the length of the lower-level L2P table in terms of the number of entries. In some instances, the controller can create the L2P pointer table and add entries to it if no lower-level L2P table has been previously created or if all lower-level L2P tables have been previously erased.

[0079] At position 360, the memory device may update the entry in the 512KB L2P table that has been read at position 320 to indicate that this 512KB logical page has been partitioned into smaller logical page sizes, and update the offset that can be used to locate data within the smaller logical pages. For example, the memory device may store a value in the most significant bit (MSB) indicating that the 512KB logical page has been partitioned, and three additional bits (e.g., bits 28, 29, and 30 of a 4B entry) that can point to an entry in the L2P pointer table associated with the selected logical page size. In some instances, the offset may be stored in the remaining bits of the entry in the 512KB L2P table (e.g., bits 0 through 27 of a 4B entry).

[0080] If the 512KB page has been partitioned into logical page pools with selected logical page sizes, then the controller and / or memory device may perform steps 365 to 375, as follows. In this case, the memory device may have already created a lower-level L2P table associated with the selected logical page size.

[0081] At position 365, the memory device can write data to one or more logical pages within the logical page pool.

[0082] At position 370, the memory device can add or update entries with physical addresses pointing to data in the corresponding lower-level L2P table. The length of the lower-level L2P table can therefore be increased.

[0083] At 375, the memory device can update the entries in the L2P pointer table that point to the lower-level L2P table to reflect the new length of the lower-level L2P table.

[0084] At position 380, the memory device may update the entry in the 512KB L2P table that has been read at position 320 to indicate that this 512KB logical page has been partitioned into smaller logical page sizes, and update the offset that can be used to locate data within the smaller logical pages. For example, the memory device may store a value in the MSB indicating that the 512KB logical page has been partitioned, and three additional bits (e.g., bits 28, 29, and 30 of a 4B entry) that can point to an entry in the L2P pointer table associated with the selected logical page size. In some instances, the offset may be stored in the remaining bits of the entry in the 512KB L2P table (e.g., bits 0 through 27 of a 4B entry).

[0085] Figure 4 Examples of operation flow 400 supporting dynamic logical page sizes of memory devices are shown according to the examples disclosed herein. In some examples, operation flow 400 may be executed by a memory device (e.g., memory device 130, 140, or 210) in response to receiving a command to write data smaller than the maximum supported logical page size supported by the memory device (e.g., from a host device).

[0086] The memory device may contain one or more logical pages that support a maximum supported logical page size x (e.g., a 512KB logical page size). For example, the memory device may contain a logical page 405 with a logical page size x. In some instances, the host device may request to write an amount of data smaller than x. The memory device may divide logical page 405 into smaller logical pages to accommodate the data. For example, the memory device may divide logical page 405 into N logical pages 410 with a size y, where y is less than x and is the size of the logical page size supported by the memory device. The memory device may then write data into one or more of the logical pages 410. In some cases, the memory device may create a lower-level L2P table with entries containing the physical address of logical page 410. In other cases, the memory device may add entries containing the physical address of logical page 410 to an existing lower-level L2P table associated with the logical page of size y.

[0087] Logical page 405 may be associated with an L2P table containing entries pointing to logical pages of size x. For example, an entry in the L2P table may contain the physical address of logical page 405. After logical page 405 is partitioned, the memory device may update the L2P table entries to indicate that logical page 405 has been partitioned into logical page 410. Additionally, the memory device may update entries to indicate the offset within a lower-level L2P table associated with the logical page 410 where the data resides. For example, the memory device may store a value in the MSB indicating that the 512KB logical page has been partitioned, and three additional bits (e.g., bits 28, 29, and 30 of a 4B entry) that may point to an entry in the L2P pointer table associated with the selected logical page size. It should be understood that any other specific numerical examples provided herein are for illustrative purposes only and are not intended to limit the claims or otherwise. In some instances, the offset may be stored in the remaining bits of the entry associated with logical page 405. In some instances, if the MSB is 0, the controller can determine that logical page 405 has not yet been partitioned, and if the MSB is 1, the controller can determine that the 512KB logical page has been partitioned. In other instances, the reverse is also true.

[0088] In this example, according to the following (assuming the MSB indicates that the 512KB logical page has been partitioned), the three extra bits can be used to point to entries in the L2P pointer table. If the three extra bits in the entry are 000, then the logical page has been partitioned into two 256KB pages, and some or all of the remaining bits in the entry represent the offset of the 256KB address. If the three extra bits in the entry are 001, then the logical page has been partitioned into four 128KB pages, and the remaining bits in the entry represent the offset of the 128KB address. If the three extra bits in the entry are 010, then the logical page has been partitioned into eight 64KB pages, and the remaining bits in the entry represent the offset of the 64KB address. If the three extra bits in the entry are 011, then the logical page has been partitioned into sixteen 32KB pages, and the remaining bits in the entry represent the offset of the 32KB address. If the three extra bits in the entry are 100, then the logical page has been partitioned into thirty-two 16KB pages, and the remaining bits in the entry represent the offset of the 16KB address. If the three extra bits in the entry are 101, then the logical page has been divided into 64 8KB pages, and the remaining bits of the entry represent the offset of the 8KB address. If the three extra bits in the entry are 110, then the logical page has been divided into 128 4KB pages, and the remaining bits of the entry represent the offset of the 4KB address. Therefore, when the memory device divides logical page 405, the L2P table entry pointing to logical page 405 can be updated to indicate the location of the smaller logical page. Other instances and combinations of the three extra bits are possible to represent different logical page divisions, and the examples provided above should not be considered as limiting the range.

[0089] Figure 5 An example of a process flow 500 supporting dynamic logical page sizes of a memory device is shown, according to the examples disclosed herein. Process flow 500 can be executed by components of the memory system, such as those described in reference to... Figure 1 The memory system 110 is described. For example, process flow 500 can be executed by a controller and a memory device, for example, referring to [references to...]. Figure 1 and 2 The memory system controllers 115 and 205, and memory devices 130, 140, and 210 are described. Process flow 500 can depict the use of an L2P table (e.g., in response to a read command received from the host device). Figure 2 Chinese description and reference Figure 3 The process described is for locating data in a memory device using an L2P table. For clarity, process flow 500 uses a specific instance of a memory device with a maximum logical page size of 512KB, but similar processes are applicable to memory devices with different maximum logical page sizes, which are also covered within the scope of this disclosure.

[0090] At point 505, the controller can receive a read command from the host device. The read command may contain an LBA of the data to be read from the memory device.

[0091] At 510, the controller can use the LBA as an index to read entries in the primary L2P table associated with the LBA (e.g., entry 225-a in primary L2P table 215). For example, the primary L2P table may be stored in the SRAM of a memory device. An entry may contain a physical address pointing to a 512KB L2P table (e.g., L2P table 220).

[0092] The 512KB L2P table may contain the following entries: (1) an entry that directly points to a 512KB logical page (if the 512KB logical page has not yet been partitioned into smaller logical pages), or (2) an entry containing an indication that the 512KB has been partitioned into smaller logical page sizes; and an offset value that can subsequently be used to locate data within the smaller logical pages. For example, the 512KB L2P table and the corresponding 512KB logical page may be stored in the NAND memory of a memory device.

[0093] At 515, the controller can add an offset to the physical address retrieved from the main L2P table based on the LBA to determine the physical address of a specific entry in the 512KB L2P table.

[0094] At 520, the controller can read an entry from the 512KB L2P table located at the physical address generated at 515. As previously described, the entry may contain: (1) a physical address that directly points to the 512KB logical page containing data (if the 512KB logical page has not yet been partitioned into smaller logical pages), or (2) an indication that the 512KB has been partitioned into smaller logical page sizes to store data, and an offset value that can be used to locate the data within the smaller logical page.

[0095] At position 525, the controller can determine whether the 512KB page has been partitioned into smaller logical pages based on the entry read at position 520. Figure 5 In the example shown, the controller can determine whether the 512KB page has been partitioned based on the value in the MSB of the entry. If the MSB is 0, the controller can determine that the 512KB logical page has not yet been partitioned into smaller logical pages. If the MSB is 1, the controller can determine that the 512KB logical page has been partitioned into smaller logical pages. Other bits in the entry can be used to indicate whether a larger logical page has been partitioned into smaller logical pages without departing from the scope of this disclosure.

[0096] If the controller determines at 525 that the 512KB logical page has not yet been segmented, then at 530, the controller may add an offset to the physical address retrieved at 520 to determine the starting physical address of the requested data (if the requested data is not located at the starting physical address of the 512KB logical page).

[0097] Next, at 535, the controller can read the requested data starting from the physical address determined at 530 and transmit the data to the host device.

[0098] If the controller determines at 525 that the 512KB logical page has been partitioned, then the controller can execute 540 to 560, as follows.

[0099] At 540, the controller can use a portion of the entries retrieved at 520 to identify entries in the L2P pointer table that point to lower-level L2P tables associated with the location of the data. Figure 5 In the example shown, the controller can use bits 28, 29, and 30 of the entry to look up the relevant entry in the L2P pointer table, and can retrieve this entry from the L2P pointer table. In this way, bits 28, 29, and 30 can be used to indicate the logical page size of previously written data, because each entry in the L2P pointer table can be associated with an L2P table of a specific logical page size.

[0100] An entry in the L2P pointer table may contain the physical address of the associated lower-level L2P table (e.g., a lower-level L2P table associated with the logical page size of the data stored within it) and the length of the lower-level L2P table.

[0101] At 545, the controller can add an offset to the physical address retrieved from the L2P pointer table to generate the physical address of a specific entry in the lower-level L2P table. In some instances, the remaining bits (e.g., bits 0 through 27) of the entry retrieved at 520 can indicate the offset value, and the controller can calculate the offset to be added to the physical address based on reading the remaining bits.

[0102] At 550, the controller can read the entry of the lower-level L2P table located at the physical address generated at 545, and can retrieve the physical address of the smaller logical page containing the requested data.

[0103] If the requested data is not located at the beginning of a smaller logical page, then at 555, the controller can add an offset to the physical address retrieved at 550 to determine the physical address of the data location within the smaller logical page.

[0104] At 560, the controller can start reading data from the location pointed to by the physical address generated at 555 within a smaller logical page, and then transfer the data to the host device.

[0105] Figure 6 A block diagram 600 illustrates a memory system 605 supporting dynamic logical page sizes for a memory device according to an example disclosed herein. The memory system 605 may be a reference... Figures 1 to 5 Examples of aspects of the described memory system. Memory system 605 may include a communication component 610, an L2P table manager 615, a size component 620, a write component 625, a physical address component 630, a read component 635, a pointer table component 640, and an offset component 645. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0106] In some instances, communication component 610 may receive a write command to write a first amount of data to a memory device, the write command being associated with a logical address. In some cases, communication component 610 may receive a second write command to write a second amount of data to a memory device, the second write command including a second logical address.

[0107] In some instances, communication component 610 may receive a read command associated with a logical address corresponding to the starting location of data stored in the memory device. In some cases, communication component 610 may transfer data to a host device of the memory device.

[0108] Upon receiving a write command from the communication component 610, the L2P table manager 615 can read the first entry of the first L2P table based on a logical address. The first L2P table is used to map a set of logical addresses to the physical addresses of corresponding first group of logical pages in the memory device. Each logical page has a first logical page size, and the first entry of the first L2P table contains the first physical address of the first logical page in the first group of logical pages.

[0109] In some instances, the L2P table manager 615 may read a first entry of a primary L2P table that maps a set of logical addresses to a corresponding set of L2P tables containing a first L2P table, based on a logical address. The first entry of the primary L2P table contains a third physical address pointing to the first L2P table, wherein reading the first entry of the first L2P table includes reading the first entry of the first L2P table based on the third physical address.

[0110] Upon receiving a second write command from the communication component 610, in some instances, the L2P table manager 615 may read a second entry of a third L2P table based on a second logical address, which is used to map the third set of logical addresses to the physical addresses of the corresponding third set of logical pages in the memory device. Each logical page has a first logical page size, and the second entry of the third L2P table contains the fifth physical address of the third logical page in the third set of logical pages.

[0111] In some instances, the L2P table manager 615 may read a second entry of a third L2P table based on a second logical address, which is used to map a third set of logical addresses to the physical addresses of corresponding third set of logical pages in a memory device. Each logical page has a first logical page size, and the second entry of the third L2P table contains the fifth physical address of the third logical page in the third set of logical pages.

[0112] Upon receiving a read command from the communication component 610, the L2P table manager 615 can read a first entry of a first L2P table based on a logical address, wherein the first entry contains a first physical address of a first logical page of a memory device having a first logical page size, and wherein the value of a first portion of the first physical address indicates a second logical page size of a second logical page of a memory containing data, the first logical page containing the second logical page.

[0113] In some instances, the L2P table manager 615 may read the first entry of the L2P pointer table based on the value of a second portion of a first physical address, the first entry of the L2P pointer table containing a third physical address.

[0114] In some instances, the L2P table manager 615 can read a third entry of the primary L2P table based on a logical address, wherein the third entry contains a third physical address pointing to the first L2P table.

[0115] Upon receiving a write command from communication component 610, size component 620 can identify a second logical page size based on the size of the first data volume. In some instances, size component 620 can select a second logical page size from a set of supported logical page sizes.

[0116] Upon receiving a second write command from communication component 610, in some instances, size component 620 may identify a third logical page size based on a second size of the second data volume. In some cases, size component 620 may identify that the second data volume corresponds to a first logical page size.

[0117] Upon receiving a read command from the communication component 610, the size component 620 can determine whether the size of the second logical page is different from the size of the first logical page based on the value of the first part of the first physical address.

[0118] The write component 625 can write at least a portion of the first data amount to a second logical page of the memory device having a second logical page size, based on a first physical address, wherein the first logical page contains the second logical page. In some instances, the write component 625 can write at least a portion of the second data amount to a fourth logical page of the memory device having a third logical page size, wherein the third logical page contains the fourth logical page. In some cases, the write component 625 can write the second data amount to a third logical page.

[0119] In some instances, the L2P table manager 615 may store a first entry of a second L2P table for mapping a second set of logical addresses to the physical addresses of corresponding second set of logical pages in a memory device, based on the second logical page size identified by the size component 620, wherein each logical page in the second set of logical pages has a second logical page size, and the first entry of the second L2P table contains the second physical address of the second logical page.

[0120] Upon receiving a read command from the communication component 610, the physical address component 630 can determine a second physical address pointing to the starting position of data within the second logical page based on whether the size of the second logical page is different from the size of the first logical page.

[0121] In some instances, the physical address component 630 can identify the value of a second portion of a first physical address, wherein the value of the second portion of the first physical address points to the first entry in the L2P pointer table.

[0122] The read component 635 can read data starting from the beginning of the data within a second logical page based on determining a second physical address. In some instances, the read component 635 can read a first entry in an L2P pointer table, which includes a third physical address, based on identifying a second portion of a first physical address. In some instances, the read component 635 can read a first portion of the data from the second logical page. In some cases, the read component 635 can read a second portion of the data from a third logical page having the same logical page size as the second logical page.

[0123] Upon receiving a write command from the communication component 610, the pointer table component 640 may store a first entry of the L2P pointer table based on the identified second logical page size. The first entry of the L2P pointer table contains a fourth physical address and the length of the second L2P table, wherein the fourth physical address points to the second L2P table.

[0124] In some instances, the pointer table component 640 may determine that two or more logical pages having a second logical page size and pointed to by a second L2P table have been deleted. In some cases, the pointer table component 640 may update the length of the second L2P table in the L2P pointer table and the length of the first L2P table in the L2P pointer table based on the determination that the two or more logical pages have been deleted.

[0125] Upon receiving a read command from communication component 610, offset component 645 may add an offset to a third physical address to determine a fourth physical address associated with a second entry in the second L2P table, wherein the offset is indicated by a third portion of the first physical address. In some instances, read component 635 may read a second entry in the second L2P table, wherein the second entry in the second L2P table contains at least a portion of the second physical address.

[0126] In some instances, the offset component 645 can add a second offset to a second entry in the second L2P table to generate a second physical address.

[0127] In some instances, offset component 645 can add an offset to a first physical address to determine a second physical address.

[0128] Upon receiving a read command from communication component 610, in some instances, read component 635 may read a third entry of the primary L2P table based on a logical address, wherein the third entry includes a third physical address pointing to the first L2P table. In some cases, offset component 645 may add a third offset to the third physical address to generate a fourth physical address pointing to the first entry of the first L2P table, wherein reading the first entry of the first L2P table includes reading the first entry of the first L2P table based on the fourth physical address.

[0129] Figure 7 A flowchart illustrating one or more methods 700 for supporting dynamic logical page sizes of a memory device according to various aspects of this disclosure is shown. Operation of method 700 may be implemented by the memory system or its components described herein. For example, operation of method 700 may be provided by reference to... Figure 6 The described memory system performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the memory system to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0130] At 705, the memory system may receive a write command to write a first amount of data to the memory device, the write command being associated with a logical address. Operation 705 may be performed according to the method described herein. In some instances, aspects of operation 705 may be referenced... Figure 6 The described communication component is executed.

[0131] In some instances, the memory system may store virtual block information associated with the memory device and may allocate physical addresses for data to be written based on the virtual block information. For example, the memory system may track which virtual blocks in the memory device are free, allocate physical addresses for data based on the free virtual blocks, and write the data to the allocated physical addresses in the memory device. In some instances, the memory system may create a mapping between the LBAs allocated to data and the physical addresses of the data stored in the memory device, and may store the mapping in a change log stored in the memory system. The memory system may then use the mapping stored in the change log to read the data. In some cases, the memory system may determine to erase the mapping stored in the change log (e.g., due to change log size limitations, entering a low-power mode). To avoid losing the mapping, the memory system may determine to store the mapping in one or more L2P tables stored in the memory device. In some cases, steps 710 to 725 may be implemented in response to the memory system determining to store the mapping in the one or more L2P tables. In some other cases, steps 710 to 725 may be implemented in response to receiving a write command from the host device at step 705.

[0132] At 710, the memory system can read a first entry of a first L2P table based on a logical address, wherein the first L2P table is used to map a set of logical addresses to the physical addresses of corresponding first group of logical pages in the memory device, each logical page having a first logical page size, and wherein the first entry of the first L2P table contains the first physical address of the first logical page in the first group of logical pages. Operation 710 can be performed according to the method described herein. In some instances, aspects of operation 710 may be referenced from... Figure 6 The L2P table manager described is executed.

[0133] At 715, the memory system can identify the second logical page size based on the size of the first data amount. Operation 715 can be performed according to the method described herein. In some instances, aspects of operation 715 can be referenced. Figure 6 The component of the described size is executed.

[0134] At 720, the memory system may write at least a portion of a first data amount to a second logical page of the memory device having a second logical page size, based on a first physical address, the first logical page containing the second logical page. Operation 720 may be performed according to the method described herein. In some instances, aspects of operation 720 may be referenced from... Figure 6 The described write component is executed.

[0135] At 725, the memory system may store a first entry of a second L2P table, based on an identification of a second logical page size, for mapping the second set of logical addresses to the physical addresses of the corresponding second set of logical pages in the memory device, each logical page in the second set of logical pages having a second logical page size, wherein the first entry of the second L2P table contains the second physical address of the second logical page. Operation 725 may be performed according to the method described herein. In some instances, aspects of operation 725 may be referenced from... Figure 6 The L2P table manager described is executed.

[0136] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a write command to write a first amount of data to a memory device, the write command being associated with a logical address; reading a first entry of a first L2P table based on the logical address, wherein the first L2P table is used to map a set of logical addresses to physical addresses of corresponding first set of logical pages in the memory device, each logical page having a first logical page size, and wherein the first entry of the first L2P table contains a first physical address of the first logical page in the first set of logical pages; identifying a second logical page size based on the size of the first data amount; writing at least a portion of the first data amount to a second logical page in the memory device having a second logical page size, the first logical page containing the second logical page, based on the first physical address; and storing a first entry of a second L2P table for mapping a second set of logical addresses to physical addresses of corresponding second set of logical pages in the memory device, each logical page in the second set of logical pages having a second logical page size, based on the identified second logical page size, wherein the first entry of the second L2P table contains a second physical address of the second logical page.

[0137] Some instances of the method 700 and device described herein may further include operations, features, components, or instructions for: reading a first entry of a primary L2P table that maps a set of logical addresses to a corresponding set of L2P tables containing a first L2P table, the first entry of the primary L2P table containing a third physical address pointing to the first L2P table, wherein reading the first entry of the first L2P table includes reading the first entry of the first L2P table based on the third physical address.

[0138] In some cases of the method 700 and device described herein, the primary L2P table may be stored in a first type of memory, and the first L2P table may be stored in a second type of memory.

[0139] Some instances of the method 700 and device described herein may further include operations, features, components, or instructions for: storing a first entry of an L2P pointer table based on identifying a second logical page size, the first entry of the L2P pointer table containing a fourth physical address and the length of a second L2P table, wherein the fourth physical address points to the second L2P table.

[0140] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for: receiving a second write command to write a second amount of data to a memory device, the second write command including a second logical address; based on the second logical address, reading a second entry of a third L2P table for mapping a third set of logical addresses to physical addresses of corresponding third set of logical pages in the memory device, each logical page possibly having a first logical page size, the second entry of the third L2P table including a fifth physical address of a third logical page in the third set of logical pages; identifying a third logical page size based on a second size of the second amount of data; and writing at least a portion of the second amount of data to a fourth logical page of the memory device having a third logical page size, wherein the third logical page includes the fourth logical page.

[0141] In some cases of the method 700 and apparatus described herein, the third logical page size may be different from the second logical page size, and the method 700 and apparatus described herein may further include operations, features, components, or instructions for: storing a second entry of an L2P pointer table based on identifying the third logical page size, the second entry of the L2P pointer table containing a sixth physical address and the length of a fourth L2P table, wherein the sixth physical address points to the fourth L2P table associated with the fourth logical page.

[0142] In some embodiments of the method 700 and apparatus described herein, the third logical page size may be the same as the second logical page size, and the method 700 and apparatus described herein may further include operations, features, components, or instructions for updating the length of the second L2P table in the first entry of the L2P pointer table based on the fact that the third logical page size is the same as the second logical page size.

[0143] In some instances of the method 700 and device described herein, the first L2P table and the third L2P table may be the same L2P table.

[0144] In some cases of the method 700 and device described herein, the first L2P table and the third L2P table may be different L2P tables.

[0145] Some examples of the method 700 and device described herein may further include operations, features, components, or instructions for: determining that two or more logical pages having a second logical page size and pointed to by a second L2P table may have been deleted, and updating the length of the second L2P table in the L2P pointer table and the length of the first L2P table in the L2P pointer table based on the determination that the two or more logical pages may have been deleted.

[0146] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for: receiving a second write command to write a second amount of data to a memory device, the second write command containing a second logical address; based on the second logical address, reading a second entry of a third L2P table for mapping a third set of logical addresses to physical addresses of corresponding third set of logical pages in the memory device, each logical page potentially having a first logical page size, the second entry of the third L2P table containing a fifth physical address of a third logical page in the third set of logical pages; identifying that the second amount of data corresponds to the first logical page size; and writing the second amount of data to the third logical page.

[0147] In some instances of the method 700 and apparatus described herein, the first logical page size may be the largest logical page size among a set of supported logical page sizes associated with the memory device, the set of supported logical page sizes including a second logical page size.

[0148] In some instances of the method 700 and device described herein, identifying a second logical page size may include operations, features, components, or instructions for selecting a second logical page size from the set of supported logical page sizes.

[0149] Figure 8 A flowchart illustrating one or more methods 800 for supporting dynamic logical page sizes of a memory device according to various aspects of this disclosure is shown. Operation of method 800 may be implemented by the memory system or its components described herein. For example, operation of method 800 may be provided by reference to... Figure 6 The described memory system performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the memory system to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0150] At 805, the memory system may receive a read command associated with a logical address of the starting location of data stored in the memory device. Operation 805 may be performed according to the methods described herein. In some instances, aspects of operation 805 may be referenced from... Figure 6 The described communication component is executed.

[0151] At 810, the memory system can read a first entry of a first L2P table based on a logical address, wherein the first entry contains a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing data, the first logical page containing the second logical page. Operation 810 can be performed according to the method described herein. In some instances, aspects of operation 810 may be referenced from... Figure 6 The L2P table manager described is executed.

[0152] At 815, the memory system can determine whether the second logical page size differs from the first logical page size based on the value of the first portion of the first physical address. Operation 815 can be performed according to the method described herein. In some instances, aspects of operation 815 can be found in references. Figure 6 The component of the described size is executed.

[0153] At 820, the memory system can determine a second physical address pointing to the starting location of data within the second logical page based on a determination of whether the size of the second logical page differs from the size of the first logical page. Operation 820 can be performed according to the method described herein. In some instances, aspects of operation 820 can be found in references... Figure 6 The physical address component described is executed.

[0154] At 825, the memory system can read data starting from the beginning of the data within the second logical page based on the second physical address. Operation 825 can be performed according to the method described herein. In some instances, aspects of operation 825 can be found in references. Figure 6 The described reading component is executed.

[0155] At 830, the memory system can transfer data to the host device of the memory device. Operation 830 can be performed according to the method described herein. In some instances, aspects of operation 830 can be found in references. Figure 6 The described communication component is executed.

[0156] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a read command associated with a logical address of the starting location of data stored in a memory device; reading a first entry of a first L2P table based on the logical address, wherein the first entry contains a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing data, the first logical page containing the second logical page; determining, based on the value of the first portion of the first physical address, whether the second logical page size is different from the first logical page size; determining, based on the determination of whether the second logical page size is different from the first logical page size, a second physical address pointing to the starting location of data within the second logical page; reading data from the starting location of data within the second logical page based on the second physical address; and transferring the data to a host device of the memory device.

[0157] In some instances of the method 800 and apparatus described herein, the second logical page size may differ from the first logical page size, and determining the second physical address may include operations, features, components, or instructions for: identifying a value of a second portion of the first physical address, wherein the value of the second portion of the first physical address points to a first entry in an L2P pointer table; reading a first entry in the L2P pointer table, which contains a third physical address, based on identifying the value of the second portion of the first physical address; adding an offset to the third physical address to determine a fourth physical address associated with a second entry in the second L2P table, wherein the offset may be indicated by a third portion of the first physical address; and reading a second entry in the second L2P table, wherein the second entry in the second L2P table contains at least a portion of the second physical address.

[0158] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for adding a second offset to a second entry in a second L2P table to generate a second physical address.

[0159] In some instances of the method 800 and device described herein, the second logical page size may be the same as the first logical page size, and determining the second physical address may include operations, features, components, or instructions for adding an offset to the first physical address to determine the second physical address.

[0160] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for: reading a third entry of a primary L2P table based on a logical address, wherein the third entry contains a third physical address pointing to a first L2P table; and adding a third offset to the third physical address to generate a fourth physical address pointing to a first entry of the first L2P table, wherein reading the first entry of the first L2P table includes reading the first entry of the first L2P table based on the fourth physical address.

[0161] In some instances of the method 800 and apparatus described herein, reading data from the beginning of data within a second logical page may include operations, features, components, or instructions for: reading a first portion of data from the second logical page and reading a second portion of data from a third logical page having the same logical page size as the second logical page.

[0162] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0163] Describe an apparatus. The apparatus may include a memory device and a controller for the memory device, the controller being configured to cause the apparatus to: receive a write command to write a first amount of data to the memory device, the write command being associated with a logical address; based on the logical address, read a first entry of a first L2P table, wherein the first L2P table is used to map a set of logical addresses to physical addresses of corresponding first group of logical pages in the memory device, each logical page having a first logical page size, and wherein the first entry of the first L2P table contains a first physical address of the first logical page in the first group of logical pages; identify a second logical page size based on the size of the first data amount; write at least a portion of the first data amount to a second logical page in the memory device having a second logical page size, the first logical page containing the second logical page, based on the first physical address; and based on the identified second logical page size, store a first entry of a second L2P table for mapping a second set of logical addresses to physical addresses of corresponding second group of logical pages in the memory device, each logical page in the second group of logical pages having a second logical page size, wherein the first entry of the second L2P table contains a second physical address of the second logical page.

[0164] In some instances, the controller may be further configured to cause the device to read a first entry of a primary L2P table that maps a set of logical addresses to a corresponding set of L2P tables containing a first L2P table, the first entry of the primary L2P table containing a third physical address pointing to the first L2P table, wherein reading the first entry of the first L2P table includes reading the first entry of the first L2P table based on the third physical address.

[0165] In some cases, the primary L2P table may be stored in a first type of memory, and the secondary L2P table may be stored in a second type of memory.

[0166] In some examples, the controller may be further configured to cause the device to store a first entry of the L2P pointer table based on the identification of a second logical page size. The first entry of the L2P pointer table contains a fourth physical address and the length of the second L2P table, wherein the fourth physical address points to the second L2P table.

[0167] In some instances, the controller may be further configured to cause the device to receive a second write command to write a second amount of data to a memory device, the second write command including a second logical address; based on the second logical address, read a second entry of a third L2P table for mapping a third set of logical addresses to physical addresses of corresponding third set of logical pages in the memory device, each logical page may have a first logical page size, the second entry of the third L2P table including a fifth physical address of a third logical page in the third set of logical pages; identify a third logical page size based on a second size of the second amount of data; and write at least a portion of the second amount of data to a fourth logical page of the memory device having a third logical page size, wherein the third logical page includes the fourth logical page.

[0168] In some cases, the third logical page size is different from the second logical page size, and the controller may be further configured to cause the device to store a second entry of the L2P pointer table based on the identification of the third logical page size. The second entry of the L2P pointer table includes a sixth physical address and the length of the fourth L2P table, wherein the sixth physical address points to the fourth L2P table associated with the fourth logical page.

[0169] In some instances, the third logical page size is the same as the second logical page size, and the controller may be further configured to cause the device to update the length of the second L2P table in the first entry of the L2P pointer table based on the fact that the third logical page size is the same as the second logical page size.

[0170] In some cases, the first L2P table and the third L2P table can be the same L2P table.

[0171] In some cases, the first L2P table and the third L2P table can be different L2P tables.

[0172] In some instances, the controller may be further configured to cause the device to determine that two or more logical pages having a second logical page size and pointed to by a second L2P table may have been deleted, and to update the length of the second L2P table in the L2P pointer table and the length of the first L2P table in the L2P pointer table based on the determination that the two or more logical pages may have been deleted.

[0173] In some cases, the controller may be further configured to cause the device to: receive a second write command to write a second amount of data to the memory device, the second write command containing a second logical address; based on the second logical address, read a second entry of a third L2P table for mapping a third set of logical addresses to physical addresses of corresponding third set of logical pages in the memory device, each logical page may have a first logical page size, the second entry of the third L2P table containing a fifth physical address of a third logical page in the third set of logical pages; identify that the second amount of data corresponds to the first logical page size; and write the second amount of data to the third logical page.

[0174] In some examples, the first logical page size is the largest logical page size among a set of supported logical page sizes associated with the memory device, which includes the second logical page size.

[0175] In some instances, the controller may be further configured to enable the device to select a second logical page size from the set of supported logical page sizes.

[0176] Describe an apparatus. The apparatus may include a memory device and a controller for the memory device, the controller being configured to cause the apparatus to: receive a read command associated with a logical address of the starting location of data stored in the memory device; read a first entry of a first L2P table based on the logical address, wherein the first entry contains a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing data, the first logical page containing the second logical page; determine, based on the value of the first portion of the first physical address, whether the second logical page size is different from the first logical page size; determine, based on the determination of whether the second logical page size is different from the first logical page size, a second physical address pointing to the starting location of data within the second logical page; read data from the starting location of the data within the second logical page based on the second physical address; and transfer the data to a host device of the memory device.

[0177] In some instances, the second logical page size may differ from the first logical page size, and the controller may be further configured to cause the device to: identify a value of a second portion of a first physical address, wherein the value of the second portion of the first physical address points to a first entry in an L2P pointer table; based on identifying the value of the second portion of the first physical address, read a first entry in the L2P pointer table, the first entry in the L2P pointer table containing a third physical address; add an offset to the third physical address to determine a fourth physical address associated with a second entry in a second L2P table, wherein the offset may be indicated by a third portion of the first physical address; and read a second entry in the second L2P table, wherein the second entry in the second L2P table contains at least a portion of the second physical address.

[0178] In some cases, the controller may be further configured to cause the device to make a second offset to a second entry in a second L2P table to generate a second physical address.

[0179] In some instances, the second logical page size may be the same as the first logical page size, and in order to determine the second physical address, the controller may be further configured to cause the device to add an offset to the first physical address to determine the second physical address.

[0180] In some cases, the controller may be further configured to cause the device to: read a third entry of a primary L2P table based on a logical address, wherein the third entry contains a third physical address pointing to a first L2P table, and add a third offset to the third physical address to generate a fourth physical address pointing to a first entry of the first L2P table, wherein in order to read the first entry of the first L2P table, the controller may be further configured to cause the device to read the first entry of the first L2P table based on the fourth physical address.

[0181] In some examples, the controller may be further configured to cause the device to read a first portion of data from a second logical page and a second portion of data from a third logical page having the same logical page size as the second logical page.

[0182] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0183] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0184] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0185] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0186] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0187] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0188] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0189] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0190] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0191] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0192] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0193] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0194] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Memory devices; as well as A controller for the memory device and configured to cause the memory device to: Receive a write command to write a first amount of data to the memory device, the write command being associated with a logical address; At least partially based on the logical address, a first entry of a first logical-to-physical table is read, wherein the first logical-to-physical table is used to map a plurality of logical addresses to physical addresses of corresponding first plurality of logical pages, each having a first logical page size, and wherein the first entry of the first logical-to-physical table includes the first physical address of the first logical page among the first plurality of logical pages. The size of the second logical page is identified, at least in part, based on the size of the first data volume; At least a portion of the first data amount is written to a second logical page of the memory device having the second logical page size, based at least partially on the first physical address; as well as At least in part based on identifying the second logical page size, a first entry of a second logical-to-physical table is stored for mapping a second plurality of logical addresses to the physical addresses of corresponding second plurality of logical pages of the memory device, each of the second plurality of logical pages having the second logical page size, wherein the first entry of the second logical-to-physical table includes the second physical address of the second logical page.

2. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: At least in part based on the logical address, a first entry of a primary logical-to-physical table used to map multiple logical addresses to corresponding multiple logical-to-physical tables including the first logical-to-physical table is read, the first entry of the primary logical-to-physical table including a third physical address pointing to the first logical-to-physical table, and The reading of the first entry from the first logical-to-physical table includes reading the first entry from the first logical-to-physical table based at least in part on the third physical address.

3. The memory device of claim 2, wherein the main logic-to-physical table is stored in a first type of memory, and the first logic-to-physical table is stored in a second type of memory.

4. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: Based at least in part on identifying the size of the second logical page, a first entry of a logical-to-physical pointer table is stored, the first entry of the logical-to-physical pointer table including a fourth physical address and the length of the second logical-to-physical table, wherein the fourth physical address points to the second logical-to-physical table.

5. The memory device of claim 4, wherein the controller is further configured to cause the memory device to: Receive a second write command to write a second amount of data to the memory device, the second write command including a second logical address; At least in part based on the second logical address, a second entry of a third logical-to-physical table for mapping a third plurality of logical addresses to physical addresses of corresponding third plurality of logical pages of the memory device is read, each logical page having the first logical page size, the second entry of the third logical-to-physical table including the fifth physical address of the third logical page among the third plurality of logical pages; The third logical page size is identified, at least in part, based on the second size of the second data volume; as well as At least a portion of the second data amount is written to a fourth logical page of the memory device having the size of the third logical page, wherein the third logical page includes the fourth logical page.

6. The memory device of claim 5, wherein the third logical page size is different from the second logical page size, and the controller is further configured to cause the memory device to: At least in part based on identifying the size of the third logical page, a second entry of the logical-to-physical pointer table is stored, the second entry of the logical-to-physical pointer table including a sixth physical address and the length of the fourth logical-to-physical table, wherein the sixth physical address points to the fourth logical-to-physical table associated with the fourth logical page.

7. The memory device of claim 5, wherein the third logical page size is the same as the second logical page size, and the controller is further configured to cause the memory device to: The length of the second logical-to-physical table in the first entry of the logical-to-physical pointer table is updated, at least in part, based on the fact that the third logical page size is the same as the second logical page size.

8. The memory device of claim 5, wherein the first logical-to-physical table and the third logical-to-physical table are the same logical-to-physical table.

9. The memory device of claim 5, wherein the first logical-to-physical table and the third logical-to-physical table are different logical-to-physical tables.

10. The memory device of claim 4, wherein the controller is further configured to cause the memory device to: It has been determined that two or more logical pages with the second logical page size and pointed to by the second logical-to-physical table have been deleted; and Based at least in part on the determination that the two or more logical pages have been deleted, update the length of the second logical-to-physical table in the logical-to-physical pointer table and the length of the first logical-to-physical table in the logical-to-physical pointer table.

11. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: Receive a second write command to write a second amount of data to the memory device, the second write command including a second logical address; At least in part based on the second logical address, a second entry of a third logical-to-physical table for mapping a third plurality of logical addresses to physical addresses of corresponding third plurality of logical pages of the memory device is read, each logical page having the first logical page size, the second entry of the third logical-to-physical table including the fifth physical address of the third logical page among the third plurality of logical pages; The second data volume is identified as corresponding to the first logical page size; as well as Write the second amount of data to the third logical page.

12. The memory device of claim 1, wherein the first logical page size is the largest logical page size among a plurality of supported logical page sizes associated with the memory device, the plurality of supported logical page sizes including the second logical page size.

13. The memory device of claim 12, wherein, in order to identify the second logical page size, the controller is configured to cause the memory device to: The second logical page size is selected from the plurality of supported logical page sizes.

14. A memory device comprising: Memory devices; as well as A controller for the memory device and configured to cause the memory device to: Receive a read command associated with a logical address of the starting location of data stored in the memory device; At least in part based on the logical address, a first entry of a first logical to physical table is read, wherein the first entry includes a first physical address of a first logical page of the memory device having a first logical page size, and wherein the value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing the data, the first logical page including the second logical page; Whether the second logical page size is different from the first logical page size is determined at least in part based on the value of the first portion of the first physical address; At least in part, based on determining that the second logical page size is the same as the first logical page size, a second physical address pointing to the starting location of the data within the second logical page is determined, wherein, in order to determine the second physical address, the controller is further configured to cause the memory device to: Add an offset to the first physical address to determine the second physical address; The data is read from the starting position of the data within the second logical page, at least in part based on the second physical address; as well as The host device that transmits the data to the memory device.

15. The memory device of claim 14, wherein the controller is further configured to cause the memory device to: At least in part based on the logical address, a third entry of the primary logical-to-physical table is read, wherein the third entry includes a third physical address pointing to the first logical-to-physical table; and A third offset is added to the third physical address to generate a fourth physical address pointing to the first entry of the first logical-to-physical table, wherein the controller is configured to cause the memory device to read the first entry of the first logical-to-physical table at least in part based on the fourth physical address.

16. The memory device of claim 14, wherein, in order to read the data starting from the beginning position of the data within the second logical page, the controller is further configured to cause the memory device to: Read the first portion of the data from the second logical page; and The second portion of the data is read from a third logical page having the same logical page size as the second logical page.

17. A memory device comprising: Memory devices; as well as A controller for the memory device and configured to cause the memory device to: Receive a read command associated with a logical address corresponding to the starting location of data stored in the memory device; At least in part based on the logical address, a first entry of a first logical to physical table is read, wherein the first entry includes a first physical address of a first logical page of the memory device having a first logical page size, and wherein the value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing the data, the first logical page including the second logical page; Whether the second logical page size is different from the first logical page size is determined at least in part based on the value of the first portion of the first physical address; At least in part, based on the determination that the size of the second logical page is different from the size of the first logical page, a second physical address pointing to the starting location of the data within the second logical page is determined, wherein, in order to determine the second physical address, the controller is configured to cause the memory device to: Identify the value of a second portion of the first physical address, wherein the value of the second portion of the first physical address points to a first entry in the logical-to-physical pointer table; The first entry of the logical-to-physical pointer table is read, at least in part, based on the value that identifies the second portion of the first physical address, the first entry of the logical-to-physical pointer table including the third physical address; An offset is added to the third physical address to determine a fourth physical address associated with a second entry in the second logical-to-physical table, wherein the offset is indicated by a third portion of the first physical address; and Read the second entry of the second logical-to-physical table, wherein the second entry of the second logical-to-physical table includes at least a portion of the second physical address; The data is read from the starting position of the data within the second logical page, at least in part based on the second physical address; as well as The host device that transmits the data to the memory device.

18. The memory device of claim 17, wherein the controller is further configured to cause the memory device to: Add a second offset to the second entry in the second logical-to-physical table to generate the second physical address.

19. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a write command to write a first amount of data to a memory device, the write command being associated with a logical address; At least partially based on the logical address, a first entry of a first logical-to-physical table is read, wherein the first logical-to-physical table is used to map a plurality of logical addresses to the physical addresses of corresponding first plurality of logical pages of the memory device, each logical page having a first logical page size, and wherein the first entry of the first logical-to-physical table includes the first physical address of the first logical page among the first plurality of logical pages; The size of the second logical page is identified, at least in part, based on the size of the first data volume; At least a portion of the first data amount is written to a second logical page of the memory device having the second logical page size, based at least partially on the first physical address; as well as At least in part based on identifying the second logical page size, a first entry of a second logical-to-physical table is stored for mapping a second plurality of logical addresses to the physical addresses of corresponding second plurality of logical pages of the memory device, each of the second plurality of logical pages having the second logical page size, wherein the first entry of the second logical-to-physical table includes the second physical address of the second logical page.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part based on the logical address, a first entry of a primary logical-to-physical table used to map multiple logical addresses to corresponding multiple logical-to-physical tables including the first logical-to-physical table is read, the first entry of the primary logical-to-physical table including a third physical address pointing to the first logical-to-physical table, and The reading of the first entry from the first logical-to-physical table includes reading the first entry from the first logical-to-physical table based at least in part on the third physical address.

21. The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the processor to: Based at least in part on identifying the size of the second logical page, a first entry of a logical-to-physical pointer table is stored, the first entry of the logical-to-physical pointer table including a fourth physical address and the length of the second logical-to-physical table, wherein the fourth physical address points to the second logical-to-physical table.

22. The non-transitory computer-readable medium of claim 21, wherein the instructions are further executable by the processor to: Receive a second write command to write a second amount of data to the memory device, the second write command including a second logical address; At least in part based on the second logical address, a second entry of a third logical-to-physical table for mapping a third plurality of logical addresses to physical addresses of corresponding third plurality of logical pages of the memory device is read, each logical page having the first logical page size, the second entry of the third logical-to-physical table including the fifth physical address of the third logical page among the third plurality of logical pages; The third logical page size is identified, at least in part, based on the second size of the second data volume; as well as At least a portion of the second data amount is written to a fourth logical page of the memory device having the size of the third logical page, wherein the third logical page includes the fourth logical page.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a read command associated with a logical address of the starting location of data stored in the memory device; At least in part based on the logical address, a first entry of a first logical to physical table is read, wherein the first entry includes a first physical address of a first logical page of the memory device having a first logical page size, and wherein the value of a first portion of the first physical address indicates a second logical page size of a second logical page of the memory containing the data, the first logical page including the second logical page; Whether the second logical page size is different from the first logical page size is determined at least in part based on the value of the first portion of the first physical address; At least in part, based on the determination that the second logical page size is the same as the first logical page size, a second physical address pointing to the starting location of the data within the second logical page is determined, wherein, in order to determine the second physical address, the instruction, when executed by the processor of the electronic device, further causes the electronic device to: Add an offset to the first physical address to determine the second physical address; The data is read from the starting position of the data within the second logical page, at least in part based on the second physical address; as well as The host device that transmits the data to the memory device.

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