Display driving circuit and operating method thereof

Abstract

A display driving circuit according to an example embodiment of the inventive concept and an operating method thereof are disclosed. The display driving circuit can include an interface configured to receive a synchronization data packet and image data from outside, a memory configured to receive the image data from the interface in a command mode, a synchronization controller configured to receive the synchronization data packet and generate a flag control signal and an internal synchronization signal, a flag generator configured to generate a first flag signal and a second flag signal, and an image controller configured to receive the image data from the memory in the command mode and from the interface in a video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization data packet, and configured to adjust a generation time of the second flag signal.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0170744, filed on December 8, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] At least one technical concept of the inventive idea relates to a display driving circuit, specifically, to a display driving circuit for driving a display panel to display an image on the display panel and a method for operating the display driving circuit. Background Technology

[0003] A display device includes a display panel for displaying images and a display driving circuit for driving the display panel. The display driving circuit drives the display panel by receiving image data from a processor and applying image signals corresponding to the received image data to data lines on the display panel. The display device can be implemented in various forms such as liquid crystal displays (LCDs), light-emitting diode displays (LEDs), organic LED displays (OLEDs), and active-matrix OLEDs (AMOLEDs).

[0004] The display device can be operated in various operating modes under the control of the host, and may require seamless switching of operating modes to switch between operating modes. Summary of the Invention

[0005] At least one problem that the inventive concept aims to solve is to provide a display driver circuit that operates in command mode and video mode, which are multiple operating modes.

[0006] A display driving circuit, operating in video mode and command mode according to an exemplary embodiment of the inventive concept, is provided for solving a technical problem. The display driving circuit may include: an interface configured to receive synchronization data packets and image data from an external source; a memory configured to receive image data from the interface in command mode; a synchronization controller configured to receive synchronization data packets from the interface and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal in response to the flag control signal; and an image controller configured to receive image data from the memory in command mode, receive image data from the interface in video mode, and drive a display panel based on the image data. The synchronization controller is configured to calculate a delay time between the generation time of the first flag signal and the reception time of the synchronization data packet, and is configured to adjust the generation time of the second flag signal based on the delay time.

[0007] A method is provided for a display driving circuit operating in video mode and command mode according to an example embodiment of the inventive concept to solve a technical problem. The method may include the steps of: receiving a command from a host to change from command mode to video mode; generating a first flag signal to transmit the generated first flag signal to the host; receiving a synchronization data packet according to the first flag signal; and adjusting the generation time of a second flag signal based on a delay time between the generation time of the first flag signal and the reception time of the synchronization data packet according to the first flag signal and switching the mode to video mode.

[0008] A method for operating a display driving circuit according to an example embodiment of the inventive concept is provided for solving a technical problem. The method may include the following steps: generating a first flag signal and transmitting the generated first flag signal to a host; receiving a synchronization data packet and image data according to the first flag signal; storing the image data in a memory based on a result of comparing a delay time between the generation time of the first flag signal and the reception time of the synchronization data packet according to the first flag signal with a reference time; and adjusting the generation time of a second flag signal by changing the reference time based on the delay time. Attached Figure Description

[0009] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a display system according to an example embodiment of the inventive concept;

[0011] Figure 2 This is a block diagram illustrating a partial structure of a display device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 and Figure 4 This is a flowchart illustrating a method of operating a display driving circuit according to an example embodiment of the inventive concept;

[0013] Figures 5 to 7 This is a timing diagram illustrating the operation of a display driving circuit according to an exemplary embodiment of the inventive concept;

[0014] Figures 8A to 8C This is a block diagram illustrating a synchronous controller for a display driving circuit according to an exemplary embodiment of the inventive concept;

[0015] Figure 9 This is a flowchart illustrating a method of operating a display driving circuit according to an example embodiment of the inventive concept;

[0016] Figure 10 and Figure 11This is a timing diagram illustrating the operation of a display driving circuit according to an exemplary embodiment of the inventive concept;

[0017] Figure 12 This is a diagram illustrating the internal vertical synchronization signal and internal horizontal synchronization signal generated by the display driving circuit according to an exemplary embodiment of the inventive concept;

[0018] Figure 13A This is a block diagram illustrating a partial structure of a display device according to an example embodiment of the inventive concept; and

[0019] Figure 13B This is a timing diagram illustrating the operation of a display driving circuit according to an example embodiment of the inventive concept. Detailed Implementation

[0020] In the following description, various exemplary embodiments of the inventive concept will be described in conjunction with the accompanying drawings.

[0021] Figure 1 This is a block diagram illustrating a display system according to an example embodiment of the inventive concept.

[0022] The display system 10 according to an example embodiment of the inventive concept can be mounted on or otherwise interfaced with an electronic device having image display capabilities. For example, the electronic device may include a smartphone, a tablet PC, a portable multimedia player (PMP), a camera, a wearable device, an Internet of Things (IoT) device, a television, a digital video disc (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, navigation devices, a Global Positioning System (GPS) receiver, an Advanced Driver Assistance System (ADAS), a vehicle device, furniture, or various measuring devices.

[0023] Reference Figure 1 The display system 10 may include a host 200, a display driving circuit 110 (or a display driving integrated circuit), and / or a display panel 120. In an example embodiment, the display driving circuit 110 and the display panel 120 may be implemented as a single module, which may be referred to as the display device 100. For example, the display driving circuit 110 may be mounted on a circuit film such as a tape-on-coat (TCP), chip-on-film (COF), or flexible printed circuit (FPC), and may be attached to the display panel 120 via tape-on-brush (TAB) or mounted on a non-display area of ​​the display panel 120 via chip-on-glass (COG) or chip-on-plastic (COP).

[0024] The host 200 can control the display system 10 as a whole. The host 200 can generate image data IDT to be displayed on the display panel 120, and can transmit the image data IDT, synchronization data packet SYNC_PAC, and command CMD (e.g., mode change command) to the display driver circuit 110. Figure 1 In this diagram, the image data IDT, the synchronization data packet SYNC_PAC, and the command CMD are shown as separate signals, but they can be transmitted to the display driver circuit 110 in a single data packet and can be separated from each other in the interface 111 of the display driver circuit 110.

[0025] Host 200 may be an application processor. However, the inventive concept is not limited thereto, and host 200 may be implemented as various types of processors such as central processing unit (CPU), microprocessor, multimedia processor, and graphics processor. In an example embodiment, host 200 may be implemented as an integrated circuit (IC), and may be implemented as a mobile application processor (AP) or system-on-a-chip (SoC).

[0026] The host 200 may include a display processor 210 and an interface 220. The display processor 210 can control the operation of the display device 100. The display processor 210 can transmit image data IDT to be displayed on the display device 100, a synchronization data packet SYNC_PAC for timing control, and a command CMD for changing the operating mode of the display device 100 to the display device 100 through the interface 220.

[0027] The display driving circuit 110 can display an image on the display panel 120 by converting the image data IDT received from the host 200 into an image signal for driving the display panel 120 and supplying the image signal to the display panel 120.

[0028] The display driver circuit 110 can operate in multiple operating modes. Operating modes may include a command mode that receives only image data IDT from the host 200, and a video mode that receives both image data IDT and a synchronization data packet SYNC_PAC for timing control from the host 200. For example, the display device 100 can display a still image in command mode and a moving image in video mode. The display driver circuit 110 can switch operating modes in response to a command CMD received from the host 200. To seamlessly switch operating modes from command mode to video mode, the display driver circuit 110 can operate in a switching mode between intervals of operation in command mode and intervals of operation in video mode. The operation of the display driver circuit 110 in the switching mode will be described in detail in the following figures.

[0029] The display driver circuit 110 may include an interface 111, a memory 112, a synchronization controller 113, a display controller 114 (image controller), a driver 115, and / or a flag generator 116. The display driver circuit 110 can receive image data IDT, synchronization data packets SYNC_PAC, and commands CMD from the host 200 via the interface 111. In an example embodiment, the interface 220 of the host 200 and the interface 111 of the display driver circuit 110 may be a Mobile Industry Processor Interface (MIPI).

[0030] The memory 112 can store image data IDT received via interface 111 in command mode and can also transmit the image data IDT to the display controller 114. In an example embodiment, the memory 112 may be graphics RAM (GRAM). On the other hand, in video mode, the image data IDT received via interface 111 is not stored in the memory 112 and can be transmitted to the display controller 114.

[0031] Synchronization controller 113 can receive synchronization data packets SYNC_PAC via interface 111. Synchronization controller 113 can receive synchronization data packets SYNC_PAC via interface 111 in video mode and generate internal synchronization signals VSYNC and HSYNC based on the synchronization data packets SYNC_PAC. Synchronization controller 113 can output an internal vertical synchronization signal VSYNC with the same period as the vertical synchronization data packets of synchronization data packet SYNC_PAC, and can also output an internal horizontal synchronization signal HSYNC with the same period as the horizontal synchronization data packets of synchronization data packet SYNC_PAC.

[0032] On the other hand, in command mode, the synchronization controller 113 can directly generate internal synchronization signals VSYNC and HSYNC without receiving the synchronization data packet SYNC_PAC. The internal synchronization signals VSYNC and HSYNC may include the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC.

[0033] Synchronization controller 113 can transmit the flag control signal FCS to flag generator 116. Synchronization controller 113 can generate the flag control signal FCS in a switching mode used to switch from command mode to video mode so that the synchronization data packet SYNC_PAC is synchronized with the internal synchronization signals VSYNC and HSYNC.

[0034] Display controller 114 can generate control signals for controlling driver 115 by receiving image data IDT and internal synchronization signals VSYNC and HSYNC. Driver 115 can supply voltage to the gate lines and data lines of display panel 120 in response to the control signals. (See below for further details.) Figure 2 The operation of the display controller 114 and driver 115 is described in detail.

[0035] Flag generator 116 can generate flag signal TE (or tear effect control signal) in response to flag control signal FCS, and can transmit flag signal TE to host 200. For example, the rising edge of flag signal TE can be regarded as the generation time of flag signal TE. In this application, depending on the context, the term "time" can refer to a point in time or a period of time.

[0036] The host 200 can receive the flag signal TE and control the generation or transmission time of the synchronization data packet SYNC_PAC based on the flag signal TE. Therefore, the generation time of the internal synchronization signals VSYNC and HSYNC (i.e., the start time of each cycle of the internal synchronization signals VSYNC and HSYNC used for synchronization) can vary according to the flag signal TE. For example, the generation time of the internal vertical synchronization signal VSYNC can be determined based on the generation time of the flag signal TE.

[0037] The generation time of the flag signal TE can be controlled based on a preset reference time TR. For example, the reference time TR can be preset by the host 200. The time from the generation time of the flag signal TE to the predicted time when the display driver circuit 110 will receive the synchronization data packet SYNC_PAC can be set as the reference time TR. Therefore, the display driver circuit 110 can be configured such that the flag signal TE is generated by the reference time TR before the generation time of the internal synchronization signals VSYNC and HSYNC.

[0038] In an example embodiment, during a switching mode for transitioning from command mode to video mode, the synchronization controller 113 can adjust the reference time TR based on the generation time of the first flag signal, the reception time of the synchronization data packet SYNC_PAC, and the generation times of the internal synchronization signals VSYNC and HSYNC. For example, the synchronization controller 113 can calculate the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet SYNC_PAC, and can change the reference time TR based on the result of comparing the delay time with the reference time TR. The synchronization controller 113 can adjust the generation time of the second flag signal to be transmitted after the first flag signal by adjusting the reference time TR, and can generate a flag control signal FCS based on the adjusted generation time of the second flag signal. The display driver circuit 110 can synchronize the synchronization data packet SYNC_PAC with the internal synchronization signals VSYNC and HSYNC by generating the flag control signal FCS for adjusting the generation time of the flag signal TE, and can perform a seamless transition from command mode to video mode.

[0039] Display panel 120 is a display unit on which an image is actually displayed, and can be one of the following: thin-film transistor liquid crystal display (TFT-LCD), organic light-emitting diode display (OLED), field emission display, plasma display panel (PDP), etc., which are display devices that display two-dimensional images by receiving image signals transmitted electrically. Display panel 120 can also be implemented as another type of flat panel display or flexible display panel.

[0040] Figure 2 This is a block diagram illustrating a partial structure of a display device according to an example embodiment of the inventive concept, and it can be used with... Figure 1 The display controller 114, driver 115 and display panel 120 correspond to each other.

[0041] Reference Figure 1 and Figure 2 The driver 115 may include a scan driver 115_1 and a data driver 115_2. However, the display driver circuit 110 may not include the scan driver 115_1, which may be included in the display device 100 in a separate configuration from the display driver circuit 110.

[0042] The display panel 120 includes a plurality of pixels PX arranged in a matrix and can display an image for each frame. The display panel 120 may include scan lines SL1 to SLn arranged in the row direction, data lines DL1 to DLm arranged in the column direction, and pixels PX formed at the intersections of scan lines SL1 to SLn and data lines DL1 to DLm.

[0043] Scan driver 115_1 can sequentially select scan lines SL1 to SLn by sequentially supplying scan on signals to scan lines SL1 to SLn in response to scan control signal CTRL1 provided from display controller 114. Based on the scan on signals output from scan driver 115_1, scan lines SL1 to SLn are sequentially selected, and grayscale voltages corresponding to pixels PX are applied to pixels PX connected to the selected scan lines via data lines DL1 to DLm, enabling display operation. During periods when scan on signals are not supplied to scan lines SL1 to SLn, scan off signals (e.g., scan voltages with a logic high level) can be supplied to scan lines SL1 to SLn.

[0044] In response to the data control signal CTRL2, the data driver 115_2 converts the data DATA corresponding to the image data IDT into an image signal as an analog signal and provides the image signal to the data lines DL1 to DLm. The data driver 115_2 may include a plurality of channel amplifiers, each of which can provide the image signal to at least one data line corresponding to each of the amplifiers.

[0045] The display controller 114 can control the overall operation of the display panel 120. The display controller 114 can be implemented in hardware, software, or a combination of hardware and software. For example, the display controller 114 can be implemented as digital logic circuits and registers that perform various functions.

[0046] The display controller 114 can receive image data IDT, internal horizontal sync signal HSYNC, and internal vertical sync signal VSYNC, and can generate control signals (e.g., scan control signal CTRL1 and data control signal CTRL2) for controlling the data driver 115_2 and the scan driver 115_1 based on the received signals. Additionally, the display controller 114 can convert the format of the image data IDT received from the external display driver circuit 110 to conform to the interface specification with the data driver 115_2, and can transmit the converted data DATA to the data driver 115_2.

[0047] Figure 3 and Figure 4 This is a flowchart illustrating a method for operating a display driving circuit according to an example embodiment of the inventive concept. Figure 3 This is a flowchart illustrating the operation of the display driver circuit in preparing to switch from command mode to video mode. Figure 4 yes Figure 3 An example of operation S50, which may include operations S51 to S57.

[0048] Reference Figure 1 and Figure 3 In operation S10, the display driver circuit 110 can receive a command CMD for changing from command mode to video mode. In response to the command CMD, the display driver circuit 110 can operate in the switching mode.

[0049] In operation S20, the display driver circuit 110 can generate a first flag signal and transmit the first flag signal to the host 200. When the host 200 receives the first flag signal, the host 200 can transmit a synchronization data packet SYNC_PAC to the display driver circuit 110. In operation S30, the display driver circuit 110 can receive the synchronization data packet SYNC_PAC from the host 200.

[0050] In operation S40, the display driver circuit 110 can calculate the delay time between the generation time (or transmission time) of the first flag signal and the reception time of the synchronization data packet SYNC_PAC. For example, the display driver circuit 110 can calculate the time difference between the reception time of the synchronization data packet SYNC_PAC and the generation time of the internal vertical synchronization signal VSYNC, and can calculate the delay time by calculating the difference between the reference time TR and the time difference.

[0051] In operation S50, the display driver circuit 110 can adjust the generation time (or transmission time) of the second flag signal transmitted after the first flag signal based on the delay time, and switch the mode to video mode. For example, when the delay time is consistent with the reference time TR, it can be seen that the vertical synchronization data packet included in the synchronization data packet SYNC_PAC transmitted from the host 200 and the internal vertical synchronization signal VSYNC are synchronized with each other. Therefore, the display driver circuit 110 can generate the second flag signal based on the reference time TR, and the mode can be seamlessly switched from command mode to video mode.

[0052] Reference Figure 1 and Figure 4 In operation S51, the display driver circuit 110 can determine whether the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet is consistent with the reference time TR. In this specification, the term "consistent" can mean that the difference between two values ​​is within a set error range, and the error range corresponding to the consistent reference can be preset in the control logic of the display driver circuit 110.

[0053] When the delay between the generation time of the first flag signal and the reception time of the synchronization data packet matches the reference time TR, the display driver circuit 110 can switch the mode to video mode in operation S53. After the first flag signal, a second flag signal can be generated based on the reference time TR.

[0054] When the mode is switched to video mode, the display driver circuit 110 can generate internal synchronization signals VSYNC and HSYNC based on the synchronization data packet SYNC_PAC corresponding to the first flag signal. The image data IDT received after transmitting the first flag signal can be transmitted to the display controller 114 instead of being stored in the memory 112.

[0055] When the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet differs from the reference time TR, the display drive circuit 110 can store the image data IDT in the memory 112 during operation S55. In this specification, the term "different" may mean that the difference between two values ​​is outside a set error range.

[0056] In operation S57, the display driving circuit 110 can adjust the generation time of the second flag signal based on the reference time TR, and can switch the mode to video mode. The flag signal TE may include the first flag signal and the second flag signal generated after the first flag signal.

[0057] For example, in operation S57, the display driver circuit 110 can change the reference time TR to match the delay time, and adjust the generation time of the second flag signal according to the changed reference time TR. The display driver circuit 110 can generate internal synchronization signals VSYNC and HSYNC in video mode based on the synchronization data packet SYNC_PAC corresponding to the second flag signal. The image data IDT received after transmitting the second flag signal can be transmitted to the display controller 114 instead of being stored in the memory 112.

[0058] Figures 5 to 7 This is a timing diagram illustrating the operation of a display driving circuit according to an example embodiment of the inventive concept. Figures 5 to 7 This is a timing diagram used to explain the operation of the display driver circuit in preparing to switch from command mode to video mode. Figure 6 and Figure 7 The description will omit previous references. Figure 5 The given description.

[0059] Reference Figure 1 and Figure 5 The display driver circuit 110 can receive data packets PAC from the host 200. The data packets PAC may include commands CMD, image data IDT1 and IDT2, vertical synchronization data packets VS, and horizontal synchronization data packets HS. In some example embodiments, the data packets PAC may be a set of bits.

[0060] The first image data IDT1 received in command mode can be stored in memory 112. The image can be displayed on display panel 120 based on the first data DATA1 corresponding to the first image data IDT1, with a time difference from the time the first image data IDT1 is received.

[0061] When a command CMD for mode switching is received in command mode, the display driving circuit 110 can operate in switching mode from time T0. The flag signal TE transmitted in command mode is masked, and the image can be displayed on the display panel 120 according to the first data DATA1 until new image data is received.

[0062] The display driver circuit 110 can transmit the first flag signal TE1 to the host 200 based on a reference time TR. The host 200 can transmit the vertical synchronization data packet VS upon receiving the first flag signal TE1. In some example embodiments, the first reception time TP1 of the vertical synchronization data packet VS based on the first flag signal TE1 can be a delay time TD from the first generation time TT1 of the first flag signal TE1. The first generation time TT1 of the first flag signal TE1 can correspond to the rising edge of the first flag signal TE1.

[0063] The reference time TR can be a reference time used to determine a first generation time TT1 before generating the first flag signal TE1 before generating the internal vertical synchronization signal VSYNC. Based on the preset reference time TR, the display driver circuit 110 can generate the first flag signal TE1, and then generate the internal vertical synchronization signal VSYNC after the reference time TR has elapsed.

[0064] Including Figure 5 The generation time TV1 of the internal vertical synchronization signal VSYNC shown and described in the following timing diagram can refer to the start time of one cycle of the internal vertical synchronization signal VSYNC. A frame can begin at the start time of one cycle of the internal vertical synchronization signal VSYNC, and the interval from the start time of one cycle of the internal vertical synchronization signal VSYNC to the start time of the next cycle can refer to a frame.

[0065] Figure 5 An example is shown where the delay time TD is consistent with the preset reference time TR. (Refer to...) Figure 5 Since the delay time TD is consistent with the preset reference time TR, the first reception time TP1 of the vertical synchronization data packet VS received after the display driver circuit 110 transmits the first flag signal TE1 can be consistent with the generation time TV1 of the internal vertical synchronization signal VSYNC. Therefore, the display driver circuit 110 can switch to video mode after transmitting the first flag signal TE1, and the second image data IDT2 received after transmitting the first flag signal TE1 is not stored in the memory 112, but can be directly converted into the second data DATA2.

[0066] The display driver circuit 110 can generate a second flag signal TE2 based on a reference time TR in video mode and transmit the second flag signal TE2 to the host 200. The host 200 can receive the second flag signal TE2 and transmit the vertical synchronization data packet VS.

[0067] Reference Figure 1 and Figure 6The display driver circuit 110 can receive data packets PAC from the host 200. The data packets PAC may include commands CMD, image data IDT1, IDT2' and IDT3, vertical synchronization data packets VS and horizontal synchronization data packets HS.

[0068] The display driver circuit 110 can transmit the first flag signal TE1' to the host 200 in switching mode. The host 200 receives the first flag signal TE1' and transmits the vertical synchronization data packet VS. In some example embodiments, the first reception time TP1' of the vertical synchronization data packet VS based on the first flag signal TE1' can be a delay time TD' from the first generation time TT1' of the first flag signal TE1'.

[0069] Reference Figure 6 An example is described where the delay time TD' differs from a preset first reference time TR1. In detail, an example is described where the delay time TD' is shorter than the first reference time TR1. The display driver circuit 110 can calculate the delay time TD' by calculating the difference between the first reference time TR1 and the difference time TC'. In some example embodiments, the difference time TC' can be the time between the first reception time TP1' of the vertical synchronization data packet VS based on the first flag signal TE1' and the generation time TV1' of the internal vertical synchronization signal VSYNC.

[0070] Because the first reception time TP1' of the vertical synchronization data packet VS based on the first flag signal TE1' is inconsistent with the generation time TV1' of the internal vertical synchronization signal VSYNC, the display driving circuit 110 can continue to operate in the switching mode without switching to the video mode. The second image data IDT2' received after transmitting the first flag signal TE1' can be stored in the memory 112 and then converted into the second data DATA2' after a predetermined time, or optionally, after a desired time.

[0071] The display driver circuit 110 can reset the second reference time TR2 to match the delay time TD'. For example, the second reference time TR2 can be calculated by subtracting the difference time TC' from the first reference time TR1.

[0072] The display driving circuit 110 can adjust the second generation time TT2 of the second flag signal TE2' based on the second reference time TR2. The display driving circuit 110 can transmit the second flag signal TE2' to the host 200 at the adjusted second generation time TT2, and the host 200 can transmit the vertical synchronization data packet VS upon receiving the second flag signal TE2'. In some example embodiments, the second reception time TP2 of the vertical synchronization data packet VS based on the second flag signal TE2' can be delayed by a delay time TD' from the second generation time TT2 of the second flag signal TE2'.

[0073] Since the delay time TD' is consistent with the second reference time TR2, the second reception time TP2 of the vertical synchronization data packet VS received after the display driver circuit 110 transmits the second flag signal TE2' can be consistent with the generation time TV2 of the internal vertical synchronization signal VSYNC. Therefore, the display driver circuit 110 can switch to video mode after transmitting the second flag signal TE2', and the third image data IDT3 received after transmitting the second flag signal TE2' is not stored in the memory 112, but can be directly converted into third data DATA3.

[0074] However, with Figure 6 Unlike other systems, when the delay time TD' of the vertical synchronization data packet VS based on the second flag signal TE2' differs from the second reference time TR2, the display driver circuit 110 may not operate in video mode. To generate the third flag signal for the next frame, the third reference time can be readjusted based on the delay time TD'.

[0075] Reference Figure 1 and Figure 7 The display driver circuit 110 can receive data packets PAC from the host 200. The data packets PAC may include commands CMD, image data IDT1, IDT2” and IDT3”, vertical synchronization data packets VS and horizontal synchronization data packets HS.

[0076] The display driver circuit 110 can transmit the first flag signal TE1” to the host 200 in switching mode, and the host 200 can transmit the vertical synchronization data packet VS when it receives the first flag signal TE1”. In some example embodiments, the first reception time TP1” of the vertical synchronization data packet VS based on the first flag signal TE1” can be delayed by a delay time TD” from the first generation time TT1” of the first flag signal TE1”.

[0077] Reference Figure 7The example described is where the delay time TD” differs from a preset first reference time TR1”, specifically, the delay time TD” is greater than the first reference time TR1”. The display driving circuit 110 can calculate the delay time TD” by adding the difference time TC” to the first reference time TR1”. In some example embodiments, the difference time TC” can be the time between the first reception time TP1” of the vertical synchronization data packet VS based on the first flag signal TE1” and the time TVE after the first reference time TR1” has elapsed since the generation of the first flag signal TE1”.

[0078] Because the first reception time TP1” of the vertical synchronization data packet VS based on the first flag signal TE1” is inconsistent with the generation time TV1” of the internal vertical synchronization signal VSYNC, the display driving circuit 110 can continue to operate in the switching mode without switching to the video mode. The second image data IDT2” received after the transmission of the first flag signal TE1” can be stored in the memory 112 and then converted into the second data DATA2 after a predetermined time, or optionally, after a desired time.

[0079] The display driver circuit 110 can be configured to generate an internal vertical synchronization signal VSYNC after generating a first flag signal TE1” and then after a first reference time TR1”. When the delay time TD” is longer than the first reference time TR1”, that is, when no vertical synchronization data packet VS is received even after the first reference time TR1” has elapsed after the generation of the first flag signal TE1”, the display driver circuit 110 can increase the corresponding frame extension time ET. By generating the internal vertical synchronization signal VSYNC after an extension time ET from the time TVE after the generation of the first reference time TR1” following the generation of the first flag signal TE1”, the interval of frames in which the image based on the first data DATA1 is displayed on the display panel 120 can be increased. That is, the display driver circuit 110 can delay the generation time TV1” of the internal vertical synchronization signal VSYNC corresponding to the first flag signal TE1” to be later than the time TVE after the generation of the first reference time TR1” following the generation of the first flag signal TE1”. In an example embodiment, the display driver circuit 110 can increase the interval of frames in units of brightness adjustment; for example, the extension time ET can be a multiple of the brightness adjustment unit.

[0080] The display driver circuit 110 can reset the second reference time TR2” to match the delay time TD”. For example, the second reference time TR2” can be calculated by adding the difference time TC” to the first reference time TR1”.

[0081] The display driver circuit 110 can adjust the second generation time TT2 of the second flag signal TE2" based on the second reference time TR2". The display driver circuit 110 can transmit the second flag signal TE2" to the host 200 at the adjusted second generation time TT2". The host 200 can receive the second flag signal TE2" and transmit the vertical synchronization data packet VS. In some example embodiments, the second reception time TP2" of the vertical synchronization data packet VS based on the second flag signal TE2" can be delayed by a delay time TD from the second generation time TT2".

[0082] Since the delay time TD" is consistent with the second reference time TR2", the second reception time TP2" of the vertical synchronization data packet VS received after the display driver circuit 110 transmits the second flag signal TE2" can be consistent with the generation time TV2" of the internal vertical synchronization signal VSYNC. Therefore, the display driver circuit 110 can switch to video mode after transmitting the second flag signal TE2". The third image data IDT3" received after transmitting the second flag signal TE2" is not stored in the memory 112, but can be directly converted into the third data DATA3".

[0083] However, with Figure 7 Unlike other systems, when the delay time TD” of the vertical synchronization data packet VS based on the second flag signal TE2” differs from the second reference time TR2”, the display driver circuit 110 may not operate in video mode. In order to generate the third flag signal for the next frame, the third reference time may be readjusted based on the delay time TD”.

[0084] Figures 8A to 8C This is a block diagram illustrating a synchronous controller for a display driving circuit according to an example embodiment of the inventive concept. Figure 8A It can be a diagram used to explain the operation of the synchronization controller in command mode. Figure 8B It can be a diagram used to explain the operation of the synchronization controller in switching modes. Figure 8C This could be a diagram used to explain the operation of the synchronization controller in video mode. Optionally, Figure 8B This can be used to explain the synchronous controller in referring to Figure 10 and Figure 11 A diagram describing the operation of the video storage mode in the video mode description. Figure 8C This can be used to explain the synchronous controller in referring to Figure 10 and Figure 11 A diagram illustrating the operation of the normal video mode.

[0085] Reference Figure 1 and Figure 8AThe synchronization controller 113 may include a synchronization packet detector 113_1, a synchronization signal generator 113_2, a delay calculator 113_3, and / or an internal synchronization controller 113_4. Each of the synchronization packet detector 113_1, the synchronization signal generator 113_2, the delay calculator 113_3, and the internal synchronization controller 113_4 may be implemented in hardware or software.

[0086] In command mode, the internal synchronization controller 113_4 can control the synchronization signal generator 113_2. Under the control of the internal synchronization controller 113_4, the synchronization signal generator 113_2 can generate the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC. Under the control of the internal synchronization controller 113_4, the synchronization signal generator 113_2 can adjust the generation and output times of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC. That is, in command mode, the synchronization controller 113 can directly determine the timing and generation period of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC.

[0087] Reference Figure 1 and Figure 8B In switching mode, the synchronization packet detector 113_1 can detect the synchronization packet SYNC_PAC and transmit the detected synchronization packet SYNC_PAC to the delay calculator 113_3. The delay calculator 113_3 can calculate the delay time TD.

[0088] The delay calculator 113_3 can obtain the time difference between the reception time of the vertical synchronization data packet SYNC_PAC and the generation time of the internal vertical synchronization signal VSYNC, and can use the time difference and the reference time TR to calculate the delay time TD. Therefore, a new reference time can be set, and based on the newly changed reference time, the delay calculator 113_3 can transmit the flag control signal FCS to the flag generator 116.

[0089] In switching mode, the synchronization controller 113 can directly determine the timing and generation period of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC.

[0090] Reference Figure 1 and Figure 8CWhen the reference time matches the calculated delay time, the display driver circuit 110 can operate in video mode. In video mode, the synchronization packet detector 113_1 can detect the synchronization packet SYNC_PAC and transmit the detected synchronization packet SYNC_PAC to the synchronization signal generator 113_2. The synchronization signal generator 113_2 can generate an internal vertical synchronization signal VSYNC and an internal horizontal synchronization signal HSYNC based on the vertical synchronization packets and horizontal synchronization packets included in the synchronization packet SYNC_PAC. For example, the synchronization signal generator 113_2 can generate the internal vertical synchronization signal VSYNC based on the vertical synchronization packets included in the synchronization packet SYNC_PAC, and generate the internal horizontal synchronization signal HSYNC based on the horizontal synchronization packets included in the synchronization packet SYNC_PAC.

[0091] That is, in video mode, the synchronization controller 113 does not directly determine the timing and generation period of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC, but can determine the timing and generation period based on the received synchronization data packet SYNC_PAC.

[0092] Figure 9 This is a flowchart illustrating a method for operating a display driving circuit according to an example embodiment of the inventive concept. Figure 9 This is a flowchart illustrating the operation of the display driving circuit in video mode. Specifically, the display driving circuit can perform operations S100 to S700 in video mode, which may include normal video mode and video memory mode.

[0093] Reference Figure 1 and Figure 9 In operation S100, the display driver circuit 110 can calculate the delay time between the generation time of the flag signal TE and the reception time of the synchronization data packet SYNC_PAC in video mode. For example, the display driver circuit 110 can obtain the time difference between the reception time of the synchronization data packet SYNC_PAC and the generation time of the internal vertical synchronization signal VSYNC, and can calculate the delay time using the reference time TR and the time difference. In the following operations, the image data IDT can be stored in memory based on the result of comparing the delay time with the reference time TR, and the generation time of the second flag signal can be adjusted by changing the reference time TR based on the delay time.

[0094] In operation S200, the display driver circuit 110 can determine whether the delay time matches the reference time TR. When the delay time matches the reference time TR, the display driver circuit 110 can operate in normal video mode in operation S300. Figure 8CAs described, in normal video mode, the synchronization controller 113 does not directly determine the timing and generation period of the internal vertical synchronization signal VSYNC and the internal horizontal synchronization signal HSYNC, but can determine the timing and generation period based on the received synchronization data packet SYNC_PAC. In normal video mode, the image data IDT received from the host 200 may not be stored in memory 112 and can be provided to the display controller 114 via interface 111. Even after operation S300 in normal video mode, operations S100 to S700 can be executed again.

[0095] In operation S400, the display driver circuit 110 can determine whether the delay time is less than the reference time TR. When the delay time is less than the reference time TR, the display driver circuit 110 can execute operations S600 and S700. When the delay time is greater than the reference time TR, the display driver circuit 110 can execute operations S500 to S700. At least some of operations S500 to S700 can be executed in parallel with each other.

[0096] In operation S500, the display driver circuit 110 can increase the interval of the corresponding frame at the time of receiving the synchronization data packet SYNC_PAC. When the synchronization data packet SYNC_PAC is received after the expected time (the time elapsed from the generation time of the flag signal TE to the reference time TR), it becomes difficult to generate the internal synchronization signals VSYNC and HSYNC based on the synchronization data packet SYNC_PAC. Therefore, the display driver circuit 110 can increase the interval of the corresponding frame without generating the internal vertical synchronization signal VSYNC to start a new frame. In some example embodiments, the display driver circuit 110 can increase the interval of the frame in brightness adjustment units, and the increased interval of the frame can be adjusted according to the delay time. For example, as the delay time increases, the increased frame period can increase. Because the display driver circuit 110 according to the inventive concept adjusts the length of the frame interval in brightness adjustment units, changes in the brightness of the image displayed on the display panel 120 can be reduced or prevented regardless of the increase in the frame interval.

[0097] In operation S600, the display driver circuit 110 can store the image data IDT received from the host 200 in the memory 112. When the display driver circuit 110 receives the synchronization data packet SYNC_PAC from the host 200 at a time different from the expected time (e.g., the time elapsed from the generation time of the flag signal TE to the reference time TR), the display driver circuit 110 can operate in memory video mode even when executing video mode by temporarily storing the image data IDT in the memory 112. The display driver circuit 110 can temporarily store the image data IDT in the memory 112 and then provide a signal to the display panel 120, causing an image to be displayed on the display panel 120 based on the image data IDT.

[0098] In operation S700, the display driving circuit 110 can adjust the generation time of the next flag signal TE, which will be transmitted after the flag signal TE, by changing the reference time TR based on the delay time. For example, the display driving circuit 110 can change the reference time TR to match the delay time and adjust the generation time of the next flag signal TE accordingly. After performing operation S700, operation S100 can be performed again to operation S700.

[0099] Even when operating in video mode, the display driver circuit 110 according to the inventive concept can operate in normal video mode or video memory mode based on the reception time of the synchronization data packet SYNC_PAC received from the outside. When the reception time of the synchronization data packet SYNC_PAC received from the outside differs from the expected time, the image data IDT can be temporarily stored in memory 112, allowing the display driver circuit 110 to operate similarly to that in command mode. In video memory mode, by changing the generation time of the next flag signal TE and the reference time TR, the display driver circuit 110 can adjust the synchronization data packet SYNC_PAC to be received from the host 200 at the expected time in the next frame. Therefore, when displaying different images on the display panel 120 in video mode, the display driver circuit 110 can achieve smooth image transitions.

[0100] Figure 10 and Figure 11 This is a timing diagram illustrating the operation of a display driving circuit according to an example embodiment of the inventive concept. Figure 10 and Figure 11 This is a timing diagram used to explain the operation of the display driver circuit in video mode. Figure 11 The description will omit previous references. Figure 5 The given description.

[0101] Reference Figure 1 and Figure 10The display driver circuit 110 can receive data packets PAC from the host 200 and can transmit flag signals TE to the host 200. The data packet PAC may include commands CMD, image data IDT1A, IDT2A, and IDT3A, a vertical synchronization data packet VS, and a horizontal synchronization data packet HS. For the display driver circuit 110, the first image data IDT1A, the second image data IDT2A, and the third image data IDT3A can be received sequentially from the host 200.

[0102] When the delay time matches the preset reference time, the display driving circuit 110 can operate in normal video mode. Therefore, the first image data IDT1A received from the host 200 is not stored in the memory 112, but is directly converted into first data DATA1A, and the image based on the first data DATA1A can be displayed on the display panel 120.

[0103] The display driver circuit 110 can transmit a first flag signal TE1A to the host 200 based on a first reference time TRV1. The host 200 can receive the first flag signal TE1A and transmit a vertical synchronization data packet VS. In some example embodiments, the first reception time TPV1 of the vertical synchronization data packet VS based on the first flag signal TE1A can be delayed by a first delay time TDV1 from the first generation time TTV1 of the first flag signal TE1A.

[0104] According to the preset first reference time TRV1, the display driving circuit 110 can generate a first flag signal TE1A, and then generate an internal vertical synchronization signal VSYNC after the first reference time TRV1 has elapsed.

[0105] exist Figure 10 The text describes an example where the first delay time TDV1 is shorter than a preset first reference time TRV1. The display driving circuit 110 can calculate the first delay time TDV1 by calculating the difference between the first reference time TRV1 and the difference time TCV. In some example embodiments, the difference time TCV can be the time between the first reception time TPV1 of the vertical synchronization data packet VS based on the first flag signal TE1A and the generation time TVV1 of the internal vertical synchronization signal VSYNC.

[0106] Because the first reception time TPV1 of the vertical synchronization data packet VS based on the first flag signal TE1A is inconsistent with the generation time TVV1 of the internal vertical synchronization signal VSYNC, the display driving circuit 110 can operate in video memory mode. The second image data IDT2A received after transmitting the first flag signal TE1A can be stored in memory 112 and then converted into second data DATA2A after a predetermined time, or optionally, after a desired time.

[0107] The display driving circuit 110 can reset the second reference time TRV2 based on the first delay time TDV1. For example, the second reference time TRV2 can be set to be consistent with the first delay time TDV1, and can be calculated by subtracting the difference time TCV from the first reference time TRV1.

[0108] The display driving circuit 110 can adjust the second generation time TTV2 of the second flag signal TE2A based on the second reference time TRV2. The display driving circuit 110 can transmit the second flag signal TE2A to the host 200 at the adjusted second generation time TTV2, and the host 200 can transmit the vertical synchronization data packet VS upon receiving the second flag signal TE2A. In some example embodiments, the second reception time TPV2 of the vertical synchronization data packet VS based on the second flag signal TE2A can be delayed by a second delay time TDV2 from the second generation time TTV2 of the second flag signal TE2A.

[0109] The second delay time TDV2 can be consistent with the second reference time TRV2. Since the second delay time TDV2 is consistent with the second reference time TRV2, the second reception time TPV2 of the vertical synchronization data packet VS received after the display driver circuit 110 transmits the second flag signal TE2A can be consistent with the generation time TVV2 of the internal vertical synchronization signal VSYNC. Therefore, the display driver circuit 110 can operate in normal video mode after transmitting the second flag signal TE2A, and the third image data IDT3A received after transmitting the second flag signal TE2A is not stored in the memory 112 and can be directly converted into third data DATA3A. However, with... Figure 10 Unlike other modes, when the second delay time TDV2 is different from the second reference time TRV2, the display driving circuit 110 can operate in video memory mode, and the third image data IDT3A can be temporarily stored in memory 112.

[0110] Reference Figure 1 and Figure 11 The display driver circuit 110 can receive data packets PAC from the host 200 and can transmit flag signals TE to the host 200. The data packet PAC may include command CMD, image data IDT1B, IDT2B, and IDT3B, vertical synchronization data packet VS, and horizontal synchronization data packet HS. For the display driver circuit 110, the first image data IDT1B, the second image data IDT2B, and the third image data IDT3B can be received sequentially from the host 200.

[0111] When the delay time matches the preset reference time, the display driving circuit 110 can operate in normal video mode. Therefore, the first image data IDT1B received from the host 200 is not stored in the memory 112, but is directly converted into first data DATA1B, and the image based on the first data DATA1B can be displayed on the display panel 120.

[0112] The display driver circuit 110 can transmit a first flag signal TE1B to the host 200 based on a first reference time TRV1B. The host 200 can receive the first flag signal TE1B and then transmit the vertical synchronization data packet VS. In some example embodiments, the first reception time TPV1B of the vertical synchronization data packet VS based on the first flag signal TE1B can be delayed by a first delay time TDV1B from the first generation time TTV1B of the first flag signal TE1B.

[0113] The display driver circuit 110 can be configured to generate an internal vertical synchronization signal VSYNC after the first flag signal TE1B is generated and a first reference time TRV1B has elapsed. However, because the display driver circuit 110 uses the vertical synchronization data packet VS received from the host 200 to generate the internal vertical synchronization signal VSYNC in video mode, it becomes difficult to use the vertical synchronization data packet VS to generate the internal vertical synchronization signal VSYNC when the first delay time TDV1B is longer than the first reference time TRV1B. Therefore, when the vertical synchronization data packet VS is not received even after the first reference time TRV1B has elapsed after the first flag signal TE1B is generated, the display driver circuit 110 can increase the frame extension time ETB. That is, by generating the internal vertical synchronization signal VSYNC after an extended time ETB from the time TVEB after the first reference time TRV1B has elapsed following the generation of the first flag signal TE1B, the display driving circuit 110 can increase the interval of frames in which the image based on the first data DATA1B is displayed on the display panel 120, and can delay the generation time TVV1B of the internal vertical synchronization signal VSYNC corresponding to the first flag signal TE1B to be later than the time TVEB after the first reference time TRV1B has elapsed following the generation of the first flag signal TE1B.

[0114] exist Figure 11The text describes an example where the first delay time TDV1B is longer than a preset first reference time TRV1B. The display driving circuit 110 can calculate the first delay time TDV1B by adding the first reference time TRV1B to the difference time TCVB. In some example embodiments, the difference time TCVB can be the time between the first reception time TPV1B of the vertical synchronization data packet VS based on the first flag signal TE1B and the time TVEB after the first reference time TRV1B has elapsed since the generation of the first flag signal TE1B.

[0115] Because the first reception time TPV1B of the vertical synchronization data packet VS based on the first flag signal TE1B is inconsistent with the generation time TVV1B of the internal vertical synchronization signal VSYNC, the display driving circuit 110 can operate in video memory mode. The second image data IDT2B received after transmitting the first flag signal TE1B can be stored in memory 112 and then converted into second data DATA2B after a predetermined time, or optionally, after a desired time.

[0116] The display driver circuit 110 can reset the second reference time TRV2B based on the first delay time TDV1B. For example, the second reference time TRV2B can be set to be consistent with the first delay time TDV1B, and can be calculated by adding the difference time TCVB to the first reference time TRV1B.

[0117] The display driving circuit 110 can adjust the second generation time TTV2B of the second flag signal TE2B based on the second reference time TRV2B. The display driving circuit 110 can transmit the second flag signal TE2B to the host 200 at the adjusted second generation time TTV2B, and the host 200 can transmit the vertical synchronization data packet VS upon receiving the second flag signal TE2B. In some example embodiments, the second reception time TPV2B of the vertical synchronization data packet VS based on the second flag signal TE2B can be delayed by a second delay time TDV2B from the second generation time TTV2B of the second flag signal TE2B.

[0118] The second delay time TDV2B can be consistent with the second reference time TRV2B. Since the second delay time TDV2B is consistent with the second reference time TRV2B, the second reception time TPV2B of the vertical synchronization data packet VS received after the display driver circuit 110 transmits the second flag signal TE2B can be consistent with the generation time TVV2B of the internal vertical synchronization signal VSYNC. Therefore, the display driver circuit 110 can operate in normal video mode after transmitting the second flag signal TE2B, and the third image data IDT3B received after transmitting the second flag signal TE2B is not stored in the memory 112 and can be directly converted into third data DATA3B. However, with... Figure 11 Unlike other methods, when the second delay time TDV2B is different from the second reference time TRV2B, the display driving circuit 110 can operate in video memory mode, and the third image data IDT3B can be temporarily stored in memory 112.

[0119] Figure 12 This is a diagram illustrating the internal vertical synchronization signal and internal horizontal synchronization signal generated by the display driving circuit according to an example embodiment of the inventive concept.

[0120] Reference Figure 12 The display panel 120 can be operated by an internal vertical synchronization signal VSYNC with a vertical period VP and an internal horizontal synchronization signal HSYNC with a horizontal period HP. The vertical period VP may include a first vertical edge time period VBP, a vertical activity time period VACT, and a second vertical edge time period VFP. The first vertical edge time period VBP may include a vertical velocity action VSA as a vertical response time period. In an example embodiment, the first vertical edge time period VBP may be a vertical trailing edge time period, and the second vertical edge time period VFP may be a vertical leading edge time period. The vertical period VP may correspond to one frame period.

[0121] The horizontal period HP may include a first horizontal edge time period (HBP), a horizontal activity time period (HACT), and a second horizontal edge time period (HFP). The first horizontal edge time period (HBP) may include the horizontal velocity action (HSA) as a horizontal response time period. In an example embodiment, the first horizontal edge time period (HBP) may be a horizontal trailing edge time period, and the second horizontal edge time period (HFP) may be a horizontal leading edge time period.

[0122] During the vertical activity period (VACT) and the horizontal activity period (HACT), multiple scan lines included in the display panel 120 are executed (e.g., ...). Figure 2The scanning of SL1 to SLn and the data input for pixels connected to the scan lines are performed. That is, multiple scan lines SL1 to SLn can be scanned sequentially during the vertical activity period VACT, and data input for pixels connected to the scan lines can be performed during the horizontal activity period HACT.

[0123] Reference Figure 7 , Figure 9 and Figure 11 The described operation of increasing the frame period can mean increasing the second vertical edge time period VFP in the vertical period VP of the internal vertical synchronization signal VSYNC.

[0124] Figure 13A This is a block diagram illustrating a partial structure of a display device according to an example embodiment of the inventive concept, and it can be used with... Figure 1 The driver 115 corresponds to the display panel 120. Figure 13B This is a timing diagram illustrating the operation of a display driving circuit according to an example embodiment of the inventive concept. Figure 13A In the text, OLED panels are described as... Figure 1 An example of display panel 120, and omitting the... Figure 2 Redundant descriptions of the same figure labels in the figures.

[0125] Reference Figure 13A and Figure 13B The display panel 120a includes multiple data lines DL1 to DLm, multiple scan lines SL1 to SLn, multiple emission control lines EL1 to ELn, and multiple pixels PX' between the lines. Each of the multiple pixels PX' can be connected to a corresponding scan line, data line, and emission control line.

[0126] The emission control driver 115_3 can be connected to multiple emission control lines EL1 to ELn, and can control the emission time of pixel PX' by sequentially applying emission control signals ECS to pixel PX'. Each of the pixels PX' can include a corresponding OLED and can include a transistor that supplies or blocks the drive current supplied to the OLED corresponding to the image signal. The emission control signal ECS provided by each of the multiple emission control lines EL1 to ELn can turn on / off the transistor that supplies drive current to the OLED, thereby controlling the emission time of the OLED.

[0127] The brightness value of each pixel PX' can vary according to the duty cycle of the transmit control signal ECS. As the duty cycle of the transmit control signal ECS (e.g., the length of the on-time ONT of the transmit control signal ECS compared to the period ECST of the transmit control signal ECS) increases, the transmit time of pixel PX' can be increased, and the brightness of pixel PX' can be increased. In this way, the transmit control driver 115_3 can adjust the brightness of the display panel 120a by adjusting the pulse width modulation (PWM) of the transmit control signal ECS under the control of the display controller 114.

[0128] A frame period corresponding to the period of the internal vertical synchronization signal VSYNC can be increased or decreased in units of the period of the transmit control signal ECS, ECST. Therefore, referring to... Figure 7 , Figure 9 and Figure 11 The described operation of increasing the frame period can be performed in units of the period ECST of the transmit control signal ECS. In some example embodiments, the unit of the period ECST of the transmit control signal ECS can be a brightness adjustment unit of pixel PX'.

[0129] When the internal vertical synchronization signal VSYNC is received later than expected, the display driving circuit according to the inventive concept can increase the extension time ET and ETB of the corresponding frame (i.e., the first vertical period VP1 of the internal vertical synchronization signal VSYNC). In some example embodiments, the extension time ET and ETB can be a multiple of the period ECST of the transmit control signal ECS, i.e., a multiple of the brightness adjustment unit. Therefore, even with an increased frame period, the brightness of the display panel 120a can be maintained, and flickering that appears to change the brightness of the display panel 120a can be reduced or prevented when changing the operating mode.

[0130] One or more of the elements disclosed above may include or be implemented with one or more processing circuits, such as hardware including logic circuits; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0131] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A display driving circuit operating in video mode and command mode, the display driving circuit comprising: The interface is configured to receive synchronization data packets and image data from the outside; The memory is configured to receive image data from the interface in command mode; The synchronization controller is configured to receive synchronization data packets from the interface and generate flag control signals and internal synchronization signals. A flag generator is configured to generate a first flag signal and a second flag signal in response to a flag control signal; as well as The image controller is configured to receive image data from memory in command mode, receive image data from an interface in video mode, and drive the display panel based on the image data. The synchronization controller is configured to calculate the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet. The synchronization controller is configured to adjust the generation time of the second flag signal by changing the reference time based on the result of comparing the delay time with the reference time. The reference time is the time between the time when a specific flag signal is generated and the predicted time to receive a synchronization data packet based on the specific flag signal. The specific flag signal includes a first flag signal or a second flag signal.

2. The display driving circuit according to claim 1, wherein, The synchronization controller is configured to generate flag control signals and internal synchronization signals based on a reference time.

3. The display driving circuit according to claim 2, wherein, The synchronization controller is configured to delay the generation time of the internal synchronization signal until after the reception time of the synchronization data packet when the delay time is longer than the reference time.

4. The display driving circuit according to claim 1, wherein, The synchronization controller includes: The synchronization packet detector is configured to receive synchronization packets; A synchronization signal generator is configured to generate an internal synchronization signal. A delay calculator is configured to calculate a delay time to generate a flag control signal; and The internal synchronization controller is configured to control the synchronization signal generator.

5. The display driving circuit according to claim 4, wherein, In command mode, the synchronization signal generator is configured to control the generation time of the internal synchronization signal according to the control of the internal synchronization controller.

6. The display driving circuit according to claim 4, wherein, In the transition mode from command mode to video mode, the delay calculator is configured to generate a flag control signal based on the result of calculating the delay time.

7. The display driving circuit according to claim 4, wherein, In video mode, the delay calculator is configured to generate a flag control signal based on the result of calculating the delay time.

8. A method for operating a display driver circuit in video mode and command mode, the method comprising the following steps: Receive commands from the host to change from command mode to video mode; Generate a first flag signal to transmit the generated first flag signal to the host; Receive synchronization data packets according to the first flag signal; as well as The generation time of the second flag signal is adjusted by changing the reference time based on the result of comparing the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet according to the first flag signal with a reference time, and the mode is switched to video mode. The reference time is the time between the time when a specific flag signal is generated and the predicted time to receive a synchronization data packet based on the specific flag signal. The specific flag signal includes a first flag signal or a second flag signal.

9. The method according to claim 8, wherein, The steps to switch to video mode include: when the delay time matches the reference time, switch to video mode.

10. The method according to claim 8, wherein, The steps to switch the mode to video mode include: storing the image data received from the host in memory when the delay time is different from the reference time.

11. The method according to claim 10, wherein, The steps to switch the mode to video mode also include: when the delay time is greater than the reference time, increasing the frame period by delaying the generation time of the internal synchronization signal corresponding to the image data.

12. The method according to claim 11, wherein, The steps to increase the frame period include increasing the frame period by a multiple of the brightness adjustment unit.

13. A method for operating a display driving circuit in video mode and command mode, the method comprising the following steps: Receive commands from the host to change from command mode to video mode; Generate a first flag signal and transmit the generated first flag signal to the host; Receive synchronization data packets and image data based on the first flag signal; Image data is stored in memory based on the result of comparing the delay time between the generation time of the first flag signal and the reception time of the synchronization data packet according to the first flag signal with a reference time; as well as The generation time of the second flag signal is adjusted by changing the reference time based on the result of comparing the delay time with the reference time, and the mode is switched to video mode. The reference time is the time between the time when a specific flag signal is generated and the predicted time to receive a synchronization data packet based on the specific flag signal. The specific flag signal includes a first flag signal or a second flag signal.

14. The method according to claim 13, wherein, The display driver circuit operates in command mode for directly generating internal synchronization signals, video mode for generating internal synchronization signals based on synchronization data packets received from the host, and switching mode for preparing to switch from command mode to video mode. In the switching mode, the steps of storing image data in memory and adjusting the generation time of the second flag signal are performed.

15. The method according to claim 14, wherein, The video modes include a normal video mode for generating internal synchronization signals based on synchronization data packets received from the host, and a video memory mode for directly generating internal synchronization signals. The step of storing image data includes comparing the delay time with a reference time in normal video mode, and When the delay time differs from the reference time, image data is stored in memory in video memory mode.

16. The method according to claim 13, wherein, The steps of storing image data in memory include: storing image data received from the host in memory when the delay time is different from the reference time.

17. The method according to claim 13, wherein, The steps of storing image data in memory include: increasing the frame period by delaying the generation time of the internal synchronization signal corresponding to the image data when the delay time is greater than the reference time.

18. The method according to claim 17, wherein, The steps to increase the frame period include increasing the frame period by a multiple of the brightness adjustment unit.

19. The method according to claim 13, wherein, The steps for adjusting the generation time of the second flag signal include adjusting the reference time to match the delay time.

20. The method according to claim 19, wherein, The steps to adjust the reference time to match the delay time include: calculating the time difference between the time of receiving the synchronization data packet and the time of generating the internal vertical synchronization signal; and adjusting the reference time to match the delay time based on the time difference.

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