Single-rail storage circuit with row-specific voltage supply line and boost circuit

Abstract

The present application relates to a single-rail storage circuit having row-specific voltage supply lines and boost circuits. A single-rail storage circuit is disclosed, comprising an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array to facilitate read and write operations on selected memory cells. The peripheral circuitry includes, but is not limited to, a boost circuit for the row. Each boost circuit is connected to a word line for a row and a discrete voltage supply line for the same row. During a read of any selected memory cell in the row, each boost circuit for a row is configured to increase the voltage level on the word line and the voltage supply line for the row. During the read operation, increasing the voltage level on the word line and the voltage supply line effectively increases the read current, thereby reducing the probability of a read failure. The present application also discloses a method for operating the storage circuit.

Description

Technical Field

[0001] The present invention relates to memory circuits, and more particularly, to embodiments of single-rail memory circuits and methods of operation. Background Art

[0002] A memory circuit typically includes an array of memory cells arranged in rows and columns and peripheral circuitry that is connected to the array and facilitates various functions (e.g., read and write functions) in the memory cells. Historically, memory circuits have been single-rail memory circuits. That is, the same positive supply voltage (e.g., VDD) will be used to power the entire memory circuit, including the memory cells and the peripheral circuitry. Unfortunately, as cell sizes are scaled (e.g., by reducing transistor size) to reduce area consumption, and VDD is lowered to reduce power consumption, memory cells in single-rail memory circuits have become more susceptible to read failures, particularly, sensing failures and read stability failures (also referred to herein as static noise margin (SNM) failures). Summary of the Invention

[0003] Disclosed herein are embodiments of a single-rail storage circuit configured to avoid read failures (e.g., sensing failures and / or SNM failures). The storage circuit may include an array of memory cells arranged in rows and columns. The storage circuit may further include word lines for the rows, voltage supply lines for the rows, and boost circuits for the rows. Each word line for each row may be connected to all memory cells in the row. Each voltage supply line for each row may be connected to all memory cells in the row. Each boost circuit for each row may be incorporated into a row decoder and may be connected to the word line for the row and the voltage supply line for the row. Each boost circuit for each row may be configured to simultaneously increase the voltage levels on the word line and voltage supply line for the row during a storage function for any selected memory cell in the same row. For example, each boost circuit for each row may be configured to perform a synchronous and simultaneous increase in the voltage levels on the word line and voltage supply line for the row during a read operation for any selected memory cell within the row. During a read operation for a selected memory cell within the row, simultaneously increasing the voltage levels on the word line and voltage supply line for the row can effectively boost (ie, increase) the read current, thereby reducing the probability of a read failure.

[0004] This document also discloses method embodiments associated with operating the aforementioned memory circuit. Specifically, the method may include providing a memory circuit. The memory circuit may include an array of memory cells arranged in rows and columns. The memory circuit may further include word lines for the rows, voltage supply lines for the rows, and boost circuits for the rows. Each word line for each row may be connected to all memory cells in the row. Each voltage supply line for each row may be connected to all memory cells in the row. Each boost circuit for each row may be incorporated into a row decoder and may be connected to the word line for the row and the voltage supply line for the row. The method may further include, by the boost circuit for the row, simultaneously increasing the voltage levels on the word line and the voltage supply line for the row during a store function for any selected memory cell in the row. For example, the synchronous and simultaneous increase in the voltage levels on both the word line and the voltage supply line for the row may be specifically performed by the boost circuit for the row during a read operation for a selected memory cell in the row. Increasing the voltage levels on the word line and the voltage supply line for the row during a read operation may effectively boost (i.e., increase) the read current, thereby reducing the probability of a read failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0006] Figure 1A A schematic diagram illustrating a conventional static random access memory (SRAM) circuit;

[0007] Figure 1B For illustration purposes, Figure 1A Schematic diagram of an SRAM cell in an SRAM circuit;

[0008] Figure 2 Schematic diagram illustrating read sensing failure in a 6T-SRAM cell;

[0009] Figure 3 Schematic diagram illustrating read stability failure in a 6T-SRAM cell;

[0010] Figure 4A A schematic diagram illustrating the disclosed SRAM circuit;

[0011] Figure 4B For illustration purposes, Figure 4A Schematic diagram of an SRAM cell in an SRAM circuit;

[0012] Figure 4C For illustration purposes, Figure 4A Schematic diagram of a row-specific boost circuit in an SRAM circuit;

[0013] Figure 5A timing diagram illustrating signal states within a row-specific boost circuit during a read operation for a selected SRAM cell;

[0014] Figure 6A and Figure 6B are different graphs illustrating exemplary voltage level changes on BLT, BLC, WL, and VSL during a read operation with Iread boosting;

[0015] Figure 7 A flowchart illustrating an embodiment of the disclosed method. DETAILED DESCRIPTION

[0016] As described above, a memory circuit typically includes an array of memory cells arranged in rows and columns and peripheral circuitry that is connected to the array and facilitates various memory functions (e.g., read operations and write operations) in the memory cells. Historically, memory circuits have been single-rail memory circuits. That is, the same positive supply voltage (e.g., VDD) from the same positive supply voltage rail will be used to power the entire memory circuit, including the memory cells and the peripheral circuitry. Unfortunately, as cell sizes are scaled (e.g., by reducing transistor size) to reduce area consumption, and VDD is lowered to reduce power consumption, memory cells in single-rail memory circuits become more susceptible to read failures, in particular, sensing failures and read stability failures (also referred to herein as static noise margin (SNM) failures).

[0017] For example, Figure 1A 1 is a schematic diagram illustrating an exemplary static random access memory (SRAM) circuit 100. This SRAM circuit 100 includes an array of six-transistor (6T) SRAM cells 101 arranged in rows (see row an) and columns (see column AN). The SRAM circuit 100 also includes a controller 195 and peripheral circuits 191-193 connected to the array, in communication with the controller 195, and configured to facilitate various memory functions (e.g., read operations and write operations) in response to control signals from the controller 195. Figure 1Bis a schematic diagram illustrating the 6T-SRAM cell 101 in more detail. The 6T-SRAM cell 101 includes a first inverter including a first pull-up transistor 102 and a first pull-down transistor 103 connected in series between a positive supply voltage rail 121 and ground; and a second inverter cross-coupled to the first inverter and including a second pull-up transistor 112 and a second pull-down transistor 113 connected in series between the positive supply voltage rail 121 and ground. The 6T-SRAM cell further includes a first access transistor 104 (also referred to herein as a first pass-gate transistor) connected in series between a true bitline (BLT) 131 for the column containing the cell and a data storage node 105 located at the junction between the first pull-up transistor 102 and the first pull-down transistor 103, and having a gate connected to a wordline 140 for the row containing the SRAM cell; and a second access transistor 114 (also referred to herein as a second pass-gate transistor) connected in series between a complement bitline (BLC) 132 for the column containing the cell and a complement data storage node 115 located at the junction between the second pull-up transistor 112 and the second pull-down transistor 113, and having a gate connected to the wordline 140 for the row.

[0018] Historically, SRAM circuits have been single-rail memory circuits. However, with each new technology node, cell size and VDD have decreased, and as a result, cells have become more susceptible to read failures, including read sensing failures and read stability failures (i.e., SNM failures). Figure 2 and Figure 3 The two different failure mechanisms are explained separately.

[0019] Specifically, Figure 2 Indicates a read sense failure. Figure 1A-1B refer to Figure 2If the SRAM cell stores a data value of "0" on the first data storage node 105 and a complement data value of "1" on the second data storage node 115, and a read operation is initiated (e.g., after precharging the BLs 131-132 of the column, activating the WL 140 of the row), a read current (Iread) will flow from the precharged BLT 131 through the first access transistor 104 to the data storage node 105, and thus, the voltage level on the BLT 131 will drop, while the voltage level on the BLC 132 remains unchanged (i.e., at VDD). Ideally, the voltage drop on the BLT 131 will be detectable by the sensing circuit so that the stored data value is read as "0". However, if the voltage drop on the BLT 131 is relatively small (e.g., see differential 201), the sensing circuit may not detect the voltage drop, and the stored data value will be read as "1". This read failure mechanism is referred to herein as a sense failure.

[0020] Figure 3 Describes a read stability failure. Figure 1A-1B refer to Figure 3 If an SRAM cell stores a data value of "0" on first data storage node 105 and a complement data value of "1" on second data storage node 115, and a read operation is initiated (e.g., by activating WL 140 for the row after precharging BLs 131-132 for the column), Iread will flow from the precharged BLT 131 via first access transistor 104 to data storage node 105. As a result, the voltage level on BLT 131 will decrease, while the voltage level on BLC 132 will remain unchanged. Ideally, as Iread flows to data storage node 105, first pull-down transistor 103 will continuously pull the voltage level on data storage node 105 down to ground. However, if the drive current of first pull-down transistor 103 is insufficient, the voltage level on first data storage node 105 will increase. If the voltage level on first data storage node 105 increases above the threshold voltage (Vt) of second pull-down transistor 113, the data values ​​stored on nodes 105 and 115 may switch. This read failure mechanism is referred to herein as a read stability failure (or read SNM failure).

[0021] Exemplary SRAM circuit configurations designed to avoid the above-described read failure mechanisms include multi-port SRAM circuits that incorporate additional transistors into the SRAM cell (e.g., eight or ten transistors instead of six transistors) to create discrete read ports and / or dual-rail SRAM circuits that use a relatively high positive supply voltage (referred to as the cell supply voltage (VCS)) from one positive supply voltage rail to power the SRAM cell itself, and a relatively low positive supply voltage (VDD) from a different positive supply voltage rail (not shown) to power peripheral circuits including BL precharge and WL activation. Unfortunately, such solutions can result in a significant increase in area consumption and / or a significant increase in power consumption.

[0022] In view of the foregoing, disclosed herein are embodiments of a more robust single-rail memory circuit configured to avoid read failures (e.g., read sensing failures and / or read stability failures) even when the memory cell size is scaled to reduce area consumption and / or when the positive supply voltage (VDD) on the single positive voltage rail is reduced to reduce power consumption. Specifically, the memory circuit may include an array of memory cells (e.g., static random access memory (SRAM) cells, such as six transistor (6T) SRAM cells) arranged in rows and columns, and peripheral circuitry connected to the array for facilitating memory functions (e.g., read operations and write operations). The peripheral circuitry for a row may include a row decoder having a boost circuit for each row. Each boost circuit for each row may be connected to a word line and a discrete voltage supply line for each row, and may be configured to simultaneously increase the voltage level on the word line and the voltage supply line for the row during a memory function in any selected cell within the same row. For example, each boost circuit in a row can be a read current (Iread) boost circuit configured to simultaneously increase the voltage levels on the word line and voltage supply line of the row during a read operation for any selected memory cell in the row, so as to effectively increase Iread and thereby reduce the probability of read failures. Such a memory circuit configuration provides substantially the same benefits for read operations as a dual-rail memory circuit, without requiring the two positive supply voltage rails to be constantly set to two different positive voltage levels (e.g., VDD and VCS greater than VDD) for powering peripheral circuits and memory cells, respectively. Thus, it is a low-leakage, low-dynamic-power solution. Method embodiments associated with the operation of such a memory circuit are also disclosed herein.

[0023] More specifically, embodiments of a memory circuit 400 are disclosed herein, such as Figure 4A As shown in the schematic diagram.

[0024] The memory circuit 400 may include an array of memory cells 401 arranged in rows (see row an) and columns (see column AN). That is, the memory cells 401 within the array may be arranged in straight lines, wherein the first lines are substantially parallel and oriented in a first direction (e.g., X direction), the second lines are substantially parallel and oriented in a second direction perpendicular to the first direction (e.g., Y direction), and each memory cell is located in a first row and a second row (i.e., at the intersection between a row of memory cells and a column of memory cells). For ease of explanation, Figure 4A The memory circuit 400 shown includes three rows of memory cells in the X direction and three columns of memory cells in the Y direction. However, it should be understood that Figure 4A This is not intended to be limiting. Alternatively, the array may include any number of rows of memory cells and any number of columns of memory cells. Furthermore, the rows may be oriented in the Y direction and the columns may be oriented in the X direction.

[0025] Memory cell 401 can be any suitable type of memory cell in which: (a) each memory cell in the array is connected to and powered by a voltage supply; (b) a read operation on a memory cell in the array requires word line activation; and (c) increasing the activated word line and voltage level of the voltage supply during a read operation is beneficial (e.g., increases the read current (Iread), thereby minimizing or preventing read failures). In some embodiments, memory cell 401 can be a static random access memory (SRAM) cell, such as a six transistor (6T) SRAM cell (as described in more detail below and in Figure 4B Schematic diagram of ).

[0026] The memory circuit 400 may also include row-specific word lines (WLs) (e.g., see WL 440a for row a, WL 440b for row b, and so on, up to WL 440n for row n). Each of the WLs 440a-440n in each of the rows an may be connected to all of the memory cells 401 in its corresponding row an.

[0027] The memory circuit 400 may also include row-specific voltage supply lines (VSLs) (e.g., see VSL 421a for row a, VSL 421b for row b, and so on, up to VSL 421n for row n). Each of the VSLs 421a-421n for each row in row an can be connected to all memory cells 401 in its corresponding row an. It should be noted that the row-specific VSLs are separated from each other so that the voltage level on any one VSL in the memory circuit is independent of the voltage level on any other VSL in the memory circuit. Thus, each VSL connected to all memory cells 401 in a particular row (and no memory cells in any other row) can simultaneously power all memory cells 401 in the particular row with a positive supply voltage. However, by using a separate VSL for each row, the positive supply voltage level on any one VSL (depending on the components in the peripheral circuitry incorporated into the row) can be selectively adjusted so that it is different (e.g., higher or lower) than the positive supply voltage level on the other VSLs. For example, depending on the components in the peripheral circuitry incorporated into the row, the positive supply voltage level on VSL can be selectively adjusted during a memory function (e.g., a read operation or a write operation) for any selected memory cell within the row to improve performance, reduce failures, etc. Thus, the disclosed memory circuit configuration differs from Figure 1A to Figure 1B The memory circuit configuration shown in and discussed above is advantageous because rather than using a single positive supply voltage rail 121 to simultaneously power all memory cells in the array at the same positive supply voltage level, a row-specific VSL is used.

[0028] The memory circuit 400 may also include any other row-specific or column-specific lines required to facilitate read and / or write functions. It will be appreciated that whether additional row-specific and / or column-specific lines are required will depend on the type of memory cells employed in the array.

[0029] For example, as described above, the memory cell 401 may be a 6T-SRAM cell, such as Figure 4B In this case, the memory circuit 400 may further include column-specific true and complement bit line pairs (BLT / BLC pairs) (e.g., BLT 431A and BLC 432A for column A; BLT 431B and BLC 432B for column B, and so on, up to BLT 431N and BLC 432N for column N), and each bit line of each true and complement bit line pair may be connected to all memory cells 401 in its corresponding column AN.

[0030] Each 6T-SRAM cell may include a first inverter including a first pull-up transistor 402 (e.g., a p-type field effect transistor (PFET)) and a first pull-down transistor 403 (e.g., an n-type field effect transistor (NFET)) connected in series between a row-specific voltage supply line (VSL) 421 and a ground rail 422. As described above, VSL 421 is row-specific, connected to and powering only the memory cells in a particular row, and is not connected to all memory cells within the array.

[0031] Each 6T-SRAM cell may also include a second inverter that is cross-coupled to the first inverter and includes a second pull-up transistor 412 (e.g., a PFET) and a second pull-down transistor 413 (e.g., an NFET) connected in series between VSL 421 and a ground rail 422. Those skilled in the art will recognize that by cross-coupling the first inverter and the second inverter, the junction between the first pull-up transistor 402 and the first pull-down transistor 403 (also referred to herein as the first data storage node 405 or the true node) will be connected to (i.e., will control) the gates of the second pull-up transistor 412 and the second pull-down transistor 413. Furthermore, the junction between the second pull-up transistor 412 and the second pull-down transistor 413 (also referred to herein as the second data storage node 415 or the complement node) will be connected to (i.e., will control) the gates of the first pull-up transistor 402 and the first pull-down transistor 403.

[0032] Each 6T-SRAM cell 401 may further include: a first access transistor 404 (also referred to herein as a first pass-gate transistor) (e.g., an NFET), which is connected in series between a column-specific true bit line (BLT) 431 (i.e., the BLT for the column containing the SRAM cell) and a first data storage node 405, and has a gate connected to a row-specific WL 440 (i.e., the WL for the row containing the SRAM cell); and a second access transistor 414 (also referred to herein as a second pass-gate transistor), which is connected in series between a column-specific complement bit line (BLC) 432 (i.e., the BLC for the column containing the SRAM cell) and a second data storage node 415, and which also has a gate connected to the same row-specific WL 440.

[0033] The memory circuit 400 may also include a controller 495 and peripheral circuitry connected to an array powered by a single positive voltage rail 420 set at a first positive supply voltage level (e.g., at a relatively low VDD), the array communicating with the controller 495 and configured to facilitate various memory functions (e.g., read operations and write functions) in response to control signals from the controller 495. As with conventional memory circuits (e.g., conventional SRAM circuits), the peripheral circuitry may include row peripheral circuitry 491. The row peripheral circuitry 491 may be connected to the WLs 440a-440n of row an and may include, for example, a row decoder configured to facilitate WL activation to provide memory cell access during a memory function (e.g., a read operation or a write operation). The peripheral circuitry may also include column peripheral circuitry 492. The column peripheral circuitry 492 may be connected to the BL for column AN and may include a column decoder configured to facilitate BL biasing during a memory function. Finally, the peripheral circuitry may include additional peripheral circuitry 493 that is also electrically connected to the BL for column AN and that includes sensing circuitry configured to sense changes in electrical characteristics of the BL (e.g., voltage or current) during a read operation to determine the data value stored in the selected memory cell.

[0034] Generally, such peripheral circuits are known in the art; however, as described above, the memory circuit 400 disclosed herein includes novel row-specific VSLs 421a-421n for simultaneously powering the memory cells in each row, rather than a single positive supply voltage rail that simultaneously powers all memory cells in the memory array. Thus, in the memory circuit 400 disclosed herein, the row peripheral circuits 491 are connected to both the WLs 440a-440n and the VSLs 421a-421n, and include novel features not found in the row peripheral circuits of conventional memory circuits (e.g., within the row decoder). Specifically, in the disclosed memory circuit embodiment, the row decoder of the peripheral circuit 491 may include row-specific boost circuits 480a-480n. Each boost circuit 480a-480n for each row an may be connected to the positive supply voltage rail 420, and for the same row, may be connected to both the WLs 440a-440n and the VSLs 421a-421n. Furthermore, each boost circuit 480a-480n of each row can be configured to simultaneously and temporarily increase the positive supply voltage levels on the WL of the row (after being activated) and the VSL of the row from a first positive supply voltage level (e.g., from VDD) to a second positive supply voltage level (e.g., VDD+) that is greater than the first positive voltage level. This simultaneous and temporary increase in the voltage levels on the WL and VSL of the row can be synchronized and performed during a memory function for any selected memory cell within the row to improve performance, reduce failures, etc.

[0035] For example, each row-specific boost circuit 480a-480n in a row decoder of the peripheral circuit 491 for a row can be a row-specific read current (Iread) boost circuit. Each row-specific Iread boost circuit can be connected to the positive supply voltage rail 420, which, as described above, is set at a first positive supply voltage level (e.g., at a relatively low VDD to reduce power consumption). Those skilled in the art will recognize that the actual level of the first positive supply voltage level can vary depending on the technology node. For example, at a 22nm fully depleted silicon-on-insulator (FD-SOI) technology node or other similar technology nodes, the first positive supply voltage level can be set to approximately 0.45V. Each Iread boost circuit 480a-480n of each row an can be configured to activate the WL of its corresponding row (i.e., increase the voltage level on the WL of the row from ground to the first positive supply voltage level) when a read operation in any selected memory cell within the row begins. The individual Iread boost circuits 480a-480n of each row can also be configured to simultaneously and temporarily increase the voltage levels on the WL of the row and the VSL of the row during a read operation. This increase in the voltage levels on WL and VSL can, for example, be from the same first positive supply voltage level (e.g., from VDD) to the same second positive supply voltage level (e.g., VDD+) that is greater than the first positive supply voltage level during the read operation. Specifically, each Iread boost circuit 480a-480n can be configured so that after the read operation begins, the voltage levels on the WL and VSL of the row are automatically increased in a synchronized manner after the WL of the row is fully activated (i.e., once the voltage level on the WL of the row has reached the first positive supply voltage level). Those skilled in the art will recognize that the amount by which the voltage levels on the WL and VSL of the row are increased during the read operation, as well as the resulting voltage levels on the WL and VSL, will be customized according to the technology node in question to ensure that the above-mentioned read failure issues associated with traditional single-rail memory circuits are minimized or avoided altogether. For example, at a 22 nm fully depleted silicon-on-insulator (FD-SOI) technology node or other similar technology nodes, each Iread boost circuit 480 a - 480 n can be configured such that the voltage levels on WL and VSL are simultaneously increased by approximately 100 mV (e.g., from a first positive supply voltage level of approximately 0.45 V to a second positive supply voltage level of approximately 0.55 V). As discussed in more detail below, simultaneously increasing the voltage levels on WL and VSL for a row during a read operation of any selected memory cell within the row effectively boosts (i.e., increases) the Iread through the selected memory cell, thereby reducing the probability of read failures, and in particular, reducing the probability of read sensing failures or read stability failures (i.e., read SNM failures).Finally, each Iread boost circuit 480a-480n may also be configured to lower the voltage level on WL of the row back to ground and lower the voltage level on VSL of the row back to the first positive supply voltage level when the read operation is complete.

[0036] Figure 4C is a schematic diagram illustrating an exemplary row-specific Iread boost circuit 480 that may be incorporated into a row decoder of a peripheral circuit 491 for a row an in the memory circuit 400 .

[0037] As shown, the Iread boost circuit 480 may include a pair of coupling capacitors (CC) (e.g., a first CC 489.1 and a second CC 489.2). CCs 489.1 and 489.2 may be connected in series between a first boost node 471 on the WL 440 of the row and a second boost node 472 on the VSL 421 of the same row.

[0038] The Iread boost circuit 480 may include a WL driver 485. The WL driver 485 may include a first PFET 473 and a first NFET 474 connected in series between the positive supply voltage rail 420 and the ground rail 422. As described above, the positive supply voltage rail 420 may be set at a first positive supply voltage level (e.g., at a relatively low VDD). The WL driver 485 may also include a WL driver output node 475 located at the connection between the first PFET 473 and the first NFET 474 and connected to the WL 440 of the row (e.g., adjacent to the first boost node 471).

[0039] Iread boost circuit 480 may include a coupling capacitor (CC) driver 487. CC driver 487 may include a second PFET 476 and a second NFET 477 connected in series between positive supply voltage rail 420 and ground rail 422. CC driver 487 may include a CC driver output node 478 located at the junction between second PFET 476 and second NFET 477 and connected to intermediate node 469 between CCs 489.1 and 489.2.

[0040] The Iread boost circuit 480 may include a header switch 488. The header switch 488 may be, for example, the third PFET 479 connected in series between the positive supply voltage rail 420 and the VSL 421 of the row (eg, adjacent to the second boost node 472).

[0041] The Iread boost circuit 480 may also include a synchronization circuit 468 having an input node 497 for receiving a row-specific read control signal. It should be noted that depending on the state of the row-specific read control signal (i.e., high or low), the start or completion of a read operation in any selected memory cell in the row can be triggered. In some embodiments, the read control signal can be an inverted read clock signal (RCLKb). That is, the read control signal can be an inverted version of the read clock signal (RCLK) arriving at the input node 497. In this case, switching RCLKb from a high level to a low level on the input node 497 can trigger the start of a read operation in any selected memory cell in the row to which the Iread boost circuit 480 is connected, while switching RCLKb from a low level to a high level on the input node 497 can trigger a signal to indicate the end of this read operation.

[0042] Synchronization circuit 468 can be configured to cause WL driver 485 to initially increase the voltage level on WL 440 from ground to a first positive supply voltage level when RCLKb on input node 497 goes low, and once the WL for the row reaches the first positive supply voltage level, automatically cause CC driver 487 to simultaneously charge CCs 489.1 and 489.2, thereby simultaneously and temporarily increasing the voltage level on WL 440 for the row and VSL 421 (e.g., from a first positive supply voltage level to a second positive supply voltage level).

[0043] Synchronization circuit 468 may be further configured to cause WL driver 485 to reduce the voltage level on WL 440 to ground and cause CC driver 487 to stop charging CCs 489.1 and 489.2, thereby causing the voltage level on VSL 421 to fall back to the first positive supply voltage level. When RCLKb on input node 497 switches back to a high level, it indicates the end of the read operation.

[0044] In some embodiments, the synchronization circuit 468 may include a plurality of logic gates to adjust the voltage levels on WL and VSL, as described above. The logic gates may include: a pair of inverters (i.e., a first inverter 481 and a second inverter 483); an OR gate 482; an AND gate 484; and a NAND gate 486.

[0045] The first inverter 481 and the second inverter 483 may be connected in series between the input node 497 and the gate of the first NFET 474 of the WL driver 485. The first inverter 481 may receive RCLKb from the input node 497, invert RCLKb into RCLK, and output RCLK to the second inverter 483. The second inverter 483 may receive RCLK, invert RCLK into a first word line driver control signal (WLDCN), and apply WLDCN to the gate of the first NFET 474 of the WL driver 485.

[0046] AND gate 484 can receive a pair of inputs, including RCLK from first inverter 481 and a feedback signal (FBK), which is sent from WL driver output node 475 to AND gate 484 along feedback path 467. AND gate 484 can perform a conventional logical AND combination and can output a synchronous control signal (SC). Those skilled in the art will recognize that using conventional logical AND combination, SC will be low (i.e., a logical value of "0") unless both inputs to the AND gate are high (i.e., a logical value of "1").

[0047] The OR gate 482 may receive a pair of inputs, including RCLKb from the input node 497 and SC from the AND gate 484. The OR gate 482 may perform a conventional logical OR combination, may output a second word line driver control signal (WLDCP), and may apply WLDCP to the gate of the first PFET 473 of the WL driver 485. Those skilled in the art will recognize that for a conventional logical OR combination, WLDCP will be high (i.e., a logical value of “1”) unless both inputs to the OR gate are low (i.e., a logical value of “0”).

[0048] NAND gate 486 may receive a pair of inputs, including SC from AND gate 484 and WLDCP from OR gate 482. NAND gate 486 may perform a conventional logical NAND combination, may output a CC driver control signal (CCDC), and may apply CCDC to the gates of second PFET 476 and second NFET 477 of CC driver 487.

[0049] The RCLK from the first inverter 481 of the synchronization circuit 468 may also be applied to the gate of the third PFET of the header switch 488. Optionally, the synchronization circuit 468 may include a delay element 463 (e.g., a resistor) in series between the output of the first inverter 481 and the gate of the third PFET 479 of the header switch 488 downstream of the input to the AND gate 484.

[0050] refer to Figure 4C Combine Figure 5 , a read operation for a selected 6T-SRAM cell in a specific row and a specific column of the array can be performed as follows.

[0051] Before a read operation (see Figure 5 At time T1, RCLKb on input node 497 of the Iread boost circuit 480 for a particular row will be high. RCLK will be low, and the third PFET of header switch 488 will be turned on, thereby maintaining the voltage level on VSL 421 for the particular row at the first positive supply voltage level (e.g., VDD). Furthermore, both WLDCN and WLDCP will be high, turning on only the first NFET 474 of WL driver 485, pulling down WL driver output node 475, and grounding the WL 440 for that row. Consequently, the inputs to AND gate 484 (i.e., RCLK and FBK) are low and low, and the output from AND gate 484 (i.e., SC) is low. The inputs to OR gate 482 (i.e., SC and RCLKb) are low and high, and the output from OR gate 482 (i.e., WLDCP) is high, keeping the first PFET 473 of WL driver 485 off. The inputs of NAND gate 486 (i.e., SC and WLDCP) are low and high, and the output of NAND gate 486 (i.e., CCDC) is high. Therefore, the second PFET 476 of CC driver 487 is turned off, the second NFET 477 of CC driver 487 is turned on, and the voltage level on CC driver output node 478 is pulled low. As a result, at time T1, CCs 489.1 and 489.2 are unpowered, and the voltage levels on WL 440 and VSL 421 of the row are stabilized at ground and the first positive supply voltage level, respectively.

[0052] Before starting a read operation, a column decoder in the column's peripheral circuit 492 may respond to some control signals (e.g., from the controller 495) so that the bit lines (BLT and BLC) of a particular column are precharged to a first positive supply voltage level. It should be noted that BL precharging for a read operation is known in the art, and therefore, details are omitted from this description to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0053] After precharging the BL of a particular column, RCLKb switches from high to low, triggering the start of a read operation (see Figure 5Even if RCLKb switches to low, the output of AND gate 484 (i.e., SC) will remain low, and therefore, the output of OR gate 482 (i.e., WLDCP) will switch to low, thereby turning on the first PFET 473 of WL driver 485. In addition, when RCLKb switches to low, the output of first inverter 481 (i.e., RCLK) goes high. When RCLK goes high, the third PFET 479 of header switch 488 turns off and the output of second inverter 483 (i.e., WLDCN) goes low (see FIG. Figure 5 When WLDCN goes low, the first NFET 474 of the WL driver turns off. Therefore, the first PFET 473 turns on, the first NFET 474 turns off, and the voltage level on the WL driver output node 475 is pulled up, and thus the voltage level on the WL 440 and the feedback path 467 is also pulled up (see Figure 5 At this time, WL has been activated (ie, the voltage level on WL has increased from ground to the first positive supply voltage level to turn on the access transistor).

[0054] When the voltage level on the WL driver output node 475 is pulled up, the inputs of the AND gate 484 (i.e., RCLK and FBK) will be high and high. Therefore, the output of the AND gate 484 (i.e., SC) will switch from low to high (see Figure 5 When SC switches from low to high, the output of OR gate 482 (i.e., WLDCP) switches from low to high, thereby turning off the first PFET 473 of WL driver 485 (after the WL driver output node 475 is pulled up). It should be noted that the first NFET 474 of WL driver 485 remains off, and therefore, the voltage level on the WL driver output node 475 remains high (see Figure 5 When WLDCP switches from low to high, the inputs to NAND gate 486 (i.e., SC and WLDCP) will both be high, and therefore, the output of NAND gate 486 (i.e., CCDC) will switch to low (see Figure 5 When CCDC is low, the second PFET 476 of CC driver 487 is turned on and the second NFET 477 is turned off, causing CC driver output node 478 to be pulled up, thereby charging CC 489.1 and 489.2, so BOOST goes high (see Figure 5The sequential charging of CCs 489.1-489.2 will cause the voltage levels on WL 440 and VSL 421 of a particular row to rise synchronously, more specifically, simultaneously. It should be noted that CCs 489.1-489.2 may be of the same size so that the voltage levels on WL and VSL are both raised from the same first positive supply voltage level (e.g., VDD) to the same second positive supply voltage level (e.g., VDD+) (see FIG. Figure 5 time T9).

[0055] Consider a read operation in which a selected 6T-SRAM cell in a particular row and a particular column has a stored data value of "0" on the first data storage node 405 and a complementary stored data value of "1" on the second data storage node 415. As described above, before the read operation begins, the BLT 431 and BLC 432 are precharged to the first positive supply voltage level. At time T1, the first and second access transistors 404 and 414 will be turned off. The second data storage node 415 will be at the first positive supply voltage level (indicating the complementary stored data value of "1"). Therefore, the first pull-up transistor 402 will be turned off, the first pull-down transistor 403 will be turned on, and the voltage level on the first data storage node 405 will remain at ground (indicating the stored data value of "0"). Furthermore, since the first data storage node 405 is at ground, the second pull-up transistor 412 will be turned on, the second pull-down transistor 413 will be turned off, and the voltage level on the second data storage node 415 will remain at the first positive supply voltage level. However, at time T9, the WL 440 of the row containing the selected 6T-SRAM cell has been activated (i.e., the voltage level on the WL of the row has increased from ground to the first positive supply voltage level). Therefore, the first and second access transistors 404 and 414 are already turned on, and since the first data storage node 405 is at ground and the BLT 431 is precharged, a read current (Iread) flows from the BLT 431 via the first access transistor 404 to the first data storage node 405, causing the voltage level on the BLT 431 to drop.

[0056] Furthermore, at time T9, the voltage levels on WL 440 and VSL 421 are also raised (eg, from a first positive supply voltage level to a second positive supply voltage level (eg, VDD+). As a result, due to WL 440 applies a higher voltage to the respective gates of the first access transistor and the second access transistor 404 and 414, and thus the drive strength of the first access transistor and the second access transistor 404 and 414 is increased. In addition, the voltage level on the second data storage node 415 has been pulled up to the second positive supply voltage level by the second pull-up transistor 412 (which is turned on), and therefore, since the second data storage node 415 applies a higher voltage to the gate of the first pull-down transistor 403, the drive strength of the first pull-down transistor 403 is increased. The voltage level on BLC432 (VBLC) is generally maintained at the first positive supply voltage level. However, it should be noted that VBLC may be pulled up depending on the level of the boost voltage applied to the gate of the second access transistor 414. By increasing the drive strength of both the first access transistor 404 and the first pull-down transistor 403 during the read operation, the pre-charged BLT The amount of read current (Iread) flowing in the direction 431 toward the first data storage node 405 (which is at ground indicating storage of a "0" data value) will increase (i.e., boost), causing the voltage level on BLT (i.e., VBLT) to drop more than otherwise.

[0057] For example, in some embodiments, Iread may increase from less than 0.5 μA (e.g., from about 0.38 μA or less), which would result in only a minimal decrease in VBLT, to greater than 1.5 μA (e.g., to about 2.1 μA or greater), resulting in a significant decrease in VBLT.

[0058] More specifically, if Figure 6A and Figure 6B As shown in the diagram of FIG, during a read operation after the BLT 431 and the BLC 432 have been precharged to a first positive supply voltage level (e.g., VDD), and after the WL is activated (i.e., the voltage level has increased from ground to the first positive supply voltage level (see time 602), the voltage levels on the WL 440 and VSL 421 of the row are substantially simultaneously raised to a second positive supply voltage level (e.g., VDD+), and because the first data storage node 405 is at a low level, the voltage level on the BLT 431 (VBLT) will begin to decrease (see time 603). Due to the boosted voltages on the WL and VSL, the difference 601 between the reduced voltage level on the BLT 431 (VBLT) and the voltage level on the BLC 432 (VBLC) (which, as discussed above, is typically maintained at the first positive supply voltage level, e.g., VDD) will be significantly greater than the difference if Iread is not activated (e.g., as discussed above). Figure 2 As shown). In some embodiments, the differential 601 can be increased from less than 50 mV without Iread boosting (e.g., from about 36 mV or less) to greater than 100 mV with Iread boosting (e.g., to about 149 mV or greater). This increase in the differential 601 ensures that it can be detected by the sensing circuit and the value of the data stored on the first data storage node 405 can be accurately determined. Thus, read sensing failures (e.g., a failure in which the drop in the voltage level on the BLT is insufficient to be detected, causing the value of the data stored on the first data storage node 405 to be erroneously read as “1”) can be avoided. Furthermore, by pulling up the voltage level on the second data storage node 415 to the second positive supply voltage level during the read operation, and by increasing the drive strength of the first pull-down transistor 403, the first pull-up transistor 402 remains disconnected, and the first pull-down transistor 403 continuously pulls down the voltage level on the first data storage node 405 to ground. Thus, read stability failures (also known as SNM failures) (e.g., a failure in which a read operation causes a switching of the stored data value) can also be avoided.

[0059] At a certain time T10, when RCLKb switches from a low level back to a high level to indicate the end of the read operation, the output of the first inverter 481 (i.e., RCLK) will switch to a low level. Once RCLK switches to a low level, the third PFET 479 of the header switch 488 will turn on and pull the voltage level on VSL 421 back from the second positive supply voltage level (e.g., VDD+) to the first positive supply voltage level (e.g., VDD) (see time T11). As described above, the line between the output of the first inverter 481 and the gate of the third PFET 479 can optionally include a delay element 463 located downstream of the input of the AND gate 484. This delay element 463 can be specifically configured to delay switching the third PFET 479 to the on state, thereby delaying the reduction of the voltage level on VSL 421. The delay of delay element 463 may, for example, be set so that the drop in the voltage level on VSL 421 from the second positive supply voltage level to the first positive supply voltage level coincides with the drop in the voltage level on WL 440 from the second positive supply voltage level (e.g., VDD) to ground at time T12, as discussed below (see Figure 5 Optional delay indicated by reference numeral 563 in the figure).

[0060] It should be noted that Figure 6A The diagram of shows an exemplary read operation in which synchronization circuit 468 does not include optional delay element 463, so that at the end of the read operation, the voltage level on VSL 421 begins to decrease at time 665, and shortly thereafter at time 666, the voltage level on WL 440 begins to decrease. Figure 6BThe diagram of FIG. 4 illustrates an exemplary read operation in which synchronization circuit 468 includes delay element 463, so that at the end of the read operation, the voltage levels on VSL 421 and WL 440 begin to decrease at approximately the same time (see time 663) (e.g., see also Figure 5 The offset voltage drop of VSL represented by the dashed line 563 in FIG.

[0061] In any case, at time T11, the output of the second inverter 483 (i.e., WLDCN) switches from a low level to a high level, and the output of the AND gate 484 (i.e., SC) switches from a high level to a low level. At time T12, when SC is low and WLDCP is high, the output of the NAND gate 486 (i.e., CCDC) switches back to a high level. Furthermore, at time T12, when WLDCN is high and SC is low, the first NFET 474 of the WL driver 485 turns back on, and the output of the OR gate 482 (i.e., WLDCP) remains high, thus keeping the first PFET 473 off. Consequently, the first NFET 474 pulls the voltage level on the WL driver output node 475 down from the second positive supply voltage level (e.g., VDD+) to ground, thereby pulling the voltage level on the WL 440 down from the second positive supply voltage level (e.g., VDD+) to ground. At time T13, CCDC is high, so the second PFET 476 of CC driver 487 is turned off and the second NFET 477 of CC driver 487 is turned on. Consequently, CC driver output node 478 is pulled back to ground. At time T14, CC 489.1 and 489.2 are no longer charging or raising the voltage levels on WL 440 and VSL 421. Note that when WL driver output node 475 is low, the FBK input to AND gate 484 will also be low; however, since RCLK is low at this time, SC will remain low.

[0062] In the above embodiment, CCs 489.1-489.2 are described as being substantially identical so that when they are simultaneously charged from the same CC driver output node 478, the voltage levels on WL 440 and VSL 421 are simultaneously increased by substantially the same amount (e.g., approximately 100 mV) from the same first positive supply voltage level (e.g., VDD of approximately 0.45 V) to the same second positive supply voltage level (e.g., VDD+ of approximately 0.55 V). However, it should be understood that this description is not intended to be limiting. Alternatively, CCs 489.1-489.2 may be different, and more specifically, may have different sizes. Thus, when CCs 489.1-489.2 are simultaneously charged from the same CC driver output node 478, the voltage levels on WL 440 and VSL 421 will increase simultaneously, but by different amounts. Consequently, the voltage levels on WL 440 and VSL 420 will both be greater than the first positive supply voltage level but different from each other (e.g., at VDD+ and VDD++).

[0063] Finally, it should be noted that because in this case, each Iread boost circuit 480a-480n within the row decoder of the peripheral circuit 491 for a row includes a WL driver 485 that activates the WL of a particular row when a read operation is initiated (e.g., in response to a switch of RCLKb from high to low), and also includes a CC driver 487 that is synchronized with the WL driver 485 so that the voltage levels on the WL and VSL connected to the Iread boost circuit can be simultaneously boosted and temporarily boosted in a synchronized manner during the read operation, the row decoder may also include discrete circuits (e.g., discrete WL drivers, not shown) for facilitating write operations. It should be noted that because peripheral circuits for facilitating write operations are well known in the art, such circuit details are omitted from this specification to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0064] refer to Figure 7 This document also discloses a method embodiment related to the above-mentioned storage circuit embodiment.

[0065] Specifically, method embodiments may include providing a storage circuit, such as described in detail above and in Figures 4A to 4C In general, the memory circuit 400 may include an array of memory cells 401, such as Figure 4A As shown, the memory cells 401 are arranged in rows an and columns AN. The memory cells 401 may be, for example, static random access memory (SRAM) cells, such as six-transistor (6T) SRAM cells, as shown in FIG. Figure 4BAs shown. The memory circuit 400 may further include word lines (WL) 440a-440n, voltage supply lines (VSL) 421a-421n, and boost circuits 480a-480n for row an. Specifically, each WL 440a-440n of each row an may be connected to all memory cells 401 in the row. Each VSL 421a-421n of each row an may be connected to all memory cells 401 in the row and may provide a positive supply voltage thereto. The memory circuit 400 may further include a controller 495 and peripheral circuitry connected to the array, the array being powered by a positive voltage rail 420 (the positive voltage rail 420 being set to a first positive supply voltage level, such as a relatively low VDD), communicating with the controller 495, and being configured to facilitate various memory functions (e.g., read operations and write operations) in response to control signals from the controller 495. As discussed in detail above, the peripheral circuits may include peripheral circuits 491 for rows (including a row decoder with boost circuits 480a-480n for row an), peripheral circuits 492 for columns (including a column decoder), and additional peripheral circuits 493 (including sensing circuits).

[0066] Method embodiments may also include using peripheral circuits 491-493 to facilitate the performance of a storage function (see process steps 704-706). The storage function may include a write operation to store a data value on a data storage node of a selected memory cell 401 and a read operation to read a stored data value from a data storage node of the selected memory cell 401. Method embodiments may also include, during a storage function for a selected memory cell in a particular row and a particular column, activating a WL of a particular row containing the selected memory cell (i.e., increasing the voltage level on the WL of the particular row from ground to a first positive voltage level (e.g., to VDD)). The WL activation of the row may be performed by a boost circuit for the particular row. Method embodiments may also include, during a storage function after activating the WL of the particular row, simultaneously and temporarily increasing the voltage levels on the WL and VSL of the particular row. The boost circuit of the particular row may boost the voltage levels on the WL and VSL of the particular row. Boosting the WL and VSL of a particular row may, for example, include simultaneously and temporarily increasing the voltage levels on the WL and VSL of the row from a first positive supply voltage level to a second positive supply voltage level (e.g., to VDD+) that is greater than the first positive voltage level, and in a synchronous manner to improve performance, reduce failures, etc.

[0067] In some cases, the row-specific boost circuits 480a-480n may specifically be row-specific read current (Iread) boost circuits that are incorporated into a row decoder of peripheral circuitry for a row and are specifically configured to facilitate performing read operations.

[0068] For example, before a read operation of a selected 6T-SRAM cell in a particular row and a particular column of a memory array begins, a BL precharge can be performed (see process step 710). Specifically, the bit lines (BLT and BLC) of the particular column can be precharged to a first positive supply voltage level. The BL precharge of the particular column can be performed by a column decoder and in response to certain control signals (e.g., from a controller).

[0069] A read operation may then be initiated (see process step 712). The initiation of a read operation may be performed by the Iread boost circuit for a particular row in response to a toggle (e.g., from high to low) of a row-specific read control signal received at an input node of the Iread boost circuit.

[0070] After the read operation is initiated, the voltage level on the WL of the particular row may be increased from ground to the first positive supply voltage level (i.e., the WL of the particular row may be activated) (see process step 714). The activation of the WL of the particular row may be performed by the Iread boost circuit of the particular row in response to the toggling of the read control signal.

[0071] After activating the WL of a particular row, the voltage levels on the WL and VSL of the particular row can be increased simultaneously and temporarily (see process step 716). The voltage levels on the WL and VSL of the particular row can be increased simultaneously and temporarily by the Iread boost circuit of the particular row. For example, the voltage levels on the WL and VSL of the particular row can be increased simultaneously and temporarily from a first positive supply voltage level to a second positive supply voltage level greater than the first positive voltage level (e.g., to VDD+) to reduce read failures (discussed in detail below).

[0072] When the voltage levels on WL and VSL of a particular row are raised, the data value stored within the 6T-SRAM cell can be determined (see process step 718). For example, the stored data value can be determined by a sensing circuit configured to detect the difference between the voltage levels (VBLT and VBLC) on the bit lines (BLT and BLC, respectively) of a particular column. For example, if the sensing circuit determines that VBLT < VBLC, then the data value stored on the first data storage node is "0," and vice versa.

[0073] It should be noted that increasing the voltage levels on the WL and VSL of a particular row in process step 716, and then performing the sensing operation in process step 718, effectively reduces the possibility of read failures. For example, if the 6T-SRAM cell stores a data value of "0" on the first data storage node 405 and a complementary data value of "1" on the second data storage node 415, then when the WL 440 connected to the 6T-SRAM cell is activated in process step 714 and the voltage levels on the WL 440 and VSL 421 connected to the 6T-SRAM cell are increased in process step 716, the drive strength of the first access transistor 404 and the second access transistor 414 will increase due to the higher voltage applied to their respective gates by WL 440. In addition, the voltage level on the second data storage node 415 will be pulled up to the second positive supply voltage level by the second pull-up transistor 412 (which is turned on). Therefore, the drive strength of the first pull-down transistor 403 will also increase due to the higher voltage applied to the gate of the first pull-down transistor 403 by the second data storage node 415. When the first data storage node 405 stores a data value of "0", the amount of read current (Iread) flowing from the precharged BLT 431 toward the first data storage node 405 is increased by increasing the drive strength of both the first access transistor 404 and the first pull-down transistor 403. As a result, the voltage level drop (i.e., VBLT) on the BLT 431 increases compared to when there is no Iread boost.

[0074] More specifically, as discussed in detail above with respect to the memory circuit embodiments, by increasing the drive strength of both the first access transistor 404 and the first pull-down transistor 403 during a read operation, the amount of read current (Iread) flowing in the direction from the precharged BLT 431 toward the first data storage node 405 (which is at ground indicating a stored data value of "0") will be increased (i.e., boosted), as will the decrease in VBLT. For example, in some embodiments, Iread can be increased from less than 0.5 μA (e.g., from approximately 0.38 μA or less) to greater than 1.5 μA (e.g., to approximately 2.1 μA or greater). Figures 6A to 6BAs shown, by boosting Iread in this manner, the difference 601 between the reduced voltage level (VBLT) on BLT 431 and the voltage level (VBLC) on BLC 432 (which, as described above with respect to the circuit embodiments, is typically maintained at a first positive voltage level) can be significantly increased. For example, in some embodiments, the difference 601 can be increased from less than 50 mV (e.g., from approximately 36 mV or less) without Iread boosting to greater than 100 mV (e.g., to approximately 149 mV or greater) with Iread boosting. The increase in the difference 601 ensures that it can be detected by the sensing circuitry and that the data value stored on the first data storage node 405 can be accurately determined at process step 718. Thus, at process step 718, read sense failures (e.g., failures in which the voltage level on BLT does not drop sufficiently to be detected, thereby causing the data value stored on the first data storage node 405 to be erroneously read as "1") can be avoided. Furthermore, by pulling up the voltage level on the second data storage node 415 to the second positive supply voltage level during the read operation and increasing the drive strength of the first pull-down transistor 403, the first pull-up transistor 402 remains off, and the first pull-down transistor 403 continuously pulls down the voltage level on the first data storage node 405 to ground. Therefore, read stability failures (also known as SNM failures) can also be avoided at process step 718.

[0075] After process step 718, a read operation can be completed by lowering the voltage levels on VSL and WL for the particular row to the first positive supply voltage level and to ground, respectively (see process step 720). A read operation can be completed by the Iread boost circuit for the particular row in response to a toggle in the state of a row-specific read control signal received at the input node of the Iread boost circuit (e.g., returning from a low level to a high level).

[0076] It should be understood that the terms used herein are for describing disclosed structures and methods and are not intended to be restrictive. For example, as used herein, the singular forms "one", "an" and "described" are also intended to include plural forms, unless the context clearly indicates other forms. In addition, as used herein, the terms "include", "comprise" and / or "have" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other characteristics, integers, steps, operations, elements, components, and / or combinations thereof. In addition, as used herein, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "up", "down", "below", "above", "parallel", "vertical" etc. are intended to describe the relative positions shown in the drawings (unless otherwise indicated), and terms such as "contact", "direct contact", "adjacent", "directly adjacent", "close by", are intended to show that at least one element is in physical contact with another element (no other components separate the elements). The term "laterally" is used herein to describe the relative position of elements, and more specifically, to indicate that an element is positioned to the side of another element, relative to above or below another element, as the elements are oriented and illustrated in the drawings. For example, an element that is laterally adjacent to another element would be next to the other element, an element that is laterally adjacent to another element would be directly next to the other element, and an element that laterally surrounds another element would be adjacent to and abut the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with the elements of other claims specifically claimed.

[0077] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A storage circuit structure, comprising: Memory cells, arranged in rows and columns; word lines for the rows, wherein each word line for each row is connected to all of the memory cells in the row; voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all of the memory cells in the row; boost circuits for the rows, wherein each boost circuit for each row is connected to the word line for the row and the voltage supply line for the row, wherein each boost circuit for each row is configured to increase voltage levels on the word line and the voltage supply line for the row during a read operation to read stored data values ​​in memory cells in the row; and a positive voltage rail at a first positive voltage level, wherein each boost circuit in each row is connected to the positive voltage rail; wherein each boost circuit of each row is configured to increase the voltage level on the word line of the row from ground to the first positive voltage level when the read operation starts; and Wherein, each boost circuit of each row is further configured to increase the voltage levels on both the word line and the voltage supply line of the row from the first positive voltage level to a second positive voltage level greater than the first positive voltage level when the voltage level on the word line has reached the first positive voltage level.

2. The structure according to claim 1, wherein Each boost circuit of each row is configured to boost the voltage levels on the word line and the voltage supply line of the row.

3. The structure according to claim 1, wherein The increase in the voltage levels on the word line and the voltage supply line for the row during the read operation boosts read current.

4. The structure according to claim 1, wherein Each boost circuit in each row includes: two coupling capacitors connected in series between the word line of the row and the voltage supply line; a word line driver having a word line driver output node connected to the word line; a coupling capacitor driver having a coupling capacitor driver output node connected to an intermediate node between the two coupling capacitors; a header switch connected between the positive voltage rail and the voltage supply line of the row; a synchronization circuit connected to the word line driver, the coupling capacitor driver, and the header switch; and A feedback path is provided from the word line driver output node to the synchronization circuit, wherein the feedback path ensures that the synchronization circuit causes the voltage levels on the word line of the row and the voltage supply line to synchronize and increase simultaneously when the word line driver switches the voltage level on the word line to the first positive voltage level.

5. The structure according to claim 1, wherein The storage unit includes a static random access memory unit.

6. A storage circuit structure comprising: Memory cells, arranged in rows and columns; word lines for the rows, wherein each word line for each row is connected to all of the memory cells in the row; Voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all the memory cells in the row boost circuits for the rows, wherein each boost circuit for each row is connected to the word line for the row and the voltage supply line for the row and is configured to synchronously and simultaneously increase the voltage levels on the word line and the voltage supply line for the row, wherein each boost circuit for each row is configured to perform the synchronous and simultaneous increase of the voltage levels on the word line and the voltage supply line for the row during a read operation; and a positive voltage rail at a first positive voltage level, wherein each boost circuit of each row is connected to the positive voltage rail; wherein each boost circuit of each row is configured to increase the voltage level on the word line of the row from ground to the first positive voltage level when the read operation starts; and Among them, each boost circuit of each row is further configured to increase the voltage level on the word line and the voltage supply line of the row from the first positive voltage level to a second positive voltage level greater than the first positive voltage level when the voltage level on the word line has reached the first positive voltage level.

7. The structure according to claim 6, further comprising: a first bit line and a second bit line of the column, wherein each memory cell in each particular row and each particular column comprises a six-transistor static random access memory cell, the six-transistor static random access memory cell comprising: a first inverter comprising a first pull-up transistor and a first pull-down transistor, the first pull-up transistor and the first pull-down transistor connected in series between the voltage supply line and a ground rail for the particular row; a second inverter cross-coupled to the first inverter and comprising a second pull-up transistor and a second pull-down transistor connected in series between the voltage supply line and the ground rail for the particular row; a first access transistor connected in series between a first bit line of the particular column and a first storage node at a junction between the first pull-up transistor and the first pull-down transistor; and a second access transistor connected between a second bit line of the particular column and a second storage node at a junction between the second pull-up transistor and the second pull-down transistor; The word line of the specific row is connected to the gates of the first access transistor and the second access transistor.

8. The structure of claim 6, further comprising a controller that causes one voltage boosting circuit for one row at a time to perform said synchronized and simultaneous increase of said voltage levels on said word line and said voltage supply line for said one row.

9. The structure according to claim 6, wherein Each boost circuit in each row includes: two coupling capacitors connected in series between the word line of the row and the voltage supply line; a word line driver having a word line driver output node connected to the word line; a coupling capacitor driver having a coupling capacitor driver output node connected to an intermediate node between the two coupling capacitors; a header switch connected between the positive voltage rail and the voltage supply line of the row; a synchronization circuit connected to the word line driver, the coupling capacitor, and the header switch; and A feedback path is provided from the word line driver output node to the synchronization circuit, wherein the feedback path ensures that the synchronization circuit causes the synchronized and simultaneous increase in the voltage levels on the word line and the voltage supply line of the row when the word line driver switches from the voltage level on the word line to the first positive voltage level.

10. The structure according to claim 9, in, The wordline driver comprises: a first p-type field effect transistor and a first n-type field effect transistor connected in series between the positive voltage rail and a ground rail, and having the wordline driver output node located at a connection between the first p-type field effect transistor and the first n-type field effect transistor; wherein the coupling capacitor driver comprises: a second p-type field effect transistor and a second n-type field effect transistor connected in series between the positive voltage rail and the ground rail, and having the coupling capacitor driver output node located at a connection between the second p-type field effect transistor and the second n-type field effect transistor; and Wherein, the header switch includes a third p-type field effect transistor.

11. The structure according to claim 10, wherein The synchronization circuit comprises: a first inverter receiving an inverted read clock signal and outputting a read clock signal, wherein the inverted read clock signal is row-specific; a second inverter receiving the read clock signal and outputting a first word line driver control signal, wherein the first word line driver control signal is applied to a gate of the first n-type field effect transistor of the word line driver; an AND gate receiving the read clock signal and a feedback signal sent from the word line driver output node along the feedback path, and outputting a synchronization control signal; an OR gate receiving the inverted read clock signal and the synchronization control signal and outputting a second word line driver control signal, wherein the second word line driver control signal is applied to a gate of the first p-type field effect transistor of the word line driver; and a NAND gate that receives the synchronization control signal and the second word line driver control signal and outputs a coupling capacitor driver control signal, wherein the coupling capacitor driver control signal is applied to gates of the second p-type field effect transistor and the second n-type field effect transistor of the coupling capacitor driver, and wherein the read clock signal is also applied to the gate of the third p-type field effect transistor of the header switch.

12. A method of operating a structure of a memory circuit, comprising: The memory circuit is provided, the memory circuit comprising: memory cells arranged in rows and columns; word lines for the rows, wherein each word line for each row is connected to all the memory cells in the row; and voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all the memory cells in the row; and boosting circuits for the rows, wherein each boosting circuit for each row is connected to the word line for the row and the voltage supply line for the row; and increasing the voltage levels on the word line and the voltage supply line of the row by a voltage boost circuit of the row, wherein the storage circuit further comprises a positive voltage rail at a first positive voltage level; wherein each boost circuit of each row is connected to the positive voltage rail; The method further comprises performing a read operation to read the stored data values ​​in the memory cells in the row; and Wherein, the execution of the read operation includes: at the beginning of the read operation, increasing the voltage level on the word line of the row from ground to the first positive voltage level through the boost circuit of the row; and when the voltage level on the word line of the row reaches the first positive voltage level, the increase of the voltage levels on the word line and the voltage supply line of the row causes the voltage levels on both the word line and the voltage supply line of the row to increase from the first positive voltage level to a second positive voltage level greater than the first positive voltage level.

13. The method according to claim 12, wherein: The increasing of the voltage levels on the word line and the voltage supply line of the row is synchronized and simultaneous.

14. The method according to claim 12, wherein: During a read operation, the increasing of the voltage levels on the word line and the voltage supply line of the row is performed to boost read current.

15. The method according to claim 14, wherein By boosting the read current during the read operation, the method reduces the probability of read failures.

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