For retrieving status information of memory devices

Abstract

This application relates to status information retrieval for a memory device. In some instances, a memory device may include a set of status registers, each of which can be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information and an indication to output status information from one or more specific status registers in response to the command. In response to the command and the indication, the memory device may output status information containing any type of status information from any number of status registers in a single stream or burst.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 119,290, filed December 11, 2020, entitled “Status Information Retrieval for a Memory Device”, by Tanpairoj et al., which is assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to the retrieval of status information for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (such as DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (such as NAND memory cells) can retain their programmed state for a long time, even in the absence of external power. Summary of the Invention

[0006] Describe a device. In some instances, the device may include: a set of status registers, each configured to store a corresponding set of status information for a memory device; and a controller for the memory device, wherein the controller is coupled to the set of status registers and configured such that the device: receives a command to output status information associated with the memory device; receives an indication from one or more of the status registers in the set of status registers; and outputs one or more sets of status information corresponding to the one or more status registers in response to the command and the indication from the one or more status registers.

[0007] Describe an apparatus. In some instances, the apparatus may include a controller for a memory device, wherein the controller is configured such that the apparatus: transmits a command for outputting status information associated with the memory device to the memory device; transmits an indication of one or more status registers from a set of status registers associated with the memory device to the memory device, each status register in the set of status registers being associated with a corresponding set of status information for the memory device; and receives from the memory device, in response to the command and the indication of the one or more status registers, one or more sets of status information corresponding to the one or more status registers.

[0008] A non-transitory computer-readable medium storing code is described. In some instances, the non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a command to output status information associated with a memory device, wherein the memory device includes a set of status registers each configured to store a set of corresponding status information for the memory device; receive an indication from one or more of the status registers in the set of status registers; and, in response to the command and the indication from the one or more status registers, output one or more sets of status information corresponding to the one or more status registers.

[0009] A non-transitory computer-readable medium storing code is described. In some instances, the non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit a command for outputting status information associated with the memory device to the memory device; transmit an indication of one or more status registers from a set of status registers associated with the memory device to the memory device, each status register being associated with a corresponding set of status information for the memory device; and receive one or more sets of status information corresponding to the one or more status registers from the memory device in response to the command and the indication of the one or more status registers. Attached Figure Description

[0010] Figure 1 This document describes examples of systems that support the retrieval of status information for memory devices, based on the examples disclosed herein.

[0011] Figure 2 This document describes an example of a timing diagram that supports the retrieval of state information for a memory device, based on the examples disclosed herein.

[0012] Figure 3 A block diagram illustrating a memory device for retrieving status information of a memory device according to aspects of this disclosure.

[0013] Figure 4 A block diagram illustrating an apparatus for retrieving status information of a memory device according to aspects of this disclosure.

[0014] Figure 5 and 6 The flowchart illustrates one or more methods for retrieving state information for a memory device, based on examples disclosed herein. Detailed Implementation

[0015] Some memory systems may include multiple memory devices and a memory system controller configured to manage the multiple memory devices. In some cases, such memory systems may be referred to as managed memory systems. For example, a system that includes multiple NAND memory devices (e.g., a die containing NAND memory cells, which may be referred to as a NAND die) and a memory system controller may be referred to as a managed NAND (mNAND) system. In some cases, the memory system controller may be configured to exchange signaling with a host device of the memory devices and exchange related signaling with the memory devices. For example, a host device may send commands to the memory system controller (e.g., read or write commands), and the memory system controller may transmit corresponding commands to the memory devices (e.g., read, program, or erase commands) in response to at least some of the commands issued by the host. Thus, the memory devices may perform various operations in response to commands issued by the memory system controller to satisfy commands issued by the corresponding host.

[0016] In some cases, the memory system controller may request various types of status information from the memory device. For example, the memory system controller may issue a command to the memory device and then later (e.g., after issuing one or more commands to one or more other memory devices) request status information from the memory device regarding the status of the operation commanded by the previous command (e.g., whether the operation was successful, unsuccessful, or pending). In some cases, the memory system controller may additionally or alternatively request one or more other types of status information, such as whether the memory device or a portion of the memory device is in a ready or busy state, or the temperature status or power status of the memory device, and other instances.

[0017] Several sets of status information (e.g., several bytes of status information) may be stored in corresponding status registers at the memory device. In some cases, at least some status registers may be dedicated to corresponding portions of the memory device (e.g., storing status information specific to a corresponding portion of the memory device), such as a corresponding plane of a memory array within the memory device or other addressable units of the memory within the memory device.

[0018] Commands used to output status information for a memory device are referred to herein as status commands. In some memory systems, the memory system controller may have to issue (e.g., transmit) a separate status command to the memory device for each set of status information desired by the memory system controller. For example, the memory system controller may have to issue a first status command for the memory device to output a first set of status information from a first status register, a second status command for the memory device to output a second set of status information from a second status register, and so on. Furthermore, in some cases, for each issued status command, the memory system controller may also have to issue an indication of a corresponding address, where the indicated address corresponds to a memory device (e.g., in multiple memory devices) or a portion of a memory device (e.g., a plane of an array within a memory device) that is expected to correspond to the issued status command. For example, to obtain status information for a first plane of a first memory device, the memory system controller may have to issue a status command and the address of the first memory device to the first memory device, the first plane, or both. Therefore, in some cases, the memory system controller may have to issue both a command and an address for each status register from which the memory system controller expects status information. Alternatively, in some cases, the memory system controller may have to issue different types of status commands to obtain different types of status information from the memory device (e.g., from different status registers that store different types of status information).

[0019] Using a separate status command or a separate combination of status command and address for each set of status information that the memory device will output (e.g., each status register that the memory device will output its contents) can lead to undesirable signaling overhead. For example, for each byte of status information that the memory system controller expects, the memory system controller may have to output both a status command and an address indicating both. Furthermore, in some cases, status-related signaling can be exchanged between the memory system controller and the memory device via the same bus as the data bus; therefore, this signaling overhead can affect the amount of data exchanged, latency, or both. Alternatively, using different types of status commands for different types of status information introduces undesirable complexity and can become unsustainable as the complexity of the memory device increases and additional types of status information are desired. This signaling overhead and complexity problem is further exacerbated by an increase in the number of memory dies in the memory system, an increase in the processing power requirements of the memory system, or both.

[0020] As described herein, a single status command may be issued by the memory system controller to request the memory device to output multiple sets of different status information (e.g., from multiple different status registers). Alternatively, a single type of status command may be issued by the memory system controller to request the memory device to output multiple different types of status information. For example, the memory system controller may issue a single status command and a single indication of a status register, and status information will be output from the status register in response to the single status command. The indication of the status register may instruct the memory device to output the contents of a single indicated status register or multiple indicated status registers in response to the single status command, which may include the contents of all status registers of the memory device. Thus, multiple sets of status information from multiple status registers and possibly containing multiple different types of status information may be streamed from the memory device in response to a single status command and associated indication (e.g., as a single burst direct-connect output). Therefore, the teachings herein may reduce signaling overhead, reduce latency in data exchange with the memory device, reduce system complexity, enhance system adaptability (because new types of status information and status registers can be introduced), or any combination thereof, and other benefits that should be understood by those skilled in the art.

[0021] While specific examples are explained herein in the context of a memory system controller issuing status commands and exchanging related signaling with the memory device, it should be understood that the teachings herein can also be applied in the context of a host device directly issuing status commands and exchanging related signaling with the memory device (e.g., in the context of an unmanaged memory system or device). Furthermore, while specific examples are explained herein in the context of a NAND memory device, it should be understood that the teachings herein can be extended to memory devices and memory systems containing any type of memory cell.

[0022] First, refer to Figure 1 The features of this disclosure are described within the context of the system described. (Refer to...) Figure 2 The features of this disclosure are described within the context of a timing diagram. These and other features of this disclosure are illustrated in reference to... Figures 3 to 6 The device diagrams and flowcharts described are further illustrated and referenced in the description of the device diagrams and flowcharts related to the retrieval of state information for memory devices.

[0023] Figure 1 This is an example of a system 100 that supports the retrieval of status information for a memory device, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0024] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital Storage (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0025] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or any other computing device containing memory and processing devices.

[0026] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system 105 may use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0027] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Serial Advanced Technology Attachment (SATA) interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM slot interfaces), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface of each memory device 130 included in memory system 110 or via a corresponding physical host interface of each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0028] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The examples show two memory devices 130-a and 130-b, but it should be understood that the memory system 110 may contain any number of memory devices 130. Furthermore, it should be understood that when the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0029] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface). The memory system controller 115 may include control components configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which are generally referred to as access operations. The memory system controller 115 may use associated protocols to couple to and exchange signaling with the memory device 130 via an interface, wherein the protocols may be the same as or different from the physical host interface. For example, the memory system controller 115 may use the ONFI protocol to exchange signaling with the memory device 130.

[0030] In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0031] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, discarded item collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0032] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0033] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and may be used within local memory 120 for subsequent retrieval of host system 105 or manipulation (e.g., updates) by host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0034] although Figure 1 An example of memory system 110 has been described as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be internal to memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, in some cases, one or more functions attributed herein to memory system controller 115 may be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. Examples of managed memory devices are mNAND devices, which may be, for example, UFS devices, eMMC devices, flash devices, USB flash devices, SD cards, or SSDs, and other possibilities.

[0035] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells.

[0036] In some instances, memory device 130 may each include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115.

[0037] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0038] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) when configured to store two bits of information, as three-level cells (TLC) when configured to store three bits of information, as four-level cells (QLC) when configured to store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density than SLC memory cells, but may involve narrower read or write margins or greater complexity in some cases to support the circuitry.

[0039] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0040] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0041] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or read operation), and block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, an older page 175 may not be updatable in some cases until the entire block 170 containing page 175 is erased.

[0042] Each memory device 130 may include a set of corresponding status registers 140, and each status register 140 may store a set of corresponding status information for the memory device 130. In some cases, at least some status registers 140 of the memory device may be dedicated to a corresponding portion of the memory device 130 (e.g., a corresponding plane 165 of the memory device 130) and may store a set of status information containing at least some information specific to said corresponding portion of the memory device 130. For example, status registers 140 may store information about the status of a previously commanded operation (e.g., success, failure, paused, pending), whether the memory device 130 or a portion thereof (the array of memory devices 130, the cache of memory devices 130, or plane 165 of memory devices 130 or other corresponding portions) is in a ready or busy state, temperature information for the memory device 130 or a portion thereof, or power or voltage information for the memory device 130 or a portion thereof. In some cases, different status registers 140 may store different types of status information. Therefore, for example, multiple status registers 140 may correspond to the same portion of memory device 130 but store different types of status information for that portion of memory device 130. Alternatively, some status registers 140 may store several sets of status information specific to a corresponding portion of memory device 130, while one or more other status registers 140 may collectively store several sets of status information applied to memory device 130, as well as other possibilities that should be understood by those skilled in the art.

[0043] In some examples, the memory system controller 115 may request the memory device 130 to output status information. For example, the memory system controller 115 may transmit a status command to the memory device to check the status of an operation corresponding to a command previously sent to the memory device 130 or to see if the memory device 130 or a portion thereof is ready for another command. Whether for these or any other number of reasons, the memory system controller 115 may transmit the status command along with an indication of status information output by the memory device 130 in response to the status command to the memory device 130. For example, the indication of status information output by the memory device 130 in response to the status command may be an indication of one or more status registers 140 of the memory device 130, and the memory device 130 may transmit status information stored by any of the status registers 140 included in the indicated group to the memory system controller 115 in response to a single status command.

[0044] The indication of one or more status registers 140 associated with a status command can instruct any number of status registers 140 to output status information (e.g., one status register 140, multiple status registers 140, or all status registers 140 of memory device 130), so that memory device 130 can output any number of groups of status information (e.g., bytes) in response to a single status command.

[0045] System 100 may include any number of non-transitory computer-readable media supporting the retrieval of status information for the memory device. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0046] As noted elsewhere, although specific instances are described herein in the context of memory system controller 115 transmitting status commands and associated indications of one or more status registers 140 to memory device 130 and responsively receiving one or more sets of status information, it should be understood that in some cases, host system 105 may alternatively transmit status commands and associated indications of one or more status registers 140 to memory device 130 and responsively receive one or more sets of status information (e.g., in system 100 where memory system controller 115 is absent).

[0047] Figure 2 This is an example of a timing diagram 200 illustrating signaling supporting the retrieval of status information for a memory device, based on the examples disclosed herein. Timing diagram 200 illustrates the types of information transmitted back and forth to the memory device. Figure 2 The example describes information as being exchanged via a single bus 210, but it should be understood that in other examples, some information may alternatively be exchanged via one or more different buses. In some examples, the memory device may be used as a reference. Figure 1 An example of the described memory device 130. The memory device may be, for example, referenced in the following text. Figure 1 The memory system controller 115 described or referenced Figure 1 The host system 105 switch described Figure 2 The signaling is illustrated in the example.

[0048] During the first time period t1, the memory system controller or host system may transmit a status command 215 to the memory device via bus 210. The status command 215 may instruct the memory device to output status information. In some examples, the status command 215 may not be specified but may be applicable to a specific status register from which the memory device will output status information or to a specific type of status information that the memory device will output. The status register may be a reference... Figure 1 The status register 140 is described.

[0049] During the second time period t2, the memory system controller or host system may transmit the SR indication 225 to the memory device via bus 210. The SR indication 225 may be associated with a status command 215 (e.g., based on the relative timing of receiving the status command 215 and the SR indication 225). The SR indication 225 may indicate from which status register(s) the memory device 130 will output status information in response to the status command 215. The SR indication 225 may indicate any number of status registers of the memory device (e.g., one status register, multiple status registers, or all status registers). Although in Figure 2 In the examples described, SR indication 225 is separate from and follows status command 215, but it should be understood that in some instances, SR indication 225 may alternatively be incorporated into status command 215 (e.g., it is a component of status command 215).

[0050] During the third time period t3, the memory device can output status information to the memory system controller or host system via bus 210. The status information output in a single stream (e.g., as a single burst) can include status information from one or more status registers indicated by SR indicator 225. Therefore, because SR indicator 225 can indicate any number of status registers of the memory device, the memory device can output status information from any number of status registers (e.g., any number from 1 to N, where the memory device may contain N status registers) during the third time period t3 in response to the same status command 215 and SR indicator 225. For example, in Figure 2 In the example described, SR1 240 may be the status information from the first status register indicated by SR indication 225 (e.g., stored by the first status register), SR2 245 may be the status information from the second status register indicated by SR indication 225, SR3 250 may be the status information from the third status register indicated by SR indication 225, and SRN 255 may be the status information from the Nth status register indicated by SR indication 225.

[0051] In some cases, SR indicator 225 may indicate a first status register (e.g., SR1 240) and a number of status registers. For example, each status register of the memory device may have a unique corresponding address (e.g., an index). The address may, for example, be within a status register-specific address space (e.g., an index set). SR indicator 225 may indicate the lowest address status register in a group of one or more status registers and a number of status registers (e.g., any number from 1 to N). The memory device may output status information from the status register with the indicated address and from any consecutive address status registers as needed to generate the indicated number of status registers. Thus, for example, if the indicated number is 1, the memory device may output status information from the status register with the indicated address and nothing else, or if the indicated number is greater than 1, the memory device may output status information from the status register with the indicated address and one or more others (e.g., one or more other status registers with progressively increasing or otherwise sequentially adjacent associated addresses or indices), possibly including all status registers of the memory device.

[0052] In some cases, the SR indicator 225 may indicate (e.g., contain) a value corresponding to a unique status register or a unique combination of status registers. For example, an 8-bit SR indicator 225 can indicate up to 256 (256) unique combinations of one or more specific status registers based on a mapping between the value of the SR indicator 225 and corresponding unique combinations of one or more specific status registers. The memory system controller or host system may indicate the value via the SR indicator 225 using a lookup table, and the memory device may use, for example, a matching lookup table to identify one or more status registers indicated by the SR indicator 225. Examples of mappings between possible values ​​of the SR indicator 225 and corresponding unique combinations of one or more specific status registers are shown in Table 1 below.

[0053] numerical values Status Register 0 0 1 1 2 2 3 1 and 2 4 4 5 4 and 0 ... ... ... ... ... ... 255 All bytes

[0054] Table 1

[0055] For example, as shown in Table 1, a value of zero (0) in SR indicator 225 may indicate that the memory device will output a set of status information from a first status register having address or index zero (0), and a value of one (1) in SR indicator 225 may indicate that the memory device will output a set of status information from a second status register having address or index one (1). Alternatively, a value of three (3) in SR indicator 225 may indicate that the memory device will output a set of status information from both a second status register having address or index one (1) and a third status register having address or index two (2). Any unique combination of any number of status registers may be defined and mapped to (e.g., assigned) a corresponding value indicated by SR indicator 225. In some cases, a value (e.g., 255 (255) shown in the example in Table 1) may indicate that, when included in SR indicator 225, the memory device will output the status information stored in each status register (i.e., all status registers) of the memory device in response to the associated status command 215.

[0056] In some cases, SR indicator 225 may indicate (e.g., include) a bitmap, wherein each bit of the bitmap may correspond to a corresponding status register of the memory device, and wherein the logical value of the bit may indicate whether a set of status information stored in the corresponding status register will be output by the memory device in response to the associated status command 215. Thus, by setting one or more bits of the bitmap to a specific logical value (e.g., a (1)), the memory system controller or host device may instruct the memory device to output one or more sets of status information stored in any number of one or more status registers. For example, if all bits of SR indicator 225 are set to a specific logical value, then the memory device may output the status information stored in each status register (i.e., all status registers) of the memory device in response to the associated status command 215.

[0057] As described herein, status information from any number of status registers can be output by the memory device in response to a single status command 215 and associated SR indication 225 in a single burst (e.g., without intermediary signaling). This or other features described herein can reduce signaling overhead (e.g., quantity) via bus 210 associated with the status information reported by the memory device. Additionally or alternatively, this or other features described herein can enhance the availability of bus 210 or other resources (e.g., processing resources of the memory device, memory system controller, or host system) to exchange other signaling (e.g., data), which can provide throughput benefits, latency benefits, or both. Additionally or alternatively, this or other features described herein can reduce the overall system complexity by eliminating the need for separate types of status commands for different types of status information, and can improve the system's adaptability to future increases in the amount or type of status information stored by the memory device, or any combination thereof. Further benefits will be apparent to those skilled in the art.

[0058] In some examples, the memory system controller or host system may transmit a status command 215 and an associated SR indication 225 to the memory device based on one or more previous commands, such as access (e.g., read, write, or erase) commands, that have been transmitted to the memory device. For example, during a period prior to t1, the memory system controller or host system may have transmitted commands for performing operations (e.g., access operations) on the memory device, and the memory system controller or host system may transmit the status command 215 and the associated SR indication 225 to check the status of the operation, the availability of the memory device 130 or a portion thereof for subsequent (e.g., pending commands) operations, or any combination thereof.

[0059] Figure 3 A block diagram 300 illustrates a memory device 305 supporting state information retrieval for a memory device, based on examples disclosed herein. The memory device 305 may be used as a reference. Figure 1 and 2 Examples of aspects of the described memory device. Memory device 305 may include a receiving component 310, an output component 315, and an identification component 320. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0060] The receiving component 310 can receive commands that output status information associated with the memory device. In some instances, the receiving component 310 can receive indications from one or more status registers in a set of status registers.

[0061] The output component 315 can output one or more sets of status information corresponding to one or more status registers in response to a command and an indication of one or more status registers.

[0062] In some instances, the instruction may indicate multiple status registers in a set of status registers, and the output component 315 may output several sets of corresponding status information for the multiple status registers in response to commands and instructions.

[0063] In some instances, the instruction may indicate all the status registers in a set of status registers, and the output component 315 may output several sets of corresponding status information for each of the status registers in the set of status registers in response to the command and instruction.

[0064] In some instances, the instruction may indicate a first status register in a set of status registers and a certain number of status registers, and the output component 315 may, in response to the command and instruction, output a set of corresponding status information for each of the certain number of status registers equal to the indicated number, the certain number of status registers including the first status register.

[0065] In some instances, the indicator may indicate a value in a set of values, and the identification component 320 may identify one or more status registers based on a mapping between a set of values ​​and a set of status registers.

[0066] In some cases, each status register in a set of status registers is associated with a corresponding address within an address space specific to that set of status registers, and a number of status registers correspond to a first status register and one or more status registers each having an address following the address of the first status register. In some cases, the indication of one or more status registers comprises a bitmap, each bit of which corresponds to a corresponding status register in the set of status registers and indicates whether the memory device will output corresponding status information for that corresponding status register. In some cases, the status registers in a set of status registers correspond to corresponding portions of a memory array within the memory device, and a set of corresponding status information for the status registers comprises a set of bits, each indicating a different type of status information associated with the corresponding portion of the memory array.

[0067] In some cases, each status register in at least a subset of a set of status registers is associated with a corresponding plane of the memory array within the memory device. In some cases, a set of status information included in one or more sets indicates whether an operation performed by the memory device has failed or successfully completed, whether the memory device or a portion thereof is idle or busy, temperature information for the memory device or a portion thereof, power or voltage information for the memory device or a portion thereof, or any combination thereof. In some cases, a set of status registers and the memory array within the memory device reside on the same die.

[0068] Figure 4A block diagram 400 illustrates a device 405 supporting status information retrieval for a memory device, based on an example disclosed herein. Device 405 may be used as a reference. Figure 1 and 2 Examples of aspects of the described host device may be provided for reference. Figure 1 and 2 An example of a controller within an mNAND device is described. Device 405 may include a transmission component 410, a receiving component 415, and an identification component 420. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0069] The transmission component 410 can transmit commands for outputting status information associated with the memory device to the memory device. In some instances, the transmission component 410 can transmit indications of one or more status registers from a set of status registers associated with the memory device, each of the status registers being associated with a corresponding set of status information for the memory device.

[0070] The receiving component 415 can receive one or more sets of status information corresponding to one or more status registers from the memory device in response to a command and an indication of one or more status registers.

[0071] In some instances, the instruction may indicate all the status registers in a set of status registers, and the receiving component 415 may receive several sets of corresponding status information for each of the status registers in the set of status registers in response to the command and instruction.

[0072] In some instances, the instruction may indicate a first status register in a set of status registers and a certain number of status registers, and the receiving component 415 may, in response to the command and instruction, receive a set of corresponding status information for each of the certain number of status registers equal to the indicated number, the certain number of status registers including the first status register.

[0073] The identification component 420 can identify a value in a set of values ​​based on a mapping between a set of values ​​and a set of status registers, wherein the indications of one or more status registers contain values.

[0074] In some cases, each status register in a set of status registers is associated with a corresponding address within an address space specific to said set of status registers, and a number of status registers correspond to a first status register and one or more status registers each having an address following the address of the first status register. In some cases, the indication of one or more status registers includes a bitmap, each bit of which corresponds to a corresponding status register in the set of status registers and indicates whether the memory device will output corresponding status information for the corresponding status register. In some cases, a set of status information included in one or more sets of status information indicates whether an operation performed by the memory device has failed or successfully completed, whether the memory device or a portion of the memory device is idle or busy, temperature information for the memory device or a portion of the memory device, power or voltage information for the memory device or a portion of the memory device, or any combination thereof.

[0075] In some instances, the memory device is on a first die within the device, and the controller is on a second die within the device. In some instances, the controller is coupled to the memory device via a first interface, configured to be coupled to a host device for the memory device via a second interface, and configured to receive commands for the memory device from the host device via the second interface.

[0076] Figure 5 The illustration shows a flowchart of one or more methods 500 for retrieving state information of a memory device, in accordance with aspects of this disclosure. Operation of method 500 may be implemented by the memory device or its components described herein. For example, operation of method 500 may be performed by reference to... Figure 3 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0077] At 505, a command can be received by the memory device to output status information associated with the memory device, wherein the memory device includes a set of status registers, each configured to store a set of corresponding status information for the memory device. Operation 505 can be performed according to the methods described herein. In some instances, aspects of operation 505 may be referenced from... Figure 3 The described receiving component is executed.

[0078] In operation 510, an indication from one or more status registers in a set of status registers can be received by a memory device. Operation 510 can be performed according to the methods described herein. In some instances, aspects of operation 510 may be referenced. Figure 3 The described receiving component is executed.

[0079] In step 515, one or more sets of status information corresponding to one or more status registers can be output from the memory device in response to a command and indications from one or more status registers. Operation 515 can be performed according to the methods described herein. In some instances, aspects of operation 515 may be derived from references... Figure 3 The output component described is executed.

[0080] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command to output status information associated with a memory device, wherein the memory device includes a set of status registers each configured to store a set of corresponding status information for the memory device; receiving indications from one or more of the status registers in the set of status registers; and outputting one or more sets of status information corresponding to the one or more status registers in response to the command and the indications from the one or more status registers.

[0081] In some instances of the method 500 and apparatus described herein, the indication may indicate a set of status registers in a set of status registers, and the operation, feature, component, or instruction for outputting one or more sets of status information may include an operation, feature, component, or instruction for outputting several sets of corresponding status information for a set of status registers in response to a command and indication.

[0082] In some instances of the method 500 and apparatus described herein, the indication may indicate all the status registers in a set of status registers, and the operation, feature, component, or instruction for outputting one or more sets of status information may include the operation, feature, component, or instruction for outputting several sets of corresponding status information for each of the status registers in the set of status registers in response to the command and indication.

[0083] In some instances of the method 500 and apparatus described herein, an instruction may indicate a first state register in a set of state registers and a number of state registers, and an operation, feature, component, or instruction for outputting one or more sets of state information may include an operation, feature, component, or instruction for outputting a set of corresponding state information for each of the number of state registers equal to the indicated number, in response to a command and instruction, said number of state registers including the first state register.

[0084] In some instances of the method 500 and apparatus described herein, each of a set of status registers may be associated with a corresponding address within an address space specific to the set of status registers, and a number of status registers may correspond to a first status register and one or more status registers each having an address following the address of the first status register.

[0085] In some instances of the method 500 and apparatus described herein, the indication may indicate a value in a set of values, and the method or apparatus may further include operations, features, components or instructions for identifying one or more status registers based on a mapping between a set of values ​​and a set of status registers.

[0086] In some instances of the method 500 and apparatus described herein, the indication of one or more status registers comprises a bitmap, each bit of which corresponds to a corresponding status register in a set of status registers and indicates whether the memory device may output corresponding status information for the corresponding status register.

[0087] In some instances of the method 500 and apparatus described herein, a set of status registers corresponds to a corresponding portion of a memory array within a memory device, and a set of corresponding status information for the status registers includes a set of bits, each indicating a different type of status information associated with the corresponding portion of the memory array.

[0088] In some instances of the method 500 and apparatus described herein, each state register in at least a subset of a set of state registers may be associated with a corresponding plane of a memory array within a memory device.

[0089] In some instances of the method 500 and apparatus described herein, a set of status information included in one or more sets of status information indicates whether an operation performed by the memory device has failed or been successfully completed, whether the memory device or a portion thereof is idle or busy, temperature information for the memory device or a portion thereof, power or voltage information for the memory device or a portion thereof, or any combination thereof.

[0090] In some instances of the method 500 and apparatus described herein, a set of status registers and a memory array within the memory device may be on the same die.

[0091] Figure 6 The illustration shows a flowchart of one or more methods 600 for retrieving status information of a memory device, in accordance with aspects of this disclosure. Operation of method 600 may be implemented by a host device, an mNAND controller, or a component of the host device or mNAND controller described herein. For example, operation of method 600 may be implemented by reference to... Figure 4 The described device performs the functions. In some instances, a host (e.g., a host device and / or an mNAND controller) may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0092] At 605, commands can be transmitted for outputting status information associated with the memory device. Operation 605 can be performed according to the methods described herein. In some instances, aspects of operation 605 may be derived from references... Figure 4 The described transport component is executed.

[0093] At 610, indications of one or more status registers from a set of status registers associated with a memory device can be transmitted, each status register in the set associated with a corresponding set of status information for the memory device. Operation 610 can be performed according to the methods described herein. In some instances, aspects of operation 610 may be derived from references... Figure 4 The described transport component is executed.

[0094] In operation 615, one or more sets of status information corresponding to one or more status registers can be received in response to a command and indications from one or more status registers. Operation 615 can be performed according to the methods described herein. In some instances, aspects of operation 615 may be derived from references. Figure 4 The described receiving component is executed.

[0095] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a command to the memory device for outputting status information associated with the memory device; transmitting an indication of one or more status registers from a set of status registers associated with the memory device, each status register being associated with a corresponding set of status information for the memory device; and receiving one or more sets of status information corresponding to the one or more status registers from the memory device in response to the command and the indication of the one or more status registers.

[0096] In some instances of the method 600 and apparatus described herein, the indication may indicate all the status registers in a set of status registers, and the operation, feature, component, or instruction for receiving one or more sets of status information may include the operation, feature, component, or instruction for receiving several sets of corresponding status information for each of the status registers in the set of status registers in response to a command and indication.

[0097] In some instances of the method 600 and apparatus described herein, the indication may indicate a first status register in a set of status registers and a number of status registers, and the operation, feature, component, or instruction for receiving one or more sets of status information may include an operation, feature, component, or instruction for receiving a set of corresponding status information for each of the number of status registers equal to the indicated number in response to a command and indication, said number of status registers including the first status register.

[0098] In some instances of the method 600 and apparatus described herein, each of a set of status registers may be associated with a corresponding address within an address space specific to the set of status registers, and a number of status registers may correspond to a first status register and one or more status registers, each having an address following the address of the first status register.

[0099] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for identifying values ​​in a set of values ​​based on a mapping between a set of values ​​and a set of status registers, wherein the indications of one or more status registers contain the values.

[0100] In some instances of the method 600 and apparatus described herein, the indication of one or more status registers includes a bitmap, each bit of which corresponds to a corresponding status register in a set of status registers and indicates whether the memory device may output corresponding status information for the corresponding status register.

[0101] In some instances of the method 600 and apparatus described herein, a set of status information included in one or more sets of status information indicates whether an operation performed by the memory device has failed or been successfully completed, whether the memory device or a portion thereof is idle or busy, temperature information for the memory device or a portion thereof, power or voltage information for the memory device or a portion thereof, or any combination thereof.

[0102] It should be noted that the above methods describe possible implementation schemes, and the operations and steps may be rearranged or otherwise modified, and other implementation schemes are possible. Furthermore, portions from two or more of the methods may be combined.

[0103] Describe an apparatus. The apparatus may include: a set of status registers, each configured to store a corresponding set of status information for a memory device; and a controller for the memory device, wherein the controller is coupled to the status registers and configured such that the apparatus: receives a command to output status information associated with the memory device; receives an indication from one or more of the status registers in the set of status registers; and outputs one or more sets of status information corresponding to the one or more status registers in response to the command and the indication from the one or more status registers.

[0104] In some instances, the indication may indicate multiple status registers in the set of status registers, and in order to output the one or more sets of status information, the controller may be configured such that the device responds to the command and the indication by outputting several sets of corresponding status information for the set of status registers.

[0105] In some instances, the indication may indicate all the status registers in the set of status registers, and in order to output the one or more sets of status information, the controller may be configured such that the device, in response to the command and the indication, outputs several sets of corresponding status information for each of the set of status registers.

[0106] In some instances, the indication may indicate a first status register and a number of status registers in the set of status registers, and in order to output the one or more sets of status information, the controller may be configured such that the device, in response to the command and the indication, outputs the set of corresponding status information for each of the number of status registers in the set of status registers equal to the indicated number, the number of status registers including the first status register.

[0107] In some instances, each of the set of status registers may be associated with a corresponding address within an address space specific to the set of status registers, and the number of status registers may correspond to the first status register and one or more status registers each having an address following the address of the first status register.

[0108] In some instances, the indication may indicate a value from a set of values, and the controller may be configured such that the device identifies one or more status registers based on a mapping between the set of values ​​and the set of status registers.

[0109] In some instances, the indication of the one or more status registers includes a bitmap, each bit of which corresponds to a corresponding status register in the set of status registers and indicates whether the device may output the corresponding status information for the corresponding status register.

[0110] Some instances of the device may include a memory array within the memory device, wherein a status register in a set of status registers corresponds to a corresponding portion of the memory array, and wherein the set of corresponding status information for the status registers includes a set of bits, each indicating a different type of status information associated with the corresponding portion of the memory array.

[0111] Some instances of the device may include a memory array within the memory device, wherein each state register in at least a subset of the set of state registers may be associated with a corresponding plane of the memory array.

[0112] In some instances, one set of status information included in the one or more sets of status information may indicate whether an operation performed by the memory device has failed or been successfully completed, whether the memory device or a portion thereof is idle or busy, temperature information for the memory device or a portion thereof, power or voltage information for the memory device or a portion thereof, or any combination thereof.

[0113] Some instances of the device may include a memory array within the memory device, wherein the set of status registers, the controller, and the memory array may be on the same die.

[0114] Describe an apparatus. The apparatus may include a controller for a memory device, wherein the controller is configured such that the apparatus: transmits a command for outputting status information associated with the memory device to the memory device; transmits an indication of one or more status registers from a set of status registers associated with the memory device to the memory device, each status register in the set of status registers being associated with a corresponding set of status information for the memory device; and receives from the memory device one or more sets of status information corresponding to the one or more status registers in response to the command and the indication of the one or more status registers.

[0115] In some instances, the indication may indicate all the status registers in the set of status registers, and in order to receive the one or more sets of status information, the controller may be configured such that the device, in response to the command and the indication, receives several sets of corresponding status information for each of the set of status registers.

[0116] In some instances, the indication may indicate a first status register and a number of status registers in the set of status registers, and in order to receive the one or more sets of status information, the controller may be configured such that the device, in response to the command and the indication, receives the set of corresponding status information for each of the number of status registers in the set equal to the indicated number, the number of status registers including the first status register.

[0117] In some instances, each of the set of status registers may be associated with a corresponding address within an address space specific to the set of status registers, and the number of status registers may correspond to the first status register and one or more status registers each having an address following the address of the first status register.

[0118] In some instances, the controller may be further configured such that the device identifies a value in the set of values ​​based on a mapping between a set of values ​​and the set of status registers, wherein the indication of one or more status registers includes the value.

[0119] In some instances, the indication of the one or more status registers includes a bitmap, each bit of which corresponds to a corresponding status register in the set of status registers and indicates whether the device may output the corresponding status information for the corresponding status register.

[0120] In some instances, the memory device may be on a first die within the device, and the controller may be on a second die within the device.

[0121] In some instances, the controller may be coupled to the memory device via a first interface, the controller may be configured to be coupled to a host device for the memory device via a second interface, and the controller may be configured to receive commands for the memory device from the host device via the second interface.

[0122] In some instances, one set of status information included in the one or more sets of status information indicates whether an operation performed by the memory device has failed or been successfully completed, whether the memory device or a portion thereof is idle or busy, temperature information for the memory device or a portion thereof, power or voltage information for the memory device or a portion thereof, or any combination thereof.

[0123] The information and signals described herein can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have various bit widths.

[0124] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if there is any conductive path between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) can be open or closed, depending on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0125] The term "coupling" refers to a condition that moves from an open-circuit relationship between components (where signals cannot currently be transmitted between components via a conductive path) to a closed-circuit relationship between components (where signals can be transmitted between components via a conductive path). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0126] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch positioned between two components is turned on, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller affects the flow of signals between the components using previously permitted conductive paths.

[0127] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0128] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0129] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed descriptions include specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0130] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dashed reference numeral followed by a second reference numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0131] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on a computer-readable medium or transmitted as one or more instructions or code via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the above-described functions can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0132] For example, the various specification boxes and modules described in connection with this disclosure may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0133] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0134] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically copy data magnetically, while optical discs copy data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0135] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: a set of status registers each configured to store a set of corresponding status information for a memory device; and a controller for the memory device, wherein the controller is coupled with the set of status registers and configured to cause the memory system to: receive a command to output status information associated with the memory device; receive an indication of one or more status registers of the set of status registers, wherein the indication indicates a first status register of the set of status registers and a value indicating a number of status registers of the set of status registers; and output one or more sets of status information corresponding to the one or more status registers in response to the command and the indication of the one or more status registers.

2. The memory system of claim 1, wherein the indication indicates a plurality of status registers of the set of status registers, and wherein to output the one or more sets of status information, the controller is configured to cause the memory system to: output a number of sets of corresponding status information for the plurality of status registers in response to the command and the indication.

3. The memory system of claim 1, wherein the indication indicates all status registers of the set of status registers, and wherein to output the one or more sets of status information, the controller is configured to cause the memory system to: output a number of sets of corresponding status information for each status register of the set of status registers in response to the command and the indication.

4. The memory system of claim 1, wherein to output the one or more sets of status information, the controller is configured to cause the memory system to: output the set of corresponding status information for each status register of the number of status registers equal to the indicated number, including the first status register, in response to the command and the indication.

5. The memory system of claim 4, wherein each status register of the set of status registers is associated with a respective address within an address space specific to the set of status registers, and wherein the number of status registers corresponds to the first status register and one or more status registers each having an address subsequent to the address of the first status register.

6. The memory system of claim 1, wherein the indication indicates a value of a set of values, and wherein the controller is configured to cause the memory system to: identify the one or more status registers based at least in part on a mapping between the set of values and the set of status registers.

7. The memory system of claim 1, wherein the indication of the one or more status registers comprises a bitmap, each bit of the bitmap corresponding to a respective status register of the set of status registers and indicating whether the memory system is to output the corresponding status information for the respective status register.

8. The memory system of claim 1, further comprising: a memory array within the memory device, wherein a state register of the set of state registers corresponds to a respective portion of the memory array, and wherein the set of corresponding state information for the state register comprises a plurality of bits each indicating a different type of state information associated with the respective portion of the memory array.

9. The memory system of claim 1, further comprising: a memory array within the memory device, wherein each state register of at least a subset of the set of state registers is associated with a respective plane of the memory array.

10. The memory system of claim 1, wherein a set of state information included in the one or more sets of state information indicates whether an operation by the memory device was completed successfully or unsuccessfully, whether the memory device or a portion of the memory device is idle or busy, temperature information for the memory device or a portion of the memory device, power or voltage information for the memory device or a portion of the memory device, or any combination thereof.

11. The memory system of claim 1, further comprising: a memory array within the memory device, wherein the set of state registers, the controller, and the memory array are on a same die.

12. A memory system, comprising: a memory device; and a controller for the memory device, wherein the controller is configured to cause the memory system to: transmit, to the memory device, a command for the memory device to output state information associated with the memory device; transmit, to the memory device, an indication of one or more state registers of a set of state registers associated with the memory device, each state register of the set of state registers being associated with a set of corresponding state information for the memory device, wherein the indication indicates a first state register of the set of state registers and a value indicating a number of state registers of the set of state registers; and receive, from the memory device, one or more sets of state information corresponding to the one or more state registers in response to the command and the indication of the one or more state registers.

13. The memory system of claim 12, wherein the indication indicates all state registers of the set of state registers, and wherein to receive the one or more sets of state information, the controller is configured to cause the memory system to: receive, in response to the command and the indication, a number of sets of corresponding state information for each state register of the set of state registers.

14. The memory system of claim 12, wherein to receive the one or more sets of state information, the controller is configured to cause the memory system to: receive, in response to the command and the indication, a set of corresponding state information for each state register of the set of state registers. receiving the set of corresponding state information for each of the certain number of status registers equal to the indicated number of status registers in response to the command and the indication, the certain number of status registers including the first status register.

15. The memory system of claim 14, wherein each status register of the set of status registers is associated with a respective address within an address space specific to the set of status registers, and wherein the certain number of status registers corresponds to the first status register and one or more status registers each having an address subsequent to the address of the first status register.

16. The memory system of claim 12, wherein the controller is further configured to cause the memory system to: identify a value of a set of values based at least in part on a mapping between the set of values and the set of status registers, wherein the indication of the one or more status registers comprises the value.

17. The memory system of claim 12, wherein the indication of the one or more status registers comprises a bitmap, each bit of the bitmap corresponding to a respective status register of the set of status registers and indicating whether the memory system will output the corresponding state information for the respective status register.

18. The memory system of claim 12, wherein: the memory device is on a first die within the memory system; and the controller is on a second die within the memory system.

19. The memory system of claim 18, wherein: the controller is coupled with the memory device via a first interface; the controller is configured to be coupled with a host device for the memory device via a second interface; and the controller is configured to receive a command for the memory device from the host device via the second interface.

20. The memory system of claim 12, wherein a set of status information included in the one or more sets of status information indicates whether an operation by the memory device is failed or successfully completed, whether the memory device or a portion of the memory device is idle or busy, temperature information for the memory device or a portion of the memory device, power or voltage information for the memory device or a portion of the memory device, or any combination thereof.

21. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a command to output status information associated with a memory device, wherein the memory device comprises a set of status registers each configured to store a set of corresponding status information for the memory device; receive an indication of one or more status registers of the set of status registers, wherein the indication indicates a first status register of the set of status registers and a value indicating a number of status registers of the set of status registers; and output one or more sets of status information corresponding to the one or more status registers in response to the command and the indication.

22. The non-transitory computer-readable medium of claim 21, wherein the indication indicates all of the set of status registers, and wherein the instructions to output the one or more sets of status information cause the electronic device to: output a number of sets of corresponding status information for each status register in the set of status registers in response to the command and the indication.

23. The non-transitory computer-readable medium of claim 21, wherein the instructions to output the one or more sets of status information cause the electronic device to: output the set of corresponding status information for each status register in the certain number of status registers equal to the indicated number, including the first status register, in response to the command and the indication.

24. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit, to a memory device, a command for the memory device to output status information associated with the memory device; transmit, to the memory device, an indication of one or more status registers in a set of status registers associated with the memory device, each status register in the set of status registers being associated with a corresponding set of status information for the memory device, wherein the indication indicates a first status register in the set of status registers and a value indicating a number of status registers in the set of status registers; and receive, from the memory device, one or more sets of status information corresponding to the one or more status registers in response to the command and the indication of the one or more status registers.

25. The non-transitory computer-readable medium of claim 24, wherein the indication indicates all of the set of status registers, and wherein the instructions to receive the one or more sets of status information cause the electronic device to: receive a number of sets of corresponding status information for each status register in the set of status registers in response to the command and the indication.

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