Electronic device and smart refresh method for performing a smart refresh operation

Abstract

An electronic device for performing an intelligent refresh operation and an intelligent refresh method are disclosed. The electronic device includes a target address generation circuit that generates a count signal by counting the number of times each logical level combination of addresses input by performing internal read and write operations during an activation operation is combined, stores the count signal as a storage count signal when the count signal is counted more than the storage count signal stored in the target address generation circuit, and stores an address corresponding to the count signal as a target address; and a refresh control circuit that controls an intelligent refresh operation on the target address.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Application No. 63 / 125,188, filed December 14, 2020; U.S. Application No. 63 / 125,174, filed December 14, 2020; and Korean Patent Application No. 10-2021-0091220, filed July 12, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure may generally relate to an electronic device for performing a smart refresh operation by counting the number of times each logic level combination of an address is input. Background Technology

[0004] Semiconductor devices comprise multiple memory cells for storing data. Each memory cell is configured using cell capacitors and cell transistors. Semiconductor devices store data by charging or discharging the cell capacitors; ideally, the amount of charge stored in the cell capacitors should always be constant. However, the amount of charge stored in the cell capacitors varies due to voltage differences with the surrounding circuitry. Changes in the amount of charge stored in the cell capacitors mean changes in the data stored in the cell capacitors, which translates to data loss. Semiconductor devices perform refresh operations to prevent this data loss.

[0005] With advancements in manufacturing technology, the integration density of semiconductor devices has gradually increased. Consequently, the gaps between memory cells and the gaps between the word lines coupled to those cells have decreased. If the gaps between word lines are reduced, it may be difficult to maintain the data stored in the memory cells coupled to the corresponding word lines when interference occurs between adjacent word lines. In other words, the probability of data loss increases. Summary of the Invention

[0006] In an embodiment, an electronic device may include: a target address generation circuit that generates a counting signal by counting the number of times each logic level combination of an address input during an activation operation is performed by performing an internal read operation and an internal write operation; storing the counting signal as a stored counting signal when the count signal counts more than the stored counting signal stored in the target address generation circuit; and storing the address corresponding to the counting signal as a target address; and a refresh control circuit that controls an intelligent refresh operation on the target address.

[0007] In an embodiment, an electronic device may include: a target address generation circuit that generates a counting signal by counting the number of times each logic level combination of an address input during an activation operation by performing an internal read operation and an internal write operation; storing the counting signal as a stored counting signal as the count signal counts up; storing the address corresponding to the counting signal as a target address; initializing the stored counting signal during a first smart refresh operation; and outputting the target address during a second smart refresh operation; and a refresh control circuit that controls the smart refresh operation on the target address during the second smart refresh operation.

[0008] In an embodiment, the smart refresh method may include: performing internal read operations and internal write operations, the internal read operations and internal write operations generating a count signal by counting the number of times each logic level combination of the address input during the activation operation; generating a target address by generating a flag signal by comparing the count signal with a stored count signal; generating a target address from the address for performing a smart refresh operation based on the flag signal; and performing a smart refresh operation by performing a smart refresh operation on word lines adjacent to the word line corresponding to the target address in the word lines included in the storage region when a refresh command is input. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the structure of an electronic device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a diagram showing the locations of components included in an electronic device according to an embodiment of the present disclosure.

[0011] Figure 3 It is shown Figure 1 The diagram shows a block diagram of the structure of the activation control circuit included in the electronic device.

[0012] Figure 4 It is shown Figure 1 The diagram shows a block diagram of the structure of the target address generation circuit included in the electronic device.

[0013] Figure 5 It is shown Figure 4 The diagram shows a block diagram of the structure of the comparison circuit included in the target address generation circuit.

[0014] Figure 6 It is shown Figure 5 The diagram shows a block diagram of the structure of the flag signal generation circuit included in the comparison circuit shown.

[0015] Figure 7 It is shown Figure 4The diagram shows a block diagram of the structure of the intelligent refresh control circuit included in the target address generation circuit.

[0016] Figure 8 It is shown Figure 1 A block diagram of the structure of the refresh control circuit included in the electronic device shown.

[0017] Figure 9 It is used for explanation Figure 1 A diagram illustrating the operation of the first and second storage areas included in the electronic device shown.

[0018] Figure 10 This is a flowchart for explaining the smart refresh operation of an electronic device according to embodiments of the present disclosure.

[0019] Figure 11 This is a timing diagram used to explain the smart refresh operation of an electronic device according to embodiments of the present disclosure.

[0020] Figure 12 This is a block diagram illustrating the structure of an electronic device according to another embodiment of the present disclosure.

[0021] Figure 13 This is a block diagram illustrating the structure of an electronic device according to another embodiment of the present disclosure.

[0022] Figure 14 It is shown Figure 13 The diagram shows a block diagram of the structure of the target address generation circuit included in the electronic device.

[0023] Figure 15 It is shown Figure 14 The diagram shows a block diagram of the structure of the intelligent refresh control circuit included in the target address generation circuit.

[0024] Figure 16 It is shown Figure 13 A block diagram of the structure of the refresh control circuit included in the electronic device shown.

[0025] Figure 17 This is a flowchart for explaining the smart refresh operation of an electronic device according to another embodiment of the present disclosure.

[0026] Figure 18 This is a timing diagram used to explain the smart refresh operation of an electronic device according to another embodiment of the present disclosure.

[0027] Figure 19 It is shown Figures 1 to 18 The diagram shows the structure of the electronic system used in the electronic device shown. Detailed Implementation

[0028] The term "preset" means that the value of a parameter is predetermined when it is used in a method or algorithm. According to an embodiment, the value of a parameter can be set when the method or algorithm is started or when it is executed.

[0029] Terms such as "first" and "second" are used to distinguish individual components and are therefore not limited to any particular component. For example, the first component can be called the second component, and vice versa.

[0030] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component in between. On the other hand, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without the intervention of another component.

[0031] "Logic high" and "logic low" are used to describe the logic level of a signal. A signal with a "logic high" level is distinguished from a signal with a "logic low" level. For example, while a signal with a first voltage corresponds to a "logic high" level, a signal with a second voltage can correspond to a "logic low" level. According to an embodiment, a "logic high" level can be set to a voltage higher than a "logic low" level. According to an embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, according to an embodiment, a signal with a logic high level can be set to a logic low level, and according to an embodiment, a signal with a logic low level can be set to a logic high level.

[0032] The teachings of this disclosure will now be described in more detail through embodiments. These embodiments are merely illustrative of the teachings of this disclosure, and the scope of this disclosure is not limited by these embodiments.

[0033] Various embodiments relate to an electronic device that further includes a storage area for storing information about the number of inputs for each logic level combination of an address, and performs an intelligent refresh operation to refresh the word line adjacent to the most active word line based on the result of counting all logic level combinations of the address.

[0034] According to embodiments of this disclosure, the electronic device may further include a storage area for storing information about the number of inputs for each logic level combination of the address, and may perform an intelligent refresh operation to refresh the word line adjacent to the most active word line based on the result of counting all logic level combinations of the address.

[0035] Furthermore, according to embodiments of this disclosure, the electronic device can store the result of counting all logic level combinations of an address, and by using this result, the word line adjacent to the most active word line can be refreshed, thereby preventing interference between word lines.

[0036] like Figure 1 As shown, an electronic device 1 according to an embodiment of the present disclosure may include an activation control circuit 11, a target address generation circuit 12, an internal address generation circuit 13, a refresh control circuit 14, a first storage area 21, and a second storage area 22.

[0037] The activation control circuit 11 can receive an activation command ACT and a refresh command REF from an external device (e.g., a controller). The activation control circuit 11 can generate an internal read signal IRD, an internal compare signal ICMP, and an internal write signal IWT based on the activation command ACT and the refresh command REF. The activation control circuit 11 can sequentially generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. The activation control circuit 11 can generate the internal write signal IWT based on the refresh command REF.

[0038] The target address generation circuit 12 can receive the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT from the activation control circuit 11. The target address generation circuit 12 can receive the first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The target address generation circuit 12 can receive the smart refresh signal SR from the refresh control circuit 14. During the internal read operation, the target address generation circuit 12 can generate the first to sixth count signals TWC<1:6> by counting up on the first to sixth read count signals RCA<1:6> (see [link to relevant documentation]). Figure 4 This serves as information regarding the number of logic level combinations input for addresses ADD<1:N> from the first to the Nth address. When the internal read signal IRD is input, the target address generation circuit 12 can generate the first to sixth count signals TWC<1:6> by counting up from the first to sixth read count signals RCA<1:6> input from the first memory area 21 (see [link to relevant documentation]). Figure 4 When the first to sixth counting signals TWC<1:6> (see also...) Figure 4 The number of counts exceeds the first to sixth stored count signals SWC<1:6> (see also...) Figure 5 When the target address generation circuit 12 generates the first to sixth counting signals TWC<1:6> (see [reference]), it can generate the target address. Figure 4 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5The target address generation circuit 12 can receive the intelligent refresh signal SR to compare it with the first to sixth counting signals TWC<1:6> (see [link]). Figure 4 The corresponding first to Nth addresses ADD<1:N> are stored as first to Nth target addresses TAD<1:N>. During internal write operations, the target address generation circuit 12 can output to the first memory area 21 based on the first to sixth count signals TWC<1:6> (see [link to documentation]). Figure 4 The first to sixth write count signals WCA<1:6> are generated. The target address generation circuit 12 can output the first to sixth count signals TWC<1:6> to the first memory area 21 by receiving the internal write signal IWT (see [link to circuit 12]). Figure 4 The first to sixth write count signals WCA<1:6> generated by the target address generation circuit 12 can be the first to sixth count signals TWC<1:6> that have the most counts (see [link to circuit 12]). Figure 4 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5 In the intelligent refresh operation, the target address generation circuit 12 can store the first to sixth memory count signals SWC<1:6> (see [link to relevant documentation]). Figure 5 Initialize.

[0039] The internal address generation circuit 13 can receive first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The internal address generation circuit 13 can generate first to Nth internal addresses IADD<1:N> based on the first to Nth addresses ADD<1:N>. The internal address generation circuit 13 can output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. Although the internal address generation circuit 13 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, the internal address generation circuit 13 can also be implemented to generate the first to Nth internal addresses IADD<1:N> by decoding the first to Nth addresses ADD<1:N>. The number of bits in the first to Nth addresses ADD<1:N> and the number of bits in the first to Nth internal addresses IADD<1:N> can be set differently depending on the embodiment.

[0040] The refresh control circuit 14 can receive a refresh command REF from an external device (e.g., a controller). The refresh control circuit 14 can generate a smart refresh signal SR and an internal refresh signal IR based on the refresh command REF. When the refresh command REF is repeatedly input a predetermined number of times to perform a smart refresh operation, the refresh control circuit 14 can generate an enabled smart refresh signal SR. When the refresh command REF is repeatedly input a predetermined number of times to perform a self-refresh operation, the refresh control circuit 14 can generate an enabled internal refresh signal IR.

[0041] The first storage area 21 may include the first to sixteenth rows of hammer-on letter lines RWL1 to RWL16 (see [link to storage area]). Figure 2 and 9 The first storage area 21 may include hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to storage area]). Figure 2 and 9 Multiple row hammering units RC (see [link to RC]) Figure 2 and 9 During internal read operations, the first memory area 21 can output data stored on hammer-word lines RWL1 to RWL16 coupled to the first to sixteenth lines (see [link to relevant documentation]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The first to sixth write count signals WCA<1:6> in the memory are used as the first to sixth read count signals RCA<1:6>. During internal write operations, the first memory area 21 can store the first to sixth write count signals WCA<1:6> in the hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to memory area 21]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The first memory area 21 can be initialized by receiving the initialization signal INIT input during the power-on period and the startup operation for powering on the electronic device 1. All bits of the initialized first to sixth write count signals WCA<1:6> can be generated with a logic low level. Although the first memory area 21 is implemented to include the first to sixteenth rows of hammer word lines RWL1 to RWL16 (see...) Figure 2 and 9 However, the first storage area 21 can be implemented according to embodiments to include various numbers of row hammer word lines. The first storage area 21 can store the first to sixth write count signals WCA<1:6> coupled to the first to sixteenth row hammer word lines RWL1 to RWL16 (see See...). Figure 2 and 9 The RC hammer unit (see below) Figure 2 and 9 In the second memory area 22, the number of logic level combinations inputs for the first to Nth addresses ADD<1:N> are used as information to activate the first to sixteenth word lines WL1 to WL16 included in the second memory area 22 (see [link]). Figure 2 and9 ).

[0042] The second storage area 22 may include the first to the sixteenth word lines WL1 to WL16 (see [link]). Figure 2 and 9 The second storage area 22 may include lines WL1 to WL16 coupled to the first to sixteenth word lines (see [link]). Figure 2 and 9 Multiple storage units MC (see [link to storage unit MC]) Figure 2 and 9 During a read operation, the second storage area 22 can receive the read signal RD, thereby outputting the data stored in the storage unit MC (see [link to storage unit MC]). Figure 2 and 9 The data in the memory cell MC is coupled to the first to sixteenth word lines WL1 to WL16 selected by the first to Nth internal addresses IADD<1:N> (see [link to memory cell MC]). Figure 2 and 9 The word lines in the first to sixteenth word lines WL1 to WL16 (see See) are used for writing operations. During a write operation, the second memory area 22 can receive a write signal WT, thereby storing data in the word lines coupled to the first to sixteenth word lines WL1 to WL16 (see See) Figure 2 and 9 The memory cell MC of the word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 In the self-refresh operation, the second memory area 22 can receive the internal refresh signal IR, thereby updating the first to sixteenth word lines WL1 to WL16 (see [link to relevant documentation]). Figure 2 and 9 The second memory area 22 performs a refresh operation. In a smart refresh operation, the second memory area 22 can refresh word lines adjacent to those selected via the first to Nth target addresses TAD<1:N>. The read signal RD and write signal WT can be configured as signals generated internally by commands input from an external device (e.g., a controller) during read and write operations in a general activation operation. Although the second memory area 22 is implemented to include the first to sixteenth word lines WL1 to WL16 (see... Figure 2 and 9 However, the second storage area 22 may be implemented in embodiments to include a variety of number of word lines.

[0043] The first to sixteenth rows of hammer-on word lines RWL1 to RWL16 included in the first storage area 21 (see [link]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 22 (see See Figure 2 and 9In this context, word lines in the same order can be activated simultaneously via internal addresses IADD<1:N> from the first to the Nth. For example, when the first row hammer word line RWL1 included in the first memory area 21 is activated via internal addresses IADD<1:N> from the first to the Nth, see [link to relevant documentation]. Figure 2 and 9 When this is done, the first word line WL1 included in the second storage area 22 can be activated (see [link]). Figure 2 and 9 Although the hammer word lines RWL1 to RWL16 of the first to sixteenth rows included in the first storage area 21 are implemented through different word lines (see [link to documentation]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 22 (see See Figure 2 and 9 However, this is just an example, and the hammered word lines RWL1 to RWL16 and WL1 to WL16 of the first to sixteenth lines can be implemented using the same word lines.

[0044] The following will be referenced Figure 2 The location of components of electronic device 1 according to embodiments of the present disclosure is described.

[0045] The row area for controlling the first storage area 21 and the second storage area 22 can be located to the left of the first storage area 21 and the second storage area 22. The column area for controlling the first storage area 21 and the second storage area 22 can be located below the first storage area 21 and the second storage area 22. The intersection area can be located at the position where the row area intersects with the left side of the column area. According to an embodiment, the row area can be implemented to the right of the first storage area 21 and the second storage area 22, and the column area can be implemented to the top of the first storage area 21 and the second storage area 22.

[0046] The activation control circuit 11, the target address generation circuit 12, the internal address generation circuit 13, and the refresh control circuit 14 can be located in the row region 10 to control the storage area 20 having the first storage area 21 and the second storage area 22, or they can be located in both the row region 10 and the intersection region. Figure 2 The row, column, and intersection regions shown in the diagram can be implemented to include control circuitry for inputting / outputting data by activating multiple word lines included in the second memory area 22.

[0047] Figure 3 This is a block diagram illustrating an embodiment of the activation control circuit 11. (As shown in...) Figure 3 As shown, the activation control circuit 11 may include a ring oscillator 111, a ROD counter 112, and an internal signal generation circuit 113.

[0048] The ring oscillator 111 can generate a periodic signal OSC that switches between an activation command ACT and a refresh command REF. When the activation command ACT is input, the ring oscillator 111 can generate a periodically switching periodic signal OSC. When the refresh command REF is input, the ring oscillator 111 can generate a periodically switching periodic signal OSC.

[0049] ROD counter 112 can generate first to Kth oscillation counting signals OCNT<1:K> based on the periodic signal OSC. These first to Kth oscillation counting signals OCNT<1:K> are counted each time a pulse of the input periodic signal OSC occurs. The number of bits K in the first to Kth oscillation counting signals OCNT<1:K> can be set to various values ​​according to embodiments.

[0050] The internal signal generation circuit 113 can generate an internal read signal IRD, an internal compare signal ICMP, and an internal write signal IWT, which are sequentially enabled based on the refresh signal REF and the first to the Kth oscillation count signals OCNT<1:K>. When the first to the Kth oscillation count signals OCNT<1:K> are counted to a first logic level combination, the internal signal generation circuit 113 can generate the internal read signal IRD. When the first to the Kth oscillation count signals OCNT<1:K> are counted to a second logic level combination, the internal signal generation circuit 113 can generate the internal compare signal ICMP. When the first to the Kth oscillation count signals OCNT<1:K> are counted to a third logic level combination, the internal signal generation circuit 113 can generate the internal write signal IWT. When the refresh command REF is input, the internal signal generation circuit 113 can generate the internal write signal IWT, and the first to the Kth oscillation count signals OCNT<1:K> can be counted to the third logic level combination. The case where the first to the Kth oscillation counting signals OCNT<1:K> are counted as the second logic level combination can mean that the first to the Kth oscillation counting signals OCNT<1:K> are counted more often than the first to the Kth oscillation counting signals OCNT<1:K> are counted as the first logic level combination. The case where the first to the Kth oscillation counting signals OCNT<1:K> are counted as the third logic level combination can mean that the first to the Kth oscillation counting signals OCNT<1:K> are counted more often than the second logic level combination.

[0051] Figure 4 This is a block diagram illustrating an embodiment of the target address generation circuit 12. (As shown) Figure 4As shown, the target address generation circuit 12 may include an input circuit 121, an adder 122, an output circuit 123, a comparator circuit 124, and an intelligent refresh control circuit 125.

[0052] When the internal read signal IRD is input, the input circuit 121 can generate the first to sixth transfer read count signals TRC<1:6> based on the first to sixth read count signals RCA<1:6> received from the first memory area 21. When the internal read signal IRD is input, the input circuit 121 can generate the first to sixth transfer read count signals TRC<1:6> by buffering the first to sixth read count signals RCA<1:6>. Although the first to sixth read count signals RCA<1:6> and the first to sixth transfer read count signals TRC<1:6> are implemented using six bits, this is merely an example; various numbers of bits can be used to implement the first to sixth read count signals RCA<1:6> and the first to sixth transfer read count signals TRC<1:6> according to embodiments.

[0053] Adder 122 can count up the first to sixth transmission read count signals TRC<1:6>. Adder 122 can generate the first to sixth count signals TWC<1:6> by counting up the first to sixth transmission read count signals TRC<1:6>. Although the first to sixth count signals TWC<1:6> are implemented with six bits, this is merely an example, and the first to sixth count signals TWC<1:6> can be implemented with various numbers of bits according to embodiments.

[0054] During an internal write operation, the output circuit 123 can generate the first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>. When the internal write signal IWT is input, the output circuit 123 can generate the first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>. When the internal write signal IWT is input, the output circuit 123 can output the first to sixth write count signals WCA<1:6> to the first memory area 21. After performing a smart refresh operation, the output circuit 123 can initialize all bits of the first to sixth write count signals WCA<1:6> to logic low. When the reset signal RST is input after performing a smart refresh operation, the output circuit 123 can initialize all bits of the first to sixth write count signals WCA<1:6> to logic low. When the internal write signal IWT is input after a smart refresh operation, the output circuit 123 can output the first to sixth write count signals WCA<1:6> to the first memory area 21, all of which are initialized to logic low by the reset signal RST. Although the first to sixth write count signals WCA<1:6> are implemented with six bits, this is merely an example, and various numbers of bits can be used to implement the first to sixth write count signals WCA<1:6> according to embodiments.

[0055] When the internal comparison signal ICMP is input, the comparison circuit 124 can compare the first to sixth count signals TWC<1:6> with the first to sixth stored count signals SWC<1:6> stored in the comparison circuit 124 (see [link to comparison circuit]). Figure 5 The flag signal UPF is generated by comparing the two signals. When the internal comparison signal ICMP is input, the first to sixth count signals TWC<1:6> are counted more than the first to sixth stored count signals SWC<1:6> stored in the comparison circuit 124 (see [link to comparison circuit 124]). Figure 5 In the event that the comparator circuit 124 can generate an enable flag signal UPF, when the internal comparator signal ICMP is input, the counts of the first to sixth count signals TWC<1:6> are less than or equal to the first to sixth stored count signals SWC<1:6> stored in the comparator circuit 124 (see [link to comparator circuit 124]). Figure 5 In the event of an error, comparator circuit 124 can generate an inhibit flag signal UPF. When the internal comparator signal ICMP is input, the first to sixth count signals TWC<1:6> are counted more than the first to sixth stored count signals SWC<1:6> stored in comparator circuit 124 (see [link to comparator circuit 124]). Figure 5 In the case of ), the comparator circuit 124 can store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6> (see [link to comparator circuit]). Figure 5When a reset signal RST is input after a smart refresh operation, the comparator circuit 124 can convert the first to sixth memory count signals SWC<1:6> (see [link to comparator]). Figure 5 All bits of the ) are initialized to logic low.

[0056] When the flag signal UPF is input, the intelligent refresh control circuit 125 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N>. When the intelligent refresh signal SR is input, the intelligent refresh control circuit 125 can output the stored first to Nth target addresses TAD<1:N> to the second memory area 22. The intelligent refresh control circuit 125 can generate a reset signal RST, which is enabled when the first to Nth target addresses TAD<1:N> are output.

[0057] Figure 5 This is a block diagram illustrating an embodiment of the comparator circuit 124. Figure 5 As shown, the comparison circuit 124 may include a counting signal storage circuit 124_1 and a flag signal generation circuit 124_2.

[0058] When the flag signal UPF is input, the counting signal storage circuit 124_1 can store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6>. The counting signal storage circuit 124_1 can then output the stored first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6>. When the reset signal RST is input, the counting signal storage circuit 124_1 can initialize the first to sixth stored counting signals SWC<1:6>. When the reset signal RST is input, the counting signal storage circuit 124_1 can initialize all bits of the first to sixth stored counting signals SWC<1:6> to a logic low level.

[0059] The flag signal generation circuit 124_2 generates the flag signal UPF by comparing the first to sixth counting signals TWC<1:6> with the first to sixth stored counting signals SWC<1:6>. When the first to sixth counting signals TWC<1:6> are counted more than the first to sixth stored counting signals SWC<1:6>, the flag signal generation circuit 124_2 generates the enabled flag signal UPF.

[0060] Figure 6 This is a block diagram illustrating an embodiment of the flag signal generation circuit 124_2. (See diagram for example.) Figure 6 As shown, the flag signal generation circuit 124_2 may include a first comparator 210, a second comparator 220, a third comparator 230, and a logic circuit 240.

[0061] The first comparator 210 can compare the fifth and sixth counting signals TWC<5:6> with the fifth and sixth stored counting signals SWC<5:6> to generate the first detection signal DET. <1> Second detection signal DET <2> When the fifth and sixth counting signals TWC<5:6> and the fifth and sixth stored counting signals SWC<5:6> are of the same logic level combination, the first comparator 210 can generate an enable first detection signal DET. <1> When the fifth and sixth counting signals TWC<5:6> are different logic level combinations from the fifth and sixth stored counting signals SWC<5:6>, the first comparator 210 can generate an enable second detection signal DET. <2> Although the first comparator 210 is implemented to compare the two-bit fifth and sixth count signals TWC<5:6> with the two-bit fifth and sixth store count signals SWC<5:6>, this is merely an example, and the first comparator 210 may be implemented to compare various numbers of bits according to embodiments.

[0062] The second comparator 220 can compare the third and fourth counting signals TWC<3:4> with the third and fourth stored counting signals SWC<3:4> to generate the third detection signal DET. <3> and the fourth detection signal DET <4> When the third and fourth counting signals TWC<3:4> and the third and fourth stored counting signals SWC<3:4> are of the same logic level combination, the second comparator 220 can generate the enabled third detection signal DET. <3> When the third and fourth counting signals TWC<3:4> are different logic level combinations from the third and fourth stored counting signals SWC<3:4>, the second comparator 220 can generate an enabled fourth detection signal DET. <4> Although the second comparator 220 is implemented to compare the two-bit third and fourth count signals TWC<3:4> with the two-bit third and fourth store count signals SWC<3:4>, this is merely an example, and the second comparator 220 may be implemented to compare various numbers of bits according to embodiments.

[0063] The third comparator 230 can compare the first and second counting signals TWC<1:2> with the first and second stored counting signals SWC<1:2> to generate the fifth detection signal DET. <5> and the sixth detection signal DET <6> When the first and second counting signals TWC<1:2> and the first and second stored counting signals SWC<1:2> are of the same logic level combination, the third comparator 230 can generate an enabled fifth detection signal DET. <5> When the first and second counting signals TWC<1:2> and the first and second stored counting signals SWC<1:2> are different logic level combinations, the third comparator 230 can generate an enabled sixth detection signal DET. <6> Although the third comparator 230 is implemented to compare the first and second count signals TWC<1:2> of two bits with the first and second storage count signals SWC<1:2> of two bits, this is merely an example, and the third comparator 230 may be implemented to compare various numbers of bits according to embodiments.

[0064] Logic circuit 240 can be based on the first detection signal DET <1> Second detection signal DET <2> Third detection signal DET <3> Fourth detection signal DET <4> And the sixth detection signal DET <6> To generate the flag signal UPF. Logic circuit 240 can be based on the first detection signal DET. <1> Second detection signal DET <2> Third detection signal DET <3> Fourth detection signal DET <4> And the sixth detection signal DET <6> The logic level is used to generate the flag signal UPF. When the first detection signal DET... <1> and the third detection signal DET <3> Both are enabled and the sixth detection signal DET <6> When disabled, logic circuit 240 can generate a disabled flag signal UPF. When the second detection signal DET... <2> Fourth detection signal DET <4> And the sixth detection signal DET <6> When any one of them is enabled, logic circuit 240 can generate an enable flag signal UPF.

[0065] Figure 7 This is a block diagram illustrating an embodiment of the intelligent refresh control circuit 125. (As shown) Figure 7 As shown, the intelligent refresh control circuit 125 may include an address storage circuit 125_1 and a reset control circuit 125_2.

[0066] The address storage circuit 125_1 can generate the first to Nth target addresses TAD<1:N> based on the first to Nth addresses ADD<1:N>, the flag signal UPF, and the smart refresh signal SR. When the flag signal UPF is input at a logic high level, the address storage circuit 125_1 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N>. When the smart refresh signal SR is input at a logic high level, the address storage circuit 125_1 can output the stored first to Nth target addresses TAD<1:N>.

[0067] The reset control circuit 125_2 can generate a reset signal RST based on the smart refresh signal SR. When the smart refresh operation is completed after the smart refresh signal SR is input, the reset control circuit 125_2 can generate an enabled reset signal RST. The reset control circuit 125_2 can also generate an enabled reset signal RST by delaying the smart refresh signal SR until the smart refresh operation is completed.

[0068] Figure 8 This is a block diagram illustrating an embodiment of the refresh control circuit 14. (As shown) Figure 8 As shown, the refresh control circuit 14 may include a refresh counter 141 and a refresh signal generation circuit 142.

[0069] The refresh counter 141 can generate first to Jth refresh count signals RCNT<1:J> based on the refresh command REF. The refresh counter 141 can generate first to Jth refresh count signals RCNT<1:J> that count upwards each time a refresh command REF is input. The number J of bits in the first to Jth refresh count signals RCNT<1:J> can be set to various values ​​according to embodiments.

[0070] The refresh signal generation circuit 142 can generate a smart refresh signal SR and an internal refresh signal IR based on the first to Jth refresh count signals RCNT<1:J>. When the first to Jth refresh count signals RCNT<1:J> are counted to a fourth logic level combination, the refresh signal generation circuit 142 can generate the smart refresh signal SR. When the first to Jth refresh count signals RCNT<1:J> are counted to a fourth logic level combination, the refresh signal generation circuit 142 can generate the smart refresh signal SR with sequentially generated pulses. The fourth logic level combination of the first to Jth refresh count signals RCNT<1:J> can be set to the number of refresh commands REF input to perform the smart refresh operation. When the first to Jth refresh count signals RCNT<1:J> are counted to a fifth logic level combination, the refresh signal generation circuit 142 can generate the internal refresh signal IR. The fifth logic level combination of the first to Jth refresh count signals RCNT<1:J> can be set to the number of refresh commands REF input to perform the self-refresh operation.

[0071] The following will be referenced Figure 9 The operation of the first memory area 21 and the second memory area 22 for performing smart refresh operation is described in the case that the first to Nth internal addresses IADD<1:N> are used to select the logic level combination of the second word line WL2.

[0072] In the first storage area 21, during an internal read operation, the second row hammer word line RWL2 can be activated by selecting the first to Nth internal addresses IADD<1:N> of the second word line WL2. The first storage area 21 can output the first to sixth write count signals WCA<1:6> stored in the row hammer unit RC coupled to the second row hammer word line RWL2 as the first to sixth read count signals RCA<1:6>.

[0073] In the second storage area 22, when the first word line WL1(N-1) and the third word line WL3(N+1) are activated by selecting the first to Nth target addresses TAD<1:N> of the second word line WL2, a smart refresh operation can be performed.

[0074] In the first memory area 21, during an internal write operation, the second row hammer word line RWL2 can be activated by selecting the first to Nth internal addresses IADD<1:N> of the second word line WL2. The first memory area 21 can store the first to sixth write count signals WCA<1:6>, which are stored in the row hammer unit RC coupled to the second row hammer word line RWL2. At this time, because it has undergone a smart refresh operation, all bits of the first to sixth write count signals WCA<1:6> can be initialized to logic low.

[0075] In other words, the first memory area 21 can store information about the number of inputs of logic level combinations for addresses ADD<1:N> from the first to the Nth address range, and can provide the target address generation circuit 12 with the first to sixth read count signals RCA<1:6> obtained by counting all logic level combinations for addresses ADD<1:N> from the first to the Nth address range. The second memory area 22 can perform a smart refresh operation using the first to the Nth target addresses TAD<1:N>, which are information about the word lines WL1 to WL16 from the first to the sixteenth address range, that are most activated by addresses ADD<1:N> from the first to the Nth address range.

[0076] The following will be referenced Figure 10 To describe the smart refresh operation of electronic device 1 according to an embodiment of the present disclosure.

[0077] The smart refresh operation may include initialization step S1, activation detection step S2, target address generation step S3, and smart refresh execution step S4.

[0078] Initialization operation step S1 can be set as a power-on period and a startup operation for powering on electronic device 1. In initialization operation step S1, the first memory area 21 can receive the initialization signal INIT, thereby initializing the first to sixth write count signals WCA<1:6> stored in the first memory area. The first to sixth write count signals WCA<1:6> stored in the first memory area can refer to the first to sixth write count signals WCA<1:6> stored respectively in the first to sixteenth rows of hammer word lines RWL1 to RWL16. All bits of the first to sixth write count signals WCA<1:6> can be initialized to a logic low level.

[0079] The activation detection step S2 may include activation operation step S21, internal read, count and internal write operation steps S22, and comparison operation step S23.

[0080] The activation operation step S21 can be configured to receive the activation command ACT, the refresh command REF, and the first to Nth addresses ADD<1:N> from an external device (e.g., a controller).

[0081] The internal read, count, and internal write operation step S22 can be configured to generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. In the internal read, count, and internal write operation step S22, the activation control circuit 11 can generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. When the internal read signal IRD is generated in the internal read, count, and internal write operation step S22, the target address generation circuit 12 can generate the first to sixth count signals TWC<1:6> by counting upwards from the first to sixth read count signals RCA<1:6> input from the first memory area 21. In the internal read, count, and internal write operation step S22, after generating the internal read signal IRD, the activation control circuit 11 can generate the internal compare signal ICMP and the internal write signal IWT. When the internal write signal IWT is generated in the internal read, count, and internal write operation step S22, the target address generation circuit 12 can generate the first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>, and can output the first to sixth write count signals WCA<1:6> to the first memory area 21. In the internal read, count, and internal write operation step S22, the first memory area 21 can store the first to sixth write count signals WCA<1:6>.

[0082] The comparison operation step S23 can be configured to compare the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In comparison operation step S23, when the internal comparison signal ICMP is input, the target address generation circuit 12 can compare the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In comparison operation step S23, when the first to sixth counting signals TWC<1:6> are counted more than the first to sixth storage counting signals SWC<1:6> (yes), the target address generation circuit 12 can generate an enable flag signal UPF. In comparison operation step S23, when the first to sixth counting signals TWC<1:6> are counted less than or equal to the first to sixth storage counting signals SWC<1:6> (no), the target address generation circuit 12 can generate an disable flag signal UPF.

[0083] The target address generation step S3 may include a counting signal update operation step S31, a target address update operation step S32, and a target address maintenance operation step S33.

[0084] When the first to sixth counting signals TWC<1:6> are counted more than the first to sixth stored counting signals SWC<1:6> in comparison operation step S23 (yes), the counting signal update operation step S31 can be executed. In the counting signal update operation step S31, the target address generation circuit 12 can store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6> through the enabled flag signal UPF.

[0085] When the first to sixth counting signals TWC<1:6> are counted more than the first to sixth stored counting signals SWC<1:6> in comparison operation step S23 (yes), the target address update operation step S32 can be executed. In the target address update operation step S32, the target address generation circuit 12 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> through the enabled flag signal UPF.

[0086] When the first to sixth counting signals TWC<1:6> are counted as less than or equal to the first to sixth storage counting signals SWC<1:6> in the comparison operation step S23, the target address maintenance operation step S33 can be executed. In the target address maintenance operation step S33, the target address generation circuit 12 does not store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> via the inhibit flag signal UPF. In other words, the first to Nth target addresses TAD<1:N> maintain information about the most active word lines. When the target address maintenance operation step S33 ends, the method can re-enter the activation operation step S21.

[0087] The smart refresh execution step S4 can be configured to perform a smart refresh operation via a refresh command REF. In smart refresh execution step S4, when the smart refresh signal SR is input, the target address generation circuit 12 can output the stored first to Nth target addresses TAD<1:N> to the second memory area 22. In smart refresh execution step S4, the second memory area 22 can perform a smart refresh operation by activating word lines N-1 and N+1 adjacent to the word lines selected by the first to Nth target addresses TAD<1:N>. In smart refresh execution step S4, the row hammer unit RC included in the first memory area 21 can be initialized. When smart refresh execution step S4 ends, the method can then proceed to activation operation step S21.

[0088] The following will be referenced Figure 11 To describe the smart refresh operation of electronic device 1 according to an embodiment of the present disclosure.

[0089] At time T1, the activation command ACT can be input from an external device (e.g., a controller).

[0090] At time T2, the activation control circuit 11 can generate an internal read signal IRD based on the activation command ACT. The target address generation circuit 12 can receive the internal read signal IRD and generate a first to sixth count signal TWC<1:6> by counting up the first to sixth read count signals RCA<1:6> input from the first memory area 21.

[0091] At time T3, the activation control circuit 11 can generate an internal comparison signal ICMP based on the activation command ACT. When the internal comparison signal ICMP is input, the target address generation circuit 12 can generate a flag signal UPF by comparing the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. When the flag signal UPF is enabled, the target address generation circuit 12 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N>. When the flag signal UPF is enabled, the target address generation circuit 12 can store the first to sixth counting signals TWC<1:6> as the first to sixth storage counting signals SWC<1:6>. The first to sixth storage counting signals SWC<1:6> can be generated based on the first to sixth counting signals TWC<1:6> that are counted the most. When the flag signal UPF is disabled, the target address generation circuit 12 may not store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N>. When the flag signal UPF is disabled, the target address generation circuit 12 may not store the first to sixth counting signals TWC<1:6> as the first to sixth storage counting signals SWC<1:6>.

[0092] At time T4, the activation control circuit 11 can generate an internal write signal IWT based on the activation command ACT. The target address generation circuit 12 can receive the internal write signal IWT and thus output the first to sixth write count signals WCA<1:6> generated based on the first to sixth count signals TWC<1:6> to the first memory area 21. The first memory area 21 can store the first to sixth write count signals WCA<1:6> in the row hammering unit RC of the row hammering word lines activated by the first to Nth internal addresses IADD<1:N>, which are coupled to the first to sixteenth row hammering word lines RWL1 to RWL16.

[0093] At time point T5, a refresh command REF can be input from an external device (e.g., a controller). This means that the refresh command REF is repeatedly input to perform a smart refresh operation.

[0094] At time T6, the refresh control circuit 14 can generate the first pulse of the smart refresh signal SR based on the refresh command REF. The target address generation circuit 12 can output the first to Nth target addresses TAD<1:N> to the second memory area 22 via the first pulse of the smart refresh signal SR. The second memory area 22 can perform a smart refresh operation (smart refresh) by activating word line N+1 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. Simultaneously, the second memory area 22 can perform a smart refresh operation (smart refresh) by activating word line N+2 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16.

[0095] At time T7, the refresh control circuit 14 can generate a second pulse of the smart refresh signal SR based on the refresh command REF. The target address generation circuit 12 can output the first to Nth target addresses TAD<1:N> to the second memory area 22 via the second pulse of the smart refresh signal SR. The second memory area 22 can perform a smart refresh operation (smart refresh) by activating word line N-1 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. Simultaneously, the second memory area 22 can perform a smart refresh operation (smart refresh) by activating word line N-2 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16.

[0096] At time T8, the refresh control circuit 14 can generate the third pulse of the smart refresh signal SR based on the refresh command REF.

[0097] When the smart refresh operation is completed after the input smart refresh signal SR, the reset control circuit 125_2 can generate an enable reset signal RST.

[0098] When the reset signal RST is input, the counting signal storage circuit 124_1 can initialize all bits of the first to sixth stored counting signals SWC<1:6> to logic low level. That is, the first to sixth stored counting signals SWC<1:6> can be initialized (stored counting signal initialization).

[0099] The activation control circuit 11 can generate an internal write signal IWT based on the refresh command REF. The target address generation circuit 12 can receive the internal write signal IWT and thus output the first to sixth write count signals WCA<1:6>, whose bits are initialized to logic low, to the first memory area 21. The first memory area 21 can store the initialized first to sixth write count signals WCA<1:6> in the row hammer cell RC of the row hammer word lines activated by the first to Nth internal addresses IADD<1:N>, which are coupled to the first to sixteenth row hammer word lines RWL1 to RWL16. That is, the row hammer cell RC of the first memory area 21 can be initialized (RC initialization).

[0100] As can be clearly seen from the above description, the electronic device 1 according to embodiments of the present disclosure may further include a storage area storing information about the number of inputs for all logic level combinations of an address, and may perform an intelligent refresh operation to refresh word lines adjacent to the most frequently activated word lines based on the result of counting all logic level combinations of an address. Furthermore, the electronic device 1 may store the result of counting all logic level combinations of an address, and by using this result, may refresh word lines adjacent to the most frequently activated word lines, thereby preventing interference between word lines.

[0101] like Figure 12 As shown, an electronic device 2 according to another embodiment of the present disclosure may include an activation control circuit 31, a target address generation circuit 32, an internal address generation circuit 33, a counting signal input / output circuit 34, a refresh control circuit 35, a column control circuit 36, a first storage area 41, and a second storage area 42.

[0102] The activation control circuit 31 can receive an activation command ACT and a refresh command REF from an external device (e.g., a controller). The activation control circuit 31 can generate an internal read signal IRD, an internal compare signal ICMP, and an internal write signal IWT based on the activation command ACT and the refresh command REF. The activation control circuit 31 can sequentially generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. The activation control circuit 31 can generate the internal write signal IWT based on the refresh command REF. This is because the activation control circuit 31 is connected to... Figure 1 The activation control circuit 11 shown herein is implemented in the same way and performs the same operation, so its detailed description will be omitted herein.

[0103] The target address generation circuit 32 can receive the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT from the activation control circuit 31. The target address generation circuit 32 can receive the first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The target address generation circuit 32 can receive the smart refresh signal SR from the refresh control circuit 35. During the internal read operation, the target address generation circuit 32 can generate the first to sixth count signals TWC<1:6> by counting up on the first to sixth read count signals RCA<1:6> (see [link to relevant documentation]). Figure 4 This information is used to represent the number of inputs for the logic level combinations of addresses ADD<1:N> from the first to the Nth address. When the internal read signal IRD is input, the target address generation circuit 32 can generate the first to sixth count signals TWC<1:6> by counting up from the first to the sixth read count signals RCA<1:6> input from the count signal input / output circuit 34 (see [link to circuit 34]). Figure 4 When the first to sixth counting signals TWC<1:6> (see also...) Figure 4 The number of counts exceeds the first to sixth stored count signals SWC<1:6> (see also...) Figure 5 When the target address generation circuit 32 generates the first to sixth counting signals TWC<1:6> (see [link to circuit 3]), it can generate the target address. Figure 4 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5 The target address generation circuit 32 can receive the intelligent refresh signal SR to compare it with the first to sixth counting signals TWC<1:6> (see [link]). Figure 4 The corresponding first to Nth addresses ADD<1:N> are stored as first to Nth target addresses TAD<1:N>. The target address generation circuit 32 can output to the counting signal input / output circuit 34 based on the first to sixth counting signals TWC<1:6> (see [link to circuit]) by receiving the internal write signal IWT. Figure 4 The first to sixth write count signals WCA<1:6> are generated. The target address generation circuit 32 can generate the first to sixth count signals TWC<1:6> that are counted the most (see [reference]). Figure 4 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5 In the intelligent refresh operation, the target address generation circuit 32 can store the first to sixth memory count signals SWC<1:6> (see [link to relevant documentation]). Figure 5 Initialization is performed. Because the target address generation circuit 32 is initialized via... Figure 1 The target address generation circuit 12 shown in the figure is implemented in the same way and performs the same operation, so its detailed description will be omitted in this document.

[0104] The internal address generation circuit 33 can receive first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The internal address generation circuit 33 can generate first to Nth internal addresses IADD<1:N> based on the first to Nth addresses ADD<1:N>. The internal address generation circuit 33 can output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. Although the internal address generation circuit 33 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, the internal address generation circuit 33 can also be implemented to generate the first to Nth internal addresses IADD<1:N> by decoding the first to Nth addresses ADD<1:N>. The number of bits in the first to Nth addresses ADD<1:N> and the number of bits in the first to Nth internal addresses IADD<1:N> can be set differently depending on the embodiment.

[0105] The counting signal input / output circuit 34 can be located between the target address generation circuit 32 and the first memory area 41. The counting signal input / output circuit 34 can be coupled to the first memory area 41 via the row hammer input / output line RIO. The counting signal input / output circuit 34 can include an input / output sense amplifier 341 and a write driver 342. In an internal read operation, the input / output sense amplifier 341 can output the first to sixth read count signals RCA<1:6> from the first memory area 41 to the row hammer input / output line RIO to the target address generation circuit 32. In an internal write operation, the write driver 342 can output the first to sixth write count signals WCA<1:6> from the target address generation circuit 32 to the row hammer input / output line RIO. The row hammer input / output line RIO can be configured to include multiple row hammer input / output lines.

[0106] The refresh control circuit 35 can receive a refresh command REF from an external device (e.g., a controller). The refresh control circuit 35 can generate a smart refresh signal SR and an internal refresh signal IR based on the refresh command REF. When the refresh command REF is repeatedly input a predetermined number of times to perform a smart refresh operation, the refresh control circuit 35 can generate an enabled smart refresh signal SR. When the refresh command REF is repeatedly input a predetermined number of times to perform a self-refresh operation, the refresh control circuit 35 can generate an enabled internal refresh signal IR. This is because the refresh control circuit 35 communicates with... Figure 1 The refresh control circuit 14 shown herein is implemented in the same way and performs the same operation, so its detailed description will be omitted herein.

[0107] Column control circuitry 36 can be coupled to the second memory area 42 via local input / output lines LIO. During a read operation, column control circuitry 36 can output data from the second memory area 42 to the local input / output lines LIO to an external device (e.g., a controller). During a write operation, column control circuitry 36 can output data input from an external device (e.g., a controller) to the local input / output lines LIO. Column control circuitry 36 can be implemented using circuitry that performs input and output data operations in a general-purpose storage device. The local input / output lines LIO can be configured to include multiple local input / output lines.

[0108] The first storage area 41 may include the first to sixteenth rows of hammer-down text lines RWL1 to RWL16 (see [link to storage area]). Figure 2 and 9 The first storage area 41 may include hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to storage area]). Figure 2 and 9 Multiple row hammering units RC (see [link to RC]) Figure 2 and 9 During internal read operations, the first memory area 41 can output data stored on the row hammer input / output line RIO, which is coupled to the first to sixteenth row hammer word lines RWL1 to RWL16 (see [link to relevant documentation]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The first to sixth read count signals RCA<1:6> are stored in the row hammer input / output lines RIO. During internal write operations, the first memory area 41 can store the first to sixth write count signals WCA<1:6> loaded on the row hammer input / output lines RIO in the row hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to memory area 41]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The first memory area 41 can be initialized by receiving the initialization signal INIT input during the power-on period and the startup operation for powering on the electronic device 2. All bits of the first to sixth write count signals WCA<1:6> stored in the first memory area 41 can be generated with a logic low level. Although the first memory area 41 is implemented to include the first to sixteenth rows of hammer word lines RWL1 to RWL16 (see...) Figure 2 and 9However, the first storage area 41 can be implemented according to embodiments to include various numbers of row hammer word lines. The first storage area 41 can store the first to sixth write count signals WCA<1:6> coupled to the first to sixteenth row hammer word lines RWL1 to RWL16 (see See...). Figure 2 and 9 The RC hammer unit (see below) Figure 2 and 9 In this context, information about the number of logic level combinations input to addresses ADD<1:N> from the first to the Nth address is used to activate the first to sixteenth word lines WL1 to WL16 included in the second memory area 42 (see [link]). Figure 2 and 9 Because the first storage area 41 is based on... Figure 2 and 9 The first storage area 21 shown in the figure is implemented in the same manner and performs the same operations, so its detailed description will be omitted in this document.

[0109] The second storage area 42 may include the first to the sixteenth word lines WL1 to WL16 (see [link]). Figure 2 and 9 The second storage area 42 may include lines WL1 to WL16 coupled to the first to sixteenth word lines (see [link]). Figure 2 and 9 Multiple storage units MC (see [link to storage unit MC]) Figure 2 and 9 During a read operation, the second memory area 42 can receive the read signal RD, thereby outputting the memory stored on the local input / output line LIO to the local input / output line LIO and coupled to the first to sixteenth word lines WL1 to WL16 (see [link to local input / output line LIO]). Figure 2 and 9 The memory cell MC of the word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The data is stored in the local input / output line LIO. During a write operation, the second memory area 42 can receive a write signal WT, thereby storing the data loaded on the local input / output line LIO in the local input / output line LIO, coupled to the first to sixteenth word lines WL1 to WL16 (see [link to documentation]). Figure 2 and 9 The memory cell MC of the word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 In the self-refresh operation, the second memory area 42 can receive the internal refresh signal IR, thereby updating the first to sixteenth word lines WL1 to WL16 (see [link to relevant documentation]). Figure 2 and 9Perform a refresh operation. In a smart refresh operation, the second memory area 42 can refresh the word lines adjacent to the word lines selected by the first to Nth target addresses TAD<1:N>. The read signal RD and write signal WT can be set to signals generated internally by commands input from an external device (e.g., a controller) in general read and write operations. Although the second memory area 42 is implemented to include the first to sixteenth word lines WL1 to WL16 (see... Figure 2 and 9 However, the second storage area 42 can be implemented in embodiments to include various numbers of word lines. This is because the second storage area 42 is designed to be compatible with... Figure 2 and 9 The second storage area 22 shown in the figure is implemented in the same manner and performs the same operations, so its detailed description will be omitted in this document.

[0110] The first to sixteenth rows of hammer-on word lines RWL1 to RWL16 included in the first storage area 41 (see [link]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 42 (see Figure 2 and 9 In this context, word lines in the same order can be activated simultaneously via internal addresses IADD<1:N> from the first to the Nth. For example, when the first row hammer word line RWL1 included in the first memory area 41 is activated via internal addresses IADD<1:N> from the first to the Nth, see [link to relevant documentation]. Figure 2 and 9 When this is done, the first word line WL1 included in the second storage area 42 can be activated (see [link]). Figure 2 and 9 Although the hammer word lines RWL1 to RWL16 of the first to sixteenth rows included in the first storage area 41 are implemented through different word lines (see [link to documentation]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 42 (see Figure 2 and 9 However, this is just an example, and the hammered word lines RWL1 to RWL16 for lines 1 to 16 and WL1 to WL16 for lines 1 to 16 can be implemented using the same word lines.

[0111] The activation control circuit 31, target address generation circuit 32, internal address generation circuit 33, counting signal input / output circuit 34, refresh control circuit 35, and column control circuit 36 ​​can be located in column region 30. Figure 2 The column region) controls the storage area 40, which includes the first storage area 41 and the second storage area 42, or it can be located in the column region 30 ( Figure 2(column areas) and intersection areas (see column areas) Figure 2 Of the two.

[0112] As can be clearly seen from the above description, the electronic device 2 according to embodiments of the present disclosure may further include a storage area storing information about the number of inputs for all logic level combinations of an address, and may perform an intelligent refresh operation to refresh word lines adjacent to the most frequently activated word lines based on the result of counting all logic level combinations of an address. Furthermore, the electronic device 2 may store the result of counting all logic level combinations of an address, and by using this result, may refresh word lines adjacent to the most frequently activated word lines, thereby preventing interference between word lines.

[0113] like Figure 13 As shown, an electronic device 3 according to another embodiment of the present disclosure may include an activation control circuit 51, a target address generation circuit 52, an internal address generation circuit 53, a refresh control circuit 54, a first storage area 61, and a second storage area 62.

[0114] The activation control circuit 51 can receive an activation command ACT and a refresh command REF from an external device (e.g., a controller). The activation control circuit 51 can generate an internal read signal IRD, an internal compare signal ICMP, and an internal write signal IWT based on the activation command ACT and the refresh command REF. The activation control circuit 51 can sequentially generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. The activation control circuit 51 can generate the internal write signal IWT based on the refresh command REF. This is because the activation control circuit 51 is connected to... Figure 1 The activation control circuit 11 shown herein is implemented in the same way and performs the same operation, so its detailed description will be omitted herein.

[0115] The target address generation circuit 52 can receive the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT from the activation control circuit 51. The target address generation circuit 52 can receive the first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The target address generation circuit 52 can receive the first smart refresh signal SR1 and the second smart refresh signal SR2 from the refresh control circuit 54. During the internal read operation, the target address generation circuit 52 can generate the first to sixth count signals TWC<1:6> by counting up on the first to sixth read count signals RCA<1:6> (see [link to relevant documentation]). Figure 14This information is used to represent the number of logic level combinations input to addresses ADD<1:N> from the first to the Nth address. When the internal read signal IRD is input, the target address generation circuit 52 can generate the first to sixth count signals TWC<1:6> by counting up from the first to sixth read count signals RCA<1:6> input from the first memory area 61 (see [link to internal read signal generation circuit]). Figure 14 When the first to sixth counting signals TWC<1:6> (see also...) Figure 14 The number of counts exceeds the first to sixth stored count signals SWC<1:6> (see also...) Figure 5 When the target address generation circuit 52 generates the first to sixth counting signals TWC<1:6> (see [reference]), it can generate the target address. Figure 14 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5 The target address generation circuit 52 can receive the first smart refresh signal SR1 and the second smart refresh signal SR2 to convert the result with the first to sixth counting signals TWC<1:6> (see [link to circuit diagram]). Figure 14 The corresponding first to Nth addresses ADD<1:N> are stored as first to Nth target addresses TAD<1:N>. During internal write operations, the target address generation circuit 52 can output to the first memory area 61 based on the first to sixth count signals TWC<1:6> (see [link to documentation]). Figure 14 The first to sixth write count signals WCA<1:6> are generated. The target address generation circuit 52 can output to the first memory area 61 based on the first to sixth count signals TWC<1:6> by receiving the internal write signal IWT (see [link to documentation]). Figure 14 The first to sixth write count signals WCA<1:6> generated by the target address generation circuit 52 can be used to generate the first to sixth count signals TWC<1:6> that are counted the most (see [reference]). Figure 14 ) Stored as the first to sixth storage count signals SWC<1:6> (see also) Figure 5 In the intelligent refresh operation, the target address generation circuit 52 can store the first to sixth memory count signals SWC<1:6> (see [link to relevant documentation]). Figure 5 Initialize.

[0116] The internal address generation circuit 53 can receive first to Nth addresses ADD<1:N> from an external device (e.g., a controller). The internal address generation circuit 53 can generate first to Nth internal addresses IADD<1:N> based on the first to Nth addresses ADD<1:N>. The internal address generation circuit 53 can output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. Although the internal address generation circuit 53 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, the internal address generation circuit 53 can also be implemented to generate the first to Nth internal addresses IADD<1:N> by decoding the first to Nth addresses ADD<1:N>. The number of bits in the first to Nth addresses ADD<1:N> and the number of bits in the first to Nth internal addresses IADD<1:N> can be set differently depending on the embodiment.

[0117] The refresh control circuit 54 can receive a refresh command REF from an external device (e.g., a controller). Based on the refresh command REF, the refresh control circuit 54 can generate a first smart refresh signal SR1, a second smart refresh signal SR2, and an internal refresh signal IR. When the refresh command REF is repeatedly input a predetermined number of times to perform a smart refresh operation, the refresh control circuit 54 can generate the first smart refresh signal SR1 and the second smart refresh signal SR2 that are enabled sequentially. When the refresh command REF is repeatedly input a predetermined number of times to perform a self-refresh operation, the refresh control circuit 54 can generate the enabled internal refresh signal IR.

[0118] The first storage area 61 may include the first to sixteenth rows of hammer-down text lines RWL1 to RWL16 (see [link to storage area]). Figure 2 and 9 The first storage area 61 may include hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to storage area]). Figure 2 and 9 Multiple row hammering units RC (see [link to RC]) Figure 2 and 9 During internal read operations, the first memory area 61 can output data stored on hammer-word lines RWL1 to RWL16 coupled to the first to sixteenth lines (see [link to relevant documentation]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9The first to sixth write count signals WCA<1:6> in the memory are used as the first to sixth read count signals RCA<1:6>. During internal write operations, the first memory area 61 can store the first to sixth write count signals WCA<1:6> in the hammer word lines RWL1 to RWL16 coupled to the first to sixteenth rows (see [link to memory area 61]). Figure 2 and 9 The row hammer unit RC of the row hammer word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The first memory area 61 can be initialized by receiving the initialization signal INIT input during the power-on period and the startup operation for powering on the electronic device 3. All bits of the initialized first to sixth write count signals WCA<1:6> can be generated with a logic low level. Although the first memory area 61 is implemented to include the first to sixteenth rows of hammer word lines RWL1 to RWL16 (see...) Figure 2 and 9 However, the first storage area 61 can be implemented according to embodiments to include various numbers of row hammer word lines. The first storage area 61 can store the first to sixth write count signals WCA<1:6> coupled to the first to sixteenth row hammer word lines RWL1 to RWL16 (see See...). Figure 2 and 9 The RC hammer unit (see below) Figure 2 and 9 In the second memory area 62, information about the number of logic level combinations input for addresses ADD<1:N> from the first to the Nth address is used to activate the first to sixteenth word lines WL1 to WL16 (see [link to relevant documentation]). Figure 2 and 9 Because the first storage area 61 is based on... Figure 2 and 9 The first storage area 21 shown in the figure is implemented in the same manner and performs the same operations, so its detailed description will be omitted in this document.

[0119] The second storage area 62 may include the first to the sixteenth word lines WL1 to WL16 (see [link to storage area]). Figure 2 and 9 The second storage area 62 may include lines WL1 to WL16 coupled to the first to sixteenth word lines (see [link]). Figure 2 and 9 Multiple storage units MC (see [link to storage unit MC]) Figure 2 and 9 During a read operation, the second memory area 62 can receive the read signal RD, thereby outputting the data stored on the first to sixteenth word lines WL1 to WL16 (see [link to relevant documentation]). Figure 2 and 9 The memory cell MC of the word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 The data is stored in the second memory area 62. During a write operation, the second memory area 62 can receive a write signal WT, thereby storing the data in the memory coupled to the first to sixteenth word lines WL1 to WL16 (see [link to documentation]). Figure 2 and 9 The memory cell MC of the word line selected by the first to Nth internal address IADD<1:N> in ) (see Figure 2 and 9 In the self-refresh operation, the second memory area 62 can receive the internal refresh signal IR, thereby updating the first to sixteenth word lines WL1 to WL16 (see [link to relevant documentation]). Figure 2 and 9 The second memory area 62 performs a refresh operation. In a smart refresh operation, the second memory area 62 can refresh word lines adjacent to those selected via the first to Nth target addresses TAD<1:N>. The read signal RD and write signal WT can be configured as signals generated internally by commands input from an external device (e.g., a controller) during general read and write operations. Although the second memory area 62 is implemented to include first to sixteenth word lines WL1 to WL16 (see [link to documentation]). Figure 2 and 9 However, the second storage area 62 can be implemented in embodiments to include various numbers of word lines. This is because the second storage area 62 is designed to be compatible with... Figure 2 and 9 The second storage area 22 shown in the figure is implemented in the same manner and performs the same operations, so its detailed description will be omitted in this document.

[0120] The first to sixteenth rows of hammer-action word lines RWL1 to RWL16 included in the first storage area 61 (see [link to storage area]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 62 (see See Figure 2 and 9 In this context, word lines in the same order can be activated simultaneously via internal addresses IADD<1:N> from the first to the Nth. For example, when the first row hammer word line RWL1 included in the first memory area 61 is activated via internal addresses IADD<1:N> from the first to the Nth, see [link to relevant documentation]. Figure 2 and 9 When this is done, the first word line WL1 included in the second storage area 62 can be activated (see [link]). Figure 2 and 9 Although the hammer word lines RWL1 to RWL16 of the first to sixteenth rows included in the first storage area 61 are implemented through different word lines (see [link to documentation]). Figure 2 and 9 ) and the first to sixteenth word lines WL1 to WL16 included in the second storage area 62 (see See Figure 2 and 9 However, this is just an example, and the hammered word lines RWL1 to RWL16 and WL1 to WL16 of the first to sixteenth lines can be implemented using the same word lines.

[0121] The activation control circuit 51, the target address generation circuit 52, the internal address generation circuit 53, and the refresh control circuit 54 can be located in row region 50. Figure 2 The storage area 60, which controls the first storage area 61 and the second storage area 62, can be located in the row area 50 (or in the row area 50). Figure 2 (row areas) and intersection areas (see row areas) Figure 2 Of the two, the activation control circuit 51, the target address generation circuit 52, the internal address generation circuit 53, and the refresh control circuit 54 can be implemented as being located in the column region (see [link to relevant documentation]). Figure 2 The control storage area 60 is located in the column area (see [link]). Figure 2 ) and intersection areas (see Figure 2 Of the two.

[0122] Figure 14 This is a block diagram illustrating an embodiment of the target address generation circuit 52. (As shown) Figure 14 As shown, the target address generation circuit 52 may include an input circuit 521, an adder 522, an output circuit 523, a comparison circuit 524, and a smart refresh control circuit 525.

[0123] When the internal read signal IRD is input, the input circuit 521 can generate the first to sixth transmission read count signals TRC<1:6> based on the first to sixth read count signals RCA<1:6> received from the first memory area 61. When the internal read signal IRD is input, the input circuit 521 can generate the first to sixth transmission read count signals TRC<1:6> by buffering the first to sixth read count signals RCA<1:6>.

[0124] Adder 522 can count upwards on the first to sixth transmission read count signals TRC<1:6>. Adder 522 can generate the first to sixth count signals TWC<1:6> by counting upwards on the first to sixth transmission read count signals TRC<1:6>.

[0125] During an internal write operation, output circuit 523 can generate first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>. When an internal write signal IWT is input, output circuit 523 can generate first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>. When an internal write signal IWT is input, output circuit 523 can output the first to sixth write count signals WCA<1:6> to the first memory area 61. After performing a smart refresh operation, output circuit 523 can initialize all bits of the first to sixth write count signals WCA<1:6> to logic low. When a reset signal RST is input after performing a smart refresh operation, output circuit 523 can initialize all bits of the first to sixth write count signals WCA<1:6> to logic low. When the internal write signal IWT is input after the smart refresh operation is performed, the output circuit 523 can output the first to sixth write count signals WCA<1:6> to the first memory area 61, where all bits are initialized to logic low level.

[0126] When the internal comparison signal ICMP is input, the comparison circuit 524 can compare the first to sixth count signals TWC<1:6> with the first to sixth stored count signals SWC<1:6> stored in the comparison circuit 524 (see [link]). Figure 5 The flag signal UPF is generated by comparing the two signals. When the internal comparison signal ICMP is input, the first to sixth count signals TWC<1:6> are counted more than the first to sixth stored count signals SWC<1:6> stored in the comparison circuit 524 (see [link to comparison circuit]). Figure 5 In the case of a condition where the comparator circuit 524 can generate an enable flag signal UPF, when the internal comparator signal ICMP is input, the counts of the first to sixth count signals TWC<1:6> are less than or equal to the first to sixth stored count signals SWC<1:6> stored in the comparator circuit 524 (see [link to comparator circuit]). Figure 5 In the event of an error, comparator circuit 524 can generate an inhibit flag signal UPF. When the internal comparator signal ICMP is input, the first to sixth count signals TWC<1:6> are counted more than the first to sixth stored count signals SWC<1:6> stored in comparator circuit 524 (see [link to comparator circuit]). Figure 5 In the case of ), the comparator circuit 524 can store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6> (see [link to comparator circuit]). Figure 5 When a reset signal RST is input during a smart refresh operation, the comparator circuit 524 can convert the first to sixth memory count signals SWC<1:6> (see [link to relevant documentation]). Figure 5 All bits of the ) are initialized to logic low.

[0127] When the input flag signal UPF is received, the intelligent refresh control circuit 525 can store the first to Nth addresses ADD<1:N>. When the first intelligent refresh signal SR1 is received, the intelligent refresh control circuit 525 can generate the first to Nth target addresses TAD<1:N> based on the stored first to Nth addresses ADD<1:N>. When the second intelligent refresh signal SR2 is received, the intelligent refresh control circuit 525 can output the first to Nth target addresses TAD<1:N> to the second memory area 62. After the first intelligent refresh signal SR1 is received, the intelligent refresh control circuit 525 can generate an enable reset signal RST.

[0128] Figure 15 This is a block diagram illustrating an embodiment of the intelligent refresh control circuit 525. (As shown) Figure 15 As shown, the intelligent refresh control circuit 525 may include a first address storage circuit 525_1, a reset control circuit 525_2, and a second address storage circuit 525_3.

[0129] The first address storage circuit 525_1 can generate the first to Nth storage addresses SAD<1:N> from the first to Nth addresses ADD<1:N> based on the flag signal UPF and the first smart refresh signal SR1. When the flag signal UPF is input at a logic high level, the first address storage circuit 525_1 can store the first to Nth addresses ADD<1:N> as the first to Nth storage addresses SAD<1:N>. When the first smart refresh signal SR1 is input at a logic high level, the first address storage circuit 525_1 can output the stored first to Nth storage addresses SAD<1:N>.

[0130] The reset control circuit 525_2 can generate a reset signal RST based on the first smart refresh signal SR1. When the first smart refresh signal SR1 is input, the reset control circuit 525_2 can generate an enabled reset signal RST.

[0131] The second address storage circuit 525_3 can store the first to Nth storage addresses SAD<1:N>. When the second smart refresh signal SR2 is input at a logic high level, the second address storage circuit 525_3 can output the stored first to Nth storage addresses SAD<1:N> as the first to Nth target addresses TAD<1:N>.

[0132] Figure 16 This is a block diagram illustrating an embodiment of the refresh control circuit 54. (As shown) Figure 16 As shown, the refresh control circuit 54 may include a refresh counter 541 and a refresh signal generation circuit 542.

[0133] The refresh counter 541 can generate first to J refresh count signals RCNT<1:J> based on the refresh command REF. The refresh counter 541 can generate first to J refresh count signals RCNT<1:J> that count upwards with each input refresh command REF.

[0134] The refresh signal generation circuit 542 can generate a first smart refresh signal SR1, a second smart refresh signal SR2, and an internal refresh signal IR based on the first to Jth refresh count signals RCNT<1:J>. When the first to Jth refresh count signals RCNT<1:J> are counted to the fourth logic level combination, the refresh signal generation circuit 142 can generate the first smart refresh signal SR1 and the second smart refresh signal SR2 that are enabled sequentially. The fourth logic level combination of the first to Jth refresh count signals RCNT<1:J> can be set to the number of times the refresh command REF is input to perform a smart refresh operation. When the first to Jth refresh count signals RCNT<1:J> are counted to the fifth logic level combination, the refresh signal generation circuit 542 can generate the internal refresh signal IR. The fifth logic level combination of the first to Jth refresh count signals RCNT<1:J> can be set to the number of times the refresh command REF is input to perform a self-refresh operation.

[0135] The following will be referenced Figure 17 To describe the smart refresh operation of the electronic device 3 according to an embodiment of the present disclosure.

[0136] The intelligent refresh operation may include initialization operation step S10, activation detection step S20, target address generation step S30, and intelligent refresh operation step S40.

[0137] Initialization operation step S10 can be set as a power-on period and a startup operation for powering on electronic device 3. In initialization operation step S10, the first storage area 61 can receive the initialization signal INIT, thereby initializing the first to sixth write count signals WCA<1:6> stored in the first storage area 61. The first to sixth write count signals WCA<1:6> stored in the first storage area 61 can refer to the first to sixth write count signals WCA<1:6> stored respectively in the first to sixteenth rows of hammer word lines RWL1 to RWL16. All bits of the first to sixth write count signals WCA<1:6> can be initialized to a logic low level.

[0138] The activation detection step S20 may include activation operation step S210, internal read, count and internal write operation steps S220, and comparison operation step S230.

[0139] The activation operation step S210 can be configured to receive the activation command ACT, the refresh command REF, and the first to Nth addresses ADD<1:N> from an external device (e.g., a controller).

[0140] The internal read, count, and internal write operation step S220 can be configured to generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. In the internal read, count, and internal write operation step S220, the activation control circuit 51 can generate the internal read signal IRD, the internal compare signal ICMP, and the internal write signal IWT based on the activation command ACT. When the internal read signal IRD is generated in the internal read, count, and internal write operation step S220, the target address generation circuit 52 can generate the first to sixth count signals TWC<1:6> by counting upwards from the first to sixth read count signals RCA<1:6> input from the first memory area 61. In the internal read, count, and internal write operation step S220, after generating the internal read signal IRD, the activation control circuit 51 can generate the internal compare signal ICMP and the internal write signal IWT. When the internal write signal IWT is generated in the internal read, count, and internal write operation step S220, the target address generation circuit 52 can generate the first to sixth write count signals WCA<1:6> based on the first to sixth count signals TWC<1:6>, and can output the first to sixth write count signals WCA<1:6> to the first memory area 61. In the internal read, count, and internal write operation step S220, the first memory area 61 can store the first to sixth write count signals WCA<1:6>.

[0141] The comparison operation step S230 can be configured to compare the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In comparison operation step S230, when the internal comparison signal ICMP is input, the target address generation circuit 52 can compare the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In comparison operation step S230, when the first to sixth counting signals TWC<1:6> are counted more than the first to sixth storage counting signals SWC<1:6> (yes), the target address generation circuit 52 can generate an enable flag signal UPF. In comparison operation step S230, when the first to sixth counting signals TWC<1:6> are counted as less than or equal to the first to sixth storage counting signals SWC<1:6> (no), the target address generation circuit 52 can generate an disable flag signal UPF.

[0142] The target address generation step S30 may include a count signal update operation step S310, a target address update operation step S320, and a target address maintenance operation step S330.

[0143] When the first to sixth counting signals TWC<1:6> are counted more than the first to sixth stored counting signals SWC<1:6> in the comparison operation step S230 (yes), the counting signal update operation step S310 can be executed. In the counting signal update operation step S310, the target address generation circuit 52 can store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6> through the enabled flag signal UPF.

[0144] When the first to sixth counting signals TWC<1:6> are counted more than the first to sixth stored counting signals SWC<1:6> in the comparison operation step S230 (yes), the target address update operation step S320 can be executed. In the target address update operation step S320, the target address generation circuit 12 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> through the enabled flag signal UPF.

[0145] When the first to sixth count signals TWC<1:6> are counted as less than or equal to the first to sixth storage count signals SWC<1:6> (no) in the comparison operation step S230, the target address maintenance operation step S330 can be executed. In the target address maintenance operation step S330, the target address generation circuit 52 can store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> without using the disable flag signal UPF. In other words, the first to Nth target addresses TAD<1:N> can maintain information about the most active word lines. When the target address maintenance operation step S330 ends, the process can then proceed to the activation operation step S210.

[0146] The intelligent refresh operation step S40 may include the storage count signal initialization operation step S410 and the intelligent refresh execution step S420.

[0147] The storage count signal initialization operation step S410 can be set to initialize the first to sixth storage count signals SWC<1:6> (see [link to documentation]). Figure 5The initialization step S410 can be configured to initialize the row hammering units RC included in the first memory area 61. In the initialization step S410, the refresh control circuit 54 can generate a first smart refresh signal SR1 via the refresh command REF. In the initialization step S410, the target address generation circuit 52 can reset the first to sixth memory count signals SWC<1:6> (see [reference]) via the reset signal RST generated by the first smart refresh signal SR1. Figure 5 All bits of the count signal are initialized to logic low. In the storage count signal initialization operation step S410, the row hammer unit RC included in the first storage area 61 can be initialized.

[0148] The smart refresh execution step S420 can be configured to perform a smart refresh operation via a refresh command REF. In smart refresh execution step S420, when the second smart refresh signal SR2 is input, the target address generation circuit 52 can output the stored first to Nth target addresses TAD<1:N> to the second memory area 62. In smart refresh execution step S420, the second memory area 62 can perform a smart refresh operation by activating word lines N-1 and N+1 adjacent to the word lines selected by the first to Nth target addresses TAD<1:N>. When smart refresh execution step S420 ends, the process can proceed to the activation operation step S210.

[0149] The following will be referenced Figure 18 To describe the smart refresh operation of the electronic device 3 according to an embodiment of the present disclosure.

[0150] At time point T11, the activation command ACT can be input from an external device (e.g., a controller).

[0151] At time T12, the activation control circuit 51 can generate an internal read signal IRD based on the activation command ACT. The target address generation circuit 52 can receive the internal read signal IRD and generate a first to sixth count signal TWC<1:6> by counting up the first to sixth read count signals RCA<1:6> input from the first memory area 61.

[0152] At time T13, the activation control circuit 51 can generate the internal comparison signal ICMP based on the activation command ACT. The target address generation circuit 52 can generate the flag signal UPF by comparing the first to sixth count signals TWC<1:6> with the first to sixth storage count signals SWC<1:6>. When the flag signal UPF is enabled, the target address generation circuit 52 can store the first to Nth addresses ADD<1:N> as the first to Nth storage addresses SAD<1:N>. When the flag signal UPF is enabled, the target address generation circuit 52 can store the first to sixth count signals TWC<1:6> as the first to sixth storage count signals SWC<1:6>. The first to sixth storage count signals SWC<1:6> can be generated based on the first to sixth count signals TWC<1:6> with the most counts. When the flag signal UPF is disabled, the target address generation circuit 52 can choose not to store the first to Nth addresses ADD<1:N> as the first to Nth storage addresses SAD<1:N>. When the flag signal UPF is disabled, the target address generation circuit 52 may not store the first to sixth counting signals TWC<1:6> as the first to sixth stored counting signals SWC<1:6>.

[0153] At time T14, the activation control circuit 51 can generate an internal write signal IWT based on the activation command ACT. The target address generation circuit 52 can receive the internal write signal IWT and thus output the first to sixth write count signals WCA<1:6> generated based on the first to sixth count signals TWC<1:6> to the first memory area 61. The first memory area 61 can store the first to sixth write count signals WCA<1:6> in the row hammering unit RC of the row hammering word lines activated by the first to Nth internal addresses IADD<1:N>, which are coupled to the first to sixteenth row hammering word lines RWL1 to RWL16.

[0154] At time point T15, a refresh command REF can be input from an external device (e.g., a controller).

[0155] At time T16, the refresh control circuit 54 can generate a first smart refresh signal SR1 based on the refresh command REF. The target address generation circuit 52 can store the first to Nth memory addresses SAD<1:N> as the first to Nth target addresses TAD<1:N> using the first smart refresh signal SR1. When the first smart refresh signal SR1 is input, the target address generation circuit 52 can generate a reset signal RST. The refresh control circuit 54 can initialize all bits of the first to sixth memory count signals SWC<1:6> to logic low level using the reset signal RST generated after outputting the first to Nth memory addresses SAD<1:N>. That is, the first to sixth memory count signals SWC<1:6> can be initialized (memory count signal initialization).

[0156] The activation control circuit 51 can generate an internal write signal IWT based on the refresh command REF. The target address generation circuit 52 can receive the internal write signal IWT, thereby outputting first to sixth write count signals WCA<1:6>, where all bits are initialized to logic low, to the first memory area 61. The first memory area 61 can store the initialized first to sixth write count signals WCA<1:6> in the row hammering cells RC of the row hammering word lines activated by the first to Nth internal addresses IADD<1:N>, which are coupled to the first to sixteenth row hammering word lines RWL1 to RWL16. That is, the row hammering cells RC of the first memory area 61 can be initialized (RC initialization).

[0157] At time point T17, a refresh command REF can be input from an external device (e.g., a controller).

[0158] At time T18, the refresh control circuit 54 can generate the first pulse of the second smart refresh signal SR2 based on the refresh command REF. The target address generation circuit 52 can output the first to Nth target addresses TAD<1:N> to the second memory area 62 via the first pulse of the second smart refresh signal SR2. The second memory area 62 can perform a smart refresh operation (smart refresh) by activating word line N+1 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. Simultaneously, the second memory area 62 can perform a smart refresh operation (smart refresh) by activating word line N+2 adjacent to the word line selected by the first to Nth target addresses TAD<2:N> among the first to sixteenth word lines WL1 to WL16.

[0159] At time T19, the refresh control circuit 54 can generate a second pulse of the second smart refresh signal SR2 based on the refresh command REF. The target address generation circuit 52 can output the first to Nth target addresses TAD<1:N> to the second memory area 62 via the second pulse of the second smart refresh signal SR2. The second memory area 62 can perform a smart refresh operation (smart refresh) by activating word line N-1 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. Simultaneously, the second memory area 62 can perform a smart refresh operation (smart refresh) by activating word line N-2 adjacent to the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16.

[0160] As can be clearly seen from the above description, the electronic device 3 according to embodiments of the present disclosure may further include a storage area storing information about the number of inputs for all logic level combinations of the address, and may perform an intelligent refresh operation to refresh the word line adjacent to the most frequently activated word line based on the result of counting all logic level combinations of the address. Furthermore, the electronic device 3 may store the result of counting all logic level combinations of the address, and by using this result, may refresh the word line adjacent to the most frequently activated word line, thereby preventing interference between word lines.

[0161] Figure 19 This is a block diagram illustrating the structure of an electronic system 1000 according to an embodiment of the present disclosure. Figure 19 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

[0162] The host 1100 and the semiconductor system 1200 can transmit signals to each other using an interface protocol. Examples of interface protocols used between the host 1100 and the semiconductor system 1200 may include MMC (Multimedia Card), ESDI (Enhanced Small Digital Disk Interface), IDE (Electronic Integrated Drive), PCI-E (Peripheral Component Interconnect), ATA (Advanced Technology Accessories), SATA (Serial ATA), PATA (Parallel ATA), SAS (Serial Attached SCSI), and USB (Universal Serial Bus).

[0163] Semiconductor system 1200 may include controller 1300 and electronic device 1400 (K:1). Controller 1300 may control electronic device 1400 (K:1) to perform intelligent refresh operations. Each electronic device 1400 (K:1) may additionally include a storage area storing information about the number of inputs for all logic level combinations of an address, and may perform intelligent refresh operations on word lines adjacent to the most frequently activated word lines based on the result of counting all logic level combinations of an address. Each electronic device 1400 (K:1) may store the result of counting all logic level combinations of an address, and by using this result, may refresh word lines adjacent to the most frequently activated word lines, thereby preventing interference between word lines.

[0164] Can be used Figure 1 Electronic device 1 shown in the image Figure 12 Electronic device 2 shown in the figure and Figure 13 Each electronic device 1400 (K:1) is implemented using the electronic device 3 shown in the figure. According to the embodiment, each electronic device 1400 (K:1) can be implemented using one of DRAM (Dynamic Random Access Memory), PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetic Random Access Memory), and FRAM (Ferroelectric Random Access Memory).

[0165] Although some embodiments of the present teachings have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions and substitutions can be made without departing from the scope and spirit of the present teachings as defined in the appended claims.

Claims

1. An electronic device, comprising: A target address generation circuit generates a counting signal by counting the number of times each logic level combination of the address input during an activation operation is performed by performing an internal read operation and an internal write operation. When the counting signal is counted more than the stored counting signal stored in the target address generation circuit, the counting signal is stored as the stored counting signal, and the address corresponding to the counting signal is stored as the target address. as well as A refresh control circuit controls the intelligent refresh operation on the target address. The target address generation circuit initializes the row hammer unit after performing the intelligent refresh operation. The row hammer unit stores the same counting signal as the stored counting signal.

2. The electronic device according to claim 1, wherein, The target address generation circuit stores the counting signal that is counted most frequently among the logic level combinations of the address as the stored counting signal.

3. The electronic device according to claim 1, wherein, The smart refresh operation is the operation of refreshing one of the multiple word lines included in the storage area that is arranged adjacent to the word line selected through the target address.

4. The electronic device according to claim 1, wherein, The target address generation circuit includes: The input circuit generates a transmission read count signal based on the read count signal received from the memory area when an internal read signal is input. An adder that generates the count signal by counting up on the transmitted read count signal; An output circuit that generates a write count signal based on the count signal when an internal write signal is input, and outputs the write count signal to the memory area; A comparison circuit generates a flag signal by comparing the counting signal with the stored counting signal, stores the counting signal as the stored counting signal again when the flag signal is generated, and initializes the stored counting signal when a reset signal is input; and The intelligent refresh control circuit stores the address when the flag signal is input, outputs the stored address as the target address when the intelligent refresh signal is input, and generates the reset signal by delaying the intelligent refresh signal.

5. The electronic device according to claim 4, wherein, The comparison circuit includes: A counting signal storage circuit that stores the counting signal as the stored counting signal when the flag signal is input, and initializes the stored counting signal when the reset signal is input; and A flag signal generation circuit generates the flag signal when the count signal is counted upwards more than the stored count signal.

6. The electronic device according to claim 4, wherein, The intelligent refresh control circuit includes: An address storage circuit stores the address when the flag signal is input, and outputs the stored address as the target address when the smart refresh signal is input; and A reset control circuit generates the reset signal by delaying the smart refresh signal until the smart refresh operation is completed.

7. The electronic device according to claim 4, wherein, The storage area includes: A first storage area has multiple row hammer word lines and multiple row hammer units coupled to the multiple row hammer word lines, and during the internal read operation, outputs the read count signal stored in the row hammer unit of the row hammer word line selected by an internal address among the multiple row hammer word lines, and during the internal write operation, stores the write count signal in the row hammer unit of the row hammer word line selected by the internal address among the multiple row hammer word lines; and The second storage area includes multiple word lines and multiple storage cells coupled to the multiple word lines. In the smart refresh operation, the second storage area refreshes the word lines adjacent to the word line selected by the target address. In the read operation, it outputs first data stored in the storage cells of the word lines selected by the internal address that are coupled to the multiple word lines. In the write operation, it stores second data in the storage cells of the word lines selected by the internal address that are coupled to the multiple word lines.

8. The electronic device according to claim 7, further comprising: An activation control circuit is used to generate an internal read signal and an internal write signal to control the internal read operation by receiving an activation command and a refresh command, and to generate an internal comparison signal to control the internal write operation. as well as An internal address generation circuit that generates the internal address based on the address.

9. The electronic device according to claim 8, wherein, The activation control circuit, the internal address generation circuit, the target address generation circuit, and the refresh control circuit are located in the row region to control the storage area, or are located in both the row region and the intersection region.

10. The electronic device according to claim 7, further comprising: An activation control circuit is used to generate an internal read signal and an internal write signal to control the internal read operation by receiving an activation command and a refresh command, and to generate an internal comparison signal to control the internal write operation. An internal address generation circuit that generates the internal address based on the address; An input / output control circuit is coupled to the first memory area via a row hammer input / output line. During the internal read operation, the input / output control circuit receives and outputs the read count signal via the row hammer input / output line, and during the internal write operation, it receives and outputs the write count signal via the row hammer input / output line. as well as A column control circuit, coupled to the second storage area via a local input / output line, receives and outputs the first data via the local input / output line during the read operation, and receives and outputs the second data via the local input / output line during the write operation.

11. The electronic device according to claim 10, wherein, The activation control circuit, the internal address generation circuit, the target address generation circuit, the refresh control circuit, the input / output control circuit, and the column control circuit are located in the column region to control the storage area, or are located in both the column region and the intersection region.

12. An electronic device, comprising: A target address generation circuit generates a counting signal by counting the number of times each logic level combination of the address input during an activation operation is performed by performing an internal read operation and an internal write operation. When the counting signal is counted up, the counting signal is stored as a storage counting signal. The address corresponding to the counting signal is stored as a target address. The storage counting signal is initialized during a first smart refresh operation, and the target address is output during a second smart refresh operation. as well as A refresh control circuit that controls the intelligent refresh operation on the target address during the second intelligent refresh operation. The target address generation circuit initializes the row hammer unit after performing the intelligent refresh operation. The row hammer unit stores the same counting signal as the stored counting signal.

13. The electronic device according to claim 12, wherein, The first smart refresh operation and the second smart refresh operation are executed sequentially using a refresh command.

14. The electronic device according to claim 12, wherein, The target address generation circuit stores the counting signal that is counted most frequently among the logic level combinations of the address as the stored counting signal.

15. The electronic device according to claim 12, wherein, The second smart refresh operation refreshes the word lines among the multiple word lines included in the storage area that are arranged adjacent to the word line selected by the target address.

16. The electronic device according to claim 12, wherein, The target address generation circuit includes: The input circuit generates a transmission read count signal based on the read count signal received from the memory area when an internal read signal is input. An adder that generates the count signal by counting up on the transmitted read count signal; An output circuit that, when an internal write signal is input, generates a write count signal based on the count signal and outputs the write count signal to the memory area. A comparison circuit generates a flag signal by comparing the counting signal with the stored counting signal, stores the counting signal as the stored counting signal again when the flag signal is generated, and initializes the stored counting signal when a reset signal is input; and The intelligent refresh control circuit stores the address as a storage address when the flag signal is input, generates the reset signal when the first intelligent refresh signal is input, and outputs the storage address as the target address when the second intelligent refresh signal is input.

17. The electronic device according to claim 16, wherein, The comparison circuit includes: A counting signal storage circuit that stores the counting signal as the stored counting signal when the flag signal is input, and initializes the stored counting signal when the reset signal is input; and A flag signal generation circuit generates the flag signal when the count signal is counted upwards more than the stored count signal.

18. The electronic device according to claim 16, wherein, The intelligent refresh control circuit includes: A first address storage circuit stores the address when the flag signal is input, and outputs the stored address as the storage address when the first smart refresh signal is input. A reset control circuit that generates an enabling reset signal when the first smart refresh signal is input; and The second address storage circuit outputs the stored address as the target address when the second intelligent refresh signal is input.

19. The electronic device according to claim 16, wherein, The storage area includes: A first storage area includes a plurality of row hammer word lines and a plurality of row hammer units coupled to the plurality of row hammer word lines. During the internal read operation, the first storage area outputs a read count signal stored in the row hammer unit of the row hammer word line selected by an internal address among the plurality of row hammer word lines, and during the internal write operation, stores the write count signal in the row hammer unit of the row hammer word line selected by the internal address among the plurality of row hammer word lines; and The second storage area includes a plurality of word lines and a plurality of storage cells coupled to the plurality of word lines. When the second smart refresh signal is input, the second storage area refreshes the word line adjacent to the word line selected by the target address. During a read operation, it outputs first data stored in the storage cell of the word line selected by the internal address coupled to the plurality of word lines. During a write operation, it stores second data in the storage cell of the word line selected by the internal address coupled to the plurality of word lines.

20. The electronic device of claim 19, further comprising: An activation control circuit is used to generate an internal read signal and an internal write signal to control the internal read operation by receiving an activation command and a refresh command, and to generate an internal comparison signal to control the internal write operation. as well as An internal address generation circuit that generates the internal address based on the address.

21. The electronic device according to claim 20, wherein, The activation control circuit includes: A ring oscillator that generates a periodic signal that switches upon input of either the activation command or the refresh command; A ROD counter generates an oscillating count signal that is counted each time a pulse of the input periodic signal is received; and An internal signal generation circuit generates the internal read signal when the oscillation count signal is counted to a first logic level combination, generates the internal write signal when the oscillation count signal is counted to a second logic level combination, and generates the internal comparison signal when the oscillation count signal is counted to a third logic level combination.

22. The electronic device according to claim 13, wherein, The refresh control circuit includes: A refresh counter that generates a refresh count signal that is counted based on the number of times the refresh command is input; and A refresh signal generation circuit generates a first smart refresh signal to control the first smart refresh operation when the refresh count signal is counted to a fourth logic level combination, and generates a second smart refresh signal to control the second smart refresh operation when the refresh count signal is counted to a fifth logic level combination.

23. A smart refresh method, comprising: Perform internal read and internal write operations, which generate a counting signal by counting the number of times each logic level combination of the address input during the activation operation is performed. A target address is generated by comparing the counting signal with the stored counting signal to generate a flag signal, and a target address for performing a smart refresh operation is generated from the address based on the flag signal. When a refresh command is input, the smart refresh operation is performed by refreshing the word line adjacent to the word line corresponding to the target address in the word lines included in the storage area. as well as After performing the intelligent refresh operation, the row hammer unit is initialized, and the row hammer unit stores the same count signal that is being counted as the stored count signal.

24. The intelligent refresh method according to claim 23, wherein, The storage count signal is initialized during the smart refresh operation.

25. The intelligent refresh method according to claim 23, wherein, The generated target address includes: A counting signal update operation is performed, wherein when a flag signal is enabled because the counting signal is counted more than the stored counting signal, the counting signal is stored as the stored counting signal; Perform a target address update operation, wherein the target address update operation stores the address as the target address when the flag signal is enabled; and A target address maintenance operation is performed, which maintains the target address when the flag signal is disabled.

26. The intelligent refresh method according to claim 23, wherein, The execution of intelligent refresh includes: Perform a storage count signal initialization operation, wherein the storage count signal initialization operation initializes the storage count signal during the first smart refresh operation; and A second smart refresh is executed, in which the target address is output to the storage area and the smart refresh operation is performed to refresh the word line adjacent to the word line corresponding to the target address.

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