Storage system

Abstract

The present invention relates to a memory system. The memory system comprises a normal memory area adapted to store normal data, a secure memory area adapted to store secure data, a first row hammer detection circuit adapted to sample and count activated partial rows in the normal memory area to select a first row to be refreshed, and a second row hammer detection circuit adapted to count all activated rows in the secure memory area to select a second row to be refreshed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 123,703, filed December 10, 2020, and to Korean Patent Application No. 10-2021-0154680, filed November 11, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to a storage system. Background Technology

[0004] As memory integration density increases, the spacing between multiple word lines in the memory decreases. As the spacing between word lines decreases, the coupling effect between adjacent word lines increases.

[0005] Furthermore, word lines switch between active and inactive states whenever data is input to or output from a memory cell. As the coupling effect between adjacent word lines increases, data stored in memory cells coupled to word lines located adjacent to frequently active word lines may be corrupted (i.e., lost). This phenomenon is known as "word line interference" or "row hammering." The concern is that data in a memory cell may be corrupted due to row hammering before the cell is refreshed.

[0006] Figure 1 This is a schematic diagram used to describe the hammering.

[0007] exist Figure 1 In this code, "WLL" represents a word line that has been activated too many times (i.e., over-activated), and "WLL-1" and "WLL+1" represent word lines adjacent to word line "WLL". Furthermore, "CL" represents a memory cell coupled to the over-activated word line "WLL", and "CL-1" and "CL+1" represent memory cells coupled to adjacent word lines "WLL-1" and "WLL+1", respectively. Each memory cell includes a cell transistor TL, TL-1, or TL+1 and a cell capacitor CAPL, CAPL-1, or CAPL+1. Additionally, "BL0" and "BL1" represent bit lines.

[0008] When word line "WLL" is activated or deactivated, the voltage levels of adjacent word lines "WLL-1" and "WLL+1" may increase or decrease due to the coupling effect between the overactivated word line "WLL" and its adjacent word lines "WLL-1" and "WLL+1", thus affecting the amount of charge stored in cell capacitors CL-1 and CL+1. Therefore, the more frequently word line "WLL" switches between active and inactive states, the greater the change in the amount of charge stored in the cell capacitors CAPL-1 and CAPL+1 of adjacent memory cells "CL-1" and "CL+1", leading to data degradation in the memory cells.

[0009] Furthermore, electromagnetic waves generated when word lines switch between active and inactive states may corrupt data by charging electrons into or discharging electrons from the cell capacitors of memory cells coupled to adjacent word lines.

[0010] To address the line hammering problem, the main approach is to detect lines that have been activated multiple times (i.e., word lines) and refresh the adjacent lines of those lines. Summary of the Invention

[0011] Embodiments of the present invention relate to improving the ability to protect storage systems from row hammer attacks.

[0012] According to one embodiment of the present invention, a storage system includes: a normal storage area adapted to store normal data; a secure storage area adapted to store secure data; a first row hammer detection circuit adapted to sample a portion of the activated rows in the normal storage area and count the number of activations of the sampled rows to select a first row to be refreshed from the sampled rows; and a second row hammer detection circuit adapted to count the number of activations of all rows in the secure storage area to select a second row to be refreshed.

[0013] According to another embodiment of the present invention, a storage system includes: a memory including a normal area adapted to store normal data and a secure area adapted to store secure data; and a host including: an error correction code storage area adapted to store error correction codes corresponding to secure data; and an error correction circuit adapted to correct errors in data read from the secure area based on the error correction codes stored in the error correction code storage area.

[0014] According to another embodiment of the present invention, a storage system includes: a normal storage area adapted to store normal data; a secure storage area adapted to store secure data; and a processor including a cache memory, wherein the processor is only allowed to access the secure storage area via the cache memory.

[0015] According to another embodiment of the present invention, a storage system includes: a normal storage area adapted to store normal data; a secure storage area adapted to store secure data; a first row hammer detection circuit adapted to sample a portion of the activated rows in the normal storage area and count the number of activations of the sampled rows to select a first row to be refreshed; a second row hammer detection circuit adapted to count the number of activations of all rows in the secure storage area to select a second row to be refreshed; a cache memory adapted to store error correction codes corresponding to the secure data; and an error correction circuit adapted to correct errors in data read from the secure area based on the error correction codes stored in the cache memory.

[0016] According to another embodiment of the present invention, a storage system includes: a memory comprising: a normal region adapted to store normal data; a secure region adapted to store secure data; a first row hammer detection circuit adapted to count the number of activations of rows in the normal region in a random row counting manner to detect rows to be refreshed; and a processor comprising: a second row hammer detection circuit adapted to count the number of activations of rows in the secure region in a full row counting manner to detect rows to be refreshed. Attached Figure Description

[0017] Figure 1 This is a schematic diagram used to describe the hammering.

[0018] Figure 2 This is a block diagram illustrating a storage system according to an embodiment of the present invention.

[0019] Figure 3 This illustrates an embodiment of the present invention. Figure 2 The diagram shows a detailed block diagram of the memory.

[0020] Figure 4 This illustrates an embodiment of the present invention. Figure 2 The detailed block diagram of the memory controller is shown below.

[0021] Figure 5 This illustrates an embodiment of the present invention. Figure 2 The table shows an example of the counting results stored in the last-level cache memory. Detailed Implementation

[0022] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0023] Figure 2 This is a block diagram illustrating a storage system 200 according to an embodiment of the present invention.

[0024] refer to Figure 2 The storage system 200 may include a processor 210 and a memory 250.

[0025] Processor 210 may include processor core 211, cache controller 213, different levels of cache memories 215, 217, and 219, and memory controller 221. The components included in processor 210 may communicate via memory bus 223. Processor 210 may be an entity that processes data or signals. Examples of processor 210 may include a microprocessor, central processing unit (CPU), graphics processing unit (GPU), application processor (AP), digital signal processor (DSP), etc.

[0026] Processor core 211 may include circuitry for processing instructions of the computing system. Processor core 211 may be single-core or multi-core. Processor core 211 may use different levels of cache memories 215, 217, and 219 to access data stored in memory 250.

[0027] Cache memories 215, 217, and 219 can be divided into several levels. Lower cache levels may offer faster operation, but may also have smaller capacities. Cache controller 213 manages cache memories 215, 217, and 219 and determines whether to retrieve data for processor core 211 from one of these cache memories or from memory 250. Processor core 211 may preferentially retrieve the required data from cache memories 215, 217, and 219. When the required data is not cached in cache memories 215, 217, and 219, processor core 211 may retrieve the required data from memory 250 via memory controller 221.

[0028] The memory controller 221 can control the operation of the memory 250. The processor 210 can access the memory 250 via the memory controller 221. That is, the processor 210 can write data to the memory 250 and read data stored in the memory 250 via the memory controller 221. The memory controller 221 can send commands / addresses (CA) to the memory 250 to control the operation of the memory 250, and can send data (DATA) to and receive data (DATA) from the memory 250.

[0029] Here, although the memory controller 221 is shown here as being included in the processor 210, it will be apparent to those skilled in the art that the memory controller 221 may exist outside the processor 210. The device in the storage system 200 that includes the memory controller 221 is generally referred to as the host. Therefore, in Figure 2 In this context, processor 210 can be the host.

[0030] Memory 250 can perform operations instructed by memory controller 221. Memory 250 can be one type of random access memory such as dynamic random access memory (DRAM), static RAM (SRAM), phase-change RAM (PCRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), etc. It can also be another type of memory that requires refresh operations. For example, memory 250 may be a memory in which data may be lost due to row hammering.

[0031] Figure 3 This illustrates an embodiment of the present invention. Figure 2 A detailed block diagram of the memory 250 shown.

[0032] refer to Figure 3 The memory 250 may include a control circuit 310, a first row hammer impact detection circuit 320, and a cell array 330.

[0033] The control circuit 310 can control the overall operation of the memory 250. The control circuit 310 can control the internal components of the memory 250, enabling the memory to perform operations indicated by the command / address CA, such as activation operations, precharge operations, read operations, write operations, and refresh operations.

[0034] Cell array 330 may include multiple storage cells arranged in multiple rows and multiple columns. Cell array 330 may include a normal area 331 and a secure area 333. Normal area 331 may be a storage cell area (i.e., a storage area or memory area) for storing general data, and secure area 333 may be a storage cell area for storing security-critical data. Because normal area 331 and secure area 333 are used to distinguish different strategies applied to them, normal area 331 and secure area 333 can be distinguished by address. For example, when the number of rows in the cell array is N+1, the range of normal area 331 can be from row 0 to row K, while the range of secure area 333 can be from row K+1 to row N. Because secure area 333 can store only a portion of security-critical data, the size of secure area 333 can be much smaller than the size of normal area 331. For example, the size of normal area 331 can be tens to thousands of times larger than the size of secure area 333.

[0035] The first row hammer detection circuit 320 can select rows to be refreshed by sampling a subset of activated rows in the cell array 330 and counting the activation count of the sampled rows. Specifically, there may be numerous activated rows in the cell array 330, and the first row hammer detection circuit 320 can detect over-activated rows by randomly sampling some of the numerous activated rows in the cell array 330 and counting the activation count of the sampled rows. Further, the neighboring rows of the over-activated rows (i.e., rows that may have lost data due to row hammering) can be classified as rows to be refreshed.

[0036] The first-row hammer detection circuit 320 does not count the activation counts of all activated rows in the cell array 330, but only counts the activation counts of some sampled rows. This is because it is difficult for the first-row hammer detection circuit 320 to count the activation counts of all activated rows in the cell array 330, and implementing such circuitry would be too cumbersome in terms of area and current consumption. Rows classified by the first-row hammer detection circuit 320 as needing to be refreshed can be refreshed preferentially or additionally during normal refresh operations, or can be refreshed when a command (e.g., a refresh management command) is applied.

[0037] The memory controller 221 can classify rows in the safe region 333 of the cell array 330 that may have lost data due to row hammering as rows to be refreshed. Therefore, the first row hammering detection circuit 320 can exclude the safe region 333 from the management scope and select the rows to be refreshed by sampling only a portion of the activated rows in the normal region 231 to count the number of activations of the sampled rows.

[0038] Figure 4This illustrates an embodiment of the present invention. Figure 2 The detailed block diagram of the memory controller 221 shown is shown.

[0039] refer to Figure 4 The memory controller 221 may include a host interface 401, a scheduler 403, a command generator 405, a second-line hammer detection circuit 407, an error correction circuit (ECC) 409, and a memory interface 411.

[0040] The host interface 401 can be used as an interface between the memory controller 221 and other components of the processor 210. The memory controller 221 can be coupled to the memory bus 223 via the host interface 401.

[0041] Scheduler 403 can schedule operations on memory 250. Scheduler 403 can determine the order in which requests to be directed to memory 250 are sent via memory bus 223. To improve performance, scheduler 403 can change the order of requests received via memory bus 223 when operations corresponding to requests are directed to memory 250. For example, even if a read operation is requested first and then a write operation is requested via memory bus 223, the order of operations can be changed so that the write operation to memory 250 is performed before the read operation.

[0042] Command generator 405 can generate commands to be applied to memory 250 according to the order of operations determined by scheduler 403.

[0043] The memory interface 411 can be used as an interface between the memory controller 221 and the memory 250. Commands / addresses (CA) can be sent from the memory controller 221 to the memory 250 through the memory interface 411, and data (DATA) can be sent / received. The memory interface 411 can also be referred to as the physical layer (PHY) interface.

[0044] The second row hammer detection circuit 407 can select rows that need to be refreshed by counting the activation counts of all activated rows in the safe region 333 of the memory 250. The second row hammer detection circuit 407 can also detect over-activated rows by counting the activation counts of all activated rows in the safe region. Furthermore, adjacent rows of over-activated rows (i.e., rows that may lose data due to row hammering) can also be classified as rows that need to be refreshed. Since the activation operation of the memory 250 is executed according to the command of the memory controller 221, the second row hammer detection circuit 407 of the memory controller 221 can detect which row in the safe region 333 of the memory 250 is activated. For rows classified as needing refresh by the second row hammer detection circuit 407, the memory controller 221 can command the memory 250 to perform an activation operation or a refresh operation that can also prevent data loss. Therefore, data loss corresponding to the row to be refreshed can be prevented.

[0045] Since the second-row hammer impact detection circuit 407 counts the activation counts of all rows in the safe region 333 in a row-by-row counting manner, it may be operationally burdensome. However, this operation is possible because the size of the safe region 333 is relatively small. The second-row hammer impact detection circuit 407 requires storage circuitry for counting, and one of the cache memories 215, 217, and 219 of the processor 210 can be used as the storage circuitry for storing the counting results. Since the last cache memory 219 among the cache memories 215, 217, and 219 has the largest capacity, it is expected that the second-row hammer impact detection circuit 407 will use cache memory 219 as the storage circuitry. Furthermore, storage circuitry for storing the counting results can be provided in the second-row hammer impact detection circuit 407. Figure 5 An example of a count result stored in the final-level cache memory 219 is illustrated. (Reference) Figure 5 As can be seen, the number of activations is counted for each row of the security region 333. The final-level cache memory 219 can have a lowest level.

[0046] Error correction circuit 409 may be a circuit for error correction of secure region 333. Error correction circuit 409 may generate error correction codes for correcting errors in the written data during write operations to secure region 333, and store the error correction codes in one of the cache memories 215, 217, and 219 (i.e., the error correction code storage area). It is desirable to store the error correction codes in the last-level cache memory 219 among cache memories 215, 217, and 219. During read operations to secure region 333, error correction circuit 409 may correct errors in the data read from secure region 333 based on the error correction codes stored in cache memory 219. That is, during a write operation, the error correction circuit 409 can store error correction codes for correcting errors in the data stored in the secure area 333 in the cache memory 219, and during a read operation, the error correction circuit 409 can correct errors in the data read from the secure area 333 based on the error correction codes stored in the cache memory 219.

[0047] Storage system 200 can protect secure data stored in secure area 333 by distinguishing between normal area 331 and secure area 333 in the following three ways.

[0048] 1. Count of activated rows

[0049] The number of times a row is activated in the normal region 331 can be counted by the first row hammer detection circuit 320 in a random row counting manner. Since not all activated rows are counted, but only some rows are randomly selected and counted, this counting method is often unreliable. The reliability of the method for selecting rows from the row hammer attack in the normal region 331 may not be 100%.

[0050] On the other hand, the number of activations of rows activated in secure region 333 can be counted by the second row hammer detection circuit 407 in a row-wide count manner. Since all rows activated in secure region 333 are counted, rows targeted for row hammer attacks can be selected with almost 100% confidence. Therefore, data stored in secure region 333 can be more protected than data stored in normal region 331.

[0051] 2. Error Correction Method

[0052] Error correction circuit 409 can perform error correction operations only on data stored in secure area 333. Therefore, data stored in secure area 333 is more protected than data stored in normal area 331. Although additional error correction circuits may be provided in storage system 200 besides error correction circuit 409, this error correction circuit can protect both data stored in secure area 333 and data stored in normal area 331. Therefore, the fact that data stored in secure area 333 is more protected than data stored in normal area 331 remains unchanged.

[0053] 3. Access Method

[0054] Memory 250 is typically accessed via cache memories 215, 217, and 219. That is, processor core 211 does not directly access memory 250 to retrieve data; instead, it sends data from memory 250 to cache memories 215, 217, and 219. Processor core 211 can access cache memories 215, 217, and 219 to obtain data. Exceptionally, when processor core 211 needs to directly access memory 250 due to cache flush or other circumstances, processor core 211 can directly access memory 250.

[0055] Direct and indirect access to memory 250 via these cache memories 215, 217 and 219 can be controlled by cache controller 213, which allows processor core 211 to directly access the normal area 331 of memory 250, but prohibits processor core 211 from directly accessing the secure area 333 of memory 250.

[0056] If processor core 211 is allowed to directly access memory 250, memory 250 is easily vulnerable to hacking. However, because cache controller 213 prohibits processor core 211 from directly accessing secure region 333 of memory 250, secure region 333 is virtually immune to attack. In short, data stored in secure region 333 can be protected.

[0057] According to embodiments of the present invention, the ability to protect storage systems from row hammer attacks can be improved.

[0058] The effects expected from the embodiments of the present invention are not limited to those described above, and other effects not mentioned above can be clearly understood by those skilled in the art from the description.

[0059] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A memory system comprising: a normal memory area adapted to store normal data; a secure memory area adapted to store secure data; a first row hammer detection circuit adapted to sample a portion of rows activated in the normal memory area and count the number of activations of the sampled rows to select a first row to be refreshed among the sampled rows; and a second row hammer detection circuit adapted to count the number of activations of all rows in the secure memory area to select a second row to be refreshed.

2. The memory system of claim 1, further comprising: different levels of cache memory, wherein the second row hammer detection circuit stores the count corresponding to the rows activated in the secure memory area in one of the different levels of cache memory.

3. The memory system of claim 2, further comprising: the one cache memory used by the second row hammer detection circuit is a last level cache memory among the different levels of cache memory. the normal memory area, the secure memory area, and the first row hammer detection circuit are included in a memory, and 4. The storage system of claim 2, wherein, the second row hammer detection circuit is included in a memory controller adapted to control the memory. the different levels of cache memory are included in a processor including the memory controller.

5. The storage system of claim 4, wherein, 6. A memory system comprising: a normal memory area adapted to store normal data; a secure memory area adapted to store secure data; a first row hammer detection circuit adapted to sample a portion of rows activated in the normal memory area and count the number of activations of the sampled rows to select a first row to be refreshed; a second row hammer detection circuit adapted to count the number of activations of all rows in the secure memory area to select a second row to be refreshed; a cache memory adapted to store an error correction code corresponding to the secure data; and an error correction circuit adapted to correct an error of data read from the secure area based on the error correction code stored in the cache memory. the normal memory area, the secure memory area, and the first row hammer detection circuit are included in a memory, wherein the cache memory is included in a processor, and wherein the processor includes a memory controller and the second row hammer detection circuit is included in the memory controller.

7. The storage system of claim 6, wherein, the processor is allowed to access the secure memory area only via the cache memory. the second row hammer detection circuit stores the count corresponding to the rows activated in the secure memory area in the cache memory. ​ 8. The storage system of claim 7, wherein, ​ 9. The storage system of claim 7, wherein, ​ 10. The storage system of claim 7, wherein, The processor further comprises a processor core adapted to process instructions and to access the memory via the cache memory.

11. The storage system of claim 10, wherein, The memory controller further comprises: a host interface adapted to communicate with a host; a scheduler adapted to schedule operations of the memory; a command generator adapted to generate commands to be applied to the memory; and a memory interface adapted to communicate with the memory.

12. A memory system comprising: a memory comprising: a normal region adapted to store normal data; a secure region adapted to store secure data; and a first row hammer detection circuit adapted to count a number of activations of rows in the normal region in a random row count manner to detect rows to be refreshed; and a processor comprising: a second row hammer detection circuit adapted to count a number of activations of rows in the secure region in a full row count manner to detect rows to be refreshed.

13. The storage system of claim 12, wherein, The processor further comprises: different levels of cache memory, and wherein the second row hammer detection circuit stores a count corresponding to an activated row in the secure region in a last level cache memory among the different levels of cache memory.

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