Apparatus and method for performing a target refresh operation

Abstract

A semiconductor memory device and an operating method thereof are provided. The semiconductor memory device includes: first storage logic configured to store "K" addresses having different values among input addresses applied during an enable period of a reference signal as first addresses; second storage logic configured to store "L" addresses among the input addresses corresponding to a time point at which the enable period of the reference signal ends as second addresses; a sequence controller configured to determine a first output order of each of the first addresses based on the number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing together the first addresses based on the first output order and the second addresses; and refresh operation logic configured to apply the mixed addresses according to the second output order to a target refresh operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 125,079, filed on December 14, 2020, and Korean Patent Application No. 10-2021-0015548, filed on February 3, 2021, which are hereby incorporated by reference in their entirety. Technical Field

[0003] One or more embodiments described herein relate to an apparatus and method for performing a refresh operation. Background Art

[0004] Volatile memory devices store data in multiple memory cells. Each memory cell may include a transistor that acts as a switch and a capacitor that stores charge corresponding to the logical value of the data. In theory, using capacitors to store data does not consume power. However, in practice, transistors may experience leakage current, which in turn may adversely affect the charge stored in the capacitor. If the leakage is severe enough, the stored data may be lost.

[0005] To prevent this problem, the data stored in the memory cell can be read before the data is lost, and a recharge operation can be performed to attempt to restore the appropriate amount of charge corresponding to the read information. In this case, only periodic repetition of the recharge operation can maintain the data storage. This recharge operation can be referred to as a refresh operation, such as a normal refresh operation.

[0006] In addition to normal refresh operations, additional refresh operations (e.g., targeted refresh operations) can be performed on memory cells in a specific word line that is at high risk of losing data due to a phenomenon called row hammering. Row hammering is a phenomenon in which the data in a memory cell is adversely affected due to frequent activation of a specific word line or one or more adjacent word lines. To prevent row hammering, targeted refresh operations can be performed on specific word lines or adjacent word lines that have been activated more than a predetermined number of times. Summary of the Invention

[0007] One or more embodiments described herein provide an apparatus and method for selecting an address for a targeted refresh operation.

[0008] According to an embodiment of the present invention, a semiconductor memory device may include: a reference signal generator configured to generate a reference signal having an enable period, wherein the number of the enable periods and the length of each enable period are randomly determined based on an operation time; a first storage logic configured to store, as a first address, a maximum of "K" addresses having different values among input addresses applied during the enable period of the reference signal; and a second storage logic configured to store, as a first address, "L" addresses corresponding to a time point at which the enable period of the reference signal ends, among the input addresses applied during the enable period of the reference signal. an address stored as a second address; a sequence controller configured to determine output or non-output and a first output order of each of the first addresses based on the number of times each of the first addresses is repeatedly input, and determine a second output order for outputting a mixed address, wherein the mixed address is obtained by mixing the first address based on the first output order with the second address; and a refresh operation logic configured to apply the mixed address output by the sequence controller according to the second output order to a target refresh operation, wherein "K" is a natural number equal to or greater than 2, and "L" is a natural number equal to or greater than 1.

[0009] According to an embodiment of the present invention, an operating method of a semiconductor memory device may include: generating a reference signal having an enable period, wherein the number of the enable periods and the length of each enable period are randomly determined based on an operation time; storing a maximum of "K" addresses having different values among the input addresses applied during the enable period of the reference signal as first addresses; storing "L" addresses corresponding to the time point at which the enable period of the reference signal ends among the input addresses applied during the enable period of the reference signal as second addresses; determining the output or non-output and the first output order of each of the first addresses based on the number of times each of the first addresses is repeatedly input, determining a second output order for outputting a mixed address, wherein the mixed address is obtained by mixing the first address based on the first output order with the second address; and applying the mixed address output according to the second output order to a target refresh operation, wherein "K" is a natural number equal to or greater than 2, and "L" is a natural number equal to or greater than 1.

[0010] According to the present technology, multiple different addresses can be selected and stored in the enable period of a reference signal whose enable period is randomly determined, an address close to a time point at which the enable period of the reference signal ends can be additionally selected and stored, and then a selected address can be selected for a target refresh operation.

[0011] Furthermore, according to the present technology, an address for a target refresh operation can be selected based not only on the number of accesses to the address but also on the point in time when the number of accesses reaches a reference number.

[0012] Therefore, there is an effect of more effectively selecting an address having the highest probability of data loss due to the row hammer phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An embodiment of a semiconductor memory is shown.

[0014] Figure 2 An embodiment of a storage system is shown.

[0015] Figure 3 An embodiment of a target address management circuit is shown.

[0016] Figure 4 An embodiment of a storage circuit is shown.

[0017] Figure 5 An embodiment of a sequence control circuit is shown.

[0018] Figure 6 Another embodiment of a storage circuit is shown.

[0019] Figure 7A and Figure 7B An embodiment of a storage circuit is shown.

[0020] Figure 8 An embodiment of a first-order determination circuit is shown.

[0021] Figure 9 An embodiment of a second sequence determination circuit is shown.

[0022] Figure 10 One type of address management circuit that has been proposed for performing targeted refresh operations is shown. DETAILED DESCRIPTION

[0023] Various examples of the present disclosure are described in more detail below with reference to the accompanying drawings. However, aspects and features of the present disclosure may be embodied in various ways to form other embodiments, including variations of any disclosed embodiment. Accordingly, the present disclosure is not limited to the embodiments described herein. Rather, the described embodiments are provided to make this disclosure thorough and complete and to fully convey the present disclosure to those skilled in the art to which the present disclosure pertains.

[0024] Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and examples of the present disclosure. It should be noted that references to "an embodiment" or "another embodiment" etc. do not necessarily mean only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

[0025] It will be understood that although the terms "first," "second," and "third," etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish an element from another element that would otherwise have the same or similar name. Thus, a first element in one instance may be referred to as a second element or a third element in another instance without indicating any change in the elements themselves.

[0026] The accompanying drawings are not necessarily drawn to scale, and in some cases, proportions may be exaggerated to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former can be directly connected or coupled to the latter, or electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present.

[0027] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural, and vice versa. Similarly, the numerals "a" and "an" refer to one or more unless the language or context clearly indicates that there is only one.

[0028] It will also be understood that the terms "comprising," "including," "includes," and "comprising" when used in this specification specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in view of the disclosure. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the present disclosure and the related art, and should not be interpreted in an idealized or overly formal sense, unless expressly defined as such herein.

[0030] In the following description, a large number of specific details are set forth to provide a thorough understanding of the present invention. The present invention can be implemented without some or all of these specific details. In other cases, known process structures and / or processes are not described in detail to avoid unnecessary confusion of the present invention.

[0031] It should also be noted that in some cases, as is apparent to one skilled in the relevant art, features or elements described in conjunction with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless specifically stated otherwise.

[0032] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, wherein like numerals represent like elements.

[0033] Figure 1 FIG. 1 is a block diagram illustrating an embodiment of a semiconductor memory device 1000 (eg, a DRAM). In another embodiment, the memory device 1000 may be a different type of memory.

[0034] refer to Figure 1 , the semiconductor memory device 1000 includes a memory cell array 1010, a row decoder 1020, a sense amplifier 1030, a column decoder 1040, a refresh control circuit 1050, a command decoder 1060, an address buffer 1070, and a data input / output circuit 1080. The memory cell array 1010 may include memory cells arranged in row and column directions.

[0035] Figure 1 The arrangement of memory cells in the row direction is shown. Memory cells may include not only normal cells for data storage but also redundant cells for replacing memory cells in which errors have occurred. Redundant cells have substantially the same structure as normal cells. A redundant cell array including such redundant cells may be used as an additional storage area of the memory device 1000.

[0036] The command decoder 1060 may receive a command CMD1 from the controller, decode the received command, and internally generate the decoded control signal (e.g., an activation signal, a read signal, a write signal, and / or a refresh signal). The refresh control circuit 1050 may receive a refresh signal from the command decoder 1060 and output a row address to the row decoder 1020 to refresh one word line of the memory cell array 1010.

[0037] The controller may transmit an address ADD1 for designating a memory cell for writing / reading data together with a command CMD1 to the memory device 1000. The address buffer 1070 may receive the address ADD1 from the control logic and generate a row / column address.

[0038] The row decoder 1020 can decode the row address output from the refresh control circuit 1050 or the address buffer 1070 to specify a word line of the memory cell array 1010. For example, during a write / read operation, the row decoder 1020 can decode the row address output from the address buffer 1070 to enable electrical connection to the word line of the memory cell to which data is to be written / read. In addition, the row decoder 1020 can refresh the corresponding row based on the row address generated from the refresh control circuit 1050.

[0039] The sense amplifier 1030 can sense and amplify data of a memory cell electrically connected to a word line specified by the row decoder 1020, and can store the data of the memory cell. In addition, the column decoder 1040 can decode the column address output from the address buffer 1070 to specify a bit line electrically connected to a memory cell to which data is to be input / output.

[0040] The data input / output circuit 1080 outputs data from a memory cell specified by the address ADD1 in the memory cell array 1010, or inputs data to the memory cell. As a result, data input through the data input / output circuit 1080 can be written into the memory cell array 1010 based on the address ADD1, or data read from the memory cell array 1010 based on the address ADD1 can be output to the controller through the data input / output circuit 1080.

[0041] When row decoder 1020 applies a voltage to a word line corresponding to Row N to access Row N, an electromagnetic field is formed around the word line. When Row N is frequently accessed, a row hammer phenomenon may occur. According to this phenomenon, data stored in one or more rows adjacent to Row N (e.g., Row N-1 and Row N+1) may be distorted because these rows are continuously adversely affected by the electromagnetic field.

[0042] To address this effect, when a row is frequently accessed, a target refresh operation may be performed on adjacent rows. This operation is performed to prevent data stored in the memory cell array 1010 from being lost due to row hammering.

[0043] A controller controlling the memory device 1000 may count the number of accesses to each row of the memory cell array 1010 to determine whether the memory cells of the memory cell array 1010 are frequently accessed (e.g., accessed more than a predetermined number of times). As the capacity of the memory system increases, the controller may control a memory pool including multiple memory devices 1000. Therefore, the controller may have to use a relatively large amount of storage resources to count the number of accesses to each row.

[0044] Figure 10 A proposed full-count content address memory (FCCAM) scheme is shown. In this case, the scheme is implemented for a memory device that includes 16 address latches (ADD Latch & COMPARE) for storing input row addresses, 16 address comparison circuits (COMPARE) for selecting whether to apply the corresponding row addresses stored in the 16 address latches to a target refresh operation, and 16 counters (ADD CNT). Given these conditions, it is expected that a large amount of memory resources (320 μm x 65 μm) will be required to implement the scheme.

[0045] For example, the 16 row addresses entered on a first-come, first-served basis are stored in Figure 10 In the case where the same row address is repeatedly input into the address latch, if the number of repeated inputs is counted and exceeds 8K times, a target refresh operation may be applied to the row address.

[0046] In the proposed scheme, Figure 10 The performance of the address latches, address comparison circuits, and counters shown may vary significantly depending on the size of the physical resources that may be implemented. For example, 16 different row addresses may be applied to a target refresh operation, but it may not even be possible to check whether more than 16 row addresses are applied to a target refresh operation.

[0047] Figure 21 is a diagram schematically illustrating an embodiment of a memory system 100, which may include a memory controller 2000 and a memory device 1000, which may be, for example, a semiconductor memory device. The memory controller 2000 and the memory device 1000 may include an interface for communicating commands, data, control signals, and / or other information with each other. For example, a command CMD1 may include an access address ADD1, which may depend on the type of the memory device 1000. The memory controller 2000 may generate the command CMD1 and the access address ADD1 for controlling the memory device 1000, and under the control of the memory controller 2000, data DATA may be written to the memory device 1000, or data DATA may be read from the memory device 1000.

[0048] As reference Figure 1 As depicted, the memory device 1000 may include a refresh control circuit 1050. The refresh control circuit 1050 may be within or coupled to the memory device 1000. The refresh control circuit 1050 may include a target address management circuit 1200 and a refresh operation circuit (ie, refresh operation logic) 1210.

[0049] The target address management circuit 1200 may manage a target address for a target refresh operation of the memory device 1000 , the target address being intensively accessed (eg, more than a predetermined number of times) among access addresses.

[0050] The refresh operation circuit 1210 may apply the address REF_ADD<0:N> output to the target address management circuit 1200 for a target refresh operation. The refresh operation circuit 1210 may perform a target refresh operation among the operations of the refresh control circuit 1050 for controlling all refresh operations of the semiconductor memory device 1000. For example, the refresh operation circuit 1210 may perform a refresh operation on a preset number of word lines adjacent to a word line corresponding to the address REF_ADD<0:N> output to the target address management circuit 1200.

[0051] As an example, Figure 2 A memory device 1000 is shown in the memory system 100. In one embodiment, multiple memory devices may be in or coupled to the memory system 100, based on, for example, the intended application. Furthermore, the multiple memory devices may each be divided into at least one memory module. Memory modules may include, for example, dual inline memory modules (DIMMs), unbuffered dual inline memory modules (UDIMMs), registered dual inline memory modules (RDIMMs), load-reduced dual inline memory modules (LRDIMMs), and fully buffered dual inline memory modules (FBDIMMs).

[0052] Figure 3 is a diagram schematically illustrating an embodiment of a target address management circuit 1200 and a refresh operation circuit 1210 , such as may be in the refresh control circuit 1050 .

[0053] refer to Figure 3 The target address management circuit 1200 may include a reference signal generation circuit (i.e., a reference signal generator) 31, a first storage circuit (i.e., a first storage logic) 32, a second storage circuit (i.e., a second storage logic) 33, a sequence control circuit (i.e., a sequence controller) 34, and a third storage circuit (i.e., a third storage logic) 36.

[0054] The reference signal generation circuit 31 can generate a reference signal PRBS, the number of enable periods of the reference signal PRBS and the length of each enable period are randomly determined based on the operation time. In one embodiment, the operation time may refer to the time when the operation such as reading / writing is performed continuously from the time point when power is supplied to the semiconductor memory device. For example, the reference signal generation circuit 31 can repeatedly generate a reference signal PRBS, which is enabled at any time from the time point when power is supplied to the semiconductor memory device and the operation is started. The reference signal PRBS can basically remain in the enabled state for any time and then be disabled.

[0055] The first storage circuit 32 can store a maximum of K addresses having different values among the input addresses ACT_ADD<0:N> applied during the enable period of the reference signal PRBS as the first address SR_ADD<0:N>. Here, K may be a natural number greater than 2. According to one embodiment, the following description will be given as an example case where K=6.

[0056] The second storage circuit 33 may store L addresses close to a time point at which the enable period of the reference signal PRBS ends among the input addresses ACT_ADD<0:N> applied during the enable period of the reference signal PRBS as the second addresses SHADOW_ADD<0:N>.

[0057] The input address ACT_ADD<0:N> transmitted to each of the first storage circuit 32 and the second storage circuit 33 may correspond to an address input during the enable period of the reference signal PRBS among the activation addresses ICAFF<0:N> input along with the activation command ACT. For example, an address input during the disable period of the reference signal PRBS among the activation addresses ICAFF<0:N> input along with the activation command ACT may not be transmitted to the first storage circuit 32 and the second storage circuit 33. In one embodiment, the address may include N+1 bits <0:N>, where N is a natural number greater than 1.

[0058] The sequence control circuit 34 may determine whether to output or not output each of the up to six first addresses SR_ADD<0:N> stored in the first storage circuit 32, and a first output order. This determination may be based on the number of times CNT<1:6><0:3> that the corresponding up to six first addresses SR_ADD<0:N> stored in the first storage circuit 32 are repeatedly input. The sequence control circuit 34 may determine a second output order for mixing the second address SHADOW_ADD<0:N> with the up to six first addresses SR_ADD<0:N> based on the first output order, and may output the mixed address REF_ADD<0:N> together.

[0059] For example, the sequence control circuit 34 can transmit control signals SR_EN<1:6> and RST_CNT<1:6> to the first storage circuit 32 based on the number of times CNT<1:6><0:3> that the corresponding maximum six first addresses SR_ADD<0:N> stored in the first storage circuit 32 are repeatedly input, thereby determining the output or non-output of each of the maximum six first addresses SR_ADD<0:N> stored in the first storage circuit 32 and the first output order.

[0060] Furthermore, the sequence control circuit 34 may determine a second output sequence to mix the second address SHADOW_ADD<0:N> with a maximum of six first addresses SR_ADD<0:N> stored in the first storage circuit 32. The sequence control circuit 34 may then collectively output the mixed address REF_ADD<0:N> while the maximum six first addresses SR_ADD<0:N> stored in the first storage circuit 32 are output in a predetermined manner (e.g., at least one by one) according to the first output sequence. Thus, the sequence control circuit 34 may mix the second address SHADOW_ADD<0:N> with the maximum six first addresses SR_ADD<0:N> based on the first output sequence according to the second output sequence, and then collectively output the mixed address REF_ADD<0:N>.

[0061] The refresh operation circuit 1210 can apply the address REF_ADD<0:N> outputted by the sequence control circuit 34 in the target address management circuit 1200 according to the second output sequence to the target refresh operation. In one embodiment, the refresh operation circuit 1210 can perform the target refresh operation among the operations of the refresh control circuit 1050 for controlling all refresh operations of the semiconductor memory device 1000, for example, as shown in FIG. Figure 2For example, the refresh operation circuit 1210 may perform a refresh operation on a preset number of word lines adjacent to a word line corresponding to the address REF_ADD<0:N> output to the target address management circuit 1200 .

[0062] The third storage circuit 36 can receive the activation address ICAFF<0:N> applied together with the activation command ACT, output the received address as the input address ACT_ADD<0:N> during the enable period of the reference signal PRBS, and store L input addresses ACT_ADD<0:N> output sequentially starting from a predetermined time (e.g., the most recent time).

[0063] In addition, the third storage circuit 36 can output the activation command ACT input during the enable period of the reference signal PRBS as the operation command LAT_CMD. The operation command LAT_CMD may refer to a command input during the enable period of the reference signal PRBS among the activation commands ACT. For example, a command input during the disable period of the reference signal PRBS among the activation commands ACT may not be output as the operation command LAT_CMD.

[0064] Then, in response to the end of the enable period of the reference signal PRBS, the second storage circuit 33 may receive the L input addresses ACT_ADD<0:N> stored in the third storage circuit 36 and may store the received L input addresses ACT_ADD<0:N> as the second addresses SHADOW_ADD<0:N>. Whenever the enable period of the reference signal PRBS ends, the L second addresses SHADOW_ADD<0:N> stored in the second storage circuit 33 may be updated, where L is a natural number greater than 1. According to an embodiment, the following description is based on an example in which L=1.

[0065] Figure 4 It is schematically shown Figure 3 A diagram of an embodiment of the first storage circuit 32 among the components of the target address management circuit 1200 is shown.

[0066] refer to Figure 4 The first storage circuit 32 may include six address latches STR LATCH<1:6>, six counters COUNTER<1:6> and a storage control circuit (ie, a storage controller) 323, wherein the number “6” is due to the reference Figure 1 The described example assumes that K is determined to be 6. For example, other values of K may be used in other embodiments based on the intended application, for example, any natural number equal to or greater than 2 may be selected.

[0067] First, the six address latches STR LATCH<1:6> can store an externally applied input address ACT_ADD<0:N> as up to six first addresses SR_ADD<0:N> or ADD<1:6><0:N> in response to control signals SR_EN<1:6> or PI<1:6>, respectively. For example, the six address latches STR LATCH<1:6> can store an externally applied input address ACT_ADD<0:N> as first addresses SR_ADD<0:N> or ADD<1:6><0:N> therein in response to control signals SR_EN<1:6> or PI<1:6>, respectively, and then can output the stored first addresses SR_ADD<0:N> or ADD<1:6><0:N> to an external address or location, or can delete the first addresses SR_ADD<0:N> or ADD<1:6><0:N> already stored therein. In this case, as indicated by the word "up to," the six address latches STR LATCH<1:6> may receive a minimum of 0 to a maximum of six input addresses ACT_ADD<0:N> and may store the received addresses as first addresses SR_ADD<0:N> or ADD<1:6><0:N>. For example, during initial operation, the six address latches STR LATCH<1:6> may be in a state in which none of the first addresses SR_ADD<0:N> or ADD<1:6><0:N> is stored therein.

[0068] exist Figure 3 In the example, only "SR_ADD<0:N>" is used for the "first address" stored in the first storage circuit 32. Figure 4 , “SR_ADD<0:N>” and “ADD<1:6><0:N>” are used together for the “first addresses” stored in the six address latches STR LATCH<1:6> in the first storage circuit 32. This may indicate that a maximum of six “first addresses” stored in the six address latches STR LATCH<1:6> can be used for two purposes, namely, the purpose of being selected one by one to be output to the outside of the first storage circuit 32 and the purpose of being simultaneously selected for the internal comparison operation.

[0069] For example, up to six “first addresses” stored in the six address latches STR LATCH<1:6> may be selected one by one and output to the sequence control circuit 34 in response to the first control signal SR_EN<1:6> output from the sequence control circuit 34. In this case, “SR_ADD<0:N>” may represent a “first address”. For example, since the “first address” is output from only one of the six address latches STR LATCH<1:6>, the same reference numeral “SR_ADD<0:N>” may be used for all “first addresses” output from the corresponding six address latches STR LATCH<1:6>.

[0070] Furthermore, in response to the second control signal PI<1:6> output from the six counters COUNTER<1:6>, up to six “first addresses” stored in the six address latches STR LATCH<1:6> can be simultaneously used for value comparison with the input address ACT_ADD<0:N> in the first storage circuit 32. In this case, reference numerals “ADD<1:6><0:N>” may be used, for example, because the “first addresses” are simultaneously output from the six address latches STR LATCH<1:6>, different reference numerals “ADD<1:6><0:N>” may be used for the “first addresses” output from the corresponding six address latches STR LATCH<1:6>.

[0071] Therefore, due to Figure 3 Only the purpose in which the "first addresses" stored in the first storage circuit 32 are selected one by one to be output to the sequence control circuit 34 is shown, so it can be seen that only the reference numeral "SR_ADD<0:N>" is used. Figure 4 It shows the purpose in which the "first addresses" stored in the first storage circuit 32 are selected one by one to be output to the sequence control circuit 34 and the purpose in which six "first addresses" are selected at the same time for internal comparison operation, so the figure mark "SR_ADD<0:N>" is used together with the figure mark "ADD<1:6><0:N>".

[0072] As an example, the following description will be made using any one of reference signs “SR_ADD<0:N>” and reference signs “ADD<1:6><0:N>” according to the purpose of using the “first address”.

[0073] The six counters COUNTER<1:6> can count six count values CNT<1:6><0:3> in response to a third control signal INC<1:6> indicating whether up to six first addresses SR_ADD<0:N> that can be stored in the corresponding six address latches STRLATCH<1:6> are repeatedly input. The corresponding six counters COUNTER<1:6> can initialize the six internally generated count values CNT<1:6><0:3> in response to a fourth control signal RST_CNT<1:6> output from the sequence control circuit 34. In response to the operation command LAT_CMD, the third control signal INC<1:6> output from the storage control circuit 323, and the fourth control signal RST_CNT<1:6> output from the sequence control circuit 34, the corresponding six counters COUNTER<1:6> can generate the second control signal PI<1:6>, which is used to store the input address ACT_ADD<0:N> in the corresponding six address latches STR LATCH<1:6> or to delete the input address ACT_ADD<0:N> from the six address latches STR LATCH<1:6>.

[0074] As an example, assume that each of the six count values CNT<1:6><0:3> is 4-bit data <0:3>. For example, based on the intended application, in another embodiment, the number of bits of data used may be different.

[0075] The storage control circuit 323 can compare the value of the input address ACT_ADD<0:N> with the values of the corresponding up to six first addresses "ADD<1:6><0:N>" stored in the corresponding six address latches STR LATCH<1:6>, and can then selectively store the input address ACT_ADD<0:N> in the corresponding six address latches STR LATCH<1:6> in response to the comparison result, or can selectively increase each of the six count values CNT<1:6><0:3> generated by the six counters COUNTER<1:6>.

[0076] For example, when an input address ACT_ADD<0:N> is applied along with an operation command LAT_CMD, the storage control circuit 323 may compare the value of the applied input address ACT_ADD<0:N> with the corresponding up to six first addresses "ADD<1:6><0:N>" stored in the corresponding six address latches STRLATCH<1:6>. The storage control circuit 323 may then generate a third control signal INC<1:6> in response to the comparison result. The third control signal INC<1:6> generated by the storage control circuit 323 may be transmitted to the six counters COUNTER<1:6>, respectively, and used to increase the corresponding six count values CNT<1:6><0:3> generated by the six counters COUNTER<1:6> or to generate the second control signal PI<1:6>.

[0077] Furthermore, the second control signals PI<1:6> generated by the storage control circuit 323 may be respectively transmitted to the six address latches STR LATCH<1:6> and used to select whether to store the operation command LAT_CMD and the input address ACT_ADD<0:N> as the first address SR_ADD<0:N> or ADD<1:6><0:N> in the corresponding six address latches STR LATCH<1:6>. The second control signals PI<1:6> generated by the storage control circuit 323 may be respectively transmitted to the six address latches STR LATCH<1:6> and used to select whether to delete the first address SR_ADD<0:N> or ADD<1:6><0:N> stored in the six address latches STR LATCH<1:6>.

[0078] Figure 5 is a diagram schematically illustrating an embodiment of a sequence control circuit 34 , which may include a first sequence determination circuit (ie, first sequence determination logic) 341 and a second sequence determination circuit (ie, second sequence determination logic) 342 .

[0079] In operation, the first sequence determination circuit 341 can preliminarily determine the output or non-output of each of the first addresses SR_ADD<0:N> and the first output sequence based on whether each of the six count values CNT<1:6><0:3> reaches the reference value and the order in which each of the six count values CNT<1:6><0:3> reaches the reference value.

[0080] For example, until the refresh operation circuit 1210 performs a target refresh operation in response to the previous target refresh command SR_CMD and then the next target refresh command SR_CMD is input, the first order determination circuit 341 may select one or more first addresses SR_ADD<0:N> corresponding to the one or more first count values when one or more first count values have reached the reference value among the six count values CNT<1:6><0:3>. Then, the first order determination circuit 341 may put the selected first addresses into the first output order in the order in which the count values have reached the reference value.

[0081] Furthermore, until the target refresh operation is performed and then the next target refresh command SR_CMD is input, the first sequence determination circuit 341 may randomly select at least one of a maximum of six first addresses SR_ADD<0:N> stored in the first storage circuit 32 when none of the six count values CNT<1:6><0:3> have reached the reference value. The first sequence determination circuit 341 may then place the selected first address into the first output sequence.

[0082] Furthermore, in the case where the target refresh command SR_CMD is input a predetermined number of times, when one or more second count values (which have never reached the reference value or have not yet reached the reference value) exist among the six count values CNT<1:6><0:3>, the first sequence determination circuit 341 may delete one or more first addresses SR_ADD<0:N> from the first storage circuit 32. The deleted one or more first addresses SR_ADD<0:N> may correspond to the one or more second count values.

[0083] For example, until the target refresh operation is performed by the refresh operation circuit 1210 and then the next target refresh command SR_CMD is input, each time the operation command LAT_CMD is applied, the first sequence determination circuit 341 may check whether there is any first count value that has reached the reference value among the six count values CNT<1:6><0:3> output from the first storage circuit 32. When the check result indicates that such a first count value exists, the first sequence determination circuit 341 may generate a first control signal SR_EN<1:6> corresponding to the first count value and may output the generated first control signal SR_EN<1:6> to the first storage circuit 32 to select the first address SR_ADD<0:N> corresponding to the first count value. When the check result indicates that such a first count value does not exist, the first sequence determination circuit 341 can randomly select one of the six count values CNT<1:6><0:3>, generate a first control signal SR_EN<1:6> corresponding to the randomly selected first count value, and output the generated first control signal SR_EN<1:6> to the first storage circuit 32 to select the first address SR_ADD<0:N> corresponding to the randomly selected first count value.

[0084] In one embodiment, after the refresh operation circuit 1210 performs a target refresh operation, multiple operation commands LAT_CMD may be input when the next target refresh command SR_CMD is input. Similarly, after the refresh operation circuit 1210 performs a target refresh operation, when the next target refresh command SR_CMD is input, the enable period of the reference signal PRBS may be repeated one or more times. Therefore, after the refresh operation circuit 1210 performs a target refresh operation, when the next target refresh command SR_CMD is input, at least one or more first count values among the six count values CNT<1:6><0:3> output from the first storage circuit 32 may have reached the reference value.

[0085] When the target refresh command SR_CMD is input a predetermined number of times (for example, when the target refresh operation is performed a predetermined number of times by the refresh operation circuit 1210), when one or more second count values (never reaching the reference value) exist among the six count values CNT<1:6><0:3> stored in the first storage circuit 32, the first sequence determination circuit 341 may generate a fourth control signal RST_CNT<1:6> corresponding to the one or more second count values. The first sequence determination circuit 341 may then output the generated fourth control signal RST_CNT<1:6> to the first storage circuit 32 to delete one or more first addresses SR_ADD<0:N> from the first storage circuit 32. The deleted one or more first addresses SR_ADD<0:N> correspond to the one or more second count values.

[0086] In addition, regarding reference Figure 4 Regarding the operation of the first storage circuit 32, since only one of the six count values CNT<1:6><0:3> increases in response to a single operation command LAT_CMD, it may be impossible for two of the six count values CNT<1:6><0:3> to reach the reference value simultaneously. Therefore, the first count value that first reaches the reference value may be any of the six count values CNT<1:6><0:3>. If multiple first count values reach the reference value in response to multiple operation commands LAT_CMD, the order in which the corresponding first count values reach the reference value will inevitably differ.

[0087] Thus, when there are multiple first count values, the first sequence determination circuit 341 can define a first output sequence, in which the corresponding first count values reach the reference value according to the first output sequence. For example, to select multiple first addresses SR_ADD<0:N> corresponding to the corresponding first count values according to the first output sequence, the first sequence determination circuit 341 can generate multiple first control signals SR_EN<1:6> corresponding to the multiple first count values based on the first output sequence. The first sequence determination circuit 341 can then output the generated first control signals SR_EN<1:6> to the first storage circuit 32.

[0088] In one embodiment, when the first operation command LAT_CMD is applied, the first sequence determination circuit 341 may check the first count value CNT1<0:3> of the six count values CNT<1:6><0:3> as the first count value. Subsequently, when the second operation command LAT_CMD is applied, the first sequence determination circuit 341 may check the third count value CNT3<0:3> of the six count values CNT<1:6><0:3> as the first count value. Subsequently, when the third operation command LAT_CMD is applied, the first sequence determination circuit 341 may check the second count value CNT2<0:3> of the six count values CNT<1:6><0:3> as the first count value.

[0089] Furthermore, the first sequence determination circuit 341 may determine that the fourth to sixth count values CNT<4:6><0:3>, except for the first to third count values CNT<1:3><0:3>, among the six count values CNT<1:6><0:3>, have not yet reached the reference value. In this case, the first sequence determination circuit 341 may determine the first to third count values CNT<1:3><0:3> among the six count values CNT<1:6><0:3> as outputtable count values, and may not determine the fourth to sixth count values CNT<4:6><0:3> as outputtable count values.

[0090] In addition, when determining the first output order for the first count value to the third count value CNT<1:3><0:3> determined as the outputtable count values, the first order determination circuit 341 can determine the first count value CNT1<0:3> that first reaches the reference value as the first order, the third count value CNT3<0:3> that second reaches the reference value as the second order, and the second count value CNT2<0:3> that third reaches the reference value as the third order.

[0091] Therefore, when the first operation command LAT_CMD is applied, the first order determination circuit 341 may generate the first first control signal SR_EN1 corresponding to the first count value CNT1 <0:3> and may output the generated first first control signal SR_EN1 to the first storage circuit 32 .

[0092] Subsequently, when the second operation command LAT_CMD is applied, the first order determination circuit 341 may generate a third first control signal SR_EN3 corresponding to the third count value CNT3 <0:3> and may output the generated third first control signal SR_EN3 to the first storage circuit 32 .

[0093] Subsequently, when the third operation command LAT_CMD is applied, the first order determination circuit 341 may generate a second first control signal SR_EN2 corresponding to the second count value CNT2 <0:3> and may output the generated second first control signal SR_EN2 to the first storage circuit 32 .

[0094] In addition, the second sequence determination circuit 342 can determine the second output sequence by dividing the first addresses SR_ADD<0:N> based on the first output sequence into A based on the number of input times of the target refresh command SR_CMD input for controlling the target refresh operation, and placing B second addresses SHADOW_ADD<0:N> between the divided A first addresses SR_ADD<0:N>. Here, A and B can be natural numbers equal to or greater than 1. For example, when A and B are "1", the second sequence determination circuit 342 can determine the second output sequence by dividing the first addresses SR_ADD<0:N> based on the first output sequence into one among a maximum of six first addresses SR_ADD<0:N> (which are stored in the first storage circuit 32), and placing one second address SHADOW_ADD<0:N> for each divided first address SR_ADD.

[0095] For example, the first control signals SR_EN<1:6> may be sequentially generated according to a first output sequence (determined by the operation of the first sequence determination circuit 341) and transmitted to the first storage circuit 32. The first storage circuit 32 may output the first address SR_ADD<0:N> based on the first output sequence among the six first addresses SR_ADD<0:N> stored therein to the second sequence determination circuit 342. Furthermore, the second storage circuit 33 may output the second address SHADOW_ADD<0:N> stored therein to the second sequence determination circuit 342. Therefore, whenever A target refresh commands SR_CMD are input among the continuously input target refresh commands SR_CMD, the second sequence determination circuit 342 may place the A first addresses SR_ADD<0:N> based on the first output sequence one by one into the second output sequence and output the A first addresses as the target refresh addresses REF_ADD<0:N>.

[0096] Furthermore, whenever B target refresh commands SR_CMD are input after A target refresh commands SR_CMD, the second sequence determination circuit 342 may place the B second addresses SHADOW_ADD<0:N> one by one into the second output sequence and output the B second addresses as the target refresh addresses REF_ADD<0:N>. For example, in response to the input of an odd-numbered target refresh command SR_CMD, the second sequence determination circuit 342 may place the first addresses SR_ADD<0:N> based on the first output sequence one by one into the second output sequence and output the placed first addresses as the target refresh addresses REF_ADD<0:N>. In response to the input of an even-numbered target refresh command SR_CMD, the second sequence determination circuit 342 may place the second addresses SHADOW_ADD<0:N> one by one into the second output sequence and output the placed second addresses as the target refresh addresses REF_ADD<0:N>.

[0097] Figure 6 is a diagram illustrating an embodiment of the third storage circuit 36 , which may include an AND gate AND0 , an address latch ADD LATCH1 , and a flip-flop FF.

[0098] The AND gate AND0 may receive the active command ACT and the reference signal PRBS and perform an AND operation thereon. The active command ACT input during the enable period of the reference signal PRBS may be output as an output signal ACT_PRBS of the AND gate AND0.

[0099] Then, the address latch ADD LATCH1 can store the activation address ICAFF<0:N> in response to the output signal ACT_PRBS of the AND gate AND0, and can output the activation address ICAFF<0:N> stored in the address latch ADD LATCH1 as the input address ACT_ADD<0:N>. Therefore, the address latch ADD LATCH1 can store one activation address ICAFF<0:N> sequentially input from the most recent time, for example, one input address ACT_ADD<0:N> sequentially output from the most recent time.

[0100] Then, the flip-flop FF can synchronize the output signal ACT_PRBS of the AND gate AND0 with the clock signal CLK and output the synchronized signal as the operation command LAT_CMD. Therefore, the activation command ACT input during the enable period of the reference signal PRBS among the activation commands ACT can be output as the operation command LAT_CMD, and the operation command LAT_CMD can be synchronized with the clock signal CLK.

[0101] Figure 7A and Figure 7B It shows Figure 4 Schematic diagram of an embodiment of the first storage circuit 32 is shown in FIG. Figure 7A and Figure 7B The first storage circuit 32 may correspond to Figure 4 The first storage circuit 32 is shown, with one or more differences as discussed below.

[0102] refer to Figure 7A and Figure 7B , the first storage circuit 32 may include six address latches STR LATCH<1:6>, six counters COUNTER<1:6>, and storage control circuits 3231 , 323A, and 323B.

[0103] The storage control circuits 3231, 323A, and 323B may include an address comparison circuit (ie, address comparator) 3231, a latch control circuit (ie, latch controller) 323A, and a counter control circuit (ie, counter controller) 323B. In one embodiment, Figure 4 The "storage control circuit" in the first storage circuit 32 may use one reference numeral "323" as one component. In one embodiment, the "storage control circuit" in the first storage circuit 32 may use three reference numerals "3231, 323A, and 323B" as three components. Therefore, in one embodiment, Figure 4 The "storage control circuit" in the first storage circuit 32 may include Figure 7A and Figure 7B Three components 3231, 323A and 323B are shown.

[0104] For example, the six address latches STR LATCH<1:6> can store the externally applied input address ACT_ADD<0:N> therein as the first address SR_ADD<0:N> or ADD<1:6><0:N> in response to the second control signal PI<1:6>, respectively. Furthermore, the six address latches STR LATCH<1:6> can output the first address SR_ADD<0:N> stored therein to an external destination in response to the first control signal SR_EN<1:6>, respectively.

[0105] The address comparison circuit 3231 may sequentially compare the value of the input address ACT_ADD<0:N> with the values of the addresses ADD<1:6><0:N> stored in the corresponding six address latches STR LATCH<1:6>, and may generate six comparison signals CMP_MATCH<1:6> corresponding to the comparison results. For example, the address comparison circuit 3231 may perform an operation of sequentially comparing each of the values of the six first addresses ADD<1:6><0:N> stored in the six address latches STR LATCH<1:6> with the value of the input address ACT_ADD<0:N>, and then may generate six comparison signals CMP_MATCH<1:6> as a result of the operation.

[0106] For example, when the value of the first first address ADD1<0:N> stored in the first address latch STRLATCH1 among the six address latches STR LATCH<1:6> is the same as the value of the input address ACT_ADD<0:N>, the first comparison signal CMP_MATCH1 among the six comparison signals CMP_MATCH<1:6> may be triggered. Similarly, when the value of the fourth first address ADD4<0:N> stored in the fourth address latch STR LATCH4 among the six address latches STR LATCH<1:6> is the same as the value of the input address ACT_ADD<0:N>, the fourth comparison signal CMP_MATCH4 among the six comparison signals CMP_MATCH<1:6> may be triggered. When the values of the six first addresses ADD<1:6><0:N> stored in the six address latches STR LATCH<1:6> are all different from the value of the input address ACT_ADD<0:N>, none of the six comparison signals CMP_MATCH<1:6> may be triggered.

[0107] In addition, when there is no object to be compared with the input address ACT_ADD<0:N> (for example, when there is a latch that does not store an address among the six address latches STR LATCH<1:6>), the address comparison circuit 3231 can trigger the comparison signal corresponding to the latch to store the input address ACT_ADD<0:N> in the latch in which the address was not previously stored.

[0108] For example, when no address is stored in the six address latches STR LATCH<1:6>, the address comparison circuit 3231 may trigger the first comparison signal CMP_MATCH1, so that the input address ACT_ADD<0:N> may be stored in the first address latch STR LATCH1. Similarly, when no address is stored in the sixth address latch STRLATCH6 of the six address latches STR LATCH<1:6> and the values of the five first addresses ADD<1:5><0:N> stored in the first to fifth address latches STR LATCH<1:5> are all different from the value of the input address ACT_ADD<0:N>, the address comparison circuit 3231 may trigger the sixth comparison signal CMP_MATCH6, so that the input address ACT_ADD<0:N> may be stored in the sixth address latch STR LATCH6.

[0109] Furthermore, the counter control circuit 323B can control the counting operation of each of the six counters COUNTER<1:6> in response to each of the six comparison signals CMP_MATCH<1:6> to thereby adjust the six count values CNT<1:6><0:3> and the values of the six items of counting operation information CNT_NULL<1:6> generated in the corresponding six counters COUNTER<1:6>. For example, the counter control circuit 323B can generate six third control signals INC<1:6> for controlling the counting operation of each of the six counters COUNTER<1:6> in response to each of the six comparison signals CMP_MATCH<1:6> and the operation command LAT_CMD outputted from the address comparison circuit 3231. In one embodiment, the counter control circuit 323B may include six AND gates AND<7:12>, which are used to generate six third control signals INC<1:6> by receiving each of the six comparison signals CMP_MATCH<1:6> and the operation command LAT_CMD and performing an AND operation on each of the six comparison signals CMP_MATCH<1:6> and the operation command LAT_CMD.

[0110] Then, the six counters COUNTER<1:6> may respectively generate six count values CNT<1:6><0:3> and six items of counting operation information CNT_NULL<1:6> in response to the third control signal INC<1:6> and the fourth control signal RST_CNT<1:6>.

[0111] Furthermore, the latch control circuit 323A may control the storage operation of each of the six address latches STR LATCH<1:6> in response to each of the six pieces of counting operation information CNT_NULL<1:6>, thereby selectively storing the input address ACT_ADD<0:N> in each of the six address latches STR LATCH<1:6>. For example, the latch control circuit 323A may include six AND gates AND<1:6> configured to generate six second control signals PI<1:6> by performing an AND operation on corresponding pieces of counting operation information in the six pieces of counting operation information CNT_NULL<1:6> and the operation command LAT_CMD.

[0112] According to an embodiment, the six address latches STR LATCH<1:6>, the six counters COUNTER<1:6>, the address comparison circuit 3231 , the counter control circuit 323B, and the latch control circuit 323A in the first storage circuit 32 may operate as follows.

[0113] First, among the six counting operation information CNT_NULL<1:6>, the first counting operation information CNT_NULL1 may be in an active state, while the other counting operation information CNT_NULL<2:6> may be initialized to an inactive state. In addition, each of the six count values CNT<1:6><0:3> may be initialized to "0", and the six address latches STRLATCH<1:6> may be initialized to a state where no address is stored.

[0114] Thereafter, when the first input address ACT_ADD<0:N> is applied along with the operation command LAT_CMD, the address comparison circuit 3231 may trigger the first comparison signal CMP_MATCH1. Since the first counting operation information CNT_NULL1 is in an active state and the first comparison signal CMP_MATCH1 is triggered, the first input address ACT_ADD<0:N> may be stored as the first first address ADD1<0:N> in the first address latch STRLATCH1 among the six address latches STR LATCH<1:6>. At this time, the first counter COUNTER1 may increase the first count value CNT1<0:3> from "0" to "1" in response to the triggering of the first comparison signal CMP_MATCH1, deactivate the first counting operation information CNT_NULL1, and activate the second counting operation information CNT_NULL2.

[0115] Thereafter, when the second input address ACT_ADD<0:N> is applied along with the operation command LAT_CMD, the address comparison circuit 3231 may compare the value of the second input address ACT_ADD<0:N> with the first first address ADD1<0:N> stored in the first address latch STR LATCH1. When the comparison result indicates that the addresses have the same value, the first comparison signal CMP_MATCH1 may be triggered. At this time, since the second counting operation information CNT_NULL2 is in an active state, the first counter COUNTER1 may increase the first count value CNT1<0:3> from "1" to "2" in response to the triggering of the first comparison signal CMP_MATCH1.

[0116] When the comparison result indicates that the addresses do not have the same value, the second comparison signal CMP_MATCH2 may be triggered. At this time, since the second counting operation information CNT_NULL2 is in an active state and the second comparison signal CMP_MATCH2 is triggered, the second input address ACT_ADD<0:N> may be stored in the second address latch STR LATCH2 among the six address latches STR LATCH<1:6> as the second first address ADD2<0:N>. At this time, in response to the triggering of the second comparison signal CMP_MATCH2, the second counter COUNTER2 may increase the second count value CNT2<0:3> from "0" to "1", deactivate the second counting operation information CNT_NULL2, and activate the third counting operation information CNT_NULL3.

[0117] When a plurality of input addresses ACT_ADD<0:N> are applied along with the operation command LAT_CMD, six input addresses ACT_ADD<0:N> having different values may be stored as six first addresses SR_ADD<0:N> in the six address latches STR LATCH<1:6>. When an input address ACT_ADD<0:N> having the same value among the plurality of input addresses ACT_ADD<0:N> applied along with the operation command LAT_CMD is repeatedly input, a count value CNT<1:6><0:3> corresponding to the repeated input address ACT_ADD<0:N> input later may be incremented.

[0118] Figure 8 It shows Figure 5 FIG. 1 is a diagram of an embodiment of a first sequence determination circuit 341 of a sequence control circuit 34.

[0119] refer to Figure 8The first sequence determination circuit 341 may include an output control circuit (ie, output controller) 3412 and a reset control circuit (ie, reset controller) 3414. The reset control circuit 3414 may include a count check circuit 3415 and an AND gate AND13.

[0120] Whenever the input address ACT_ADD<0:N> is applied during the enable period of the reference signal PRBS, for example, whenever the operation command LAT_CMD is input, the output control circuit 3412 can check whether each of the six count values CNT<1:6><0:3> has reached the reference value. Based on the check result, the output control circuit 3412 can then generate six first control signals SR_EN<1:6> in response to the target refresh command SR_CMD to control the output operations of the corresponding six address latches STR LATCH<1:6>. At this time, the output control circuit 3412 can have information corresponding to the generation order of the six first control signals SR_EN<1:6> (i.e., the first output order) stored therein. Therefore, whenever the target refresh command SR_CMD is applied, the output control circuit 3412 can generate and output the six first control signals SR_EN<1:6> one by one.

[0121] Furthermore, when the target refresh command SR_CMD is input a predetermined number of times, the reset control circuit 3414 may check whether there is a second count value that has not reached the reference value among the six count values CNT<1:6><0:3>. The reset control circuit 3414 may then generate six fourth control signals RST_CNT<1:6> in response to the target refresh command SR_CMD based on the check result to control the reset operation of the corresponding six counters COUNTER<1:6>.

[0122] Furthermore, after checking whether there is a second count value that has not reached a reference value when the target refresh command SR_CMD is input a predetermined number of times, the count check circuit 3415 may generate six reset ready signals RST_GROUP<1:6> as a check result.

[0123] In addition, the AND gate AND13 can receive six reset preparation signals RST_GROUP<1:6> and the target refresh command SR_CMD, can perform an AND operation on the six reset preparation signals RST_GROUP<1:6> and the target refresh command SR_CMD, and as a result of the AND operation, can generate six fourth control signals RST_CNT<1:6> to control the reset operation of the corresponding six counters COUNTER<1:6>.

[0124] Figure 9 It shows Figure 58 is a diagram of an embodiment of the second sequence determination circuit 342 of the sequence control circuit 34 shown in FIG.

[0125] refer to Figure 9 The second sequence determination circuit 342 may include a command counter (SR Counter) 3422 and a refresh address output unit (ie, refresh address output logic) 3424. The refresh address output unit 3424 may include two address latches ADD LATCH<2:3>.

[0126] The SR counter 3422 may count the number of times the target refresh command SR_CMD is input and may divide the target refresh command SR_CMD into an odd target refresh command SR_CMD_ODD and an even target refresh command SR_CMD_EVEN.

[0127] The refresh address output unit 3424 may output the first address SR_ADD<0:N> output from the first storage circuit 32 as the target refresh address REF_ADD<0:N> in response to the odd target refresh command SR_CMD_ODD. The refresh address output unit 3424 may output the second address SHADOW_ADD<0:N> output from the second storage circuit 33 as the target refresh address REF_ADD<0:N> in response to the even target refresh command SR_CMD_EVEN.

[0128] In addition, the first address latch ADD LATCH2 in the refresh address output unit 3424 can latch the first address SR_ADD<0:N> output from the first storage circuit 32 in response to the odd target refresh command SR_CMD_ODD, and then can output the latched first address SR_ADD<0:N> as the target refresh address REF_ADD<0:N>.

[0129] In addition, the second address latch ADD LATCH3 in the refresh address output unit 3424 can latch the second address SHADOW_ADD<0:N> output from the second storage circuit 33 in response to the even target refresh command SR_CMD_EVEN, and then can output the latched second address SHADOW_ADD<0:N> as the target refresh address REF_ADD<0:N>.

[0130] Method described herein, process and / or operation can be performed by the code or instruction to be performed by computer, processor, controller or other signal processing equipment.Computer, processor, controller or other signal processing equipment can be those described herein or those except element described herein.Because the algorithm forming the basis of method (or the operation of computer, processor, controller or other signal processing equipment) is described in detail, so the code or the instruction for realizing the operation of method embodiment can convert computer, processor, controller, controller or other signal processing equipment into the special purpose processor for performing method herein.

[0131] When implemented at least in part with software, controllers, processors, devices, modules, circuits, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing the code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those in addition to the elements described herein. Because the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) is described in detail, the code or instructions for implementing the operation of the method embodiment may convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0132] The above embodiments are not limited to the specific examples and drawings described above. It will be apparent to those skilled in the art that various substitutions, modifications, and variations may be made without departing from the technical scope of the present disclosure. For example, the positions and types of logic gates and transistors in the above embodiments may be implemented differently depending on the polarity of the input signal. These embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor memory device comprising: a reference signal generator that generates a reference signal having enable periods, wherein the number of the enable periods and the length of each enable period are randomly determined based on an operation time; a first storage logic configured to: store a maximum of "K" addresses having different values among input addresses applied during the enable period of the reference signal as first addresses; a second storage logic configured to store, as second addresses, "L" addresses corresponding to a time point at which the enable period of the reference signal ends, among the input addresses applied during the enable period of the reference signal; a sequence controller that: determines output or non-output of each of the first addresses and a first output order based on the number of times each of the first addresses is repeatedly input, and determines a second output order for outputting a mixed address obtained by mixing the first addresses based on the first output order with the second addresses; as well as a refresh operation logic, the refresh operation logic applying the mixed address output by the sequence controller according to the second output sequence to a target refresh operation, Here, "K" is a natural number equal to or greater than 2, and "L" is a natural number equal to or greater than 1.

2. The semiconductor memory device according to claim 1 , further comprising a third storage logic, wherein: receiving an activation address input together with an activation command during the enable period of the reference signal, outputting the received activation address as an input address among the input addresses, and "L" input addresses sequentially outputted from a latest time are stored during the enable period of the reference signal.

3. The semiconductor memory device according to claim 2, wherein The first storage logic includes: "K" address latches; "K" counters, the "K" counters corresponding to the "K" address latches respectively; and a storage controller that compares the value of the input address with the values of the addresses stored in the corresponding "K" address latches and, in response to the comparison result, selectively stores the input address in the corresponding "K" address latches or selectively increases each of the "K" count values generated by the "K" counters.

4. The semiconductor memory device according to claim 3, wherein The sequence controller comprises: a first sequence determination logic that determines whether to output or not output each of the first addresses and the first output sequence according to whether each of the "K" count values reaches a reference value and the sequence in which each of the "K" count values reaches the reference value; and The second sequence determination logic determines the second output sequence based on the number of inputs of the target refresh command input to control the target refresh operation by dividing the first address into "A" pieces and placing "B" second addresses between the divided "A" first addresses, where "A" and "B" are natural numbers equal to or greater than 1.

5. The semiconductor memory device according to claim 4, wherein Until the target refresh operation is executed and the next target refresh command is input, When one or more first count values that have reached the reference value appear among the "K" count values, the first order determination logic selects one or more first addresses corresponding to the one or more first count values, and places the selected first addresses into the first output order in the order in which the count values have reached the reference value, and When the “K” count values have not reached the reference value, the first order determination logic randomly selects at least one of the first addresses and places the randomly selected first address into the first output order.

6. The semiconductor memory device according to claim 5, wherein: In a case where the target refresh command is input a predetermined number of times, when there are one or more second count values among the "K" count values that have never reached the reference value, the first sequence determination logic: deletes one or more first addresses corresponding to the one or more second count values from the first storage logic.

7. The semiconductor memory device according to claim 4, wherein The second order determination logic: In response to input of an odd-numbered target refresh command, placing the first addresses based on the first output order into the second output order one by one, and In response to input of an even-numbered target refresh command, the second addresses are put into the second output order one by one.

8. The semiconductor memory device according to claim 3, wherein The storage controller includes: an address comparator that sequentially compares the value of the input address with the values of the addresses stored in the corresponding "K" address latches and generates "K" comparison signals corresponding to comparison results; a counter controller that controls a counting operation of each of the K counters in response to each of the K comparison signals and adjusts the K count values and the K items of counting operation information generated by the corresponding K counters; and a latch controller configured to control a storage operation of each of the K address latches in response to each of the K items of counting operation information to selectively store the input address in each of the K address latches.

9. The semiconductor memory device according to claim 6, wherein The first order determination logic includes: an output controller that, when the input address is applied during the enable period of the reference signal, checks whether each of the "K" count values reaches the reference value, and controls output operations of corresponding "K" address latches in response to the target refresh command according to a result of the check; and A reset controller checks whether the second count value exists among the "K" count values, and controls reset operations of corresponding "K" counters in response to the target refresh command according to a result of the check.

10. The semiconductor memory device according to claim 7, wherein The second order determination logic includes: a command counter that counts the number of times the target refresh command is input and divides the input target refresh commands into the odd-numbered target refresh commands and the even-numbered target refresh commands; and The refresh address output logic outputs the first address as a target refresh address in response to the odd target refresh command, and outputs the second address as a target refresh address in response to the even target refresh command.

11. The semiconductor memory device according to claim 2, wherein The second storage logic: receiving the “L” input addresses stored in the third storage logic in response to the end of the enable period of the reference signal, and The received “L” input addresses are stored as the second address.

12. A method for operating a semiconductor memory device, the method comprising: generating a reference signal having enable periods, wherein the number of the enable periods and the length of each enable period are randomly determined based on an operation time; storing a maximum of "K" addresses having different values among input addresses applied during the enable period of the reference signal as first addresses; storing “L” addresses corresponding to a time point at which the enable period of the reference signal ends among the input addresses applied during the enable period of the reference signal as second addresses; determining output or non-output of each of the first addresses and a first output order based on the number of times each of the first addresses is repeatedly input, and determining a second output order for outputting a mixed address obtained by mixing the first addresses based on the first output order with the second addresses; and applying the mixed addresses output according to the second output order to a target refresh operation, Here, "K" is a natural number equal to or greater than 2, and "L" is a natural number equal to or greater than 1.

13. The operating method according to claim 12, further comprising: receiving an activation address input together with an activation command during the enable period of the reference signal, outputting the received activation address as an input address among the input addresses, and "L" input addresses sequentially outputted from a latest time are stored during the enable period of the reference signal.

14. The operating method according to claim 13, wherein: The steps of storing the maximum "K" addresses include: managing a maximum of "K" count values to manage the number of times each of the maximum of "K" first addresses is repeatedly input; comparing the value of the input address with the value of each of the first addresses; and In response to a result of the comparison, the input address is newly stored as the first address or a count value corresponding to one of the first addresses is incremented.

15. The operating method according to claim 14, wherein: The step of determining whether to output or not output the first address and the first output order includes performing the following operations: (a) determining the output or non-output of each of the first addresses and the first output order according to whether each of the count values of the first addresses reaches a reference value and the order in which each of the count values reaches the reference value; as well as (b) Based on the number of inputs of the target refresh command input for controlling the target refresh operation, the second output order is determined by dividing the first address into "A" pieces and placing "B" second addresses between the divided "A" first addresses, where "A" and "B" are both natural numbers equal to or greater than 1.

16. The operating method according to claim 15, wherein: The operation (a) includes: until the target refresh operation is performed and a next target refresh command is input, when one or more first count values that have reached the reference value appear among the count values of the first addresses being managed, selecting one or more first addresses corresponding to the one or more first count values, and placing the selected first addresses into the first output order in the order in which the count values have reached the reference value, and When the count values of the managed first addresses have not reached the reference value, at least one of the first addresses is randomly selected, and the selected first address is placed in the first output sequence.

17. The operating method according to claim 16, wherein: The operation (a) further includes: When the target refresh command is input a predetermined number of times, when there are one or more second count values that have never reached the reference value among the count values of the first address managed during the management count, one or more first addresses corresponding to the one or more second count values are deleted.

18. The operating method according to claim 15, wherein: The operation (b) includes: In response to input of an odd-numbered target refresh command, placing the first addresses based on the first output order into the second output order one by one, and In response to input of an even-numbered target refresh command, the second addresses are put into the second output order one by one.

19. The operating method according to claim 13, wherein: The step of storing the "L" addresses includes: In response to the end of the enable period of the reference signal, receiving the stored "L" input addresses, and The received “L” input addresses are stored as the second address.

20. The operating method according to claim 18, wherein: The operation (b) includes: counting the number of times the target refresh command is input, and dividing the input target refresh commands into the odd-numbered target refresh commands and the even-numbered target refresh commands; and The first address is output as a target refresh address in response to the odd-numbered target refresh command, and the second address is output as a target refresh address in response to the even-numbered target refresh command.

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