Memory management method, memory storage device and memory control circuit unit

Abstract

The present application provides a memory management method, a memory storage device and a memory control circuit unit for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of dies, each die including a plurality of planes, each plane including a plurality of physical erase units, and the rewritable non-volatile memory module including a total of a first number of planes. The method includes combining the plurality of physical erase units into a plurality of management units. Each management unit includes a plurality of physical erase units, each of which belongs to a different plane, and each management unit has a second number of physical erase units, wherein the second number is less than the first number.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and more particularly, to a memory management method, a memory storage device and a memory control circuit unit. BACKGROUND

[0002] Generally, a memory storage device can operate a plurality of blocks belonging to different operation units (e.g., planes, channels or dies) as a block group. The memory storage device can reserve spare blocks in advance to replace a failed block in the block group when the failed block is detected and marked. In this way, data can be prevented from being written into the failed block again. However, when a block for replacement belongs to another operation unit, the speed of data access can be seriously slowed down. If a failed block is not replaced when detected, but data in the block group is accessed by skipping the failed block, additional processing can be required when data is moved due to different numbers of blocks included in each block group. Such a bad block management method can cause the running speed of the memory storage device to be unstable. SUMMARY

[0003] The present application provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the speed stability of a memory storage device.

[0004] An example embodiment of the present application provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase units, and the number of the plurality of planes included in the rewritable non-volatile memory module is a first number. The memory management method includes combining the plurality of physical erase units into a plurality of management units. Each of the plurality of management units includes each of the plurality of physical erase units belonging to different ones of the plurality of planes, respectively, and each of the plurality of management units has a second number of the plurality of physical erase units. The second number is less than the first number.

[0005] In an example embodiment of the present application, the management unit includes a first management unit. The method further includes, in response to detecting that the first management unit includes a first failed physical erase unit, extracting a first replacement physical erase unit to replace the first failed physical erase unit. The first replacement physical erase unit belongs to the same plane as the first failed physical erase unit.

[0006] In an example embodiment of the present application, the method further includes recording replacement information of the first failed physical erase unit and the first replacement physical erase unit in a first management table.

[0007] In an example embodiment of the present application, the method further comprises accessing the first replacement physical erase block to replace the first bad physical erase block according to the first management table when accessing the first management block.

[0008] In an example embodiment of the present application, the first management table records replacement information of all bad physical erase blocks and replacement physical erase blocks in the plurality of physical erase blocks.

[0009] In an example embodiment of the present application, each of the management blocks has the same number of the plurality of physical erase blocks.

[0010] In an example embodiment of the present application, the step of grouping the plurality of physical erase blocks into the plurality of management blocks comprises grouping the plurality of physical erase blocks into the plurality of management blocks according to a second management table, wherein the second management table records all bad physical erase blocks in the rewritable non-volatile memory module.

[0011] An example embodiment of the present application provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The rewritable non-volatile memory module comprises a plurality of dies, each of the plurality of dies comprises a plurality of planes, each of the plurality of planes comprises a plurality of physical erase blocks, and the rewritable non-volatile memory module comprises a first number of the plurality of planes. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit groups the plurality of physical erase blocks into a plurality of management blocks. Each of the plurality of management blocks comprises a second number of the plurality of physical erase blocks, each of the second number of the plurality of physical erase blocks belongs to a different one of the plurality of planes, and the second number is less than the first number.

[0012] In an example embodiment of the present application, the management block comprises a first management block. In response to detecting that the first management block comprises a first bad physical erase block, the memory control circuit unit further extracts a first replacement physical erase block to replace the first bad physical erase block. The first replacement physical erase block and the first bad physical erase block belong to the same plane.

[0013] In an example embodiment of the present application, the memory control circuit unit further records replacement information of the first bad physical erase block and the first replacement physical erase block in a first management table.

[0014] In an example embodiment of the present invention, the memory control circuit unit further accesses the first replacement physical erase block unit to replace the first bad physical erase block unit according to the first management table when accessing the first management unit.

[0015] In an example embodiment of the present invention, the first management table records replacement information of all bad physical erase block units and replacement physical erase block units in the plurality of physical erase block units.

[0016] In an example embodiment of the present invention, each of the management units has the same number of the plurality of physical erase block units.

[0017] In an example embodiment of the present invention, the operation of grouping the plurality of physical erase block units into the plurality of management units includes grouping the plurality of physical erase block units into the plurality of management units according to a second management table, wherein the second management table records all bad physical erase block units in the rewritable non-volatile memory module.

[0018] An example embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase block units, and the rewritable non-volatile memory module includes a first number of the plurality of planes in total. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit groups the plurality of physical erase block units into a plurality of management units. Each of the plurality of management units includes each of the plurality of physical erase block units belonging to different ones of the plurality of planes, respectively, and each of the plurality of management units has a second number of the plurality of physical erase block units. The second number is less than the first number.

[0019] In an example embodiment of the present invention, the management unit includes a first management unit. In response to detecting that the first management unit includes a first bad physical erase block unit, the memory management circuit further extracts a first replacement physical erase block unit to replace the first bad physical erase block unit. The first replacement physical erase block unit and the first bad physical erase block unit belong to the same plane.

[0020] In an example embodiment of the present invention, the memory management circuit further records replacement information of the first bad physical erase block unit and the first replacement physical erase block unit in a first management table.

[0021] In an example embodiment of the present application, the memory management circuit is further configured to access the first replacement physical erase block unit when accessing the first management unit according to the first management table.

[0022] In an example embodiment of the present application, the first management table records replacement information of all bad physical erase block units and replacement physical erase block units in the plurality of physical erase block units.

[0023] In an example embodiment of the present application, each management unit has the same number of the plurality of physical erase block units.

[0024] In an example embodiment of the present application, the operation of grouping the plurality of physical erase block units into the plurality of management units includes grouping the plurality of physical erase block units into the plurality of management units according to a second management table, wherein the second management table records all bad physical erase block units in the rewritable non-volatile memory module.

[0025] Based on the above, the memory control circuit unit groups physical erase block units with a number less than the total number of planes in the rewritable non-volatile memory module into management units. The management units include physical erase block units belonging to different planes, respectively, so that the physical erase block units included in each management unit do not correspond to all planes. In addition, the memory control circuit unit can use physical erase block units belonging to the same plane to replace bad blocks in the management unit. In this way, the speed stability and operation flexibility of the memory storage device can be improved.

[0026] In order to make the above features and advantages of the present application more apparent, specific examples are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0028] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an example embodiment;

[0029] Figure 2 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to another example embodiment;

[0030] Figure 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

[0031] Figure 4is a schematic diagram of a memory storage device according to an example embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a management of a rewritable non-volatile memory module according to an example embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a memory control circuit unit coupled with a rewritable non-volatile memory module according to an example embodiment of the present invention;

[0035] Figure 8A is a schematic diagram of a rewritable non-volatile memory module according to an example embodiment of the present invention;

[0036] Figure 8B is a schematic diagram of a rewritable non-volatile memory module according to an example embodiment of the present invention;

[0037] Figure 9 is a flowchart of a memory management method according to an example embodiment of the present invention. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0039] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit unit). The memory storage device is typically used with a host system so that the host system can write data to or read data from the memory storage device.

[0040] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an example embodiment. And Figure 2 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to another example embodiment.

[0041] Please refer to Figure 1 and Figure 2The host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are coupled to a system bus 110.

[0042] In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can write data to the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 is coupled to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0043] In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a motherboard 20 of the host system 11. The number of data transfer interfaces 114 can be one or more. Through the data transfer interface 114, the motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner. The memory storage device 10 can be, for example, a USB 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, or the like I / O device through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0044] In an exemplary embodiment, the host system referred to is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is illustrated as a computer system, however, Figure 3is a schematic diagram of a host system and a memory storage device according to another example embodiment. Please refer to Figure 3 In another example embodiment, the host system 31 can also be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded memory storage device 34, etc. The embedded memory storage device 34 includes an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) 342, etc.

[0045] Figure 4 is a schematic block diagram of a memory storage device according to an example embodiment of the present application. Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

[0046] The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In the present exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be appreciated that the present application is not limited thereto, and the connection interface unit 402 can also be compatible with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 402 can be packaged in a chip with the memory control circuit unit 404, or the connection interface unit 402 is disposed outside a chip containing the memory control circuit unit 404.

[0047] The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 406 according to instructions of the host system 11.

[0048] The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a Multi Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), other flash memory modules, or other memory modules having the same characteristics.

[0049] Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

[0050] In the present exemplary embodiment, the storage units of the rewritable nonvolatile memory module 406 can constitute a plurality of physical programming units, and the physical programming units can constitute a plurality of physical erasing units. Specifically, the storage units in the same character line can form one or more physical programming units. If each storage unit can store more than two bits, the physical programming units in the same character line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a storage unit belongs to a lower physical programming unit, and the most significant bit (MSB) of a storage unit belongs to an upper physical programming unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical programming unit is greater than that of an upper physical programming unit, and / or the reliability of a lower physical programming unit is higher than that of an upper physical programming unit.

[0051] In the present exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit of writing data. For example, a physical programming unit can be a physical page or a physical sector. If a physical programming unit is a physical page, the physical programming units can include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area can include 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erasing unit is the smallest unit of erasing. That is, each physical erasing unit contains the minimum number of storage units that are erased. For example, a physical erasing unit is a physical block.

[0052] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present application. Referring to Figure 5 The memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

[0053] The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. In particular, the memory management circuit 502 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

[0054] In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0055] In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in program code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 406. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 502. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0056] In another example embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 406 and the data read from the rewritable non-volatile memory module 406. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 502 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

[0057] The host interface 504 is coupled to the memory management circuit 502. The memory management circuit 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504. In the present example embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present application is not limited thereto, and the host interface 504 can also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0058] The memory interface 506 is coupled to the memory management circuit 502 and is used to access the rewritable non-volatile memory module 406. That is, data intended to be written to the rewritable non-volatile memory module 406 is converted by the memory interface 506 into a format acceptable to the rewritable non-volatile memory module 406. Specifically, if the memory management circuit 502 is to access the rewritable non-volatile memory module 406, the memory interface 506 transmits a corresponding sequence of instructions. For example, the sequence of instructions can include a sequence of write instructions indicating data to be written, a sequence of read instructions indicating data to be read, a sequence of erase instructions indicating data to be erased, and corresponding sequences of instructions to indicate various memory operations (e.g., changing a read voltage level or performing a garbage collection operation, etc.). The sequence of instructions is generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 via the memory interface 506. The sequence of instructions can include one or more signals, or data on a bus. The signals or data can include scripts or program codes. For example, in a read instruction sequence, information such as an identification code of the read, a memory address, etc. is included.

[0059] In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

[0060] The error checking and correction circuit 508 is coupled to the memory management circuit 502 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write instruction from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for data corresponding to the write instruction, and the memory management circuit 502 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the corresponding error correcting code and / or error detecting code for the data is also read, and the error checking and correction circuit 508 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0061] The buffer memory 510 is coupled to the memory management circuit 502 and is used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

[0062] In an example embodiment, Figure 4 The rewritable non-volatile memory module 406 is also referred to as a flash memory module, the memory control circuit unit 404 is also referred to as a flash controller for controlling the flash memory module, and / or Figure 5 The memory management circuit 502 is also referred to as a flash management circuit.

[0063] Figure 6 FIG. 1 is a schematic diagram showing management of a rewritable non-volatile memory module according to an example embodiment of the present application.

[0064] Please refer to Figure 6 The memory management circuit 502 logically groups the physical units 610(0)~610(D) of the rewritable non-volatile memory module 406 into a storage area 601, a spare area 602, a replacement area 603, and a system area 604. In this example embodiment, each physical unit can refer to one or more physical erase units.

[0065] It must be understood that the terms "fetch", "move", "swap", "replace", "rotate", "split", "divide", and the like, when used in describing the operation of the memory storage device, refer to logical operations on the physical units of the rewritable non-volatile memory module 406. That is, the actual locations of the physical units of the rewritable non-volatile memory module 406 are not changed, but the physical units of the rewritable non-volatile memory module 406 are logically operated on.

[0066] The physical units 610(0)~610(A) in the storage area 601 store data. For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the spare area 602 have not yet been used to store data (e.g., valid data). When data is to be stored, the memory management circuit 502 selects a physical unit from the physical units 610(A+1)~610(B) in the spare area 602, and stores data from the host system 11 or from at least one physical unit in the storage area 601 into the selected physical unit. At the same time, the selected physical unit is associated with the storage area 601. Furthermore, after a physical unit in the storage area 601 is erased, the erased physical unit is re-associated with the spare area 602.

[0067] The physical units 610(B+1)~610(C) in the replacement area 603 are used to replace the damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit (also called a bad physical unit). In addition, if there is no available bad physical unit in the replacement area 603, the memory management circuit 502 can declare the entire memory storage device 10 as write-protected so that no more data can be written into the memory storage device 10. The physical units 610(C+1)~610(D) in the system area 604 are used to store system data, such as a logical-to-physical mapping table, a bad block management table, a device model, or other types of management data.

[0068] The memory management circuit 502 configures the logical units 612(0)~612(E) to map the physical units 610(0)~610(A) in the storage area 601. Each of the logical units 612(0)~612(E) can be mapped to one or more physical units. The memory management circuit 502 records the mapping relationship between the logical units and the physical units (also called logical-to-physical mapping information) in at least one logical-to-physical mapping table. The logical-to-physical mapping table can be stored in the physical units 610(C+1)~610(D) in the system area 604. When the host system 11 wants to read data from or write data into the memory storage device 10, the memory management circuit 502 can perform data access operations on the memory storage device 10 according to the logical-to-physical mapping table.

[0069] In an example embodiment, the rewritable non-volatile memory module 406 can include a plurality of dies and have a plurality of planes, each plane belonging to one die. The rewritable non-volatile memory module 406 can include a total number of planes equal to a first number. In the present example embodiment, the number of planes can be greater than the number of dies. That is, two or more planes can belong to one die. Each plane can include a plurality of bad physical units and a plurality of physical program units, and the plurality of physical program units combine to form one bad physical unit.

[0070] Figure 7 is a schematic diagram showing a memory control circuit unit coupled to a rewritable non-volatile memory module according to an example embodiment of the present application. Please refer to Figure 7The rewritable non-volatile memory module 406 includes two dies D0, D1, and each die includes two planes P0, P1. In the present exemplary embodiment, the rewritable non-volatile memory module 406 includes four planes, and thus has a total number of planes equal to 4 (i.e., the first number is 4). Each of the planes P0 and P1 includes a plurality of physical erase units, each of which is composed of a plurality of physical program units. However, in different embodiments, the rewritable non-volatile memory module 406 can include more or less dies, and each die can include more or less planes, without limitation.

[0071] In the present exemplary embodiment, the dies D0 and D1 are coupled to the memory control circuit unit 404 through chip enable pins, respectively. The memory control circuit unit 404 can send an enable signal to the chip enable pins of the dies D0 and D1 to enable the dies D0 and D1, respectively. After the dies are enabled, the memory control circuit unit 404 can access data through the channel 408 (e.g., a data bus). The channel 408 can include one or more channels. That is, the physical program units included in the planes P0, P1 of the die D0 and the planes P0, P1 of the die D1 are accessed via the channel 408. In an exemplary embodiment, the data stored in the planes P0 and P1 can be accessed via the channel 408 using a single plane access operation or a multiple plane access operation, where using the multiple plane access operation can access the data stored in the planes P0 and P1 in parallel.

[0072] In the present exemplary embodiment, the memory control circuit unit 404 can also enable multiple dies simultaneously through one enable signal, or enable multiple dies individually through multiple enable signals. Also, the data stored in different dies can be accessed via different channels. For example, the data stored in the planes P0 and P1 of the die D0 can be accessed via one channel, and the data stored in the planes P0 and P1 of the die D1 can be accessed via another channel. Figure 7

[0073] ​In one exemplary embodiment, the memory control circuit unit 404 combines multiple physical erase units into a single management unit, and the rewritable non-volatile memory module 406 includes multiple management units. Each of the multiple physical erase units included in each management unit belongs to a different plane, and each management unit has a fixed number of physical erase units (also referred to as the second number). In this exemplary embodiment, this second number is less than the sum of the number of the multiple planes included in the aforementioned rewritable non-volatile memory module 406 (i.e., the first number). In one exemplary embodiment, each of the multiple management units has the same number of physical erase units.

[0074] In one exemplary embodiment, when combining multiple physical erase units into a management unit, the memory control circuit unit 404 can combine multiple physical erase units into one management unit according to a bad block record management table (also known as a second management table, for example, a DBT (Defect Block Table) that records bad blocks). This bad block record management table records all bad physical erase units in the rewritable non-volatile memory module 406. Specifically, bad physical erase units may appear in the rewritable non-volatile memory module 406 due to process defects. During the initial organizer unit, the memory control circuit unit 404 can exclude bad physical erase units according to the bad block record management table and combine the multiple normal physical erase units into management units respectively.

[0075] Figure 8A This is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 8A The rewritable non-volatile memory module 406 includes four planes (planes P0 and P1 of die D0, and planes P0 and P1 of die D1). Plane P0 of die D0 includes physical erase units 810(0) to 810(M), plane P1 of die D0 includes physical erase units 820(0) to 820(M), plane P0 of die D1 includes physical erase units 830(0) to 830(M), and plane P1 of die D1 includes physical erase units 840(0) to 840(M). For ease of explanation, it is assumed that the rewritable non-volatile memory module 406 includes management units 81(0) to 81(3); however, the present invention does not limit the number of management units. Each management unit includes three physical erase units. Figure 8A As shown, the number of physical erasure units included in each management unit is less than the total number of planes included in the rewritable non-volatile memory module 406.

[0076] In an example embodiment, when a physical erase block of the rewritable non-volatile memory module 406 is damaged, the physical erase block is considered as a bad physical erase block. The damage can occur when the manufacturing process is not good, or can occur after a number of erases such that the data read from the physical erase block contains too many errors to be corrected. When the damage occurs, the memory control circuit unit 404 can extract a replacement physical erase block from the replacement area 603 to replace the damaged bad physical erase block in the storage area 601.

[0077] Figure 8B is a diagram of a rewritable non-volatile memory module according to an example embodiment of the present invention. Please refer to Figure 8B , it is assumed that the physical erase block 840(0) (a bad physical erase block in this example embodiment) is damaged. In response to detecting that the management unit 81(1) (also referred to as a first management unit) includes the physical erase block 840(0) (also referred to as a first bad physical erase block), the memory control circuit unit 404 extracts a replacement physical erase block (also referred to as a first replacement physical erase block) to replace the physical erase block 840(0). In this example embodiment, the replacement physical erase block and the bad physical erase block belong to the same plane. As shown in Figure 8B , the memory control circuit unit 404 extracts the physical erase block 840(P) belonging to the same plane as the physical erase block 840(0) to replace the bad physical erase block 840(0).

[0078] In an example embodiment, the memory control circuit unit 404 records the replacement information of the bad physical erase block and the replacement physical erase block in a bad block replacement management table (also referred to as a first management table, for example, a RUT (Replace Unit Table) that manages the replacement of bad blocks). The bad block replacement management table records the replacement information of all bad physical erase blocks and replacement physical erase blocks. For example, the memory control circuit unit 404 records the replacement information of the bad physical erase block 840(0) and the replacement physical erase block 840(P) in the bad block replacement management table. When the memory control circuit unit 404 accesses the management unit 81(1), if the accessed address is the address of the original physical erase block 840(0), the memory control circuit unit 404 changes to access the physical erase block 840(P) according to the bad block replacement management table. That is, when the memory control circuit unit 404 accesses the management unit 81(1), the memory control circuit unit 404 accesses the physical erase block 840(P) when accessing the management unit 81(1) according to the first management table. Figure 8B

[0079] Figure 9 is a flowchart of a memory management method according to an example embodiment of the present invention. Please refer to​Figure 9 In step S902, the plurality of entity erase units are combined into a plurality of management units. Each of the management units includes a plurality of entity erase units, each of which belongs to a different plane, and each of the management units has a second number of entity erase units.

[0080] In summary, the exemplary embodiments of the present application provide for operating management units composed of entity erase units whose number is less than the total number of planes that the rewritable non-volatile memory module has, and the entity erase units belong to different planes, respectively. In this way, each management unit includes entity erase units that do not correspond to all planes. In this way, the chance of normal entity erase units of the same plane being exhausted when there are too many bad blocks is reduced, so that the tolerance of each plane to bad blocks is improved, thereby reducing the chance of using entity erase units of another operating unit to replace bad blocks when entity erase units of the same operating unit are exhausted. In addition, by replacing bad blocks, the number of entity erase units included in each management unit can be kept the same without additional processing in data migration operations. In this way, the speed stability and operating flexibility of the memory storage device can be effectively improved.

[0081] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, characterized in that, A rewritable non-volatile memory module is used, wherein the rewritable non-volatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase units, and the total number of the plurality of planes included in the rewritable non-volatile memory module is a first number, the memory management method includes: The multiple entity erasure units are combined into multiple management units. Each of the plurality of management units includes a plurality of entity erasure units, each belonging to a different plurality of planes, and each of the plurality of management units has a second number of the plurality of entity erasure units. The second number is less than the first number.

2. The memory management method according to claim 1, characterized in that, The plurality of management units includes a first management unit, and the method further includes: In response to the detection that the first management unit includes a first bad entity erasure unit, a first replacement entity erasure unit is extracted to replace the first bad entity erasure unit. The first replacement entity erasure unit and the first bad entity erasure unit belong to the same plane.

3. The memory management method according to claim 2, characterized in that, The method further includes: The replacement information of the first bad entity erasure unit and the first replacement entity erasure unit is recorded in the first management table.

4. The memory management method according to claim 3, characterized in that, The method further includes: According to the first management table, the first replacement entity erasure unit is accessed when the first management unit is accessed.

5. The memory management method according to claim 3, characterized in that, The first management table records the replacement information of all bad entity erasure units and replacement entity erasure units in the plurality of entity erasure units.

6. The memory management method according to claim 1, characterized in that, Each of the plurality of management units has the same number of the plurality of entity erasure units.

7. The memory management method according to claim 1, characterized in that, The step of combining the plurality of entity erasure units into the plurality of management units includes: The plurality of entity erasure units are combined into the plurality of management units according to the second management table, wherein the second management table records all bad entity erasure units in the rewritable non-volatile memory module.

8. A memory storage device, comprising: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase units, and the total number of the plurality of planes included in the rewritable non-volatile memory module is a first number; and The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to combine the plurality of physical erasure units into a plurality of management units. Each of the plurality of management units includes a plurality of entity erasure units, each belonging to a different plurality of planes, and each of the plurality of management units has a second number of the plurality of entity erasure units. The second number is less than the first number.

9. The memory storage device according to claim 8, characterized in that, The plurality of management units includes a first management unit, and in response to detecting that the first management unit includes a first bad entity erase unit, the memory control circuit unit is further configured to extract a first replacement entity erase unit to replace the first bad entity erase unit. The first replacement entity erasure unit and the first bad entity erasure unit belong to the same plane.

10. The memory storage device according to claim 9, characterized in that, The memory control circuit unit is further used to record the replacement information of the first bad entity erasure unit and the first replacement entity erasure unit in the first management table.

11. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is further configured to access the first replacement entity erasure unit when accessing the first management unit, according to the first management table.

12. The memory storage device according to claim 10, characterized in that, The first management table records the replacement information of all bad entity erasure units and replacement entity erasure units in the plurality of entity erasure units.

13. The memory storage device according to claim 8, characterized in that, Each of the plurality of management units has the same number of the plurality of entity erasure units.

14. The memory storage device according to claim 8, characterized in that, The operation of combining the plurality of entity erasure units into the plurality of management units includes: The plurality of entity erasure units are combined into the plurality of management units according to the second management table, wherein the second management table records all bad entity erasure units in the rewritable non-volatile memory module.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase units, and the sum of the number of the plurality of planes included in the rewritable non-volatile memory module is a first number, characterized in that, The memory control circuit unit includes: Host interface, used to couple to a host system; A memory interface for coupling to the rewritable non-volatile memory module; and The memory management circuitry is coupled to the host interface and the memory interface. The memory management circuitry is used to combine the plurality of physical erase units into a plurality of management units. Each of the plurality of management units includes a plurality of entity erasure units, each belonging to a different plurality of planes, and each of the plurality of management units has a second number of the plurality of entity erasure units. The second number is less than the first number.

16. The memory control circuit unit according to claim 15, characterized in that, The plurality of management units includes a first management unit, and in response to detecting that the first management unit includes a first bad entity erase unit, the memory management circuitry is further configured to extract a first replacement entity erase unit to replace the first bad entity erase unit. The first replacement entity erasure unit and the first bad entity erasure unit belong to the same plane.

17. The memory control circuit unit according to claim 16, characterized in that, The memory management circuit is further used to record the replacement information of the first bad entity erasure unit and the first replacement entity erasure unit in the first management table.

18. The memory control circuit unit according to claim 17, characterized in that, The memory management circuitry is further configured to access the first replacement entity erasure unit when accessing the first management unit, based on the first management table.

19. The memory control circuit unit according to claim 17, characterized in that, The first management table records the replacement information of all bad entity erasure units and replacement entity erasure units in the plurality of entity erasure units.

20. The memory control circuit unit according to claim 15, characterized in that, Each of the plurality of management units has the same number of the plurality of entity erasure units.

21. The memory control circuit unit according to claim 15, characterized in that, The operation of combining the plurality of entity erasure units into the plurality of management units includes: The plurality of entity erasure units are combined into the plurality of management units according to the second management table, wherein the second management table records all bad entity erasure units in the rewritable non-volatile memory module.

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