Memory error correction based on hierarchical error detection

Abstract

This application relates to memory error correction based on hierarchical error detection. In some instances, a memory system can identify a set of bits that includes a number of error bits that cannot be corrected based on a first type of error detection procedure alone. The memory system can generate one or more sets of candidate bits based on altering different groups of bits within the set of bits and evaluate one or more sets of such candidate bits using a second type of error detection procedure until a set of candidate bits is identified as error free. Then, the memory system can correct the set of bits based on the set of candidate bits identified as error free.

Description

[0001] Cross Reference to Related Applications

[0002] The present patent application claims priority to U.S. Patent Application No. 17 / 117,913 to HANNA, filed December 10, 2020, entitled “MEMORY ERROR CORRECTION BASED ON LAYERED ERROR DETECTION,” assigned to the assignee hereof and hereby expressly incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The technical field relates to memory error correction based on layered error detection. BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states typically corresponding to a logical one or a logical zero. In some examples, an individual memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] There are a variety of types of memory devices including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), or NOT OR (NOR) and NOT AND (NAND) memory devices, among others. Memory devices can be volatile or non-volatile. Volatile memory cells, such as DRAM cells, can lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells, such as NAND memory cells, can retain their programmed state for extended periods of time even in the absence of an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a memory array; and a controller coupled with the memory array and configured to cause the apparatus to receive a set of bits from the memory array; identify that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits; update the at least two bits in the set of bits based at least in part on a second type of error detection procedure; and transmit the set of updated bits to a host device.

[0007] A non-transitory computer-readable medium storing code is described. The code, when executed by a processor of an electronic device, can cause the electronic device to receive a set of bits from a memory array; identify that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits; update the at least two bits in the set of bits based at least in part on a second type of error detection procedure; and transmit the set of updated bits to a host device.

[0008] A method is described. The method can include receiving a set of bits from a memory array; identifying that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits; updating the at least two bits in the set of bits based at least in part on a second type of error detection procedure; and transmitting the set of updated bits to a host device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 Examples of a system that supports memory error correction based on hierarchical error detection in accordance with the examples disclosed herein are described.

[0010] Figure 2 Examples of a system that supports memory error correction based on hierarchical error detection in accordance with the examples disclosed herein are described.

[0011] Figure 3 Examples of a process flow that supports memory error correction based on hierarchical error detection in accordance with the examples disclosed herein are described.

[0012] Figure 4 A block diagram of a memory system that supports memory error correction based on hierarchical error detection in accordance with the examples disclosed herein is shown.

[0013] Figure 5 and 6 A flow diagram illustrating one or several methods that support memory error correction based on hierarchical error detection in accordance with the examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] A controller for a memory device can perform an error detection procedure on a set of bits (e.g., data) before sending the bits to a host system. However, in some cases, the controller can detect an error that the controller can not be able to correct based on the error detection procedure alone. For example, the controller can perform a single error correction and double error detection (SECDED) procedure on a set of bits before sending the bits to a host system, and the SECDED procedure can allow the controller to detect that at least two bits in the set of bits are incorrect, but the SECDED procedure can not support correcting the two bits.

[0015] In some cases, in response to detecting an uncorrectable error, the controller can initiate a reset procedure of the memory device, abort a command from the host system associated with retrieving a set of bits, or both. Performing a reset procedure can involve an undesirable delay, and from a reliability perspective, it can be undesirable to abort a command, among other drawbacks that would be apparent to those skilled in the art.

[0016] However, as described herein, in response to detecting an error using a first type of error detection procedure, the controller can correct the error bits based on possibly performing a second type of error detection procedure (e.g., a cyclic redundancy check (CRC) procedure) on a larger set of bits that includes the set of bits in which the error was detected and one or more additional bits. For example, after retrieving a set of bits from a memory array, the controller can perform a first type of error detection procedure (e.g., a SECDED procedure) on the set of bits using a first type of error detection code (e.g., a SECDED code) and detect other uncorrectable errors (e.g., a double bit error). A second type of error detection code (e.g., a CRC code) applicable to the set of bits can be stored in the memory array. For example, in some cases, the set of bits can be part of a larger set of bits for which its corresponding second type of error detection code is stored in the memory array (e.g., the memory array can store a CRC code for a superset of bits, and the set of bits with the detected error is a subset of the superset of bits). The controller can generate one or more sets of candidate bits, where each can correspond to the set of bits but with a different group of N bits altered, where N is equal to the number of incorrect bits detected using the performance of the first type of error detection procedure (e.g., N can be two (2) where the first type of error detection procedure is a SECDED procedure). Then, the controller can evaluate one or more of such sets of candidate bits based on the second type of error detection code using the second type of error detection procedure (e.g., a CRC check can be performed on one or more sets of candidate bits) until a set of candidate bits is identified as being error free. When performing the second type of error detection procedure on a superset of bits of which the set of error bits is a subset, each set of candidate bits can include any additional bits within the superset of bits as well as an altered version of the set of error bits.

[0017] Bits within the set of candidate bits identified as being free of error can be used to replace error bits associated with errors detected using the first type of error detection procedure. In some cases, the controller can then transmit a set of updated (e.g., corrected) bits to the host system. Thus, these and other aspects of the teachings herein can avoid latency associated with a reset procedure, extend the error correction capability and reliability of a memory system, or both, as well as other advantages that will be apparent to those of ordinary skill in the art.

[0018] The features of the present disclosure are first described in the context of a reference Figures 1-2 The features of the present disclosure are first described in the context of a reference Figure 3 The features of the present disclosure are first described in the context of a reference Figures 4-6 The features of the present disclosure are first described in the context of a reference

[0019] Figure 1 An example of a system 100 that supports layered error detection based memory error correction in accordance with examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled with a memory system 110.

[0020] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0021] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0022] The system 100 can include a host system 105 that can be coupled with the memory system 110. In some examples, this coupling can include an interface with a host system controller 106, which can be an example of a control component configured to cause the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 can include one or more devices, and in some cases can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured for communication with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 can use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1 Although one memory system 110 is shown, the host system 105 can be coupled with any number of memory systems 110.

[0023] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals) via the physical host interface using an associated protocol. Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM slot interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0024] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 Two memory devices 130-a and 130-b are shown in the example of FIG. 1, the memory system 110 can include any number of memory devices 130. Moreover, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0025] The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations in accordance with the examples described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations at the memory devices 130 such as reading data, writing data, erasing data, or refreshing data (and other such operations), which can be generally referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with the one or more memory devices 130 to perform such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive a command or operation from the host system 105 and can convert the command or operation into instructions or appropriate commands to effectuate the desired access of the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0027] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions attributed herein to the memory system controller 115.

[0029] The memory devices 130 can include one or more arrays of non-volatile memory cells. For example, the memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory devices 130 can include one or more arrays of volatile memory cells. For example, the memory devices 130 can include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 can include (e.g., on the same die or within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 can operate in conjunction with the memory system controller 115 or can perform one or more functions attributed herein to the memory system controller 115. For example, as explained in Figure 1 The memory device 130-a can include the local controller 135-a and the memory device 130-b can include the local controller 135-b, as explained in

[0031] In some cases, the memory device 130 can be or include a NAND device (e.g., a NAND flash device). The memory device 130 can be or include a memory die 160. For example, in some cases, the memory device 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, and each page 175 can include a set of memory cells.

[0032] In some cases, the NAND memory device 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) when configured to each store two bits of information, triple-level cells (TLCs) when configured to each store three bits of information, quad-level cells (QLCs) when configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but can involve narrower read or write margins or greater complexity for supporting circuitry in some cases.

[0033] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, concurrent operations can occur within different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170 so long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 is subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across the planes 165).

[0034] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., coupled with a common word line), and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., coupled with a common digit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level) but can be erased at a second granularity level (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., group of memory cells) that can be programmed or read independently (e.g., concurrently as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., group of memory cells) that can be erased independently (e.g., concurrently as part of a single erase operation). Further, in some cases, a NAND memory cell can be erased before it can be overwritten with new data. Thus, for example, an old page 175 can not be updated until the entire block 170 containing the page 175 is erased in some cases.

[0036] The system 100 can include any number of non-transitory computer- readable media that support memory error correction based on hierarchical error detection. For example, the host system 105, the memory system controller 115, or the memory device 130 can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., the host system controller 106), the memory system controller 115, or the memory device 130 (e.g., the local controller 135), can cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more of the associated functions described herein.

[0037] In some cases, the memory system controller 115 coupled with the memory device 130 and the host system 105 can receive a set of bits (e.g., data) from the memory device 130 for transmission to the host system 105 (e.g., in response to a read command for the set of bits received by the memory system controller 115 from the host system 105, where the set of bits is stored by the memory device 130). In some examples, the memory system controller 115 can identify that the set of bits includes a number of bit errors (error bits) that cannot be corrected using a first type of error detection procedure (e.g., a SECDED procedure) based on the first type of error detection procedure (e.g., at least two bits in the set of bits are incorrect, where the first type of error detection procedure is a SECDED procedure). For example, the occurrence of errors can be related to receiving the set of bits from the memory device 130 at the memory system controller 115 (e.g., a transmission error), storing the set of bits at the local memory 120 (e.g., a storage error), or any combination thereof. The set of bits can be checked for errors using the first type of error detection procedure after the set of bits is read from the local memory 120 for transmission to the host system 105.

[0038] To avoid performing a reset of the memory system 110, aborting a related command from the host system 105, or both based on a detected error that cannot be corrected using the first type of error detection procedure, the memory system controller 115 can update (e.g., correct) at least two bits in the set of bits based on a second type of error detection procedure (e.g., a CRC procedure). For example, the memory system controller 115 can generate one or more sets of candidate bits, where each of the one or more sets of candidate bits is generated based on altering a respective N number of bits of a group within the set of bits having a detected error, where N is a corresponding number of bit errors. Additionally, the memory system controller 115 can evaluate each of the one or more sets of candidate bits using the second type of error detection procedure (e.g., a repeated instance thereof) until a set of candidate bits is identified as being error free. In some such instances, the first type of error detection procedure can be based on a first type of error detection code (e.g., a SECDED code), and the second type of error detection procedure can be based on a second type of error detection code (e.g., a CRC code), where the second type of error detection code can be stored with the memory device 130. Additionally or alternatively, the second type of error detection code can correspond to a superset of bits that includes the set of bits in which an error was detected using the first type of error detection procedure (e.g., that has been previously generated based thereon), in which case each set of candidate bits can include any additional bits of the superset and an altered version of the set of bits in which an error was detected using the first type of error detection procedure. In some cases, the memory system controller 115 can transmit a set of corrected bits to the host system 105.

[0039] Although specific examples can be described herein in the context of a NAND memory device, it should be understood that the teachings herein can be applied in the context of any type of memory.

[0040] Figure 2 An example of a system 200 that supports memory error correction based on hierarchical error detection in accordance with examples disclosed herein is illustrated. The system 200 can include a memory device 205, a controller 210, and a host system 215. In some examples, the system 200 can include one or more aspects of a memory system as described with reference to Figure 1 For example, the memory device 205 can be an example of the memory device 130 described with reference to Figure 1 For example, the memory device 205 can be an example of the memory device 130 described with reference to Figure 1 For example, the memory device 205 can be an example of the memory device 130 described with reference to Figure 1 For example, the memory device 205 can be an example of the memory device 130 described with reference to

[0041] In some examples, the memory device 205 can be an example of a NAND memory device (e.g., a memory device including one or more NAND memory arrays configured to store data from the controller 210 and retrieve data for the controller 210). The controller 210 can include local memory, such as local SRAM memory (e.g., the controller 210 can include a set of SRAM memory cells configured to store data from the memory device 205, which can be an example of the local memory 120 described below). The controller 210 can store (e.g., cache, queue) data received from the memory device 205 or the host system 215 within the local memory for some amount of time before relaying the data to the host system 215 or the memory device 205 (e.g., in response to a command received from the host system 215). Figure 1 In some examples, the memory device 205 can be an example of a NAND memory device (e.g., a memory device including one or more NAND memory arrays configured to store data from the controller 210 and retrieve data for the controller 210). The controller 210 can include local memory, such as local SRAM memory (e.g., the controller 210 can include a set of SRAM memory cells configured to store data from the memory device 205, which can be an example of the local memory 120 described below). The controller 210 can store (e.g., cache, queue) data received from the memory device 205 or the host system 215 within the local memory for some amount of time before relaying the data to the host system 215 or the memory device 205 (e.g., in response to a command received from the host system 215).

[0042] The memory device 205 can be coupled with the controller 210 (e.g., via one or more respective first buses or other signal paths), and the controller 210 can be coupled with the host system 215 (e.g., via one or more respective second buses or other signal paths). The memory device 205 can be configured to provide data (e.g., one or more bits) to the controller 210, and the controller 210 can be configured to provide data to the host system 215 (e.g., in response to a read command from the host system 215). Additionally or alternatively, the controller 210 can be configured to receive data (e.g., one or more bits) from the host system 215 and provide the data to the memory device 205, where the memory device 205 can be configured to store the data (e.g., in response to a write command from the host system 215).

[0043] In some examples, the controller 210 can receive a set of bits 220-a from a memory array of the memory device 205 (e.g., based on a read command received by the controller 210 from the host system 215, the controller 210 can direct the read command to the memory device 205). The set of bits 220-a can include any number of subsets of bits 225. For example, the set of bits 220-a can include a subset of bits 225-a, 225-b, 225-c, and 225-d. In some examples, one or more bits within a subset of bits 225 can be improperly flipped between retrieval from a memory array at the memory device 205 and later retrieval from a local memory unit of the controller 210 (e.g., from an SRAM memory unit). In some examples, the controller 210 can be configured to detect the improper flipping of one or more bits within a subset of bits 225 (e.g., based on a comparison of the set of bits 220-a to a set of bits 220-b received from the local memory unit of the controller 210). In some examples, the controller 210 can be configured to correct the improper flipping of one or more bits within a subset of bits 225 (e.g., based on a comparison of the set of bits 220-a to the set of bits 220-b received from the local memory unit of the controller 210). Figure 2In the example of FIG. 2, one or more bits within the subset of bits 225-c can be erroneous. For example, one or more transmission errors can occur based on the subset of bits 225-c being transmitted from the memory device 205 to the controller 210. Additionally or alternatively, one or more components at the controller 210 can distort a signal associated with the subset of bits 225-c such that the controller 210 determines that one or more bits in the subset of bits 225-c have a value that is flipped relative to the actual value of the bit. Additionally or alternatively, an error can occur when the subset of bits 225 is stored within a local memory of the controller 210 (e.g., due to electromagnetic interference or some other phenomenon).

[0044] Regardless of the cause, the controller 210 can identify that at least two bits in the subset of bits 225 are incorrect using a first type of error detection procedure but can be unable to correct the detected error using the same first type of error detection procedure. The first type of error detection procedure can be based on a first type of error detection code. For example, the controller 210 can identify that at least two bits in the subset of bits 225-c are incorrect using a SECDED procedure that can be based on a SECDED code. In some examples, the controller 210 can evaluate the subset of bits 225 using the first type of error detection procedure after storing a set of bits within a local memory unit (e.g., an SRAM memory unit) of the controller 210 (e.g., after reading a set of bits from such a memory unit in preparation for transmitting the set of bits to the host system 215).

[0045] In some cases, each subset of bits 225 can be associated with a respective error detection code of the first type (e.g., a respective SECDED code). For example, the subset of bits 225-a can be associated with a first error detection code of the first type, the subset of bits 225-b can be associated with a second error detection code of the first type, the subset of bits 225-c can be associated with a third error detection code of the first type, and the subset of bits 225-d can be associated with a fourth error detection code of the first type.

[0046] To correct the bit error that is detected using the first type of error detection procedure but cannot be corrected using only the first type of error detection procedure, the controller 210 can use a second type of error detection procedure. For example, the controller 210 can receive one or more parity bits associated with the erroneous subset of bits 225 from the memory device 205 and perform the second type of error detection procedure based on the parity bits. The parity bits can comprise a second type of error detection code (e.g., a CRC code).

[0047] The second type of error detection code can be associated with a set of bits 220-a that includes the erroneous subset of bits 225-c (e.g., can have been previously generated based on the set of bits 220-a and stored by the memory device 205 associated with the set of bits 220-a). As Figure 2As shown in the example of FIG. 2A, the set of bits 220-a can also include any number of additional subsets of bits 225. Thus, in some cases, the first type of error detection procedure can operate at a subset granularity level (e.g., each subset of bits 225 can be associated with and evaluated separately based on a corresponding first type of error detection code using the first type of error detection procedure), while the second type of error detection procedure can operate at a larger group granularity level (e.g., each set of bits 220 can be associated with and evaluated based on a corresponding second type of error detection code using the second type of error detection procedure). Thus, the second type of error detection procedure and code can be associated with a superset of bits relative to the bits associated with the first type of error detection procedure and code, where a set of bits 220 is a superset of the multiple subsets of bits 225.

[0048] To update the subset of bits 225-c, the controller 210 can generate one or more sets of candidate bits 220, where each of the one or more sets of candidate bits 220 is based on altering a group of corresponding N bits within the set of bits 220-a and more specifically, a group of corresponding N bits within the subset of bits 225-c corresponding to the error detected using the first type of error detection procedure. N can be equal to the number of incorrect bits associated with the detected error (e.g., N can be two (2) where the first type of error detection procedure is a SECDED procedure).

[0049] For example, if each subset of bits 225-c has x bits and N is equal to two (2), then the controller 210 can generate up to a set of candidate bits 220, where each of the sets of candidate bits 220 is different from the other sets of candidate bits. That is, a different pair of bits within the erroneous subset of bits 225-c can be altered (flipped) in order to generate each set of candidate bits 220 relative to the set of bits 220 that includes the subset of bits 225-c having the detected error. A set of candidate bits 220 can be evaluated using the second type of error detection procedure (e.g., using the CRC code associated with the set of bits 220-a) to determine whether the set of candidate bits is error free, in which case the altered pair of bits are the erroneous bits that caused the error previously detected in the erroneous subset of bits 225-c. Thus, the controller 210 can generate and evaluate one or more sets of candidate bits 220 using the second type of error detection procedure (e.g., using the CRC code) until a set of candidate bits is identified as error free.

[0050] In some cases, controller 210 can transmit a set of updated bits 220-b, or any portion thereof, to host system 215, where the set of updated bits 220-b, or the portion thereof, can correspond to (e.g., be identical to) a set of candidate bits 220, or a portion thereof, identified as being free of errors using the second type of error detection procedure. For example, the set of updated bits 220-b can include a subset of bits 225-a, 225-b, and 225-d included in the set of bits 220-a. Additionally, the set of updated bits 220-b can include a subset of bits 225-e, which can be an updated version of a subset of bits 225-c, where N bits have been updated to correct values. In some examples, after updating the subset of bits 225-c and prior to transmitting the set of updated bits 220-b, controller 210 can verify that the updated subset of bits 225-e, or each bit in the set of updated bits 220-b, is correct using one or more instances of the first type of error detection procedure (e.g., controller 210 can perform another SECDED evaluation on the updated subset of bits 225-e, or any other subset of bits 225, within the set of updated bits 220-b to verify that the changes determined using the CRC procedure are correct). In such examples, transmitting the set of updated bits 220-b, or the portion thereof, to host system 215 can be based on (e.g., dependent on, responsive to) verifying that each bit in the set of updated bits, or the portion thereof, is correct.

[0051] Figure 3 An example of a process flow 300 that supports memory error correction based on hierarchical error detection in accordance with examples disclosed herein is described. In some examples, process flow 300 can be implemented by one or more aspects of a memory device 205-a, a controller 210-a, and / or a host system 215-a. Figure 1 For example, memory device 205-a can be an example of aspects of memory device 205 described with reference to FIG. 1, memory device 130 described with reference to FIG. 2, or one or more aspects of memory device 205 described with reference to FIG. 3. Figure 2 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 1 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 2 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 1 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 2 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 1 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. Figure 1 For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3. For example, controller 210-a can be an example of aspects of controller 210 described with reference to FIG. 1, controller 210 described with reference to FIG. 2, or one or more aspects of memory system controller 115 described with reference to FIG. 3.

[0052] In some instances, memory device 205-a may be an example of a NAND memory device (e.g., a memory device comprising one or more NAND memory arrays configured to store data from controller 210-a and retrieve data for controller 210-a), and controller 210-a may be a controller for memory device 205-a comprising local memory (e.g., controller 210-a comprising SRAM memory cells configured to store such data before sending data from memory device 205-a to host system 215-a).

[0053] In some instances, prior to execution process flow 300, controller 210-a may receive a write command and a set of associated bits from host system 215-a. In some instances, controller 210-a may send a set of bits to memory device 205-a, and memory device 205-a may store the set of bits in a memory array (e.g., a NAND memory array). In some instances, memory device 205-a may also store a second type of error detection code (e.g., a CRC code) for the set of bits (e.g., within the same page of the memory array or as metadata for the set of bits). For example, memory device 205-a may generate a second type of error detection code after receiving a set of bits from controller 210-a, or controller 210-a may generate a second type of error detection code and send it to memory device 205-a.

[0054] When a set of bits and associated second-type error detection codes are stored in memory device 205-a, controller 210-a may receive a read command for the set of bits from host system 215-a. In response to the read command, controller 210-a may request a set of bits from memory device 205-a, and memory device 205-a may retrieve the set of bits and transmit the set of bits to controller 210-a.

[0055] In some cases, memory device 205-a may allow a set of bits to be transferred to controller 210-a as one or more subsets. For example, such as Figure 3 As shown in the example, memory device 205-a can transfer a first subset of a set of bits to controller 210-a at 305, and memory device 205-a can transfer a second subset of a set of bits to controller 210-a at 310. It should be understood that a set of bits described herein can include any number of subsets of the bits described herein, and therefore any number of subsets of bits can be transferred from memory device 205-a to controller 210-a, although... Figure 3two subsets are illustrated. Further, it should be understood that for error detection, a set of bits can be operated on by the controller 210-a to include different subsets, whether or not the set of bits is transmitted by the memory device 205-a as the same subset.

[0056] At 312, the memory device 205-a can transmit one or more parity bits associated with a second type of error detection procedure (e.g., a CRC code for a CRC procedure) to the controller 210-a. For example, the memory device 205-a can transmit a second type of error detection code previously stored by the memory device 205-a in association with the set of bits. Although shown as being transmitted prior to 315, the memory device 205-a can transmit the one or more parity bits at some other time (e.g., after 315), for example, in response to a request from the controller 210-a, which can be based on the controller 210-a detecting an error at 315. Figure 3

[0057] At 315, it can be determined based on the first type of error detection procedure that N bits within the first subset of bits are incorrect, but the erroneous bits cannot be corrected using only the first type of error detection procedure (e.g., two-bit errors can be detected using a SECDED procedure). As noted elsewhere, the bits in the first subset of bits can have become incorrect (e.g., can be decoded to have error values) due to one or more transmission errors associated with exchanging the set of bits between the memory device 205-a and the controller 210-a, one or more storage errors associated with storing data at the memory device 205-a or the controller 210-a for some duration of time, or any combination thereof.

[0058] At 320, the N bits can be updated based on the second type of error detection procedure. For example, the controller 210-a can update the N bits. In some examples, the controller 210-a updating the N can include the controller 210-a generating one or more sets of candidate bits, where each of the one or more sets of candidate bits is generated based on altering a group of respective Ns within the first set of bits. Each of the sets of candidate bits can also include the second subset of bits or any other bits within the set of bits corresponding to the parity bits received at 312.

[0059] Additionally, the controller 210-a updating the N bits can include the controller 210-a evaluating the one or more sets of candidate bits using the second type of error detection procedure (e.g., using the second type of error detection code received from the memory device 205-a) until a set of candidate bits is identified as being error-free, updating (e.g., correcting) the first subset of bits to include corresponding bits in the set of candidate bits identified as being error-free.

[0060] ​In some examples, the first type of error detection procedure can be based on a first type of error detection code, and the second type of error detection procedure can be based on a second type of error detection code different from the first type of error detection code. The first subset of bits can be associated with a first error detection code of the first type, and the second subset of bits can be associated with a second error detection code of the first type. Additionally or alternatively, a group of bits and a second group of bits can each be associated with a same error detection code of the second type.

[0061] At 325, after updating the N bits, each bit in the updated first subset of bits can be verified as correct using the first type of error detection procedure. For example, the controller 210-a can verify each bit in the updated first subset of bits as correct. In some examples, the controller 210-a can perform the first type of error detection procedure (e.g., a SECDED procedure) on each subset of updated bits or at least on the subset in which an error was previously identified at 315.

[0062] At 330, the updated first subset of bits or a group of updated bits including the updated first subset can be transmitted. For example, the controller 210-a can transmit the updated first subset of bits or a group of updated bits including the updated first subset to the host system 215-a. In some examples, the controller 210-a can transmit the updated first subset of bits in response to (e.g., depending on) verifying each bit in the updated first subset of bits as correct after updating the N bits at 325.

[0063] The techniques described herein can be associated with one or more advantages. For example, by performing a second type of error detection procedure after a first type of error detection procedure, the controller 210-a is able to correct errors affecting a greater number of bits than can be corrected using only the first type of error detection procedure. For example, the controller 210-a is able to correct up to double-bit errors when using SECDED by supplementing the SECDED scheme with the CRC-based error detection scheme described herein. Thus, by using the layered error detection scheme described herein, error correction capability and thus reliability of the system can be improved relative to using only an error detection scheme (e.g., a time-to-failure (FIT) rate can be reduced). Additionally, latency associated with various reset procedures can also be avoided, among other possible benefits.

[0064] Figure 4 A block diagram 400 showing a memory system 405 supporting layered error detection based memory error correction in accordance with examples disclosed herein is shown. The memory system 405 can be the memory system 405 described with reference to FIG. 1. The memory system 405 can include a controller 410 and a memory array 415. The controller 410 can include a first error detection module 420 and a second error detection module 425. The first error detection module 420 can be configured to perform a first type of error detection procedure (e.g., a SECDED procedure) on a group of bits. The second error detection module 425 can be configured to perform a second type of error detection procedure (e.g., a CRC procedure) on the group of bits. The first error detection module 420 and the second error detection module 425 can be implemented in hardware, software, or a combination of hardware and software. Figures 1-3Examples of aspects of the described memory system. The memory system 405, or various components thereof, can be examples of means for various aspects of performing memory error correction based on hierarchical error detection, as described herein. For example, the memory system 405 can include a receiving component 410, an error detection component 415, a bit updating component 420, a transmitting component 425, or any combination thereof. Each of these components can be in communication, directly or indirectly, with one another (e.g., via one or more buses).

[0065] The receiving component 410 can be configured as or otherwise support means for receiving a set of bits from a memory array. The error detection component 415 can be configured as or otherwise support means for identifying that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits (e.g., operable to detect (e.g., capable of detecting) up to a quantity of bit errors, where the quantity is greater than or equal to 2). The bit updating component 420 can be configured as or otherwise support means for updating the at least two bits in the set of bits based at least in part on a second type of error detection procedure. The transmitting component 425 can be configured as or otherwise support means for transmitting the set of updated bits to a host device.

[0066] In some examples, the first type of error detection procedure can be based at least in part on a first type of error detection code. In some examples, the second type of error detection procedure can be based at least in part on a second type of error detection code different from the first type. In some examples, the receiving component 410 can be configured as or otherwise support means for receiving a second set of bits, where the set of bits is associated with a first error detection code of the first type, the second set of bits is associated with a second error detection code of the first type, and the set of bits and the second set of bits are each associated with a same error detection code of the second type.

[0067] In some examples, to support updating the at least two bits in the set of bits, the bit updating component 420 can be configured as or otherwise support means for generating one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits. In some examples, to support updating the at least two bits in the set of bits, the bit updating component 420 can be further configured as or otherwise support means for evaluating each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as being error-free, where the set of updated bits includes the set of candidate bits identified as being error-free.

[0068] In some examples, the error detection component 415 can be configured as or otherwise support a means for verifying each bit in the set of updated bits is correct after updating at least two bits and based at least in part on the first type of error detection procedure, where transmitting the set of updated bits to the host device is based at least in part on verifying each bit in the set of updated bits is correct.

[0069] In some examples, the receiving component 410 can be configured as or otherwise support a means for receiving, from the memory array, one or more parity bits associated with the second type of error detection procedure, where updating at least two bits is based at least in part on the one or more parity bits.

[0070] In some examples, the first type of error detection procedure can be based at least in part on a SECDED code. In some examples, the second type of error detection procedure can be based at least in part on a CRC code.

[0071] In some examples, the memory array can be a NAND memory array configured to store a set of bits.

[0072] In some examples, the set of bits can be received at an SRAM memory cell, where identifying that at least two bits in the set of bits are incorrect and updating the at least two bits in the set of bits occurs after the set of bits is received at the SRAM memory cell.

[0073] Figure 5 A flow diagram illustrating a method 500 that supports memory error correction based on hierarchical error detection in accordance with examples as disclosed herein is shown. The operations of method 500 can be implemented by a memory system or its components as described herein. For example, the operations of method 500 can be performed by a memory system as described with reference to Figs. 1-4 and 6-7. Figures 1-4 In some examples, a memory system can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, a memory system can perform aspects of the described functions using special-purpose hardware.

[0074] At 505, the method can include receiving a set of bits from a memory array. Operation 505 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 505 can be performed by a receiving component 410 as described with reference to Figs. 1-4 and 6-7. Figure 4 In some examples, aspects of operation 510 can be performed by an error detection component 415 as described with reference to Figs. 1-4 and 6-7.

[0075] At 510, the method can include identifying that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits. Operation 510 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 510 can be performed by an error detection component 415 as described with reference to Figs. 1-4 and 6-7. Figure 4 In some examples, aspects of operation 510 can be performed by an error detection component 415 as described with reference to Figs. 1-4 and 6-7.

[0076] At 515, the method can include updating at least two bits of a set of bits based at least in part on a second type of error detection procedure. Operation 515 can be performed according to examples as disclosed herein. In some examples, aspects of the operation 515 can be performed by a updating component 420 as described with reference to Figure 4 The updating component 420 described is executed.

[0077] At 520, the method can include transmitting the set of updated bits to a host device. Operation 520 can be performed according to examples as disclosed herein. In some examples, aspects of the operation 520 can be performed by a transmitting component 425 as described with reference to Figure 4 The transmitting component 425 described is executed.

[0078] In some examples, apparatuses described herein can perform one or more methods, such as the method 500. An apparatus can include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a set of bits from a memory array, identifying that at least two bits of the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits, updating the at least two bits of the set of bits based at least in part on a second type of error detection procedure, and transmitting the set of updated bits to a host device.

[0079] In some examples of the method 500 and apparatuses described herein, the first type of error detection procedure can be based at least in part on a first type of error detection code, the second type of error detection procedure can be based at least in part on a second type of error detection code different from the first type, and the apparatus can include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a second set of bits, where the set of bits can be associated with a first error detection code of the first type, the second set of bits can be associated with a second error detection code of the first type, and the set of bits and the second set of bits can each be associated with a same error detection code of the second type.

[0080] In some examples of the method 500 and apparatuses described herein, the operation, feature, circuitry, logic, means, or instructions for updating at least two bits of a set of bits can include operations, features, circuitry, logic, means, or instructions for generating one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits, and evaluating each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as error-free, where the set of updated bits includes the set of candidate bits identified as error-free.

[0081] Some examples of the method 500 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, from the memory array, one or more parity bits associated with the second type of error detection procedure, where updating the at least two bits can be based at least in part on the one or more parity bits.

[0082] Some examples of the method 500 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, from the memory array, one or more parity bits associated with the second type of error detection procedure, where updating the at least two bits can be based at least in part on the one or more parity bits.

[0083] In some examples of the method 500 and the apparatus described herein, the first type of error detection procedure can be based at least in part on a SECDED code and the second type of error detection procedure can be based at least in part on a CRC code.

[0084] In some examples of the method 500 and the apparatus described herein, the memory array can be a NAND memory array configured to store a set of bits.

[0085] In some examples of the method 500 and the apparatus described herein, the set of bits can be received at a SRAM memory cell, where identifying that at least two bits of the set of bits are incorrect and updating the at least two bits of the set of bits occurs after the set of bits is received at the SRAM memory cell.

[0086] Figure 6 A flow diagram illustrating a method 600 of supporting memory error correction based on hierarchical error detection is shown in accordance with examples as disclosed herein. The operations of method 600 can be implemented by a memory system or its components as described herein. For example, the operations of method 600 can be performed by a memory system as described with reference to FIGS. 1-4 and 6-7, in accordance with examples as disclosed herein. Additionally or alternatively, some of the operations of method 600 can be performed by the receiving component 410 described with reference to FIG. 4, in accordance with examples as disclosed herein. Figures 1-4 The memory system described is configured to perform the operations of method 600. In some examples, the memory system can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special-purpose hardware.

[0087] At 605, the method can include receiving a set of bits from a memory array. The operation 605 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 605 can be performed by the receiving component 410 described with reference to FIG. 4. Figure 4 The receiving component 410 described is configured to perform the operation 605. In some examples, the receiving component 410 can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the receiving component 410 can perform aspects of the described functions using special-purpose hardware.

[0088] At 610, the method can include identifying that at least two bits in a set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits. Operation 610 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 610 can be performed by an error detection component 415 as described with reference to Figure 4 At 610, the method can include identifying that at least two bits in a set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits. Operation 610 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 610 can be performed by an error detection component 415 as described with reference to

[0089] At 615, the method can include generating one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits. Operation 615 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 615 can be performed by a bit update component 420 as described with reference to Figure 4

[0090] At 620, the method can include evaluating each of the one or more sets of candidate bits using a second type of error detection procedure until a set of candidate bits is identified as being free of errors. Operation 620 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 620 can be performed by a bit update component 420 as described with reference to Figure 4

[0091] At 625, the method can include transmitting a set of updated bits to a host device, wherein the set of updated bits includes the set of candidate bits identified as being free of errors. Operation 625 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 625 can be performed by a transmission component 425 as described with reference to Figure 4

[0092] It should be noted that the foregoing method descriptions are possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0093] An apparatus is described. The apparatus can include a memory array and a controller coupled with the memory array. The controller can be configured to cause the apparatus to receive a set of bits from the memory array, identify that at least two bits in the set of bits are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits, update the at least two bits in the set of bits based at least in part on a second type of error detection procedure, and transmit the set of updated bits to a host device.

[0094] ​​​In some examples of the apparatus, the first type of error detection procedure can be based at least in part on a first type of error detection code, the second type of error detection procedure can be based at least in part on a second type of error detection code different from the first type of error detection code, and the controller can be further configured to cause the apparatus to receive a second set of bits, wherein the set of bits can be associated with a first error detection code of the first type, the second set of bits can be associated with a second error detection code of the first type, and the set of bits and the second set of bits can each be associated with a same error detection code of the second type.

[0095] In some examples of the apparatus, to update the at least two bits of the set of bits, the controller can be configured to cause the apparatus to: generate one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits; and evaluate each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as being free of error, wherein the set of updated bits includes the set of candidate bits identified as being free of error.

[0096] In some examples of the apparatus, the controller can be further configured to verify each bit of the set of updated bits is correct after updating the at least two bits and based at least in part on the first type of error detection procedure, wherein transmitting the set of updated bits to the host device can be based at least in part on verifying each bit of the set of updated bits is correct.

[0097] In some examples of the apparatus, the controller can be further configured to receive one or more parity bits associated with the second type of error detection procedure from the memory array, wherein updating the at least two bits can be based at least in part on the one or more parity bits.

[0098] In some examples of the apparatus, the first type of error detection procedure can be based at least in part on a SECDED code, and the second type of error detection procedure can be based at least in part on a CRC code.

[0099] In some examples of the apparatus, the memory array includes a NAND memory array configured to store the set of bits.

[0100] In some examples of the apparatus, the apparatus further includes a static random (SRAM) memory unit configured to receive the set of bits, wherein the controller can be configured to cause the apparatus to identify that the at least two bits of the set of bits are incorrect and update the at least two bits of the set of bits after the set of bits is received at the SRAM memory unit.

[0101] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where buses can have a variety of bit widths.

[0102] The terms "if' and "when," "based on," "based at least in part on," and "in response to" can be interchangeable.

[0103] The terms "electronic communication," "electrically conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components can be considered to be in electronic communication (or electrically conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication (or electrically conductive contact or connected or coupled) with each other can be an open or closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components (such as switches, transistors, or other components). In some examples, the flow of signals between connected components can be interrupted, such as using one or more intervening components (such as switches or transistors), for a time.

[0104] The term "coupled" refers to the condition of moving from an open relationship between components, in which signals cannot currently pass between the components through a conductive path, to a closed relationship between the components, in which signals can pass between the components through a conductive path. If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not permit the flow of signals.

[0105] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. If there is an open circuit between components, the components are isolated from each other. For example, if a switch positioned between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller effects a change that prevents signals from flowing between the components using a conductive path through which signals previously flowed.

[0106] The devices (including memory arrays) discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during initial formation or growth of the substrate, or by any other doping method.

[0107] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" if a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "turned off" or "deactivated" if a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0108] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0109] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference number designating the component name, and a second reference number identifying the specific instance of the component among the set of like components. If only the first reference number is used in the specification, the detail specification can refer to any one of the set of like components.

[0110] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, changes to the

[0111] For example, various illustrative blocks and components described in connection with the disclosure can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0112] As used herein, including in the claims, "or" as used in a list of items prefaced by "at least one of" or "one or more of" indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0113] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0114] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory array; and a controller coupled with the memory array and configured to cause the memory device to: receive a set of bits from the memory array; identify that at least two bits in the set of bits from the memory array are incorrect based at least in part on a first type of error detection procedure operable to detect that at least two bit errors associated with the set of bits from the memory array; update the at least two bits in the set of bits from the memory array based at least in part on a second type of error detection procedure; and transmit the set of updated bits to a host device.

2. The memory device of claim 1, wherein: the first type of error detection procedure is based at least in part on a first type of error detection code; the second type of error detection procedure is based at least in part on a second type of error detection code different than the first type of error detection code; and the controller is further configured to cause the memory device to receive a second set of bits, wherein: the set of bits is associated with a first error detection code of the first type; the second set of bits is associated with a second error detection code of the first type; and the set of bits and the second set of bits are each associated with a same error detection code of the second type.

3. The memory device of claim 1, wherein to update the at least two bits in the set of bits, the controller is configured to cause the memory device to: generate one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits; and evaluate each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as error-free, wherein the set of updated bits comprises the set of candidate bits identified as error-free.

4. The memory device of claim 1, wherein the controller is further configured to: after updating the at least two bits in the set of bits and based at least in part on the first type of error detection procedure, verify that each bit in the set of updated bits is identified as error-free, wherein transmitting the set of updated bits to the host device is based at least in part on verifying that each bit in the set of updated bits is identified as error-free.

5. The memory device of claim 1, wherein the controller is further configured to: receive one or more parity bits associated with the second type of error detection procedure from the memory array, wherein updating the at least two bits is based at least in part on the one or more parity bits.

6. The memory device of claim 1, wherein: the first type of error detection procedure is based at least in part on a single error correction and double error detection (SEDED) code; and the second type of error detection procedure is based at least in part on a cyclic redundancy check (CRC) code.

7. The memory device of claim 1, wherein the memory array comprises a not-and (NAND) memory array.

8. The memory device of claim 1, wherein the memory device further comprises: a static random access memory (SRAM) memory cell configured to receive the set of bits from the memory array, wherein the controller is configured to cause the memory device to identify that the at least two bits in the set of bits are incorrect and update the at least two bits in the set of bits after the set of bits are received at the SRAM memory cell.

9. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a set of bits from a memory array; identify that at least two bits in the set of bits from the memory array are incorrect based at least in part on a first type of error detection procedure operable to detect at least two bit errors associated with the set of bits from the memory array; update the at least two bits in the set of bits from the memory array based at least in part on a second type of error detection procedure; and transmit the set of updated bits to a host device.

10. The non-transitory computer-readable medium of claim 9, wherein: the first type of error detection procedure is based at least in part on a first type of error detection code; the second type of error detection procedure is based at least in part on a second type of error detection code different than the first type; and the instructions, when executed by the processor of the electronic device, further cause the electronic device to receive a second set of bits, wherein: the set of bits is associated with a first error detection code of the first type; the second set of bits is associated with a second error detection code of the first type; and the set of bits and the second set of bits are each associated with a same error detection code of the second type.

11. The non-transitory computer-readable medium of claim 9, wherein to update the at least two bits in the set of bits, the instructions, when executed by the processor of the electronic device, cause the electronic device to: generate one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits; and evaluate each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as error free, wherein the set of updated bits comprises the set of candidate bits identified as error free.

12. The non-transitory computer-readable medium of claim 9, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: after updating the at least two bits in the set of bits and based at least in part on the first type of error detection procedure, verify that each bit in the set of updated bits is identified as error free, wherein transmitting the set of updated bits to the host device is based at least in part on verifying that each bit in the set of updated bits is identified as error free.

13. The non-transitory computer-readable medium of claim 9, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive, from the memory array, one or more parity bits associated with the second type of error detection procedure, wherein updating the at least two bits in the set of bits is based at least in part on the one or more parity bits.

14. The non-transitory computer-readable medium of claim 9, wherein: the first type of error detection procedure is based at least in part on a single error correction and double error detection (SEDED) code; and the second type of error detection procedure is based at least in part on a cyclic redundancy check (CRC) code.

15. A method performed by a memory system, the method comprising: receiving a set of bits from a memory array; identifying that at least two bits in the set of bits from the memory array are incorrect based at least in part on a first type of error detection procedure operable to detect to at least two bit errors associated with the set of bits from the memory array; updating the at least two bits in the set of bits based at least in part on a second type of error detection procedure; and transmitting the set of updated bits to a host device.

16. The method of claim 15, wherein: the first type of error detection procedure is based at least in part on a first type of error detection code; the second type of error detection procedure is based at least in part on a second type of error detection code different than the first type; and the method further comprises receiving a second set of bits, wherein: the set of bits is associated with a first error detection code of the first type; the second set of bits is associated with a second error detection code of the first type; and the set of bits and the second set of bits are each associated with a same error detection code of the second type.

17. The method of claim 15, wherein updating the at least two bits in the set of bits comprises: generating one or more sets of candidate bits, each of the one or more sets of candidate bits based at least in part on altering a respective two bits within the set of bits; and evaluating each of the one or more sets of candidate bits using the second type of error detection procedure until a set of candidate bits is identified as being free of error, wherein the set of updated bits comprises the set of candidate bits identified as being free of error.

18. The method of claim 15, further comprising: after updating the at least two bits in the set of bits and based at least in part on the first type of error detection procedure, verifying that each bit in the set of updated bits is identified as being free of error, wherein transmitting the set of updated bits to the host device is based at least in part on verifying that each bit in the set of updated bits is identified as being free of error.

19. The method of claim 15, further comprising: receiving, from the memory array, one or more parity bits associated with the second type of error detection procedure, wherein updating the at least two bits in the set of bits is based at least in part on the one or more parity bits.

20. The method of claim 15, wherein: the first type of error detection procedure is based at least in part on a single error correction and double error detection (SEDED) code; and the second type of error detection procedure is based at least in part on a cyclic redundancy check (CRC) code.

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