Contact hole forming method for semiconductor device, semiconductor device

Abstract

The application discloses a contact hole forming method of a semiconductor device and the semiconductor device, and relates to the technical field of semiconductor devices. The method comprises the following steps: forming a first barrier layer covering a first dielectric layer, the first dielectric layer being provided with a landing pad and an electrode; performing partial etching on the first barrier layer to form an etching barrier pattern at a position corresponding to the electrode; sequentially forming a plurality of second barrier layers separated by a second dielectric layer on the etching barrier pattern and the first barrier layer; performing etching on the second barrier layers, the second dielectric layer and the first barrier layer to form a capacitor at a position corresponding to the landing pad; backfilling the second dielectric layer until the capacitor is covered; and performing inclined etching on the backfilled second dielectric layer to form a contact hole in contact with the electrode, the shape of the contact hole located at the upper part of the etching barrier pattern being conical. Due to the effect of the etching barrier pattern, the etching located at the lower part of the etching barrier pattern is equivalent to vertical etching, and the problem that the bottom cannot be etched open does not occur, so that the size of the contact hole can be made smaller.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a method for forming contact holes in a semiconductor device and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing processes, as chip integration increases, the number of stacked film layers in the chip becomes higher and higher, which makes the process of creating contact holes with high aspect ratios more difficult.

[0003] Currently, in order to make the size of the contact hole smaller, the etching process of the contact hole usually uses a tilted etching technique to reduce the size of the contact hole. The contact hole shape obtained by this etching process is a cone shape, that is, the top of the contact hole is large and the bottom is small. This will cause the bottom of the contact hole to be unable to be etched, which will result in the bottom not being able to make contact with the word line or bit line below. Summary of the Invention

[0004] The purpose of this application is to provide a method for forming contact holes in a semiconductor device and a semiconductor device in order to address the shortcomings of the prior art. This purpose is achieved through the following technical solutions.

[0005] The first aspect of this application discloses a method for forming contact holes in a semiconductor device, the method comprising:

[0006] A first barrier layer is formed to cover the first dielectric layer, and landing pads and electrodes are formed within the first dielectric layer;

[0007] The first barrier layer is partially etched to form an etch barrier pattern at the corresponding position of the electrode;

[0008] Multiple layers of second barrier layers separated by a second dielectric layer are sequentially formed on the etched barrier pattern and the remaining first barrier layer, and the second barrier layer, the second dielectric layer and the first barrier layer are etched to form a capacitor electrically connected to the landing pad at the corresponding position of the landing pad.

[0009] The second dielectric layer is backfilled until it completely covers the capacitor. The backfilled second dielectric layer is then obliquely etched to form contact holes that contact the electrodes.

[0010] In the contact hole, the upper part of the etched barrier pattern is conical, and the lower part of the etched barrier pattern is square.

[0011] A second aspect of this application provides a semiconductor device comprising:

[0012] The dielectric layer includes a unit region and a core region;

[0013] The unit area includes a landing pad and a capacitor, and the landing pad is electrically connected to the capacitor;

[0014] The core area includes electrodes, contact holes, and an etched barrier pattern surrounding the contact holes;

[0015] The contact hole located in the upper part of the etch barrier pattern is conical in shape, and the contact hole located in the lower part of the etch barrier pattern is square in shape. The contact hole located in the lower part of the etch barrier pattern is in contact with the electrode.

[0016] A third aspect of this application provides an electronic device comprising the semiconductor device described in the second aspect above.

[0017] Based on the contact hole formation method and semiconductor device of the semiconductor device described in the first and second aspects above, this application has the following beneficial effects:

[0018] Before forming the contact hole, an etching barrier pattern is pre-formed between the upper contact hole position and the lower bit line. During the inclined etching process to form the contact hole, the contact hole shape above the etching barrier pattern remains conical. However, due to the effect of the etching barrier pattern, the etching below the etching barrier pattern is equivalent to vertical etching. Therefore, the contact hole shape below the etching barrier pattern becomes square. Vertical etching does not have the problem of not being able to etch the bottom, which allows the contact hole size to be made smaller. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0020] Figures 1-5 This is a schematic diagram of the contact hole formation process in a semiconductor device in the prior art;

[0021] Figure 6 This is a flowchart illustrating an embodiment of a method for forming a contact hole in a semiconductor device according to an exemplary embodiment of this application;

[0022] Figures 7-15 For the purposes of this application Figure 6 The illustrated embodiment is a schematic diagram of the contact hole formation process for a semiconductor device.

[0023] Figure 16 This is a schematic diagram comparing the shape of the contact hole formed by the prior art with the shape of the contact hole formed in this application. Detailed Implementation

[0024] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0025] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0026] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0027] See Figures 1 to 5 The existing process for forming contact holes in semiconductor devices includes the following steps:

[0028] Step 1: Form bit lines 2 and landing pads 3 in dielectric layer 1, such as... Figure 1 As shown;

[0029] Step 2: Form a barrier layer 4 of a certain thickness on the surface of dielectric layer 1, such as... Figure 2 As shown;

[0030] Step 3: Dielectric layer 51, barrier layer 6, dielectric layer 52, and barrier layer 7 are sequentially formed on the surface of barrier layer 4, as follows: Figure 3 As shown;

[0031] Step 4: Etch barrier layer 4, dielectric layer 51, barrier layer 6, dielectric layer 52, and barrier layer 7 to form capacitor 31 electrically connected to landing pad 3. Then backfill dielectric layer 53 until capacitor 31 is completely covered. A pattern transfer layer 8 and photoresist layer 9 are sequentially formed on the surface of dielectric layer 53, and a photoresist opening 91 is made at the corresponding position of bit line 2. Figure 4 As shown;

[0032] Step 5: Perform inclined etching on the bottom of the photoresist opening 91 until the bit line 2 is exposed, forming a contact hole 21 that contacts the bit line 2. Then remove the remaining pattern transfer layer 8 and photoresist layer 9. Figure 5 As shown.

[0033] From the above Figure 5 The contact hole 21 shown is cone-shaped, meaning that the top of the contact hole 21 is large and the bottom is small. This results in insufficient exposure energy at the bottom of the contact hole 21, which in turn prevents the bottom from opening and making contact with the bit line 2 below.

[0034] To address the aforementioned technical problems, this application proposes an improved method for forming contact holes in semiconductor devices. Before forming the contact hole, an etch barrier pattern is pre-formed between the upper contact hole position and the lower bit line. Thus, during the inclined etching process to form the contact hole, the contact hole shape above the etch barrier pattern remains conical. However, due to the effect of the etch barrier pattern, the etching below the etch barrier pattern is essentially vertical etching. Therefore, the contact hole shape below the etch barrier pattern becomes square. Vertical etching does not result in incomplete etching, thereby allowing the contact hole to be made smaller.

[0035] The method for forming contact holes in semiconductor devices proposed in this application will be described in detail below with specific embodiments.

[0036] Figure 6 This is a flowchart illustrating an embodiment of a contact hole formation method for a semiconductor device according to an exemplary embodiment of this application, as shown below. Figure 6 As shown, the method for forming contact holes in this semiconductor device includes the following steps:

[0037] Step 601: Form a first barrier layer covering the first dielectric layer, wherein landing pads and electrodes are formed within the first dielectric layer.

[0038] In step 601, a first dielectric layer 101 is provided, in which landing pads 30 and electrodes 20 are formed, such as Figure 7 As shown, a first barrier layer 401 is then formed covering the first dielectric layer 101, as follows. Figure 8 As shown.

[0039] In this process, the landing pad 30 in the first dielectric layer 101 is located in the cell region of the semiconductor device, and the electrode 20 is located in the core region of the semiconductor device. The landing pad 30 is used to electrically connect with the capacitor subsequently formed, and the electrode 20 is used to contact the contact hole subsequently formed.

[0040] In some embodiments, the electrode 20 in the semiconductor device may include a bit line or a word line. Of course, there are usually multiple electrodes 20 in the semiconductor device. Only one electrode 20 is shown in the figure as an example.

[0041] Similarly, there are usually multiple landing pads in the unit area; only two landing pads 30 are shown in the figure as an example.

[0042] It should be noted that, since this application utilizes a first barrier layer 401 to create the etching barrier pattern for the contact hole, in this embodiment, the thickness of the first barrier layer 401 formed during its formation is greater than that of the barrier layer formed in the prior art (e.g., ...). Figure 2 The thickness (as shown) should be 2 to 3 times thicker.

[0043] Step 602: Partially etch the first barrier layer to form an etch barrier pattern at the corresponding position of the electrode.

[0044] For step 602, a photoresist opening 50 can be formed at the corresponding position of the electrode 20 on the first barrier layer 401, such as... Figure 9 As shown, the first barrier layer 401, which is not covered by photoresist, is then thinned and etched, as follows: Figure 10 As shown, after removing the photoresist, an etching barrier pattern 501 is formed at the corresponding position on the electrode 20, such as... Figure 11 As shown.

[0045] In the process of forming the photoresist opening 50, a photoresist layer can be spin-coated on the surface of the first barrier layer 401, and the photoresist layer can be exposed and developed using a mask to obtain the photoresist opening 50.

[0046] It is worth noting that the size of the photoresist opening 50 will affect the size of the bottom of the contact hole formed subsequently. In order to ensure that the bottom of the contact hole is in complete contact with the electrode 20, the size of the photoresist opening 50 is smaller than the size of the electrode 20, and the center position of the photoresist opening 50 and the center position of the electrode 20 are on the same vertical line perpendicular to the semiconductor substrate surface.

[0047] Furthermore, the first barrier layer 401 not covered by photoresist is thinned and etched until the thickness of the first barrier layer 401 becomes the thickness required for forming a barrier layer in the prior art (e.g., Figure 2 When the thickness (as shown) is reached, the etching is stopped. At this point, the unthinned portion covered by photoresist is the etching barrier pattern 501.

[0048] In other words, the etching barrier pattern 501 is formed from a portion of the first barrier layer 401, and the etching barrier pattern can be formed without changing the existing manufacturing process, thus having the advantage of being easy to implement.

[0049] It should be noted that since the etch barrier pattern 501 is obtained by transferring the pattern from the photoresist opening 50, the center position of the etch barrier pattern 501 and the center position of the electrode 20 are also on the same vertical line perpendicular to the semiconductor substrate surface.

[0050] Step 603: Form multiple layers of second barrier layers separated by a second dielectric layer sequentially on the etched barrier pattern and the remaining first barrier layer.

[0051] In this embodiment, before forming the capacitor, multiple barrier layers separated by dielectric layers are formed, and then an elongated capacitor is etched to ensure that the capacitor does not deform.

[0052] Taking the formation of two second barrier layers as an example, a second dielectric layer 102, a second barrier layer 402, a second dielectric layer 103, and a second barrier layer 403 are sequentially formed on the etched barrier pattern and the remaining first barrier layer, as follows: Figure 12 As shown.

[0053] Since the second barrier layer 403 is located on the top layer, in order to better ensure that the capacitor does not deform, the thickness of the second barrier layer 403 is usually thicker than that of the second barrier layer 402.

[0054] In some embodiments, the first barrier layer 401 and the second barrier layers 402 and 403 may all be made of silicon nitride (SiN).

[0055] The materials of the first dielectric layer 101, the second dielectric layer 102, and 103 can all be oxides, such as silicon oxide (SiO) or silicon dioxide (SiO2).

[0056] Step 604: Etch the second barrier layer, the second dielectric layer and the first barrier layer to form a capacitor electrically connected to the landing pad at the corresponding position of the landing pad.

[0057] In step 604, the photolithography and etching areas differ between the unit region and the core region. In the unit region, capacitor holes are etched at the locations of the landing pads 30 and connected to them, and then a capacitor 60 electrically connected to the landing pads 30 is deposited. However, in the core region, the two second barrier layers 402 and 403, the two second dielectric layers 102 and 103, and the first barrier layer 401 are also etched away during the etching of the capacitor holes. Figure 13 As shown.

[0058] Step 605: Backfill the second dielectric layer until it completely covers the capacitor, and then perform tilt etching on the backfilled second dielectric layer to form contact holes that contact the electrodes.

[0059] In some embodiments, for the backfilling process of the second dielectric layer 103, after the second dielectric layer 103 is backfilled to completely cover the capacitor, the backfilled second dielectric layer 103 can also be planarized for subsequent deposition of a pattern transfer layer and photoresist on the surface of the backfilled second dielectric layer 103.

[0060] The planarization process can be achieved using CMP (chemical mechanical planarization).

[0061] In some embodiments, after backfilling the second dielectric layer 103, because the etching depth of the contact hole is relatively deep, photoresist alone is usually insufficient to cover the areas that do not want to be etched. Therefore, a pattern transfer layer 70 is first formed on the surface of the backfilled second dielectric layer 103, and then a photoresist layer 80 is spin-coated, forming a contact hole opening 801 (i.e., a photoresist opening) at the corresponding position of the electrode 20. Figure 14 As shown, the bottom of the contact hole opening 801 is then obliquely etched until the electrode 20 is exposed, thereby forming the contact hole 201 that contacts the electrode 20. Finally, the pattern transfer layer 70 and the photoresist layer 80 are removed, as shown. Figure 15 As shown.

[0062] During the tilting etching process, when the etching reaches the position of the etching barrier pattern 501, the etching below the etching barrier pattern 501 becomes equivalent to vertical etching due to the effect of the etching barrier pattern 501. Therefore, the structure etched below the etching barrier pattern 501 becomes a quadrilateral shape instead of a cone shape etched at the tilt. Furthermore, the size of the contact hole 201 located in the lower part of the etching barrier pattern 501 is smaller than the size of the electrode 20.

[0063] Therefore, although both this application and the prior art use an inclined etching process to form the contact hole, in this application, due to the effect of the etching barrier pattern 501, the formed contact hole 201 is divided into two parts. The upper part of the etching barrier pattern 501 is conical, and the lower part of the etching barrier pattern 501 is square. Since vertical etching does not have the problem of insufficient exposure energy, the bottom of the contact hole 201 can be fully opened to contact the electrode 20 below.

[0064] See Figure 16As shown, Figure (a) shows a contact hole formed by a tilting etching process in the prior art. When viewed from above, the top of the contact hole is circular, and the bottom of the contact hole is also circular, except that the size of the bottom circle is smaller than that of the top circle. Figure (b) shows a contact hole formed by a tilting etching process in this application. When viewed from above, the top of the contact hole is circular, and the pattern on the upper surface of the etching barrier pattern is also circular, except that the size of the circle on the upper surface of the etching barrier pattern is smaller than that of the top circle of the contact hole, and the bottom of the contact hole becomes square.

[0065] It should be noted that the center position of the contact hole 201 should also be on the same vertical line as the center position of the etch barrier pattern 501, which is perpendicular to the surface of the first dielectric layer 101.

[0066] This completes the above. Figure 6 The process shown involves forming an etching barrier pattern between the upper contact hole position and the lower electrode before forming the contact hole. During the inclined etching process, the contact hole shape above the etching barrier pattern remains conical. However, due to the effect of the etching barrier pattern, the etching below the etching barrier pattern is essentially vertical etching. Therefore, the contact hole shape below the etching barrier pattern becomes square. Vertical etching does not have the problem of not being able to etch the bottom, which allows the contact hole to be made smaller.

[0067] This application also proposes a semiconductor device, said semiconductor device according to the above... Figure 6 The formation method shown is used to obtain it; see [link / reference]. Figure 15 As shown, the semiconductor device includes:

[0068] The dielectric layer includes a unit region and a core region. The unit region includes a landing pad 30 and a capacitor 60, and the landing pad 30 is electrically connected to the capacitor 60. The core region includes an electrode 20, a contact hole 201, and an etch barrier pattern 501 surrounding the contact hole 201.

[0069] The contact hole located in the upper part of the etch barrier pattern 501 is conical in shape, and the contact hole located in the lower part of the etch barrier pattern 501 is square in shape. The contact hole located in the lower part of the etch barrier pattern 501 is in contact with the electrode 20.

[0070] It should be noted that, based on the description of steps 601 to 605 above, the dielectric layer in this embodiment includes a first dielectric layer 101 and second dielectric layers 102 and 103.

[0071] Furthermore, the cell region of the semiconductor device also includes a first barrier layer 401 and second barrier layers 402 and 403 surrounding the capacitor 60.

[0072] This application also proposes an electronic device, which includes the features described above. Figure 15 The aforementioned semiconductor device.

[0073] For example, the semiconductor device can be any one of dynamic random access memory (DRAM), thyristor random access memory (TRAM), static random access memory (SRAM), and non-volatile memory (such as read-only memory, flash memory, ferroelectric random access memory, magnetoresistive random access memory, etc.).

[0074] In some embodiments, the electronic device may include a smartphone, computer, tablet, wearable smart device, artificial intelligence device, or power bank.

[0075] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0076] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A contact hole forming method of a semiconductor device, characterized by, The method comprises: forming a first barrier layer covering a first dielectric layer, the first dielectric layer having a landing pad and an electrode formed therein; partially etching the first barrier layer to form an etching barrier pattern at a position corresponding to the electrode; forming a plurality of second barrier layers separated by a second dielectric layer on the etching barrier pattern and the remaining first barrier layer in sequence, and etching the second barrier layers, the second dielectric layer, and the first barrier layer to form a capacitor electrically connected to the landing pad at a position corresponding to the landing pad; backfilling the second dielectric layer until the capacitor is completely covered, and performing inclined etching on the backfilled second dielectric layer to form a contact hole in contact with the electrode; wherein, in the contact hole, the upper part of the etching barrier pattern is conical in shape, and the lower part of the etching barrier pattern is square in shape; the partially etching the first barrier layer to form an etching barrier pattern at a position corresponding to the electrode comprises: forming a photoresist opening at a position corresponding to the electrode on the first barrier layer; and removing the photoresist after thinning etching the first barrier layer not covered by the photoresist to form an etching barrier pattern at a position corresponding to the electrode.

2. The method of claim 1, wherein, the inclined etching on the backfilled second dielectric layer to form a contact hole in contact with the electrode comprises: forming a contact hole opening at a position corresponding to the electrode on the surface of the backfilled second dielectric layer; performing inclined etching on the bottom of the contact hole opening until the electrode is exposed to form a contact hole in contact with the electrode.

3. The method of claim 1, wherein, the center of the etching barrier pattern and the center of the electrode are on the same vertical line perpendicular to the surface of the first dielectric layer.

4. The method of claim 1, wherein, the center of the etching barrier pattern and the center of the contact hole are on the same vertical line perpendicular to the surface of the first dielectric layer.

5. The method of claim 1, wherein, the material of the first barrier layer and the second barrier layer is silicon nitride.

6. The method of claim 1, wherein, the electrode comprises a word line or a bit line.

7. A semiconductor device, characterized by the semiconductor device is obtained by the method of any one of claims 1-6, and the semiconductor device comprises: a dielectric layer, the dielectric layer comprising a unit region and a core region; the unit region comprises a landing pad and a capacitor, and the landing pad is electrically connected to the capacitor; the core region comprises an electrode, a contact hole, and an etching barrier pattern surrounding the contact hole; wherein, the contact hole at the upper part of the etching barrier pattern is conical in shape, the contact hole at the lower part of the etching barrier pattern is square in shape, and the contact hole at the lower part of the etching barrier pattern is in contact with the electrode.

8. An electronic device, comprising: the semiconductor device of claim 7.

9. The electronic device of claim 8, wherein, the semiconductor device is included in a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, or a mobile power supply.

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