A carbon nanotube-based metal-oxide-semiconductor capacitor structure

Abstract

The present disclosure provides a carbon nanotube-based metal-oxide semiconductor capacitor structure, comprising: a substrate; a carbon nanotube film layer on the substrate; a bottom electrode metal layer partially on the carbon nanotube film layer and partially on the substrate; a metal oxide layer on the carbon nanotube film layer; and a top electrode metal layer on the metal oxide layer; wherein the carbon nanotube film layer and the top electrode metal layer are in a circular ring structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a metal oxide semiconductor capacitor structure based on carbon nanotubes. Background Technology

[0002] As transistor feature sizes shrink, limitations imposed by physical laws such as short-channel effects and drain-induced barrier reduction, along with manufacturing costs, have made it difficult for mainstream silicon-based CMOS technology to achieve significant breakthroughs at current technology nodes, severely hindering the continuation of Moore's Law. Therefore, researchers have begun exploring the possibility of using other materials as conductive channels. Currently, carbon-based nanoelectronics has received widespread attention, particularly field-effect transistors using carbon nanotubes as channel materials. These transistors possess advantages such as high mobility, near-ballistic transport, large current density, and good manufacturing process compatibility, making them potential replacements for traditional silicon-based devices.

[0003] The low-dimensional nature of carbon nanotubes dictates that their metal-oxide-semiconductor capacitors exhibit a lateral structure, rather than the vertical structure of traditional bulk materials. Therefore, the lateral resistance, which has a negligible impact in vertical structures, becomes non-negligible in carbon nanotube capacitors, increasing the difficulty of extracting dielectric and interface characteristics and significantly affecting the accuracy of the results. Carbon nanotubes are typically only a few micrometers long, while the length of the metal gate in existing capacitance testing structures is much greater than the length of a single carbon nanotube. Consequently, overlap occurs between the underlying carbon nanotubes, increasing the lateral resistance of the semiconductor material and introducing interface states at the cross-section of the carbon nanotubes.

[0004] In summary, there is an urgent need to design a novel carbon nanotube capacitor structure to effectively solve the problems of excessive lateral resistance and inaccurate interface states in existing structures. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a metal oxide semiconductor capacitor structure based on carbon nanotubes, which aims to solve the problems of excessive lateral resistance and inaccurate interface states in existing capacitor structures.

[0006] This disclosure provides a metal-oxide-semiconductor capacitor structure based on carbon nanotubes, comprising: a substrate; a carbon nanotube thin film layer located on the substrate; a bottom electrode metal layer, partly located on the carbon nanotube thin film layer and partly located on the substrate; a metal oxide layer located on the carbon nanotube thin film layer; and a top electrode metal layer located on the metal oxide layer; wherein the carbon nanotube thin film layer and the top electrode metal layer are ring structures.

[0007] Furthermore, the carbon nanotube thin film layer, the bottom electrode metal layer, the metal oxide layer, and the top electrode metal layer are concentric ring structures, wherein the bottom electrode metal layer is a ring structure with an opening.

[0008] Furthermore, the inner diameter of the top electrode metal layer is larger than the inner diameter of the carbon nanotube film layer; the outer diameter of the top electrode metal layer is smaller than the inner diameter of the bottom electrode metal layer; the inner diameter of the metal oxide layer is smaller than the inner diameter of the top electrode metal layer; and the outer diameter of the metal oxide layer is larger than the outer diameter of the top electrode metal layer.

[0009] Furthermore, multiple carbon nanotubes in the carbon nanotube film layer are distributed in a network or array.

[0010] Furthermore, the inner diameter of the carbon nanotube film layer is 5 nm to 1 mm, and its ring width is 5 nm to 20 μm.

[0011] Furthermore, the width of the overlapping portion between the bottom electrode metal layer and the carbon nanotube thin film layer is...

[0012] Furthermore, it also includes: a first electrode plate metal layer, located on the substrate or metal oxide layer, and one end of which is connected to the top electrode metal layer; and a second electrode plate metal layer, located on the substrate or metal oxide layer, and one end of which is connected to the bottom electrode metal layer.

[0013] Furthermore, the bottom electrode metal layer is one or more of palladium, titanium, gold, platinum, tungsten, nickel, copper, zinc, cadmium, or aluminum; the top electrode metal layer is one or more of titanium, gold, aluminum, platinum, tungsten, nickel, copper, zinc, or cadmium.

[0014] Furthermore, the metal oxide layer is one or more of aluminum-based, zirconium-based, hafnium-based, gadolinium-based, gallium-based, lanthanum-based, or tantalum-based oxides.

[0015] Furthermore, the substrate is a silicon substrate, quartz substrate, or sapphire substrate with a silicon dioxide layer of a pre-determined thickness.

[0016] This disclosure provides a metal-oxide-semiconductor (MOS) capacitor structure based on carbon nanotubes. The top electrode metal layer and the carbon nanotube thin film layer adopt a ring-shaped structure, allowing for a very narrow electrode width. The overlapping area between carbon nanotubes in the entire electrode-covered carbon nanotube thin film is very small, effectively reducing lateral resistance. It also minimizes the coverage area of ​​discontinuous regions between carbon nanotubes, thereby improving the accuracy of testing and extracting electrical properties such as interface state density. Experimental results show that, compared with existing structures, the capacitance-voltage curve dispersion of the MOS capacitor structure based on carbon nanotubes provided in this disclosure is significantly smaller. Therefore, the MOS capacitor structure provided in this disclosure can accurately characterize the gate dielectric and dielectric-interface electrical properties of carbon nanotube field-effect transistors (CNTs), and has significant application value in providing guidance for the optimization of the gate dielectric and interface of CNTs, and promoting the large-scale manufacturing of CNTs and integrated circuits. Attached Figure Description

[0017] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 A schematic top view of a carbon nanotube-based metal oxide semiconductor capacitor structure according to an embodiment of the present disclosure is shown.

[0019] Figure 2 Schematic illustration Figure 1 Cross-sectional view of the carbon nanotube-based metal oxide semiconductor capacitor structure in the AA direction;

[0020] Figure 3 The capacitance-voltage curve of a capacitor structure in the prior art is schematically shown;

[0021] Figure 4 The illustration schematically shows the capacitance-voltage curve of a carbon nanotube-based metal oxide semiconductor capacitor structure with an inner diameter of 60 μm for the top electrode metal ring according to an embodiment of the present disclosure. Detailed Implementation

[0022] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0024] In describing the embodiments of this disclosure in detail, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0025] This disclosure provides a metal-oxide-semiconductor capacitor structure based on carbon nanotubes, comprising: a substrate; a carbon nanotube thin film layer located on the substrate; a bottom electrode metal layer, partly located on the carbon nanotube thin film layer and partly located on the substrate; a metal oxide layer located on the carbon nanotube thin film layer; and a top electrode metal layer located on the metal oxide layer; wherein the carbon nanotube thin film layer and the top electrode metal layer are ring structures.

[0026] The metal-oxide-semiconductor (MOS) capacitor structure based on carbon nanotubes disclosed herein features a ring-shaped structure for both the carbon nanotube thin film layer and the top electrode metal layer. This allows for a very narrow electrode width and minimizes the overlap between carbon nanotubes within the entire electrode-covered carbon nanotube thin film, effectively reducing lateral resistance. Furthermore, it minimizes the coverage area of ​​discontinuous regions between carbon nanotubes, thereby improving the accuracy of testing and extracting electrical properties such as interface state density. Experimental results show that, compared to existing structures, the capacitance-voltage curve dispersion of the MOS capacitor structure based on carbon nanotubes disclosed herein is significantly smaller. Therefore, the MOS capacitor structure disclosed herein can accurately characterize the gate dielectric and dielectric-interface electrical properties of carbon nanotube field-effect transistors (CNTs), and has significant application value in providing guidance for the optimization of CNT gate dielectrics and interfaces, and in promoting the large-scale manufacturing of CNTs and integrated circuits.

[0027] The technical solution of this disclosure will be described in detail below with reference to the structure of the carbon nanotube-based metal-oxide-semiconductor capacitor structure in a specific embodiment of this disclosure. It should be understood that... Figure 1 The material layers, shapes, and structures of the various parts of the carbon nanotube-based metal oxide semiconductor capacitor structure shown are merely exemplary to help those skilled in the art understand the technical solutions of this disclosure, and are not intended to limit the scope of protection of this disclosure.

[0028] Figure 1 A schematic top view of a carbon nanotube-based metal oxide semiconductor capacitor structure according to an embodiment of the present disclosure is shown.

[0029] like Figure 1 As shown, the metal oxide semiconductor capacitor structure based on carbon nanotubes in this embodiment includes: a substrate 10, a carbon nanotube thin film layer 20, a bottom electrode metal layer 30, a metal oxide layer 40, a top electrode metal layer 50, a first electrode plate metal layer 61, and a second electrode plate metal layer 62.

[0030] In the embodiments of this disclosure, the substrate 10 is an insulating substrate, which may specifically be a silicon substrate, a quartz substrate, or a sapphire substrate with a pre-set thickness of silicon dioxide layer. The pre-set thickness of the silicon dioxide layer may be a silicon dioxide layer with a thickness ranging from 1 nm to 50 μm.

[0031] According to embodiments of this disclosure, the carbon nanotube thin film layer 20 is located on the substrate 10 and has a ring structure. A portion of the bottom electrode metal layer 30 is located on the carbon nanotube thin film layer 20, and another portion is located on the substrate 10; that is, the bottom electrode metal layer 30 and the carbon nanotube thin film layer 20 are partially overlapped. Figure 2 As shown. The metal oxide layer 40 is located on the surface of the carbon nanotube thin film layer 20 where the bottom electrode metal layer 30 is not located, or the metal oxide layer 40 may also be partially overlapped and grown on the bottom electrode metal layer 30. The top electrode metal layer 50 is located on the upper surface of the metal oxide layer 40 and has a ring structure.

[0032] Specifically, the carbon nanotube thin film layer 20, the bottom electrode metal layer 30, the metal oxide layer 40, and the top electrode metal layer 50 are concentric annular structures. The bottom electrode metal layer 30 is an annular structure with an opening for the metal leads overlapping with the top electrode metal layer 50 to pass through. The carbon nanotube thin film layer 20, the metal oxide layer 40, and the top electrode metal layer 50 are closed annular structures. Specifically, as... Figure 1 As shown, at the opening in the annular structure of the bottom electrode metal layer 30, the carbon nanotube thin film layer 20 also has a partial gap.

[0033] Furthermore, the carbon nanotube thin film layer 20 is a thin film layer composed of multiple carbon nanotubes, wherein the multiple carbon nanotubes are distributed in a network or array to form the thin film layer, and the inner diameter of the ring is 5nm to 1mm, and the ring width is 5nm to 20μm. It should be noted that, in the embodiments of this disclosure, the inner diameter of the ring represents the inner diameter of the ring structure, the outer diameter of the ring represents the outer diameter of the ring structure, and the ring width represents the difference between the outer diameter and the inner diameter of the ring structure.

[0034] In the embodiments of this disclosure, the width of the overlapping portion (i.e., the circumferential width of the overlapping portion) of the bottom electrode metal layer 30 and the carbon nanotube thin film layer 20 is: Its inner diameter of the ring is 6nm to 1mm, and its ring width is 1nm to 100μm.

[0035] Furthermore, the bottom electrode metal layer 30 can be composed of one or more materials such as palladium, titanium, gold, platinum, tungsten, nickel, copper, zinc, cadmium or aluminum. When composed of multiple materials, the bottom electrode metal layer 30 can be formed by overlapping growth of different materials.

[0036] In the embodiments of this disclosure, the metal oxide layer 40 is an oxide with a high dielectric constant, specifically one or more of aluminum-based, zirconium-based, hafnium-based, gadolinium-based, gallium-based, lanthanum-based, and tantalum-based oxides. The metal oxide layer 40 can be a single layer of the same metal oxide or a stack of multiple metal oxides, and the doping element in the metal oxide layer 40 can be aluminum, zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, or phosphorus, etc.

[0037] Specifically, the thickness of the metal oxide layer 40 is... Between them, the inner diameter of the metal oxide layer 40 is smaller than the inner diameter of the top electrode metal layer 50, and the outer diameter of the metal oxide layer 40 is larger than the outer diameter of the top electrode metal layer 50.

[0038] In the embodiments of this disclosure, the top electrode metal layer 50 can be one or more of titanium, gold, aluminum, platinum, tungsten, nickel, copper, zinc or cadmium. When composed of multiple materials, the top electrode metal layer 50 can be formed by overlapping growth of different materials.

[0039] Specifically, the inner diameter of the top electrode metal layer 50 is preferably in the range of 6 nm to 1 mm, the ring width is preferably in the range of 1 nm to 20 μm, and the layer thickness is preferably in the range of 10 nm to 2 μm. The difference between the outer diameter of the top electrode metal layer 50 and the inner diameter of the bottom electrode metal layer 30 is preferably in the range of 1 nm to 20 μm.

[0040] According to embodiments of this disclosure, a first electrode plate metal layer 61 is located on the substrate 10 or the metal oxide layer 40, and one end is connected to the top electrode metal layer 50. A second electrode plate metal layer 62 is located on the substrate 10 or the metal oxide layer 40, and one end is connected to the bottom electrode metal layer 30. Specifically, when the outer diameter of the annulus of the metal oxide layer 40 is sufficiently large, the first electrode plate metal layer 61 can be located on the metal oxide layer 40.

[0041] Specifically, the first electrode plate metal layer 61 and the second electrode plate metal layer 62 are wiring metals, which are composed of one or more of titanium nitride, tantalum nitride, tungsten, gold, copper, indium, titanium, platinum, chromium, germanium and nickel. The distance between the first electrode plate metal layer 61, the second electrode plate metal layer 62 and the two sides of the opening in the bottom electrode metal layer 30 is greater than or equal to 1 μm.

[0042] It should be noted that the ring width, diameter, and thickness of each material layer illustrated in the embodiments of this disclosure are merely preferred examples and do not constitute a limitation of the embodiments of this disclosure. In other application scenarios, other size ranges may be selected.

[0043] Figure 3 The capacitance-voltage curves of a capacitor structure with a circular top electrode metal diameter of 60 micrometers in the prior art are schematically shown. Figure 4The figure schematically illustrates the capacitance-voltage curves of a carbon nanotube-based metal oxide semiconductor capacitor structure with an inner diameter of 60 micrometers for the top electrode metal ring according to an embodiment of the present disclosure. The capacitance-voltage curves in the figure were measured at 1 MHz, 100 kHz, 50 kHz and 10 kHz, respectively.

[0044] Among them, such as Figure 4 As shown, the specific capacitor structure corresponding to the capacitance-voltage curve can be as follows: The insulating substrate 10 is a silicon substrate with a 100nm thick silicon dioxide layer. The carbon nanotube thin film layer 20 is an array-type thin film with an inner diameter of 59.6μm and a ring width of 2.7μm. The overlap width between the bottom electrode metal layer 30 and the carbon nanotube thin film layer 20 is 0.5μm. The inner diameter of the bottom electrode metal layer 30 is 64μm, and the ring width is 2.5μm. The bottom electrode metal layer 30 is composed of palladium and gold layers, with a palladium thickness of 10nm and a gold thickness of 70nm. The metal oxide layer 40 is hafnium dioxide with a thickness of 6nm. The inner diameter of the metal oxide layer 40 is 59.8μm, and the outer diameter is 63μm. The inner diameter of the top electrode metal layer 50 is 60 μm, and the difference in diameter between the top electrode metal layer 50 and the inner ring of the carbon nanotube thin film layer 20 is 400 nm. The difference in outer diameter between the top electrode metal layer 50 and the inner diameter of the bottom electrode metal layer 30 is 1 μm. The top electrode metal layer 50 is composed of titanium and gold stacks, with the titanium layer having a thickness of 10 nm and the gold layer having a thickness of 70 nm. The first electrode plate metal layer 61 and the second electrode plate metal layer 62 are composed of titanium and gold stacks, with the titanium layer having a thickness of 15 nm and the gold layer having a thickness of 400 nm. The distance between the openings in the first electrode plate metal layer 61 and the bottom electrode metal layer 30 is 2 μm.

[0045] A comparative analysis of the specific semiconductor capacitor structure provided in this disclosure and the prior art carbon nanotube metal oxide semiconductor capacitor structure is provided, such as... Figure 3 and Figure 4 As shown, the capacitance-voltage curve of the top electrode metal provided in this disclosure, which is a ring-shaped carbon nanotube metal oxide semiconductor capacitor structure, has smaller dispersion and is more in line with the capacitance-voltage curve law.

[0046] In other embodiments, the carbon nanotube thin film layer 20, the bottom electrode metal layer 30, the metal oxide layer 40, and the top electrode metal layer 50 may also be rectangular, square, elliptical, or other shapes with the same geometric center, and are not limited to a circular ring structure with the same center. The dimensional variation trend between the layers is consistent with the above embodiments, and the embodiments disclosed herein will not be described in detail here.

[0047] It should be noted that the carbon nanotube-based metal oxide semiconductor capacitor structure provided in the embodiments of this disclosure can be fabricated using existing fabrication processes, and the embodiments of this disclosure do not limit the fabrication process of the carbon nanotube-based metal oxide semiconductor capacitor structure.

[0048] Although the present disclosure has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions should be considered illustrative or exemplary rather than limiting.

[0049] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0050] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A metal-oxide-semiconductor capacitor structure based on carbon nanotubes, characterized in that, include: Substrate (10); A carbon nanotube thin film layer (20) is located on the substrate (10); The bottom electrode metal layer (30) is partially located on the carbon nanotube thin film layer (20) and partially located on the substrate (10); A metal oxide layer (40) is located on the carbon nanotube thin film layer (20); A top electrode metal layer (50) is located on the metal oxide layer (40); wherein the carbon nanotube thin film layer (20) and the top electrode metal layer (50) are ring structures.

2. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 1, characterized in that, The carbon nanotube thin film layer (20), the bottom electrode metal layer (30), the metal oxide layer (40), and the top electrode metal layer (50) are concentric annular structures, wherein the bottom electrode metal layer (30) is an annular structure with an opening.

3. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 2, characterized in that, The inner diameter of the top electrode metal layer (50) is larger than the inner diameter of the carbon nanotube film layer (20); the outer diameter of the top electrode metal layer (50) is smaller than the inner diameter of the bottom electrode metal layer (30); the inner diameter of the metal oxide layer (40) is smaller than the inner diameter of the top electrode metal layer (50); and the outer diameter of the metal oxide layer (40) is larger than the outer diameter of the top electrode metal layer (50).

4. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 2, characterized in that, In the carbon nanotube thin film layer (20), multiple carbon nanotubes are distributed in a network or array.

5. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 3, characterized in that, The inner diameter of the carbon nanotube thin film layer (20) is 5 nm to 1 mm, and its ring width is 5 nm to 20 μm.

6. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 3, characterized in that, The width of the overlapping portion between the bottom electrode metal layer (30) and the carbon nanotube thin film layer (20) is 7. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 1, characterized in that, Also includes: The first electrode plate metal layer (61) is located on the substrate (10) or the metal oxide layer (40), and one end is connected to the top electrode metal layer (50). The second electrode plate metal layer (62) is located on the substrate (10) or the metal oxide layer (40), and one end is connected to the bottom electrode metal layer (30).

8. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 1, characterized in that, The bottom electrode metal layer (30) is one or more of palladium, titanium, gold, platinum, tungsten, nickel, copper, zinc, cadmium or aluminum; The top electrode metal layer (50) is one or more of titanium, gold, aluminum, platinum, tungsten, nickel, copper, zinc or cadmium.

9. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 1, characterized in that, The metal oxide layer (40) is one or more of aluminum-based, zirconium-based, hafnium-based, gadolinium-based, gallium-based, lanthanum-based, or tantalum-based oxides.

10. The metal-oxide-semiconductor capacitor structure based on carbon nanotubes according to claim 1, characterized in that, The substrate (10) is a silicon substrate, quartz substrate or sapphire substrate on which a silicon dioxide layer of a pre-set thickness is grown.

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