Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: providing an initial bonding structure with a memory array and a CMOS structure, the memory array comprising a substrate, a stack structure and a plurality of contact structures, the contact structures penetrating through the stack structure; removing the substrate to form a plurality of virtual channel holes penetrating through the exposed stack structure and gate line slits; and replacing a sacrificial layer in the gate line slits with a metal layer. The method does not need to consider the process window of the virtual channel holes when manufacturing the contact structures, and does not need to consider the problem that the contact structures are in contact with the virtual channel holes due to the problems such as the inclination and bending of the virtual channel holes, thereby ensuring a larger process window of the contact structures and ensuring that the virtual channel holes can better support the stack structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] As the number of layers in 3D NAND continues to increase, the tilting and shifting problems of dummy channel holes (DVs) and contact structures are becoming increasingly serious. To ensure a larger process window for the contact structures, the critical dimensions of the DVs need to be reduced to allow for a larger margin, preventing short circuits between the contact structure and the DV during etching. However, shrinking the DVs can lead to insufficient support for the word lines (WLs), resulting in WL bending and affecting the electrical performance of the device.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a semiconductor device and a semiconductor device in order to solve the problem in the prior art that it is impossible to ensure a good supporting effect of the virtual channel hole while ensuring a large process window for the contact structure.

[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: providing an initial bonding structure, the initial bonding structure including a memory array structure and a CMOS structure bonded together, the memory array structure including a substrate, a stacked structure and a plurality of contact structures, the stacked structure being located on the surface of the substrate near the CMOS structure, the stacked structure including alternately stacked insulating dielectric layers and sacrificial layers, the contact structures penetrating a portion of the stacked structure and correspondingly contacting each of the sacrificial layers; removing the substrate to expose the stacked structure; sequentially forming a plurality of virtual channel vias and gate line slits penetrating the exposed stacked structure, the virtual channel vias being alternately disposed with the contact structures, the gate line slits being located on one side of the virtual channel vias and the contact structures; and replacing the sacrificial layer with a metal layer through the gate line slits.

[0006] Optionally, an initial bonding structure is provided, comprising: providing the CMOS structure; providing the memory array structure, the memory array structure further comprising a dielectric layer, a dummy gate line slit, and a sacrificial material, the dielectric layer being located on the surface of the stacked structure away from the substrate, each of the contact structures penetrating the dielectric layer to contact the corresponding sacrificial layer, the dummy gate line slit penetrating the dielectric layer into the substrate, and the sacrificial material filling the dummy gate line slit; and bonding the CMOS structure and the memory array structure to obtain the initial bonding structure.

[0007] Optionally, removing the substrate to expose the stacked structure includes: removing the substrate to expose the stacked structure and the sacrificial material, and sequentially forming a plurality of virtual channel vias and gate line slits through the exposed stacked structure, including: forming each of the virtual channel vias through the exposed stacked structure to the dielectric layer; and removing the sacrificial material to obtain the gate line slits.

[0008] Optionally, the memory array structure includes: providing the substrate, and sequentially disposing the stacked structure and the dielectric layer on the exposed surface of the substrate; forming a virtual gate line slit penetrating the dielectric layer, the stacked structure, and into the substrate; filling the virtual gate line slit with the sacrificial material; and forming a contact structure on one side of the virtual gate line slit penetrating the dielectric layer and into the surface of each of the sacrificial layers, thereby obtaining the memory array structure.

[0009] Optionally, forming the virtual gate line slit penetrating the dielectric layer, the stacked structure, and the substrate includes: sequentially etching the dielectric layer, the stacked structure, and the substrate to form a trench; and performing wet oxidation on the trench to obtain the virtual gate line slit.

[0010] Optionally, providing the substrate, the stacked structure, and the dielectric layer arranged sequentially includes: providing the substrate; forming the stacked structure on the exposed surface of the substrate; removing a portion of the stacked structure to form a plurality of continuous stepped structures; and forming the dielectric layer on the exposed surface of the stacked structure on which the stepped structures are formed.

[0011] Optionally, the sacrificial material includes carbon.

[0012] Optionally, the memory array structure further includes a plurality of channel vias and a filling structure located in the channel vias. The channel vias penetrate the stacked structure into the substrate. The filling structure includes a high-k dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer sequentially disposed along a direction away from the sidewall of the channel via.

[0013] Optionally, the high-k dielectric layer comprises aluminum oxide.

[0014] According to another aspect of the present invention, a semiconductor device is also provided, which is fabricated using any of the methods described.

[0015] In this embodiment of the invention, firstly, an initial bonding structure having a memory array structure and a CMOS structure is provided. The memory array structure includes a substrate, a stacked structure, and multiple contact structures. The contact structures penetrate the stacked structure. Then, the substrate is removed to form multiple virtual channel vias and gate line slits penetrating the exposed stacked structure. Finally, the sacrificial layer is replaced with a metal layer through the gate line slits. In this method, the memory array structure in the initial bonding structure includes contact structures, meaning the contact structures are already formed. Then, by removing the substrate, the stacked structure is exposed. Multiple virtual channel vias and gate line slits are formed from the exposed stacked structure side (i.e., from the back side of the memory array structure). This eliminates the need to consider the process window of the virtual channel vias during contact structure fabrication, and also eliminates the need to consider issues such as tilting or bending of the virtual channel vias causing contact between the contact structure and the virtual channel vias, ensuring a larger process window for the contact structure. Simultaneously, compared to forming virtual channel vias from the front, due to actual process limitations, the aperture of the virtual channel via at the end furthest from the CMOS structure will be smaller than the aperture of the virtual channel via at the end closest to the CMOS structure, and bending or... Tilt typically occurs at the end of the virtual channel via that is far from the CMOS structure, resulting in poor support for the stacked structure. The method described in this application forms the virtual channel via and the gate line slit sequentially from the back of the memory array structure. This ensures that the aperture of the virtual channel via is larger at the end far from the CMOS structure, and that the end of the virtual channel via far from the CMOS structure does not bend or tilt. This ensures that the virtual channel via can better support the stacked structure, thereby solving the problem in the prior art that it is impossible to ensure a large process window for the contact structure while ensuring good support of the virtual channel via. This ensures good performance of the bonding structure and allows for a high number of stacked layers. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0018] Figures 2 to 25 The diagrams show the structural schematics obtained after each process step of the semiconductor device fabrication method according to this application.

[0019] The above figures include the following reference numerals:

[0020] 10. Memory array structure; 20. CMOS structure; 100. Substrate; 101. Stacked structure; 102. Contact structure; 103. Insulating dielectric layer; 104. Sacrificial layer; 105. Metal layer; 106. Virtual channel via; 107. Gate line slit; 108. Dielectric layer; 109. Sacrificial material; 110. Fill structure; 111. Channel via; 112. Step structure; 113. Third groove; 114. Insulating portion; 115. High-k dielectric layer; 116. 117. Charge blocking layer; 118. Electron trapping layer; 119. Tunneling layer; 120. Channel layer; 121. Third insulating material layer; 122. First insulating material layer; 123. Metal transition layer; 124. Metal material layer; 125. Lead-out line; 126. Fourth groove; 127. Fourth insulating material layer; 128. Metal material; 129. Fifth insulating material layer; 130. Polycrystalline silicon layer; 131. Second substrate; 132. Fifth groove. Detailed Implementation

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As mentioned in the background section, the existing technology cannot ensure both good support for the virtual channel hole and a large process window for the contact structure. To solve the above problems, in a typical embodiment of this application, a method for fabricating a semiconductor device and a semiconductor device are provided.

[0026] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.

[0027] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:

[0028] Step S101, provide as follows Figure 10 or Figure 22 The initial bonding structure shown includes a memory array structure 10 and a CMOS structure 20 bonded together. The memory array structure 10 includes a substrate 100, a stacked structure 101 and a plurality of contact structures 102. The stacked structure 101 is located on the surface of the substrate 100 near the CMOS structure 20. The stacked structure 101 includes alternately stacked insulating dielectric layers 103 and sacrificial layers 104. The contact structures 102 penetrate the stacked structure 101 and contact each of the sacrificial layers 104 in a corresponding manner.

[0029] Step S102: Remove the substrate 100 to expose the stacked structure 101, resulting in... Figure 11 The structure shown;

[0030] Step S103, as follows Figure 14 or Figure 24 As shown, a plurality of virtual channel holes 106 and gate line slits 107 are sequentially formed through the exposed stacked structure. The virtual channel holes 106 and the contact structure 102 are alternately arranged, and the gate line slits 107 are located on one side of the virtual channel holes 106 and the contact structure 102.

[0031] In step S104, the sacrificial layer 104 is replaced with a metal layer 105 through the gate line slit 107, resulting in the following: Figure 16 or Figure 25 The structure shown.

[0032] In the above method, firstly, an initial bonding structure with a memory array structure and a CMOS structure is provided. The memory array structure includes a substrate, a stacked structure, and multiple contact structures. The contact structures penetrate the stacked structure. Then, the substrate is removed to form multiple virtual channel vias and gate line slits penetrating the exposed stacked structure. Finally, the sacrificial layer is replaced with a metal layer through the gate line slits. In this method, the memory array structure in the initial bonding structure includes contact structures, meaning the contact structures are already formed. Then, by removing the substrate, the stacked structure is exposed. Multiple virtual channel vias and gate line slits are formed from the exposed stacked structure side (i.e., from the back side of the memory array structure). This eliminates the need to consider the process window of the virtual channel vias during contact structure fabrication, and also eliminates the need to consider issues such as tilting or bending of the virtual channel vias that could cause contact between the contact structure and the virtual channel vias, ensuring a larger process window for the contact structure. Simultaneously, compared to forming virtual channel vias from the front side, due to actual process limitations, the aperture of the virtual channel via at the end furthest from the CMOS structure will be smaller than the aperture at the end closest to the CMOS structure, and bending or... Tilt typically occurs at the end of the virtual channel via that is far from the CMOS structure, resulting in poor support for the stacked structure. The method described in this application forms the virtual channel via and the gate line slit sequentially from the back of the memory array structure. This ensures that the aperture of the virtual channel via is larger at the end far from the CMOS structure, and that the end of the virtual channel via far from the CMOS structure does not bend or tilt. This ensures that the virtual channel via can better support the stacked structure, thereby solving the problem in the prior art that it is impossible to ensure a large process window for the contact structure while ensuring good support of the virtual channel via. This ensures good performance of the bonding structure and allows for a high number of stacked layers.

[0033] In one specific embodiment of this application, an initial bonding structure is provided, including: as follows Figure 10 or Figure 22 As shown, the above-mentioned CMOS structure 20 is provided; and the following is provided: Figure 8 or Figure 21 The memory array structure 10 shown above further includes a dielectric layer 108, dummy gate line slits, and a sacrificial material 109. The dielectric layer 108 is located on the surface of the stacked structure 101 away from the substrate 100. Each contact structure 102 penetrates the dielectric layer 108 and contacts the corresponding sacrificial layer 104. The dummy gate line slits penetrate the dielectric layer 108 into the substrate 100, and the sacrificial material 109 fills the dummy gate line slits. The CMOS structure 20 and the memory array structure 10 are bonded together to obtain the following structure: Figure 10 or Figure 22The initial bonding structure shown above. In this embodiment, a contact structure and a virtual gate line slit are first formed on the front side of the memory array structure. Sacrificial material is filled into the virtual gate line slit, and then bonding is performed. In this way, when the gate line slit is subsequently fabricated on the back side of the memory array structure, only the sacrificial material needs to be removed to obtain the gate line slit. This avoids the problem of bending or deformation of the already bonded memory array structure caused by forming the gate line slit on the back side through a high-temperature process, which would affect the bonding effect. This further ensures better performance of the bonding structure.

[0034] To further simplify the process of forming virtual channel vias and gate line slits in the memory array structure, in another specific embodiment of this application, such as... Figure 10 as well as Figure 11 As shown, or as Figure 22 as well as Figure 23 As shown, removing the substrate to expose the stacked structure includes: removing the substrate 100 to expose the stacked structure 101 and the sacrificial material 109, as shown. Figures 12 to 14 As shown, or as Figure 23 as well as Figure 24 As shown, multiple virtual channel vias and gate line slits are sequentially formed through the exposed stacked structure, including: forming virtual channel vias 106 through the exposed stacked structure 101 to the dielectric layer; and removing the sacrificial material 109 to obtain the gate line slits 107. Since the virtual gate line slits are formed and filled with sacrificial material before bonding the memory array structure and the CMOS structure, when fabricating the gate line slits on the back side of the bonded memory array structure, only the sacrificial material needs to be removed to obtain the required gate line slits. This does not affect the already bonded memory array structure, further avoiding the problem of bending or expansion of the bonded memory array structure, and thus further ensuring better electrical performance of the semiconductor device.

[0035] According to another specific embodiment of this application, such as Figures 2 to 8 As shown, or as Figures 19 to 21 As shown, the above-mentioned memory array structure includes: providing the above-mentioned substrate 100, and sequentially depositing the above-mentioned stacked structure 101 and the above-mentioned dielectric layer 108 on the exposed surface of the above-mentioned substrate 100, to obtain the following... Figure 2 Or such as Figure 19 The structure shown; forming the virtual gate line slit extending through the dielectric layer 108, the stacked structure 101, and the substrate 100; filling the virtual gate line slit with the sacrificial material 109 to obtain the structure shown; Figure 7 or Figure 20 The structure shown; as Figure 8 or Figure 21 As shown, a contact structure 102 is formed on one side of the aforementioned virtual gate line slit, penetrating the surface of the dielectric layer 108 to each of the aforementioned sacrificial layers 104, thus obtaining the aforementioned memory array structure 10. By forming the contact structure on the front side of the memory array structure before bonding and subsequent formation of virtual channel vias, the problem of contact between the contact structure and the virtual channel via caused by considering the process window, tilting, and bending of the virtual channel via during the formation of the contact structure is further avoided, thus further ensuring a larger process window for the contact structure.

[0036] In another specific embodiment of this application, forming the virtual gate line slit penetrating the dielectric layer, the stacked structure, and the substrate includes: sequentially etching the dielectric layer, the stacked structure, and the substrate to form a trench; and performing wet oxidation on the trench to obtain the virtual gate line slit. To obtain the virtual gate line slit, in this embodiment, the dielectric layer, the stacked structure, and the substrate are sequentially etched to form a trench for the gate line slit, and then the trench is wet-oxidized to obtain the virtual gate line slit. Of course, the process for obtaining the virtual gate line slit is not limited to the wet oxidation described above, and can also be any other feasible process in the prior art. It should be noted that, to distinguish it from other trenches described below, the trench described above is referred to as the first trench in the following description.

[0037] To ensure a relatively simple and easy manufacturing process for the contact structure, in another specific embodiment of this application, such as... Figure 19 As shown, a substrate, a stacked structure, and a dielectric layer are provided sequentially, comprising: providing the substrate 100; forming a stacked structure 101 on the exposed surface of the substrate, the stacked structure 101 including alternately stacked insulating dielectric layers 103 and sacrificial layers 104; removing a portion of the stacked structure 101 to form a plurality of continuous step structures 112; and forming a dielectric layer 108 on the exposed surface of the stacked structure 101 with the step structures 112 formed. Each step structure consists of a sacrificial layer and an insulating dielectric layer sequentially arranged along a direction away from the substrate, followed by the formation of a contact structure that penetrates the insulating dielectric layer of the corresponding step structure to reach the surface or the sacrificial layer. In practical applications, to ensure that the contact structure can stop on the surface or in the corresponding sacrificial layer, in the pre-stacked structure, the thickness of each insulating dielectric layer is less than the thickness of each sacrificial layer.

[0038] Of course, to simplify the process, the aforementioned step structure can be omitted. In another specific embodiment of this application, such as... Figure 2As shown, a substrate, a stacked structure, and a dielectric layer are provided sequentially, comprising: providing a substrate 100; forming a stacked structure 101 on the exposed surface of the substrate 100, the stacked structure 101 including alternately stacked insulating dielectric layers 103 and sacrificial layers 104; and forming a dielectric layer 108 on the exposed surface of the stacked structure 101, to obtain... Figure 2 The structure is shown. Then, by setting the key dimensions of each contact structure and the corresponding etching equipment parameters, multiple contact structures 102 are formed that penetrate to the surface of or into the corresponding sacrificial layer 104, resulting in the structure shown. Figure 8 The storage array structure 10 is shown. Specifically, as... Figure 9 As shown, a second groove is first formed, then a first insulating material layer 121 is formed on the sidewall of the second groove. A metal transition layer 122 is formed on the surface of the first insulating material layer 121 away from the sidewall, as well as at the bottom and top of the groove. A metal material layer 123 is formed on the surface of the metal transition layer away from the first insulating material layer 121, and a second insulating material layer 124 is formed on the surface of the metal material layer 123 away from the metal transition layer 122, thus obtaining the contact structure described above. After forming multiple contact structures 102, they are bonded to the CMOS structure 20 to obtain the following... Figure 10 Or such as Figure 23 The initial bonding structure is shown.

[0039] In practical applications, the material of the insulating dielectric layer may include silicon oxide, the material of the sacrificial layer may include silicon nitride, and the material of the dielectric layer may include silicon oxide. In one specific embodiment, the material of the insulating dielectric layer is silicon dioxide, the material of the sacrificial layer is silicon nitride, and the material of the dielectric layer is silicon dioxide. Of course, the materials of the insulating dielectric layer, the sacrificial layer, and the dielectric layer are not limited to the materials described above, and those skilled in the art can select suitable materials as the insulating dielectric layer, the sacrificial layer, and the dielectric layer.

[0040] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate can be selected according to the actual needs of the device and may include silicon substrates, germanium substrates, silicon-germanium composites, SOI (Silicon on Insulator) substrates, or GOI (Germanium on Insulator) substrates. In other embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon on Germanium Insulator). Of course, other substrates feasible in the prior art may also be used.

[0041] In another embodiment of this application, the sacrificial material includes carbon. In practical applications, the sacrificial material can also be other materials, which can be selected by those skilled in the art according to the actual situation.

[0042] In another embodiment of this application, such as Figure 8 or Figure 21 As shown, the above-described memory array structure also includes a plurality of channel vias 111, which penetrate the stacked structure 101 to the surface of the substrate 100, such as... Figure 6 As shown, the formation process of the aforementioned channel hole involves first forming a third groove, and then sequentially depositing a high-K dielectric layer 115, a charge blocking layer 116, an electron trapping layer 117, a tunneling layer 118, a channel layer 119, and a third insulating material layer 120 on the sidewall of the third groove to obtain the channel hole. The channel hole also includes a filling structure 110, which fills the remaining portion of the aforementioned third groove, and the filling structure contacts a portion of the aforementioned tunneling layer 118, a portion of the channel layer 119, and a portion of the third insulating material layer 120. In this embodiment, the channel hole is formed before bonding, that is, the channel hole including the high-K dielectric layer is formed from the front side of the aforementioned memory array structure. This avoids the problem that the high-temperature process of forming the high-K dielectric layer on the back side of the aforementioned memory array structure after bonding would have a negative impact on the bonded structure, thus further ensuring better performance of the bonded structure.

[0043] In one specific embodiment, during the etching process to form the aforementioned channel hole, the sacrificial layer and the insulating dielectric layer have a dry etching selectivity of almost 1:1. When the sacrificial layer parallel to the substrate direction is replaced with a conductive layer, the sacrificial layer and the insulating dielectric layer have a very high wet etching selectivity, for example, 30:1 or even higher. The number of layers in the stacked structure can be determined according to specific needs.

[0044] The materials of the above-mentioned structural layers can also be any feasible materials in the prior art. For example, the charge blocking layer can be made of silicon dioxide, the electron trapping layer can be made of silicon nitride, the tunneling layer can be made of silicon dioxide, the channel layer can be made of polysilicon, the filling structure can be made of polysilicon, and the third insulating material layer can be made of silicon dioxide. Of course, the materials of these structural layers can also be replaced with other suitable materials, which will not be elaborated here.

[0045] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0046] In another embodiment of this application, the high-k dielectric layer comprises aluminum oxide. In practical applications, the high-k dielectric layer can be aluminum oxide, or it can be other materials.

[0047] According to another aspect of the present invention, a semiconductor device is also provided, wherein the semiconductor device is manufactured using any of the methods described above.

[0048] The aforementioned semiconductor device is fabricated using any of the methods described above. In this method, the memory array structure in the initial bonding structure includes a contact structure, meaning the contact structure has already been formed. Then, by removing the substrate, the stacked structure is exposed. Multiple virtual channel holes and gate line slits are formed from the exposed stacked structure side (i.e., from the back side of the memory array structure). This eliminates the need to consider the process window of the virtual channel holes during contact structure fabrication, and also eliminates the need to consider issues such as tilting or bending of the virtual channel holes that could cause contact between the contact structure and the virtual channel holes, ensuring a larger process window for the contact structure. Simultaneously, compared to forming virtual channel holes from the front side, due to actual process limitations, the aperture of the virtual channel hole at the end furthest from the CMOS structure will be smaller than the aperture at the end closest to the CMOS structure, and it may be bent or tilted. The tilting typically occurs at the end of the virtual channel via that is far from the CMOS structure, resulting in poor support for the stacked structure. The method described in this application forms the virtual channel via and the gate line slit sequentially from the back of the memory array structure. This ensures that the aperture of the virtual channel via is larger at the end far from the CMOS structure, and that the end of the virtual channel via far from the CMOS structure does not bend or tilt. This ensures that the virtual channel via can better support the stacked structure, thereby solving the problem in the prior art that it is impossible to ensure a large process window for the contact structure while ensuring good support of the virtual channel via. This ensures better performance of the semiconductor device and allows for a higher number of stacked layers.

[0049] To enable those skilled in the art to clearly understand the technical solution of this application, the following description will be provided in conjunction with embodiments.

[0050] Example 1

[0051] A method for fabricating a semiconductor device includes the following steps:

[0052] A substrate 100, a stacked structure 101, and a dielectric layer 108 are provided in sequence. An insulating dielectric layer 103 and a sacrificial layer 104 are alternately stacked in the stacked structure 101, resulting in... Figure 2 The structure shown should be noted that, for ease of description and distinction, the substrate 100 described above will be referred to as the first substrate in the following description.

[0053] like Figure 2 as well as Figure 3 As shown, a third groove 113 is formed in the aforementioned dielectric layer 108 and stacked structure 101, resulting in the following: Figure 3 The structure shown;

[0054] like Figure 4 As shown, a portion of the exposed sacrificial layer 104 of the third groove is removed to form a sub-groove in the third groove, and then an insulating portion 114 is formed in the sub-groove. The material of the insulating portion can be silicon dioxide.

[0055] like Figure 5 and Figure 6 As shown, a high-K dielectric layer 115, a charge blocking layer 116, an electron trapping layer 117, a tunneling layer 118, and a channel layer 119 are sequentially formed on the sidewall of the third groove where the insulating portion 114 is formed. Then, a third insulating material layer 120 and a filling structure 110 are sequentially filled into the remaining third groove to fill the third groove and obtain the channel hole 111.

[0056] A virtual gate line slit is formed on one side of the aforementioned channel via 111, penetrating the aforementioned dielectric layer 108, the aforementioned stacked structure 101, and the aforementioned first substrate, and the virtual gate line slit is filled with sacrificial material 109 to obtain the following result: Figure 7 The structure shown;

[0057] like Figure 8 As shown, multiple contact structures 102 are formed on one side of the aforementioned channel holes and the aforementioned sacrificial material 109. These contact structures 102 pass through the dielectric layer 108, penetrate the stacked structure 101, and contact each of the aforementioned sacrificial layers 104 in a corresponding manner, thus obtaining the memory array structure 10; as shown in the figure. Figure 8 as well as Figure 9As shown, the formation process of the contact structure 102 is as follows: a second groove is formed in the dielectric layer 108 and the stacked structure 101; a first insulating material layer 121 is formed on the sidewall of the second groove; a metal transition layer 122 is formed on the surface of the first insulating material layer 121 away from the sidewall and at the bottom and top of the groove; a metal material layer 123 is formed on the surface of the metal transition layer away from the first insulating material layer 121; and a second insulating material layer 124 is formed on the surface of the metal material layer 123 away from the metal transition layer 122, so as to fill the second groove and obtain the contact structure 102. Figure 8 In this process, lead wires 125 are provided on the surfaces of the contact structure 102, the channel hole 111, and the sacrificial material 109 that are away from the first substrate. The lead wires 125 can be made of metal.

[0058] like Figure 10 As shown, a CMOS structure 20 is provided, and the CMOS structure 20 and the memory array structure 10 are bonded together to obtain an initial bonding structure.

[0059] The first substrate in the initial bonding structure is removed to expose the stacked structure 101, resulting in the following: Figure 11 The structure shown;

[0060] A fourth groove 126 is formed, extending through the aforementioned stacked structure 101 to the dielectric layer 108, as follows: Figure 12 As shown;

[0061] like Figure 12 as well as Figure 13 As shown, a fourth insulating material layer 127 is deposited in the fourth groove 126 and on the surface of the stacked structure 101 away from the CMOS structure 20. The filled fourth groove forms a virtual channel hole 106. Furthermore, the sacrificial material in the virtual gate line slit is removed to obtain a gate line slit 107, resulting in... Figure 14 The structure shown;

[0062] like Figure 14 , Figure 15 as well as Figure 16 As shown, each of the sacrificial layers is removed through the gate line slit 107 to form a plurality of fifth grooves 132. Then, metal material 128 is filled into the fifth grooves 132 through the gate line slit 107 to form a metal layer 105. Specifically, the metal layer is composed of a titanium nitride layer and a tungsten layer.

[0063] Remove Figure 16The metal material 128 on the surface of the fourth insulating material layer 127 and the metal material 128 in the gate line slit 107 are shown above. A fifth insulating material layer 129 and a polysilicon layer 130 are sequentially deposited in the gate line slit 107 to form a gate line, resulting in the following: Figure 17 The structure shown;

[0064] like Figure 17 as well as Figure 18 As shown, the fourth insulating material layer 127 and the insulating dielectric layer 103 in contact with the fourth insulating material layer 127 are removed, and then a substrate material is deposited to form a second substrate 131.

[0065] Example 2

[0066] A method for fabricating a semiconductor device includes the following steps:

[0067] like Figure 19 As shown, a substrate 100, a stacked structure 101, and a dielectric layer 108 are provided in sequence. The stacked structure 101 has an insulating dielectric layer 103 and a sacrificial layer 104 stacked alternately. One end of the stacked structure 101 has a stepped structure 112. It should be noted that, for ease of description and distinction, the substrate 100 is referred to as the first substrate in the following description.

[0068] Forming a channel via 111, a virtual gate line slit, and a sacrificial material 109 in the virtual gate line slit within the dielectric layer 108 and the stacked structure 101, as shown, yields... Figure 20 The structure shown above, the specific structure of the channel hole 111 is as follows: Figure 6 As shown, this will not be repeated here;

[0069] like Figure 21 As shown, a plurality of contact structures 102 are formed on one side of the aforementioned channel holes and the aforementioned sacrificial material 109. These contact structures 102 pass through the dielectric layer 108, penetrate the stacked structure 101, and contact each of the aforementioned sacrificial layers 104 in a corresponding manner, thus obtaining the memory array structure 10. The specific configuration of the contact structures 102 is as follows: Figure 9 As shown. Figure 21 In this process, lead wires 125 are provided on the surfaces of the contact structure 102, the channel hole 111, and the sacrificial material 109 that are away from the first substrate. The lead wires 125 can be made of metal.

[0070] like Figure 22 As shown, a CMOS structure 20 is provided, and the CMOS structure 20 and the memory array structure 10 are bonded together to obtain an initial bonding structure.

[0071] The first substrate in the initial bonding structure is removed to expose the stacked structure 101, and a plurality of virtual channel vias 106 are formed through the stacked structure 101 to the dielectric layer 108, resulting in... Figure 23 The structure shown;

[0072] Remove Figure 23 The sacrificial material 109 in the virtual gate line slit shown results in the gate line slit 107, as... Figure 24 As shown;

[0073] like Figure 24 as well as Figure 25 As shown, each of the sacrificial layers is replaced with a metal layer 105 through the gate line slit 107. Specifically, the metal layer is composed of a titanium nitride layer and a tungsten layer.

[0074] The subsequent manufacturing process is the same as in Example 1, and will not be repeated here.

[0075] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0076] 1) The semiconductor device fabrication method of this application first provides an initial bonding structure having a memory array structure and a CMOS structure. The memory array structure includes a substrate, a stacked structure, and multiple contact structures. The contact structures penetrate the stacked structure. Then, the substrate is removed to form multiple virtual channel holes and gate line slits penetrating the exposed stacked structure. Finally, the sacrificial layer is replaced with a metal layer through the gate line slits. In this method, the memory array structure in the initial bonding structure includes contact structures, i.e., the contact structures have already been formed. Then, by removing the substrate, the stacked structure is exposed. Multiple virtual channel holes and gate line slits are formed from the exposed stacked structure side (i.e., from the back side of the memory array structure). This eliminates the need to consider the process window of the virtual channel holes when fabricating the contact structures, and also eliminates the need to consider the contact problems caused by the tilting and bending of the virtual channel holes, ensuring a larger process window for the contact structures. At the same time, compared to forming virtual channel holes from the front side, due to actual process limitations, the aperture of the virtual channel hole at the end away from the CMOS structure will be smaller than the aperture of the virtual channel hole at the end close to the CMOS structure, and bending or... Tilt typically occurs at the end of the virtual channel via that is far from the CMOS structure, resulting in poor support for the stacked structure. The method described in this application forms the virtual channel via and the gate line slit sequentially from the back of the memory array structure. This ensures that the aperture of the virtual channel via is larger at the end far from the CMOS structure, and that the end of the virtual channel via far from the CMOS structure does not bend or tilt. This ensures that the virtual channel via can better support the stacked structure, thereby solving the problem in the prior art that it is impossible to ensure a large process window for the contact structure while ensuring good support of the virtual channel via. This ensures good performance of the bonding structure and allows for a high number of stacked layers.

[0077] 2) The semiconductor device of this application is fabricated using any of the methods described above. In this method, the memory array structure in the initial bonding structure includes a contact structure, i.e., the contact structure has already been formed. Then, by removing the substrate, the stacked structure is exposed. Multiple virtual channel holes and gate line slits are formed from the exposed stacked structure side (i.e., from the back side of the memory array structure). This eliminates the need to consider the process window of the virtual channel holes during contact structure fabrication, and also eliminates the need to consider issues such as tilting or bending of the virtual channel holes causing contact between the contact structure and the virtual channel holes, ensuring a larger process window for the contact structure. Simultaneously, compared to forming virtual channel holes from the front side, due to actual process limitations, the aperture of the virtual channel hole at the end furthest from the CMOS structure will be smaller than the aperture at the end closest to the CMOS structure, and it may be bent or tilted. The tilting typically occurs at the end of the virtual channel via that is far from the CMOS structure, resulting in poor support for the stacked structure. The method described in this application forms the virtual channel via and the gate line slit sequentially from the back of the memory array structure. This ensures that the aperture of the virtual channel via is larger at the end far from the CMOS structure, and that the end of the virtual channel via far from the CMOS structure does not bend or tilt. This ensures that the virtual channel via can better support the stacked structure, thereby solving the problem in the prior art that it is impossible to ensure a large process window for the contact structure while ensuring good support of the virtual channel via. This ensures better performance of the semiconductor device and allows for a higher number of stacked layers.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: An initial bonding structure is provided, the initial bonding structure including a memory array structure and a CMOS structure bonded together, the memory array structure including a substrate, a stacked structure and a plurality of contact structures, the stacked structure being located on the surface of the substrate near the CMOS structure, the stacked structure including alternately stacked insulating dielectric layers and sacrificial layers, and the contact structures penetrating the stacked structure and contacting each of the sacrificial layers one by one. Remove the substrate to expose the stacked structure; Multiple virtual channel vias and gate line slits are sequentially formed through the exposed stacked structure. The virtual channel vias are alternately arranged with the contact structure, and the gate line slits are located on one side of the virtual channel vias and the contact structure. The sacrificial layer is replaced with a metal layer through the gate line slit.

2. The method according to claim 1, characterized in that, Provide an initial bonding structure, including: Provide the CMOS structure; The memory array structure is provided, the memory array structure further comprising a dielectric layer, a dummy gate line slit, and a sacrificial material, the dielectric layer being located on the surface of the stacked structure away from the substrate, each of the contact structures penetrating the dielectric layer to contact the corresponding sacrificial layer, the dummy gate line slit penetrating the dielectric layer into the substrate, and the sacrificial material filling the dummy gate line slit; The CMOS structure and the memory array structure are bonded together to obtain the initial bonding structure.

3. The method according to claim 2, characterized in that, Removing the substrate to expose the stacked structure includes: Remove the substrate to expose the stacked structure and the sacrificial material. A plurality of virtual channel vias and gate line slits are sequentially formed through the exposed stacked structure, including: Forming virtual channel holes that penetrate the exposed stacked structure into each of the dielectric layers; The sacrificial material is removed to obtain the gate line slit.

4. The method according to claim 2, characterized in that, The storage array structure is provided, comprising: The substrate is provided, and the stacked structure and the dielectric layer are sequentially disposed on the exposed surface of the substrate; A virtual gate line slit is formed that extends through the dielectric layer, the stacked structure, and the substrate; The sacrificial material is filled into the virtual gate line slits; The contact structure is formed on one side of the virtual gate line slit, extending through the dielectric layer to the surface of each of the sacrificial layers, to obtain the memory array structure.

5. The method according to claim 4, characterized in that, Forming the virtual gate line slit penetrating the dielectric layer, the stacked structure, and the substrate includes: The dielectric layer, the stacked structure, and the substrate are etched sequentially to form a groove; The groove is subjected to wet oxidation to obtain the virtual gate line slit.

6. The method according to claim 4, characterized in that, The system provides the substrate, the stacked structure, and the dielectric layer arranged sequentially, including: Provide the substrate; The stacked structure is formed on the exposed surface of the substrate; Remove part of the stacked structure to form multiple continuous stepped structures; The dielectric layer is formed on the exposed surface of the stacked structure having the stepped structure.

7. The method according to claim 4, characterized in that, The sacrificial material includes carbon.

8. The method according to any one of claims 1 to 6, characterized in that, The memory array structure also includes multiple channel holes that penetrate the stacked structure into the substrate. A high-k dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially disposed within the channel holes along the direction away from the sidewalls.

9. The method according to claim 8, characterized in that, The high-K dielectric layer comprises aluminum oxide.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 9.

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