Display device, display panel, and manufacturing method thereof

Abstract

The present disclosure relates to a display device, a display panel and a manufacturing method thereof, and relates to the field of display technology. The display panel disclosed in the present disclosure includes a driving backplane, a first blocking dam, a plurality of light-emitting devices and an encapsulation layer. The driving backplane has a pixel area and a peripheral area, the peripheral area includes a peripheral area surrounding the pixel area and a lead-out area, and the peripheral area has a first power line and a second power line. The first blocking dam is provided in the peripheral area, and an interruption groove is provided between the first blocking dam and the pixel area, the interruption groove exposes the first power line, and an insulating isolation layer covering the first power line is provided in the interruption groove. The light-emitting device is provided on one side of the driving backplane, and the light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode. Each light-emitting device shares the same second electrode, and the second electrode extends into the peripheral area and is located between the interruption groove and the pixel area, and is connected to the second power line. The encapsulation layer covers the light-emitting device and includes an organic layer limited to the range surrounded by the first blocking dam.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a method for manufacturing a display panel. Background Art

[0002] Display panels have become an essential component of electronic devices such as mobile phones and computers. Organic electroluminescent display panels are particularly widely used. Currently, narrowing the display panel's bezel to increase the screen-to-body ratio and reduce issues like screen failure are pressing challenges.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and to provide a display device, a display panel and a method for manufacturing a display panel, which can improve the screen-to-body ratio while ensuring normal light emission.

[0005] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0006] A driving backplane, comprising a pixel region and a peripheral region outside the pixel region, wherein the peripheral region comprises a peripheral region surrounding the pixel region and a lead-out region outside the peripheral region, and wherein the peripheral region has a first power line and a second power line in an insulated manner;

[0007] a first barrier dam disposed in the peripheral area and surrounding the pixel area, a discontinuity groove surrounding the pixel area being provided between the first barrier dam and the pixel area, the discontinuity groove exposing at least a portion of the first power line, and an insulating isolation layer covering the first power line being provided in the discontinuity groove;

[0008] a plurality of light-emitting devices disposed on one side of the driving backplane, the light-emitting devices comprising a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the driving backplane, the light-emitting devices sharing the same second electrode, the second electrode extending into the peripheral region and being located between the discontinuous groove and the pixel region, and connected to the second power line;

[0009] The encapsulation layer covers the light emitting device and includes an organic layer defined within a range surrounded by the first barrier dam.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0011] The second barrier dam is disposed in the discontinuous groove and is stacked on the insulating isolation layer. The second barrier dam is spaced apart from the sidewall of the discontinuous groove.

[0012] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0013] The third barrier dam is provided on the same surface of the driving backplane as the light emitting device and is located in the peripheral area. The third barrier dam is located between the first barrier dam and the pixel area.

[0014] In an exemplary embodiment of the present disclosure, there are a plurality of third barrier dams, which are spaced apart and distributed between the pixel region and the first barrier dam.

[0015] In an exemplary embodiment of the present disclosure, the lead-out region and the peripheral region are distributed along a column direction, the lead-out region includes a bending region and a binding region distributed along the column direction, the bending region extends along a row direction and is separated between the peripheral region and the binding region;

[0016] The first power line includes a bus portion and a connecting portion, wherein the bus portion extends along the row direction and is located in the peripheral area between the pixel area and the bending area; the connecting portion is connected to the bus portion and extends through the bending area to the binding area;

[0017] The second power line surrounds the outside of the pixel area and extends through the bending area to the binding area; the first power line is located within the range surrounded by the second power line;

[0018] The region of the discontinuous groove located between the pixel region and the bending region exposes at least a portion of the bus portion.

[0019] In an exemplary embodiment of the present disclosure, the driving backplane includes:

[0020] substrate;

[0021] A transistor layer is provided on one side of the substrate;

[0022] a first wiring layer, provided on a surface of the transistor layer facing away from the substrate and connected to the transistor layer;

[0023] a first planar layer, covering the first routing layer;

[0024] a second wiring layer, provided on a surface of the first flat layer facing away from the substrate and connected to the first wiring layer;

[0025] a second planar layer, covering the second wiring layer;

[0026] The display panel further includes a pixel definition layer, wherein the pixel definition layer and the first electrode are provided on a surface of the second planar layer facing away from the substrate and separate the light emitting devices;

[0027] The first power line is arranged on the same layer as the first routing layer;

[0028] One of the first planar layer, the second planar layer and the pixel definition layer is disposed on the same layer as the insulating isolation layer.

[0029] In an exemplary embodiment of the present disclosure, the insulating isolation layer is provided on the same layer as the first planar layer;

[0030] The first barrier dam and the second barrier dam each include a plurality of stacked insulating layers; among the insulating layers of the first barrier dam, one insulating layer is provided on the same layer as the first planar layer, and one insulating layer is provided on the same layer as the second planar layer;

[0031] In the insulating layer of the second blocking dam, one insulating layer is disposed in the same layer as the second planar layer, and another insulating layer is disposed in the same layer as the pixel definition layer.

[0032] In an exemplary embodiment of the present disclosure, the insulating layer of the first blocking dam is disposed on the same layer as the pixel definition layer.

[0033] In an exemplary embodiment of the present disclosure, the third barrier dam is disposed in the same layer as the pixel definition layer.

[0034] In an exemplary embodiment of the present disclosure, the transistor layer includes:

[0035] a semiconductor layer, disposed on one side of the substrate;

[0036] a first gate insulating layer, covering the semiconductor layer;

[0037] a first gate layer, provided on a surface of the first gate insulating layer facing away from the substrate;

[0038] a second gate insulating layer, covering the first gate layer;

[0039] a second gate layer, provided on a surface of the second gate insulating layer facing away from the substrate;

[0040] an interlayer dielectric layer, covering the second gate layer;

[0041] The first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer are disconnected in the bending region to form a bending groove extending along the row direction, and the first planar layer fills the bending groove.

[0042] In an exemplary embodiment of the present disclosure, at least one of the width of the first barrier dam, the width of the discontinuity trench, the width of the second barrier dam, and a distance between the second barrier dam and a sidewall of the discontinuity trench is 20 μm-40 μm.

[0043] In an exemplary embodiment of the present disclosure, the width of the third barrier dam is 10 μm-40 μm.

[0044] In an exemplary embodiment of the present disclosure, the distance between the boundary of the second electrode and the discontinuous groove is 50 μm-70 μm, and the maximum distance between the first barrier dam and the bending groove is 360 μm-380 μm.

[0045] According to one aspect of the present disclosure, a method for manufacturing a display panel is provided, comprising:

[0046] A driving backplane, a first blocking dam, and a plurality of light-emitting devices are formed, wherein the driving backplane has a pixel region and a peripheral region outside the pixel region, wherein the peripheral region includes a peripheral region surrounding the pixel region and a lead-out region outside the peripheral region, wherein a first power line and a second power line are insulated; the first blocking dam is provided in the peripheral region and surrounds the pixel region, a discontinuity groove surrounding the pixel region is provided between the first blocking dam and the pixel region, the discontinuity groove exposing at least a portion of the first power line, and an insulating isolation layer covering the first power line is provided in the discontinuity groove; a plurality of light-emitting devices are provided on one side of the driving backplane, wherein the light-emitting devices include a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the driving backplane, wherein each of the light-emitting devices shares the same second electrode, which extends into the peripheral region and is located between the first blocking dam and the pixel region, and is connected to the second power line;

[0047] An encapsulation layer is formed to cover the light emitting device, wherein the encapsulation layer includes an organic layer defined within a range surrounded by the first barrier dam.

[0048] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0049] The display device, display panel and manufacturing method disclosed in the present invention can protect the light-emitting device through the encapsulation layer, and can limit the scope of the organic layer of the encapsulation layer through the first blocking dam to prevent the overflow of organic materials. At the same time, although the discontinuous groove exposes the first power line, it is covered by the insulating isolation layer. Therefore, when the second electrode is formed, even if the electrode material extending into the discontinuous groove is formed on the outside of the second electrode due to the shadow effect of the mask, the first power line will not be electrically connected to the second electrode, thereby preventing the first power line and the second power line from short-circuiting and preventing the screen from being unable to light up electrically. In this way, it is possible to avoid preventing the first power line and the second power line from short-circuiting by increasing the distance between the discontinuous groove and the pixel area. That is to say, when the distance between the discontinuous groove and the second electrode is small, the first power line and the second power line can also be prevented from short-circuiting, so that the frame of the display device corresponding to the area between the second electrode and the discontinuous groove can be narrowed, thereby facilitating the improvement of the screen-to-body ratio while ensuring normal light emission.

[0050] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0052] Figure 1 FIG. 1 is a schematic top view of an embodiment of a display panel disclosed herein.

[0053] Figure 2 for Figure 1 The AA cross-section of the panel is shown in FIG.

[0054] Figure 3 for Figure 1 A BB cross-section of the panel is shown in FIG.

[0055] Figure 4 for Figure 1 Another BB cross-section of the panel is shown in FIG.

[0056] Figure 5 for Figure 1 Another BB cross-sectional view of the display panel.

[0057] Figure 6 Schematic diagram of an embodiment of the display device disclosed herein. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0060] The row direction X and column direction Y herein are merely two mutually perpendicular directions. In the drawings of this disclosure, the row direction X may be horizontal and the column direction Y may be vertical, but the present invention is not limited thereto. If the display panel is rotated, the actual directions of the row direction X and the column direction Y may change. Figure 1 The X direction in the figure exemplarily shows the row direction, and the Y direction exemplarily shows the column direction.

[0061] The phrase "A and B are arranged in the same layer" herein means that A and B are made of the same material and can be formed simultaneously using the same process, but this does not necessarily mean that they must be formed simultaneously. Furthermore, A and B can be located on the same plane in space, or they can have depressions or projections, as long as they can be formed simultaneously.

[0062] In the related art, the display panel may include a driving backplane, and a light-emitting device is provided on one side of the driving backplane. The light-emitting device may be an organic light-emitting diode (OLED), which may include a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the driving backplane. The first electrode of each light-emitting device is distributed in an array, and the second electrode is a continuous whole-layer structure, that is, each light-emitting device shares the same second electrode. The light-emitting device may be covered with an encapsulation layer for protecting the light-emitting device. The encapsulation layer includes two inorganic layers and an organic layer located between the two inorganic layers. Since the organic layer has fluidity when it is formed and easily absorbs water and oxygen, in order to prevent it from contacting the outside world and to limit its position, an annular barrier dam may be provided on the driving backplane to confine the organic layer within the barrier dam.

[0063] The driver backplane includes a pixel region, a peripheral region surrounding the pixel region, and a lead-out region located outside the peripheral region. The peripheral region is provided with a first power line and a second power line. Pixel circuitry is disposed within the pixel region. The first power line is connected to the first electrode of the light-emitting device through the pixel circuitry, and the second power line is connected to the second electrode of the light-emitting device. Furthermore, at least a portion of the barrier dam is formed simultaneously with portions of the driver backplane film using the same process. The barrier dam has an area inside the barrier dam that exposes the first power line. When forming the second electrode through a mask, due to the shadow effect of the mask, the boundary of the electrode material exceeds the designed range of the second electrode and extends onto the exposed first power line inside the barrier dam. This causes both the first and second power lines to connect to the second electrode, resulting in a short circuit and preventing the light-emitting device from emitting properly. Because the shadow range of the mask is limited, to avoid the aforementioned short circuit, the distance between the barrier dam and the pixel region can be extended, thereby increasing the distance between the exposed first power line and the pixel region. This makes it difficult for the electrode material to contact the first power line even if it exceeds the designed range. However, when the overall size of the display panel remains unchanged, extending the distance between the barrier dam and the pixel area will increase the non-luminous area, reduce the screen-to-body ratio, and result in a wider border.

[0064] Based on the above analysis of related technologies, the embodiments of the present disclosure provide a display panel that can improve the screen-to-body ratio while ensuring normal light emission. Figure 1-Figure 3 As shown, the display panel of the present disclosure may include a driving backplane BP, a first barrier dam Dam1, a light emitting device LD and an encapsulation layer TFE, wherein:

[0065] The driving backplane BP includes a pixel area PA and a peripheral area WA located outside the pixel area PA. The peripheral area WA includes an outer peripheral area EA surrounding the pixel area PA and an outfeed area FA located outside the outer peripheral area EA. A first power line VDL and a second power line VSL are insulated within the outer peripheral area WA. A first barrier dam Dam1 is provided in the outer peripheral area EA and surrounds the pixel area PA. A discontinuity trench DG is provided between the first barrier dam Dam1 and the pixel area PA, surrounding the pixel area PA. The discontinuity trench DG exposes at least a portion of the first power line VDL, and an insulating isolation layer INS is provided within the discontinuity trench DG, covering the first power line VDL. A plurality of light-emitting devices LD are provided on one side of the driving backplane BP. The light-emitting devices LD include a first electrode ANO, a light-emitting functional layer EL, and a second electrode CAT, stacked in a direction facing away from the driving backplane BP. Each light-emitting device LD shares the same second electrode CAT, which extends into the outer peripheral area EA and is located between the discontinuity trench DG and the pixel area PA. The second electrode CAT is connected to the second power line VSL. The encapsulation layer TFE covers the light emitting device LD, and includes an organic layer IJP defined within a range surrounded by the first barrier dam Dam1.

[0066] The display panel disclosed herein protects the light-emitting device LD via the encapsulation layer TFE and limits the organic layer IJP of the encapsulation layer TFE via the first barrier dam Dam1, preventing organic material from overflowing. Furthermore, although the discontinuity trench DG exposes the first power line VDL, it is covered by the insulating isolation layer INS. Therefore, when forming the second electrode CAT, even if electrode material CATr extends from the outer side of the second electrode CAT into the discontinuity trench DG due to shadowing by the mask, the first power line VDL and the second electrode CAT are not electrically connected, preventing a short circuit between the first power line VDL and the second power line VSL, thereby preventing problems such as the screen failing to illuminate. This avoids the need to increase the distance between the discontinuity trench DG and the pixel area PA to prevent a short circuit between the first power line VDL and the second power line VSL. That is, even when the distance between the discontinuity trench DG and the second electrode CAT is small, a short circuit between the first power line VDL and the second power line VSL can be prevented. This allows the display device's bezel to be narrowed in the area between the second electrode CAT and the discontinuity trench DG, thereby improving the screen-to-body ratio while ensuring normal light emission.

[0067] It should be noted that Figure 3-Figure 5 FIG3 shows the electrode material CATr formed outside the second electrode CAT and extending into the discontinuous groove DG. This is only for illustrating the beneficial effects of the present disclosure and does not mean that the electrode material CATr extending into the discontinuous groove DG must exist in the embodiments of the present disclosure.

[0068] The display panel of the present disclosure is described in detail below:

[0069] like Figure 1 As shown, the driving backplane BP may include a pixel area PA and a peripheral area WA located outside the pixel area PA. The peripheral area WA may include a peripheral area EA surrounding the pixel area PA and a lead-out area FA located outside the peripheral area EA. The peripheral area EA may be a continuous, enclosed region surrounding the pixel area PA. The lead-out area FA and the peripheral area EA may be distributed along the column direction Y and may be a region formed by partially extending the peripheral area EA. Furthermore, the lead-out area FA may include a bending area BA and a bonding area LA distributed along the column direction Y. The bending area BA extends along the row direction X and is separated from the peripheral area EA and the bonding area LA.

[0070] It should be noted that the pixel area PA and the peripheral area WA herein and the regions included therein are divided according to the functions of the regions, and it is not limited to the existence of clear physical boundaries between these regions.

[0071] like Figure 2As shown, the driving backplane BP can be formed by multiple film layers. For example, the driving backplane BP may include a substrate SU and a driving layer arranged on one side of the substrate SU. The substrate SU may be the base of the driving backplane BP, which can carry the driving layer. The substrate SU may be a hard or flexible structure, which may be a single-layer or multi-layer structure, and is not specifically limited here.

[0072] The driving layer has a driving circuit that can be used to drive each light-emitting device LD to emit light independently to display an image. The driving circuit may include a pixel circuit and a peripheral circuit. The pixel circuit may be located in the pixel area PA; of course, part of the pixel circuit may be located in the peripheral area WA. The pixel circuit may be a 7T1C, 6T1C, or other pixel circuit, as long as it can drive the light-emitting device LD to emit light, and its structure is not specifically limited here. The number of pixel circuits is the same as the number of light-emitting devices LD, and they are connected to each light-emitting device LD in a one-to-one correspondence so as to control the light emission of each light-emitting device LD separately. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). Of course, the same pixel circuit can also be connected to multiple light-emitting devices LD and drive multiple light-emitting devices LD to emit light at the same time, and there is no special limitation here.

[0073] The peripheral circuit is located within the peripheral area EA and is connected to the pixel circuit. The peripheral circuit may include a gate driver circuit, a source driver circuit, and a light-emitting control circuit. Furthermore, a first power line VDL and a second power line VSL, each insulated from each other, are provided within the peripheral area WA. The first power line VDL can be connected to each pixel circuit, thereby outputting a first power signal (VDD) to the light-emitting device LD via the pixel circuit. The second power line VSL can be connected to the second electrode CAT of the light-emitting device LD and can output a second power signal (VSS) to the light-emitting device LD. Furthermore, the peripheral circuit can output scan signals, data signals, and reset signals to the pixel circuit, thereby controlling the brightness of the light-emitting device LD. The specific driving principle of the light-emitting device LD will not be described in detail here.

[0074] The bonding area LA is provided with multiple bonding pad areas PAD. The bonding pad areas PAD can be equipped with multiple bonding pads. Peripheral circuitry, first power line VDL, and second power line VSL can all be connected to the bonding pads. The bonding pads can be bonded to a flexible circuit board, which can then be bonded to a control circuit board, allowing the display panel to display images controlled by the control circuit board. The bending area BA is flexible, allowing the lead-out area FA to be bent along the bending area BA to the side of the substrate facing away from the light-emitting device LD, thereby narrowing the bezel.

[0075] The following describes the specific structure of the driver layer:

[0076] The driving layer is formed by multiple film layers, for example, Figure 2As shown, the driving layer may include a transistor layer TL, a first wiring layer SD1, a first planar layer PLN1, a second wiring layer SD2, and a second planar layer PLN2, wherein:

[0077] like Figure 2 As shown, the transistor layer TL can be provided on one side of the substrate SU and cover the pixel area PA and the peripheral area WA. The transistors and capacitors of the driving circuit can be located in the transistor layer TL. Taking the transistor as a top-gate thin film transistor as an example, Figure 2 As shown, the transistor layer TL may include a semiconductor layer PO, a first gate insulating layer GI1, a first gate layer GA1, a second gate insulating layer GI2, a second gate layer GA2 and an interlayer dielectric layer ILD, wherein:

[0078] The semiconductor layer PO can be provided on one side of the substrate SU and can be made of polysilicon, metal oxide or other semiconductor materials. The pattern of the semiconductor layer PO depends on the distribution and connection relationship of the thin film transistors of the driving circuit and is not particularly limited here.

[0079] The first gate insulating layer GI1 may cover the semiconductor layer PO. The material of the first gate insulating layer GI1 may include inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0080] The first gate layer GA1 can be arranged on the surface of the first gate insulating layer GI1 facing away from the substrate SU, and a partial area of ​​the first gate layer GA1 is opposite to a partial area of ​​the semiconductor layer PO, that is, the orthographic projection of the first gate layer GA1 on the substrate SU and the orthographic projection of the semiconductor layer PO on the substrate SU are intersected. The first gate layer GA1 can be made of metal or other conductive materials. Taking a thin film transistor as an example, the semiconductor layer PO corresponding to the intersection area of ​​the aforementioned orthographic projection is the channel region of a thin film transistor, and the two sides of the intersection area can serve as the source and drain of the thin film transistor, and the first gate layer GA1 corresponding to the intersection area is the gate of the thin film transistor. At the same time, the first gate layer GA1 may also include a signal transmission line connecting the pixel circuit and the peripheral circuit and a plate of a capacitor. The specific pattern depends on the specific structure of the driving circuit and is not specifically limited here.

[0081] The second gate insulating layer GI2 may cover the first gate layer GA1 and the area of ​​the first gate insulating layer GI1 not covered by the first gate layer GA1. The material of the second gate insulating layer GI2 may include inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0082] The second gate layer GA2 can be disposed on the surface of the second gate insulating layer GI2 facing away from the substrate SU. The second gate layer GA2 can be made of metal or other conductive materials. The second gate layer GA2 can at least include the other plate of the pixel circuit's capacitor, thereby forming a capacitor opposite the plate of the first gate layer GA1. The second gate layer GA2 can also include signal transmission traces connecting the pixel circuit and peripheral circuits. The specific pattern depends on the specific structure of the driver circuit and is not specifically limited here.

[0083] The interlayer dielectric layer ILD may cover the second gate layer GA2 and the area of ​​the second gate insulating layer GI2 not covered by the second gate layer GA2 ; the material of the interlayer dielectric layer ILD may include inorganic insulating materials such as silicon nitride, silicon oxide and silicon oxynitride.

[0084] like Figure 2 As shown, the first wiring layer SD1 can be provided on the side of the transistor layer TL facing away from the substrate SU. For example, the first wiring layer SD1 can be provided on the surface of the interlayer dielectric layer ILD facing away from the substrate SU. The first wiring layer SD1 can be made of metal or a transparent conductive material and may include multiple wirings or connectors VDLs. At least some of the wirings and connectors VDLs can be connected to the semiconductor layer PO to achieve connections between the thin-film transistors. The specific pattern of the first wiring layer SD1 depends on the specific structure of the circuit and is not specifically limited here.

[0085] like Figure 2 As shown, the first flat layer PLN1 is arranged on the side of the first wiring layer SD1 away from the substrate SU. The first flat layer PLN1 can be made of resin or other organic materials to achieve flatness, that is, the surface of the first flat layer PLN1 away from the substrate SU is flat.

[0086] like Figure 2 As shown, the second trace layer SD2 can be provided on the surface of the first planar layer PLN1 facing away from the substrate SU and connected to the first trace layer SD1. The second trace layer SD2 can also be made of metal or other conductive materials. The specific pattern of the second trace layer SD2 depends on the specific structure of the circuit and is not specifically limited here.

[0087] like Figure 2 As shown, the second planar layer PLN2 can cover the second wiring layer SD2, and its material can be the same as that of the first planar layer PLN1 to achieve planarization.

[0088] In addition, if Figure 2 As shown, the driving circuit layer CL may further include a barrier layer BAR and a buffer layer BUF, wherein:

[0089] The blocking layer BAR may be stacked on one side of the substrate SU and cover the pixel area PA and the peripheral area WA. The blocking layer BAR may be made of inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0090] The buffer layer BUF may be disposed on the surface of the barrier layer BAR facing away from the substrate SU. Its boundary may be aligned with the boundary of the barrier layer BAR1. The material of the buffer layer BUF may also include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, but may be different from the material of the barrier layer BAR1. The semiconductor layer PO is located on the surface of the buffer layer BUF facing away from the substrate SU.

[0091] The aforementioned first gate insulating layer GI1, second gate insulating layer GI2, interlayer dielectric layer ILD, first planarizing layer PLN1, and second planarizing layer PLN2 all cover the pixel area PA and the peripheral area WA and are stacked in the bonding area LA. The first gate insulating layer GI1, second gate insulating layer GI2, and interlayer dielectric layer ILD, all made of inorganic materials, are disconnected within the bending area BA, forming a bending groove BG extending along the row direction X. This improves the flexibility of the bending area BA and prevents cracks in the inorganic material during bending. Furthermore, the bending groove BG can be a stepped groove comprising two groove segments connected sequentially in a direction away from the substrate SU. The width of the two groove segments farther from the substrate SU is greater than that of the segment closer to the substrate SU. The groove segment closer to the substrate SU penetrates the barrier layer BAR and the buffer layer BUF, while the groove segment farther from the substrate SU penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer dielectric layer ILD. The first planar layer PLN1 may extend into the bending groove BG and fill the bending groove BG. The first planar layer PLN1 may be recessed at the bending groove BG.

[0092] The first power line VDL and the second power line VSL are described in detail below:

[0093] like Figure 1 As shown, the first power line VDL and the second power line VSL are spaced apart in their orthographic projections on the substrate SU. The first power line VDL and the second power line VSL can be located in the same film layer. For example, the first power line VDL and the second power line VSL can both be located in the first wiring layer SD1. Of course, the first power line VDL and the second power line VSL can also be located in different film layers as long as they are conductive.

[0094] In some embodiments of the present disclosure, Figure 1As shown, the first power line VDL may include a bus portion VDLm and a connecting portion VDLs. The bus portion VDLm may extend along the row direction X and be located in the peripheral area EA between the pixel area PA and the bending area BA. Its length in the row direction X may be approximately equal to the width of the pixel area PA in the row direction X, and the bus portion VDLm may be connected to the pixel circuit through a plurality of power connection lines extending along the column direction Y and distributed along the row direction X. The connecting portion VDLs may be connected to the bus portion VDLm and extend through the bending area BA into the binding area LA. The connecting portion VDLs may be connected to the binding pad of the binding area LA so as to be connected to the flexible circuit board. The number of connecting portions VDLs is not specifically limited here. For example, the number of connecting portions VDLs may be two, and they may be spaced apart along the row direction X and extend along the column direction Y. In other embodiments of the present disclosure, the first power line VDL may also be around the pixel area PA.

[0095] The second power line VSL surrounds the pixel area PA and extends through the bending area BA to the binding area LA. The first power line VDL may be located within the range surrounded by the second power line VSL.

[0096] like Figure 2 As shown, the light-emitting device LD can be provided on the surface of the driving layer away from the substrate SU. For example, the light-emitting device LD can be provided on the surface of the second flat layer PLN2 away from the substrate SU. The orthographic projection of each light-emitting device LD on the substrate SU is located within the pixel area PA. The light-emitting device LD can be an organic light-emitting diode (OLED), which may include a first electrode ANO, a second electrode CAT, and a light-emitting functional layer EL located between the first electrode ANO and the second electrode CAT. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light-emitting functional layer EL can be excited to emit light. At the same time, each light-emitting device LD can be separated by a pixel definition layer PDL, thereby limiting the range of the light-emitting device LD. Wherein:

[0097] The first electrode ANO may be disposed on a surface of the second planar layer PLN2 facing away from the substrate SU. The first electrode ANO may serve as an anode of a light-emitting device LD, and the material thereof may be metal or other conductive materials.

[0098] The pixel definition layer (PDL) and the first electrodes (ANO) are disposed on the same surface of the driving backplane (BP). The pixel definition layer (PDL) includes openings that expose each first electrode (ANO), with each opening exposing one first electrode (ANO). The pixel definition layer (PDL) can be used to define individual light-emitting devices (LD), with the area corresponding to each opening corresponding to the area of ​​each light-emitting device (LD).

[0099] The light-emitting functional layer EL is at least partially located within the opening and is stacked with the first electrode ANO. The light-emitting functional layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in sequence in a direction away from the substrate SU. Of course, other structures may also be used as long as they can cooperate with the first electrode ANO and the second electrode CAT to emit light.

[0100] The light-emitting functional layer EL can be a continuous whole layer structure, which can cover the pixel definition layer PDL, extend into the opening, and be stacked with the first electrode ANO. In this case, the light-emitting color of each light-emitting device LD is the same. If color display is to be achieved, a color filter layer needs to be provided on the side of the light-emitting device LD away from the substrate SU. Each opening corresponds to a filter area, and color display is achieved through filter areas of different colors. Of course, if Figure 2 As shown, the light-emitting functional layer EL may also include a plurality of light-emitting parts distributed in an array, at least part of an area of ​​a light-emitting part is located in an opening, and each light-emitting part emits light independently, and different light-emitting parts may have different colors, so that color display can be performed directly.

[0101] The second electrode CAT can cover the light-emitting functional layer EL and can be a continuous, integral layer, allowing all light-emitting devices LD to share the second electrode CAT. Furthermore, the second electrode CAT can serve as the cathode of the light-emitting device LD and can employ a light-transmitting structure, allowing the light-emitting device LD to emit light away from the substrate SU. For example, the second electrode CAT can be made of metal such as magnesium, silver, or an alloy thereof. At a certain thickness, the second electrode CAT is both conductive and light-transmitting. Furthermore, the second electrode CAT can extend into the peripheral area EA and be connected to the second power line VSL.

[0102] In addition, if Figure 2-Figure 5 As shown, in some embodiments of the present disclosure, the display panel may further include a support layer PS, which may be provided on a surface of the pixel definition layer PDL facing away from the substrate SU and include a plurality of support pillars for supporting a mask used to form the light-emitting functional layer EL. The support layer PS may be distributed within the pixel area PA and the bonding area LA.

[0103] like Figure 2-Figure 5As shown, the encapsulation layer TFE can cover each light-emitting device LD, protecting the light-emitting device LD and preventing external water and oxygen from corroding the light-emitting device LD. For example, the encapsulation layer TFE can be implemented using thin film encapsulation, which may include a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2. The first inorganic layer CVD1 can cover the surface of the second electrode CAT facing away from the substrate SU. The organic layer IJP can be disposed on the surface of the first inorganic layer CVD1 facing away from the substrate SU, with the boundary of the organic layer IJP defined inboard of the boundary of the first inorganic layer CVD1. The boundary of the orthographic projection of the organic layer IJP on the substrate SU can extend to the peripheral area EA, ensuring that the organic layer IJP covers each light-emitting device LD. The second inorganic layer CVD2 can cover the organic layer IJP and the first inorganic layer CVD1 not covered by the organic layer IJP. The second inorganic layer CVD2 can block the intrusion of water and oxygen, and the flexible organic layer IJP can achieve planarization.

[0104] When forming the organic layer IJP, due to its fluidity, in order to limit its range, prevent it from contacting with external water and oxygen, and limit its position, a barrier dam can be used to limit its flow range. The following is a detailed description:

[0105] like Figure 3-Figure 5 As shown, the first barrier dam Dam1 can be disposed in the peripheral area EA and can be a ring-shaped structure surrounding the pixel area PA. The first barrier dam Dam1 can be formed simultaneously with at least a portion of the film layers of the driving backplane BP and the pixel definition layer PDL to simplify the process. In this manner, a discontinuity trench DG surrounding the pixel area PA exists between the first barrier dam Dam1 and the pixel area PA. This allows the first barrier dam Dam1 to be separated from other film layers and exist independently, effectively blocking the organic layer IJP. Furthermore, the discontinuity trench DG can expose at least a portion of the first power line VDL. For example, the discontinuity trench DG can expose at least a portion of the first power line VDL.

[0106] The width of the discontinuous groove DG may be 20 μm-40 μm, such as 20 μm, 30 μm, 40 μm, etc., which is not particularly limited herein. The width of the discontinuous groove DG may be the distance between the inner edge and the outer edge of its orthographic projection on the substrate.

[0107] When the second electrode CAT is formed using a mask, due to the shadow effect of the mask, the range formed by the electrode material may be larger than the designed range of the second electrode CAT, and may thus extend into the discontinuous groove DG and contact the first power line VDL, causing the first power line VDL and the second power line VSL to short-circuit. For this reason, the present disclosure provides an insulating isolation layer INS covering the first power line VDL in the discontinuous groove DG. Even if the electrode material extends into the discontinuous groove DG, it will not contact the first power line VDL, thereby preventing the first power line VDL and the second power line VSL from short-circuiting.

[0108] The first barrier dam Dam1 may include a plurality of insulating layers stacked together. Among the insulating layers Dams of the first barrier dam Dam1, one insulating layer Dams may be provided on the same layer as the first planar layer PLN1, and another insulating layer Dams may be provided on the same layer as the second planar layer PLN2. In addition, the first barrier dam Dam1 may further include an insulating layer Dams provided on the same layer as the pixel definition layer PDL. Figure 3 As shown, the first blocking dam Dam1 has three insulating layers Dams, namely the first insulating layer Dams1, the second insulating layer Dams2 and the third insulating layer Dams3. The first insulating layer Dams1, the second insulating layer Dams2 and the third insulating layer Dams3 are stacked in sequence along the direction away from the substrate SU, and the first insulating layer Dams1 is arranged on the same layer as the first flat layer PLN1, the second insulating layer Dams2 is arranged on the same layer as the second flat layer PLN2, and the third insulating layer Dams3 is arranged on the same layer as the pixel definition layer PDL.

[0109] Of course, in other embodiments of the present disclosure, Figure 5 As shown, the first barrier dam Dam1 may have only two insulating layers Dams, for example, only the first insulating layer Dams1 and the second insulating layer Dams2 , but no third insulating layer Dams3 .

[0110] The width of the first barrier dam Dam1 may be 20 μm-40 μm, such as 20 μm, 30 μm, 40 μm, etc., which is not particularly limited herein. The width of the first barrier dam Dam1 may be the distance between the inner edge and the outer edge of its orthographic projection on the substrate.

[0111] To simplify the process, the insulating isolation layer INS can be provided on the same layer as the first planar layer PLN1, the second planar layer PLN2, and the pixel definition layer PDL, thereby allowing for simultaneous formation using the same process. For example, the insulating isolation layer INS can be provided on the same layer as the first planar layer PLN1. Specifically, the area of ​​the first planar layer PLN1 extending to the first barrier dam Dam1, where the first planar layer PLN1 is exposed by the discontinuity groove DG, constitutes the insulating isolation layer INS. Of course, the insulating isolation layer INS can also be an insulating film layer made of a different material than the first planar layer PLN1, the second planar layer PLN2, and the pixel definition layer PDL, as long as it can function to insulate and isolate the second power line VSL from the first power line VDL.

[0112] In some embodiments of the present disclosure, Figure 3 and Figure 4 As shown, to further prevent overflow of the organic layer IJP, a second barrier dam Dam2 may be disposed within the discontinuity trench. The second barrier dam Dam2 may be stacked on the insulating isolation layer INS, spaced apart from the sidewalls of the discontinuity trench, and may be an annular structure surrounding the pixel area PA. The second barrier dam Dam2 may include multiple stacked insulating layers Dams. Among the insulating layers Dams of the second barrier dam Dam2, one insulating layer Dams may be co-layered with the second planarization layer PLN2, and another insulating layer Dams may be co-layered with the pixel definition layer PDL.

[0113] The width of the second barrier dam Dam2 may be 20 μm-40 μm, for example, 20 μm, 30 μm, 40 μm, etc., and is not specifically limited here. The width of the second barrier dam Dam2 may be the distance between the inner edge and the outer edge of its orthographic projection on the substrate. The spacing between the second barrier dam Dam2 and the sidewall of the discontinuity groove DG may be 20 μm-40 μm, for example, 20 μm, 30 μm, 40 μm, etc., and is not specifically limited here. The spacing between the second barrier dam Dam2 and the sidewall of the discontinuity groove DG is the distance between the outer edge of the orthographic projection of the second barrier dam Dam2 on the substrate and the outer edge of the orthographic projection of the discontinuity groove DG on the substrate, and the distance between the inner edge of the orthographic projection of the second barrier dam Dam2 on the substrate and the inner edge of the orthographic projection of the discontinuity groove DG on the substrate.

[0114] In some embodiments of the present disclosure, Figure 3 and Figure 4As shown, the display panel may further include a third barrier dam Dam3, which may be disposed on the same surface of the driving backplane BP as the light-emitting device LD. For example, the third barrier dam Dam3 is disposed on the surface of the second planar layer PLN2 facing away from the substrate. The third barrier dam Dam3 is located within the peripheral area EA and between the first barrier dam Dam1 and the pixel area PA. The third barrier dam Dam3 is an annular structure surrounding the pixel area PA, which serves to block the organic layer IJP and prevent it from overflowing. There are multiple third barrier dams Dam3, spaced apart between the pixel area PA and the first barrier dam Dam1. To simplify the process, the third barrier dam Dam3 is disposed on the same layer as the pixel definition layer PDL, allowing it to be formed simultaneously with the pixel definition layer PDL.

[0115] The width of the third barrier dam Dam3 is 10 μm-40 μm, for example, 10 μm, 20 μm, 30 μm, 40 μm, etc. The width of the third barrier dam Dam3 may be the distance between the inner edge and the outer edge of its orthographic projection on the substrate.

[0116] Of course, in other embodiments of the present disclosure, Figure 5 As shown, the display panel may not be provided with the third barrier dam Dam3.

[0117] In some embodiments of the present disclosure, Figure 3-Figure 5 As shown, the display panel may further include a fourth barrier dam Dam4, which may surround the first barrier dam Dam1 and be spaced apart from the first barrier dam Dam1. If the organic layer IJP overflows outside the first barrier dam Dam1, it can be blocked by the fourth barrier dam Dam4. The fourth barrier dam Dam4 may include multiple stacked insulating layers. Among the insulating layers of the fourth barrier dam Dam4, one insulating layer may be provided on the same layer as the first planarizing layer PLN1, and another insulating layer may be provided on the same layer as the second planarizing layer PLN2. In addition, the fourth barrier layer may also include an insulating layer provided on the same layer as the pixel definition layer PDL.

[0118] In some embodiments of the present disclosure, Figure 3 As shown, the distance L1 between the boundary of the second electrode CAT and the discontinuous groove DG is 50μm-70μm, for example, 50μm, 60μm, 70μm, etc. The distance between the boundary of the second electrode CAT and the discontinuous groove DG is the distance between the outer edge of the positive projection of the second electrode CAT on the substrate and the inner edge of the positive projection of the discontinuous groove DG on the substrate.

[0119] like Figure 3As shown, the maximum distance L2 between the first barrier dam Dam1 and the bending groove BG is 360 μm-380 μm, for example, 360 μm, 370 μm, 380 μm, etc. The maximum distance L2 between the first barrier dam Dam1 and the bending groove BG is the distance between the outer edge of the orthographic projection of the first barrier dam Dam1 on the substrate SU and the edge of the projection of the bending groove BG on the substrate SU close to the pixel area PA.

[0120] like Figure 1 As shown, the distance L3 between the pixel area PA and the boundary of the second electrode CAT may be 140 μm-160 μm, for example, 140 μm, 150 μm, 160 μm, etc. The distance L3 between the pixel area PA and the boundary of the second electrode CAT is the width of the portion of the second electrode CAT located within the peripheral area EA. This width may be the designed width of the second electrode CAT, excluding the electrode material extending into the discontinuity trench DG due to the shadow effect of the mask.

[0121] Based on the value ranges of width and distance in the above text, the distance between the pixel area PA and the bending groove BG can be 620 μm, while the distance between the pixel area PA and the bending groove BG of the display panel adopting this solution is generally 1200 μm. It can be seen that the present disclosure can significantly shorten this distance, thereby reducing the width of the lower frame (corresponding to the frame of the lead-out area FA) without causing a short circuit between the first power line VDL and the second power line VSL.

[0122] In some embodiments of the present disclosure, the display panel may further include a touch layer, which may be arranged on the side of the encapsulation layer TFE facing away from the substrate SU. For example, the touch layer may be arranged on the surface of the encapsulation layer TFE facing away from the substrate SU. The touch layer may adopt a self-capacitive or mutual-capacitive touch structure, or may adopt other touch principles such as ultrasonic waves, which are not specifically limited here.

[0123] The present disclosure provides a method for manufacturing a display panel. The structure of the display panel can refer to the embodiment of the display panel above and will not be described in detail here. The manufacturing method of the present disclosure may include:

[0124] A driving backplane BP, a first barrier dam Dam1, and a plurality of light-emitting devices LD are formed. The driving backplane BP has a pixel area PA and a peripheral area WA located outside the pixel area PA. The peripheral area WA includes a peripheral area EA surrounding the pixel area PA and a lead-out area FA located outside the peripheral area EA. The peripheral area WA has an insulated first power line VDL and a second power line VSL. The first barrier dam Dam1 is provided in the peripheral area EA and surrounds the pixel area PA. A discontinuity trench DG surrounding the pixel area PA is provided between the first barrier dam Dam1 and the pixel area PA. The discontinuity trench DG exposes at least a portion of the first power line VDL, and an insulating isolation layer INS covering the first power line VDL is provided in the discontinuity trench DG. The plurality of light-emitting devices LD are provided on one side of the driving backplane BP. The light-emitting devices LD include a first electrode ANO, a light-emitting functional layer EL, and a second electrode CAT stacked in a direction away from the driving backplane BP. Each light-emitting device LD shares the same second electrode CAT. The second electrode CAT extends into the peripheral area EA and is located between the first barrier dam Dam1 and the pixel area PA, and is connected to the second power line VSL.

[0125] An encapsulation layer TFE is formed to cover the light emitting device LD, and includes an organic layer IJP defined within a range surrounded by the first barrier dam Dam1.

[0126] It should be noted that although the steps of the manufacturing method disclosed herein are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0127] The present disclosure further provides a display device, which may include a display panel according to any of the above embodiments. The structure and beneficial effects thereof may be referred to in the embodiments of the display panel described above and will not be described in detail here. The display device of the present disclosure may be an electronic device such as a mobile phone, a tablet computer, or a television, which will not be listed here one by one.

[0128] In some embodiments of the present disclosure, Figure 6 As shown, the display device may include a display panel DP, a flexible circuit board FPC and a control circuit board MB, wherein:

[0129] The lead portion GP can be bent along the bending area BA so that the binding area LA is located on the side of the substrate SU away from the light-emitting device LD, and the flexible circuit board FPC can be electrically connected to the binding pad area PAD corresponding to the binding area LA, thereby binding the flexible circuit board FPC to the binding area LA.

[0130] The control circuit board MB can be electrically connected to the flexible circuit board FPC, so that the display panel DP can be controlled by the control circuit board MB to display images and implement touch functions. For example, the terminal device is a mobile phone, and the control circuit board MB is the mainboard of the mobile phone.

[0131] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: A driving backplane, comprising a pixel region and a peripheral region outside the pixel region, wherein the peripheral region comprises a peripheral region surrounding the pixel region and a lead-out region outside the peripheral region, and wherein the peripheral region has a first power line and a second power line in an insulated manner; a first barrier dam disposed in the peripheral area and surrounding the pixel area, a discontinuity groove surrounding the pixel area being provided between the first barrier dam and the pixel area, the discontinuity groove exposing at least a portion of the first power line, and an insulating isolation layer covering the first power line being provided in the discontinuity groove; a plurality of light-emitting devices disposed on one side of the driving backplane, the light-emitting devices comprising a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the driving backplane, the light-emitting devices sharing the same second electrode, the second electrode extending into the peripheral region and being located between the discontinuous groove and the pixel region, and connected to the second power line; the second electrode being located on a side of the insulating isolation layer away from the driving backplane; The encapsulation layer covers the light emitting device and includes an organic layer defined within a range surrounded by the first barrier dam.

2. The display panel according to claim 1, wherein: The display panel further includes: The second barrier dam is disposed in the discontinuous groove and is stacked on the insulating isolation layer. The second barrier dam is spaced apart from the sidewall of the discontinuous groove.

3. The display panel according to claim 2, wherein: The display panel further includes: The third barrier dam is provided on the same surface of the driving backplane as the light emitting device and is located in the peripheral area. The third barrier dam is located between the first barrier dam and the pixel area.

4. The display panel according to claim 3, wherein: There are a plurality of third barrier dams, which are spaced apart and distributed between the pixel region and the first barrier dam.

5. The display panel according to claim 1, wherein: The lead-out area and the peripheral area are distributed along the column direction, the lead-out area includes a bending area and a binding area distributed along the column direction, the bending area extends along the row direction and is separated between the peripheral area and the binding area; The first power line includes a bus portion and a connecting portion, wherein the bus portion extends along the row direction and is located in the peripheral area between the pixel area and the bending area; the connecting portion is connected to the bus portion and extends through the bending area to the binding area; The second power line surrounds the outside of the pixel area and passes through the bending area and extends into the binding area; The first power line is located within a range surrounded by the second power line; The region of the discontinuous groove located between the pixel region and the bending region exposes at least a portion of the bus portion.

6. The display panel according to claim 3, wherein: The driving backplane includes: substrate; A transistor layer is provided on one side of the substrate; a first wiring layer, provided on a surface of the transistor layer facing away from the substrate and connected to the transistor layer; a first planar layer, covering the first routing layer; a second wiring layer, provided on a surface of the first flat layer facing away from the substrate and connected to the first wiring layer; a second planar layer, covering the second wiring layer; The display panel further includes a pixel definition layer, wherein the pixel definition layer and the first electrode are provided on a surface of the second planar layer facing away from the substrate and separate the light emitting devices; The first power line is arranged on the same layer as the first routing layer; One of the first planar layer, the second planar layer and the pixel definition layer is disposed on the same layer as the insulating isolation layer.

7. The display panel according to claim 6, wherein: The insulating isolation layer is provided on the same layer as the first flat layer; The first barrier dam and the second barrier dam each include a plurality of stacked insulating layers; among the insulating layers of the first barrier dam, one insulating layer is provided on the same layer as the first planar layer, and one insulating layer is provided on the same layer as the second planar layer; In the insulating layer of the second blocking dam, one insulating layer is disposed in the same layer as the second planar layer, and another insulating layer is disposed in the same layer as the pixel definition layer.

8. The display panel according to claim 7, wherein: The insulating layer of the first blocking dam is disposed on the same layer as the pixel definition layer.

9. The display panel according to claim 7, wherein: The third barrier dam is disposed on the same layer as the pixel definition layer.

10. The display panel according to claim 6, wherein: The lead-out area and the peripheral area are distributed along the column direction, the lead-out area includes a bending area and a binding area distributed along the column direction, the bending area extends along the row direction and is separated between the peripheral area and the binding area; The transistor layer includes: a semiconductor layer, disposed on one side of the substrate; a first gate insulating layer, covering the semiconductor layer; a first gate layer, provided on a surface of the first gate insulating layer facing away from the substrate; a second gate insulating layer, covering the first gate layer; a second gate layer, provided on a surface of the second gate insulating layer facing away from the substrate; an interlayer dielectric layer, covering the second gate layer; The first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer are disconnected in the bending region to form a bending groove extending along the row direction, and the first planar layer fills the bending groove.

11. The display panel according to claim 2, wherein: At least one of a width of the first barrier dam, a width of the discontinuity trench, a width of the second barrier dam, and a distance between the second barrier dam and a sidewall of the discontinuity trench is 20 μm to 40 μm.

12. The display panel according to claim 3, wherein: The third barrier dam has a width of 10 μm-40 μm.

13. The display panel according to claim 10, wherein: The distance between the boundary of the second electrode and the discontinuous groove is 50 μm-70 μm, and the maximum distance between the first barrier dam and the bending groove is 360 μm-380 μm.

14. A method for manufacturing a display panel, characterized in that: include: A driving backplane, a first blocking dam, and a plurality of light-emitting devices are formed, wherein the driving backplane has a pixel region and a peripheral region outside the pixel region, wherein the peripheral region includes a peripheral region surrounding the pixel region and a lead-out region outside the peripheral region, wherein a first power line and a second power line are insulated; the first blocking dam is provided in the peripheral region and surrounds the pixel region, a discontinuity groove surrounding the pixel region is provided between the first blocking dam and the pixel region, the discontinuity groove exposing at least a portion of the first power line, and an insulating isolation layer covering the first power line is provided in the discontinuity groove; a plurality of light-emitting devices are provided on one side of the driving backplane, wherein the light-emitting devices include a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the driving backplane, wherein each of the light-emitting devices shares the same second electrode, which extends into the peripheral region and is located between the first blocking dam and the pixel region and is connected to the second power line; and the second electrode is located on a side of the insulating isolation layer away from the driving backplane; An encapsulation layer covering the light emitting device is formed, wherein the encapsulation layer includes an organic layer defined within a range surrounded by the first barrier dam.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13.

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