Calculate the corrected read voltage offset in non-volatile random access memory

Abstract

According to a method, a computer-implemented method for calibrating read voltages of a memory block. The computer-implemented method includes: determining the current operating state of a block comprising one or more word lines, and wherein one or more read voltages are associated with each of the word lines. Furthermore, for each word line in the block: selecting one of the read voltages associated with a given word line as a reference read voltage, and calculating an absolute shift value of the reference read voltage. Determining a relative shift value for each of the remaining read voltages associated with the given word line, wherein the relative shift value is determined relative to the reference read voltage. Furthermore, each of the absolute shift value and the corresponding relative shift value is used to adjust each of the read voltages associated with the given word line.

Description

Background Technology

[0001] This invention relates to data storage systems, and more specifically, to calibrating the read voltage of memory blocks configured in a multi-bit per cell mode in non-volatile random access memory (NVRAM).

[0002] NVRAM is a type of random access memory that retains the information stored on it even after the power is turned off, and it comes in many different forms. Using flash memory as an example, the performance characteristics of a typical NAND flash-based solid-state drive (SSD) are fundamentally different from those of a traditional hard disk drive (HDD). Data in a typical SSD is typically organized in pages of 4, 8, or 16KB. Furthermore, page read operations in an SSD are typically an order of magnitude faster than write operations, and the latency depends neither on the current position of the operation nor on its previous position.

[0003] Due to additional program / erase (P / E) cycles, charge leakage over time (i.e., data retention), and additional charge placed in the cells by read or program operations (i.e., read or program interference errors, respectively), the raw bit error rate (RBER) of a flash memory block will typically increase over time. Typically, the flash memory block is retired when any page in the block exhibits a codeword that reaches the page retirement error count limit. This limit is usually set to be implemented in conjunction with appropriate error correction codes (ECC), resulting in an uncorrectable bit error rate (UBER) after ECC is applied to the flash memory block that is set to be similar to the UBER in a traditional hard disk drive, for example, approximately 10. -15 However, it can be more or less.

[0004] Block calibration refers to algorithms that adjust read voltages. Block calibration has been shown to significantly improve read bitrate (RBER) and thus enhance endurance and retention, particularly for enterprise-class flash memory systems using modern 3D (3-D) three-level cell (TLC) or four-level cell (QLC) NAND flash memory. Previous attempts to maintain effective memory performance typically involved scanning the read voltage of each memory block or using a read voltage shifting algorithm that tracks and corrects the read voltage based on how the threshold voltage distribution changes due to cycling, retention, or other disturbances.

[0005] Ideally, the read voltage of each page in a memory block is updated individually. However, as memory capacity increases, the amount of storage consumed by maintaining the read voltage offset value for each page in each block also increases. For example, moving from 3 bits per cell in TLC NAND flash to 4 bits per cell in QLC NAND flash, each block implements 16 threshold voltage levels (instead of 8 in TLC) and 15 different read voltages (instead of 7 in TLC) to read any pages included within it. Furthermore, with improvements in vertical stacking and process technology, the number of layers in each new generation of 3-D NAND flash also increases. Subsequently, the number of pages in each block also increases. For example, current 3-D QLC NAND flash can have more than 90 layers and more than 4,000 pages per block. Therefore, if all these 15 different read voltages in 3-D QLC NAND are calibrated independently (or individually), the amount of metadata involved in storing a single set of read offset values ​​for each page or group of pages in a block and the number of calibration reads per page increase significantly.

[0006] As memory capacity continues to increase, so do the reliability issues associated with memory. Therefore, in addition to the increased number of read voltage offsets associated with each page in each block of memory, conventional calibration engines also experience an increase in processing overhead due to decreased memory reliability. Summary of the Invention

[0007] According to a method, a computer-implemented method for calibrating read voltages of a memory block. The computer-implemented method includes: determining the current operating state of a block comprising one or more word lines, and wherein one or more read voltages are associated with each of the word lines. Furthermore, for each word line in the block: selecting one of the read voltages associated with a given word line as a reference read voltage, and calculating an absolute shift value of the reference read voltage. Determining a relative shift value for each of the remaining read voltages associated with the given word line, wherein the relative shift value is determined relative to the reference read voltage. Furthermore, each of the absolute shift value and the corresponding relative shift value is used to adjust each of the read voltages associated with the given word line.

[0008] Thus, as a result of actually calculating only one of the voltage shift values, the computer-implemented method is able to determine the voltage shift values ​​of all read voltages associated with a given word line and / or page group. This significantly reduces processing overhead and performance latency while ensuring high read performance and efficient memory usage. In some cases, these significant improvements are achieved by implementing a process that recognizes the relative shifts between read voltages at certain boundaries of device operating states, for example, as will be described in further detail below.

[0009] Continuing with the computer-implemented method described above, in some cases, the process of determining the relative shift value of each of the remaining read voltages associated with a given word line includes: matching the current operating state of the block with a corresponding one of a plurality of predetermined operating states. Furthermore, the relative shift value is extracted from a predetermined voltage map assigned to the matched predetermined operating state. Additionally, depending on some cases, the predetermined voltage map corresponding to the current operating state of the block is used to determine the relative shift value of the remaining read voltage.

[0010] Therefore, a predetermined voltage map corresponding to the current operating state of the block can be used to determine the relative shift value for the remaining read voltages. For example, the current operating state of the block currently being calibrated can be matched with a corresponding one of a plurality of predetermined operating states. Furthermore, the relative shift value can be simply extracted from the predetermined voltage map assigned to the matching predetermined operating state. This ultimately allows the voltage shift value for all read voltages associated with a given word line to be determined as a result of calculating only one of the shift values, for example, as will be described in further detail below. This further reduces processing overhead and performance latency while also ensuring high read performance and efficient memory usage.

[0011] According to another method, a computer program product is used to calibrate the read voltage of a memory block. The computer program product includes a computer-readable storage medium having program instructions. Furthermore, the program instructions are readable by a processor and / or executable by a processor to cause the processor to perform the aforementioned method.

[0012] According to yet another method, a system includes: a plurality of NVRAM blocks configured to store data; a processor; and logic integrated with and / or executable by the processor. The logic is configured to, for each of the blocks: perform the aforementioned method.

[0013] According to another method, a computer-implemented method for calibrating read voltages of a memory block. This computer-implemented method includes: determining the current operating state of a block containing pages of more than one type, wherein at least one read voltage is associated with each of the page types. Furthermore, for each word line in the block: dividing the read voltages into groups based on the corresponding page type. Furthermore, for each group of read voltages in a given word line: selecting one of the read voltages in the given group as a reference read voltage. An absolute shift value of the reference read voltage is also calculated. A relative shift value is determined for each remaining read voltage in the given group, wherein the relative shift value is determined relative to the reference read voltage. Furthermore, each of the absolute shift value and the corresponding relative shift value is used to adjust each of the read voltages in the given group.

[0014] Thus, as a result of actually calculating only one of the voltage shift values, this computer-implemented method is also able to determine the voltage shift values ​​of all read voltages associated with a given word line and / or page group. This significantly reduces processing overhead and performance latency while ensuring high read performance and efficient memory usage. In some cases, these significant improvements are achieved by implementing a process that recognizes the relative shifts between read voltages at certain boundaries of device operating states, for example, as will be described in further detail below.

[0015] Other aspects and embodiments of the invention will become apparent from the following detailed description, which, when taken in conjunction with the accompanying drawings, illustrates the principles of the invention by way of example. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a non-volatile memory card based on one method;

[0017] Figure 2 This is a schematic diagram of a data storage system architecture based on one method;

[0018] Figure 3 It is based on a system diagram of one method;

[0019] Figure 4A It is based on a conceptual diagram of a method that includes block-strip and page-strip;

[0020] Figure 4B It is a partial perspective view of a 3-D non-volatile memory structure based on one method;

[0021] Figure 5 It is a graph showing the threshold voltage shift phenomenon according to one method;

[0022] Figure 6A It is based on the method flowchart of one method;

[0023] Figure 6B It is based on the method flowchart of one method;

[0024] Figure 7 It is a table that presents multiple operational states based on a single method;

[0025] Figure 8A It is a table that presents voltage mapping based on a method;

[0026] Figure 8B It is a series of tables based on page type voltage mapping, presented according to a method;

[0027] Figure 9 It is based on a network architecture of one method;

[0028] Figure 10 It is based on a method that can be used with Figure 9 The representative hardware environment associated with the server and / or client;

[0029] Figure 11 It is a hierarchical data storage system based on a method. Detailed Implementation

[0030] The following description is intended to illustrate the general principles of the invention and not to limit the inventive concepts claimed herein. Furthermore, the specific features described herein can be used in a variety of possible combinations and permutations with other described features.

[0031] Unless otherwise expressly defined herein, all terms shall be given the broadest possible interpretation, including the meaning implied in the specification and the meaning as understood by those skilled in the art and / or as defined in dictionaries, papers, etc.

[0032] It should also be noted that, as used in the specification and appended claims, unless otherwise stated, the singular forms “a,” “an,” and “the” include plural objects. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0033] The following description discloses several methods for data storage systems, their operation, and / or components. It should be understood that the various methods described herein can be implemented using various storage media, including, for example, NVRAM technologies such as NAND flash memory, NOR flash memory, phase-change memory (PCM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM). For the purpose of providing context and to assist the reader only, various methods may be described with reference to one type of non-volatile memory. This is done by way of example only and should not be considered as limiting the invention as defined in the claims.

[0034] In a general approach, a computer-implemented method is used to calibrate read voltages of a memory block. This computer-implemented method includes: determining the current operating state of a block comprising one or more word lines, and wherein one or more read voltages are associated with each of the word lines. Furthermore, for each word line in the block: selecting one of the read voltages associated with a given word line as a reference read voltage, and calculating an absolute shift value of the reference read voltage. Determining a relative shift value for each of the remaining read voltages associated with the given word line, wherein the relative shift value is determined relative to the reference read voltage. Furthermore, each of the absolute shift value and the corresponding relative shift value is used to adjust each of the read voltages associated with the given word line.

[0035] In another general approach, a computer program product is used to calibrate the read voltage of a memory block. This computer program product includes a computer-readable storage medium having program instructions. Furthermore, the program instructions are readable by a processor and / or executable by a processor to cause the processor to perform the aforementioned method.

[0036] In yet another general approach, a system includes: a plurality of NVRAM blocks configured to store data; a processor; and logic integrated with and / or executable by the processor. The logic is configured to perform the aforementioned method for each of the blocks.

[0037] In another general approach, a computer-implemented method is used to calibrate read voltages of a memory block. This computer-implemented method includes: determining the current operating state of a block containing pages of more than one type, wherein at least one read voltage is associated with each of the page types. Furthermore, for each word line in the block: dividing the read voltages into groups based on the corresponding page type. Furthermore, for each group of read voltages in a given word line: selecting one of the read voltages in the given group as a reference read voltage. An absolute shift value of the reference read voltage is also calculated. A relative shift value is determined for each remaining read voltage in the given group, wherein the relative shift value is determined relative to the reference read voltage. Furthermore, each of the absolute shift value and the corresponding relative shift value is used to adjust each of the read voltages in the given group.

[0038] Figure 1 A memory card 100 according to one method is shown. It should be noted that although the memory card 100 is depicted as an exemplary non-volatile data storage card in this method, various other types of non-volatile data storage cards may be used in the data storage system according to alternative methods. Therefore, the structure and / or components of the memory card 100 are not intended to limit the invention, but are presented as non-limiting examples.

[0039] Furthermore, as an alternative, this memory card 100 may be implemented in combination with features from any other methods listed herein, such as those described with reference to other figures. However, this memory card 100 and other memory cards presented herein can be used in various applications and / or in arrangements that may or may not be specifically described in the illustrative methods listed herein. Moreover, the memory card 100 presented herein can be used in any desired environment.

[0040] Continue to refer to Figure 1 The memory card 100 includes a gateway 102, a general-purpose processor (GPP) 112 (such as an ASIC, FPGA, CPU, etc.) connected to a GPP memory 114 (which may include RAM, ROM, battery-supported DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, etc., or combinations thereof), and multiple memory controllers 108, which in this example include flash memory controllers. Each memory controller 108 is connected via channel 106 to multiple NVRAM memory modules 104 (which may include NAND flash memory or other non-volatile memory types such as those listed above).

[0041] According to various methods, one or more of the controllers 108 may be or include one or more processors and / or any logic for controlling any subsystem of the memory card 100. For example, controller 108 typically controls the functions of the NVRAM memory module 104, such as data writing, data recycling, data reading, etc. Controller 108 may operate using logic known in the art as well as any logic disclosed herein, and therefore may be considered, in various methods, as a processor for any description of the non-volatile memory included herein.

[0042] Furthermore, controller 108 can be configured and / or programmable to execute or control some or all of the methods presented herein. Therefore, controller 108 can be considered to be configured to perform various operations through logic programmed into one or more chips, modules, and / or blocks; software, firmware, and / or other instructions available for one or more processors, and combinations thereof.

[0043] Still referencing Figure 1 Each memory controller 108 is also connected to a controller memory 110, which preferably includes a cache that replicates the non-volatile memory structure according to the various methods described herein. However, depending on the desired method, the controller memory 110 may be battery-supported DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, or a combination thereof.

[0044] As previously mentioned, depending on the desired approach, memory card 100 can be implemented in various types of data storage systems. Figure 2 A data storage system architecture 200 according to an exemplary method is shown, but it is by no means intended to limit the invention. Furthermore, it should be noted that... Figure 2 The data storage system 220 may include in Figure 1 The various components found in the method.

[0045] See Figure 2 The data storage system 220 includes multiple interface cards 202 configured to communicate with one or more processor systems 201 via I / O interconnects 204. The data storage system 220 may also include one or more independent redundant array of disks (RAID) controllers 206 configured to control data storage in multiple non-volatile data storage cards 208. The non-volatile data storage cards 208 may include NVRAM, flash memory cards, RAM, ROM, and / or some other known types of non-volatile memory.

[0046] I / O interconnect 204 may include any known communication protocol, such as Fibre Channel (FC), Ethernet FC (FCoE), Infiniband, Internet Small Computer System Interface (iSCSI), Transmission Control Protocol / Internet Protocol (TCP / IP), High Speed ​​Peripheral Component Interconnect (PCIe), and / or any combination thereof.

[0047] The RAID controller 206 in the data storage system 220 can execute a parity scheme similar to that used in RAID-5, RAID-6, and RAID-10, or some other suitable parity scheme that a person skilled in the art will understand upon reading this specification.

[0048] Each processor system 201 includes one or more processors 210 (e.g., CPU, microprocessor, etc.) and local data memory 211 (e.g., ... Figure 10 RAM 1014, Figure 10 (ROM 1016, etc.) and I / O adapter 218 configured to communicate with data storage system 220.

[0049] Refer again Figure 1 Memory controller 108 and / or other controllers described herein (e.g., memory controller 108 and / or other controllers described herein). Figure 2 The RAID controller 206 is capable of performing various functions on the stored data according to the desired method. Specifically, the storage controller may include logic configured to perform any one or more of the following functions, which are by no means intended to be an exclusive list. In other words, depending on the desired method, the logic of the storage system may be configured to perform additional or alternative functions, as will be understood by those skilled in the art upon reading this specification.

[0050] garbage collection

[0051] Garbage collection in the context of the SSD memory controller described herein may include the process of identifying data blocks to be reclaimed for future use and relocating all pages still valid within them. Furthermore, depending on the specific controller and / or the corresponding garbage collection operation unit, logical erase blocks (LEBs) may be identified for reclamation and / or relocation. Typically, one LEB corresponds to one block stripe, but alternative implementations may consider constructing a fixed number of block stripes with LEBs.

[0052] A physical "block" represents the smallest unit of non-volatile memory (e.g., NAND flash) that can be erased and is thus ready to be written to. However, a typical garbage collection operation unit is usually multiple physical blocks of non-volatile memory, and is also referred to here as a LEB. This is because parity information, similar to RAID, is added to the LEB. Therefore, in the event of a page or block failure, data can only be reconstructed if all blocks in the LEB still retain data. Thus, once all still valid data from all blocks in the LEB has been successfully relocated to a new location, individual blocks from the garbage collection unit can only be erased individually or as a single unit. Therefore, a complete garbage collection unit is garbage collected as a single unit. Furthermore, the size of the LEB directly affects the write amplification caused by garbage collection. The larger the LEB, the greater the likelihood that irrelevant data is stored together in the LEB, and therefore more LEB data may have to be relocated during garbage collection.

[0053] Typically, blocks from different chips and / or flash channels are grouped together, allowing blocks from the same group to be read or written in parallel, thus increasing the total bandwidth. The two methods mentioned above can also be combined, using blocks from different flash channels that can be accessed in parallel to form RAID stripes.

[0054] It should also be noted that an LEB can include any number of physical memory blocks as physical erase units. Furthermore, organizing memory blocks as LEBs not only allows for the addition of RAID-like parity protection schemes between memory blocks from different memory chips, memory planes, and / or channels, but also allows for significant performance enhancements through greater parallelism. For example, multiple non-volatile memory blocks can be grouped together in a RAID stripe. Those skilled in the art will understand upon reading this specification that RAID schemes generally improve reliability and reduce the probability of data loss.

[0055] The exemplary method is by no means intended to limit the invention; the memory controller (e.g., see...) Figure 1108) can perform garbage collection internally. As previously described, garbage collection may include selecting LEBs to be relocated, after which all data still valid on the selected LEBs may be relocated (e.g., moved). After the still valid data has been relocated, the LEBs can be erased and subsequently used to store new data. The amount of data relocated from the garbage-collected LEBs determines the write amplification. Furthermore, an efficient way to reduce write amplification includes implementing heat segregation.

[0056] thermal isolation

[0057] In this context, "hot writes" refers to the rate (e.g., frequency) at which data is updated (e.g., rewritten with new data). Memory blocks considered "hot" tend to have frequent update rates, while memory blocks considered "cold" have slower update rates than hot blocks.

[0058] Tracking write heat for logical pages may involve, for example, allocating a specific number of bits in the logical-to-physical table (LPT) mapping entry of the page to track how many write operations the page has undergone within a specific time period or window. Typically, host write operations increase write heat, while internal relocation writes decrease write heat. The actual increase and / or decrease in write heat can be deterministic or probabilistic.

[0059] Similarly, a specific number of additional bits in the LPT of each logical page can be used to track read heat. To reduce metadata, read heat can also be tracked at the physical block level, where a separate counter can be maintained for each block for straddling and non-straddling reads. However, it should be noted that when determining memory block heat using certain methods, the number of read requests and / or read operations performed on a memory block may not contribute to heat isolation. For example, a high read frequency does not necessarily mean a high update rate for a particular memory block if data is read frequently. Conversely, a high frequency of read operations performed on a given memory block can indicate the importance, value, etc., of the data stored in the memory block.

[0060] Write thermal isolation can be achieved by grouping memory blocks with the same and / or similar write hot values. Specifically, the write thermal isolation method can group hot write memory pages together in some memory blocks, while grouping cold write memory pages together in other memory blocks. Therefore, the write thermal isolation LEB is often occupied by either hot or cold write data.

[0061] The advantages of write hot isolation are twofold. First, performing garbage collection on write-hot memory blocks also prevents the relocation of write-cold data. Without hot isolation, frequent updates to write-hot data also lead to undesirable relocations of all write-cold data co-located with the hot data on the same LEB. Therefore, for methods implementing write hot isolation, write amplification caused by garbage collection is much lower.

[0062] Secondly, the relative write heat of data can be used for wear leveling purposes. For example, hot-write data can be placed in healthier (e.g., younger) memory blocks, while cold-write data can be placed in less healthy (e.g., older) memory blocks relative to those healthier blocks. Thus, the rate at which relatively older blocks wear out is effectively slowed down, thereby improving the overall durability of a given data storage system that achieves write heat isolation.

[0063] Write allocation

[0064] Write allocation involves placing the data to be written into a free space within an open LEB. Once all pages in an LEB have been written, the LEB is closed and placed in a pool that holds occupied LEBs. Typically, LEBs in the occupied pool become eligible for garbage collection. The number of open LEBs is usually limited, and any closed LEB can be replaced immediately or after a certain delay by a newly opened LEB.

[0065] During execution, garbage collection can occur simultaneously with user write operations. For example, when a user (e.g., a host) writes data to the device, the device controller can continuously perform garbage collection on LEBs containing invalid data to make room for new incoming data pages. As mentioned above, the LEB on which garbage collection is being performed will typically have some pages that are still valid at the time of the garbage collection operation; therefore, these pages are preferably relocated (e.g., written) to a new LEB.

[0066] Furthermore, the foregoing functionality is in no way intended to limit the capabilities of any storage system described and / or suggested herein. Rather, the foregoing functionality is presented by way of example, and depending on the desired approach, the logic of the storage system may be configured to perform additional or alternative functionality, as will be understood by those skilled in the art upon reading this specification.

[0067] Now for reference Figure 3System 300 is illustrated according to one method. Alternatively, system 300 may be implemented in combination with features from any other methods listed herein, such as those described with reference to other accompanying figures; however, such system 300 and other systems presented herein can be used in a variety of applications and / or in arrangements that may or may not be specifically described in the illustrative methods listed herein. Furthermore, system 300 presented herein can be used in any desired environment, such as in combination with a controller.

[0068] As shown in the figure, system 300 includes a write cache 302 coupled to several other components including a garbage collector 304. As previously described, garbage collector 304 can be used to free up LEB cells by relocating valid data and providing non-volatile memory blocks to be erased for later reuse. Therefore, garbage collector 304 can reclaim blocks of contiguous physical space according to a desired method. According to an exemplary method, a block erasure unit can be used to track and / or complete the erasure of non-volatile memory blocks handed over by garbage collector 304.

[0069] The write cache 302 is also coupled to the free block manager 306, which can track free non-volatile memory blocks after they have been erased. Furthermore, as those skilled in the art will recognize upon reading this description, the free block manager 306 can use erased free non-volatile memory blocks to create free stripes of non-volatile memory blocks from different channels (e.g., block stripes).

[0070] Still referencing Figure 3 The write cache 302 is coupled to the LPT manager 308 and the memory I / O unit 310. The LPT manager 308 maintains a logical-to-physical mapping of logical addresses to physical pages in memory. According to one example, which is by no means intended to limit the invention, the LPT manager 308 may maintain a logical-to-physical mapping of 4 KiB logical addresses. The memory I / O unit 310 communicates with the memory chip to perform low-level operations, such as reading one or more non-volatile memory pages, writing non-volatile memory pages, erasing non-volatile memory blocks, etc.

[0071] To better understand the difference between block-strip and page-strip as used in this article Figure 4AThis is based on a conceptual diagram 400 of one method. The LEB is constructed from block strips, and typically a single block strip is used to construct the LEB. However, alternative methods may use multiple block strips to form the LEB. Alternatively, this conceptual diagram 400 can be implemented by combining features from any other methods listed herein, such as those described with reference to other accompanying figures; however, such a conceptual diagram 400 and other conceptual diagrams presented herein can be used for various applications and / or permutations, which may or may not be specifically described in the illustrative methods listed herein. Furthermore, the controller conceptual diagram 400 presented herein can be used in any desired environment. Therefore, Figure 4A The exemplary non-volatile memory controller concept diagram 400 can be implemented in a cache architecture. However, depending on the desired approach, Figure 4A Conceptual diagram 400 can be implemented when defining the organization of data stored in non-volatile memory. Therefore, two implementation methods are described below in turn.

[0072] Non-volatile memory

[0073] Looking at it now Figure 4A Conceptual diagram 400 includes a set of M+1 aggregation planes, labeled "Plane 0" to "Plane M". An aggregation plane consists of all physical planes that have the same plane index on different channels. It should be noted that aggregation planes are also simply referred to as planes here.

[0074] When implemented using data stored in non-volatile memory, each physical plane on a channel can include a large set of blocks, typically on the order of 1024, 2048, or larger. Additionally, one or more physical planes may contain several extra blocks that can be used as replacement blocks for bad blocks (e.g., poorly performing blocks, blocks with undesirable characteristics, etc.).

[0075] In each plane of a nonvolatile memory, individual blocks from each channel form a corresponding block stripe. Therefore, the number of block stripes supported by a given method of nonvolatile memory can be determined by the number of blocks per plane and the number of planes.

[0076] In the exploded view of plane 0, concept diagram 400 further illustrates a single block stripe (block stripe 0) from the set of block stripes supported in the remaining planes. Block stripe 0 of plane 0 is shown as comprising 11 blocks, one block for each channel labeled "Channel 0" to "Channel 10". It should be noted that the association between blocks and block stripes can change over time, as block stripes are typically decomposed after they have been garbage collected. Erased blocks can be placed in a free block pool, whereby a new block stripe is assembled from blocks in the free block pool when a write allocation requests a new block stripe. For example, referring to concept diagram 400, block 10 from channel 0 and block 41 from channel 4 are currently associated with the shown block stripe 0 of plane 0. Furthermore, the shown block stripe 0 holds N+1 page stripes, and each block therefore holds N+1 pages labeled "Page 0" to "Page N".

[0077] Cache architecture

[0078] Still referencing Figure 4A When implemented in a cache architecture, each page block shown in the decomposition diagram of aggregation plane 0 can constitute a unique block from a channel. Similarly, each channel contributes a single, independent block that forms a block stripe. For example, referring to conceptual diagram 400, block 10 from channel 0 includes all pages within it (pages 0 to N), while block 41 from channel 4 corresponds to all pages within it, and so on.

[0079] In the context of a memory controller, for example, one capable of implementing RAID at the channel level, a block stripe consists of multiple blocks, which is equal to one stripe of a block. See also... Figure 4A Multiple blocks of aggregation plane 0 constitute block stripe 0. Although all blocks in a block stripe typically belong to the same aggregation plane, in some methods, one or more blocks of a block stripe may belong to different physical planes. Thus, each aggregation plane may include one or more block stripes. Therefore, according to the illustrative method, blocks 0 to 10 from different physical planes can constitute a block stripe.

[0080] in spite of Figure 4A Whether conceptual diagram 400 is implemented using a non-volatile memory and / or cache architecture, the number of pages in each block and / or the number of channels in each plane can vary depending on the desired approach in different methods. According to one exemplary method, which is by no means intended to limit the invention, a block may include 1024 pages, but may include more or fewer pages in various methods. Similarly, the number of channels per plane and / or the number of planes can vary depending on the desired approach.

[0081] Still referencing Figure 4AA page stripe is a collection of all pages with the same page index within a block stripe. For example, page stripe 0 comprises the first page (page 0) of each channel in block stripe 0 of plane 0, and similarly, page stripe N comprises the last page (page N) of each channel in block stripe 0 of plane 0.

[0082] In some methods, Figure 4A The general memory architecture shown in conceptual diagram 400 is also implemented using a 3-D memory structure. For example, Figure 4B A representative view of a 3-D non-volatile memory structure 450 according to one method is depicted. Alternatively, this structure 450 can be implemented by combining features from any other methods listed herein, for example, with reference to other figures (e.g., Figure 4A The structures described herein are not included here. However, such structure 450 and other structures presented herein can be used in a variety of applications and / or substitutions, which may or may not be specifically described in the illustrative methods listed herein. Furthermore, structure 450 presented herein can be used in any desired environment. Therefore, Figure 4B (and other graphs) can be considered to include any possible permutations.

[0083] As shown in the figure, each layer 452 of the 3-D non-volatile memory structure 450 extends along the x-axis and y-axis. Each of these layers 452 contains multiple memory components (not shown), such as voltage supply lines, sensor stacks, transistors, etc., which are used for implementation Figure 4A The conceptual diagram 400 illustrates a general memory architecture for a non-volatile memory device, as those skilled in the art will understand after reading this description. Furthermore, the layers 452 are arranged in a stacked manner along the z-axis to increase storage density and efficiency. (The last sentence appears to be incomplete and possibly refers to a different concept.) Figure 4B Cells of different bit lines (in the x or y dimension) are logically combined to form pages. Therefore, each block includes multiple word lines, and each word line has multiple read voltages associated with it. For example, in TLC, each word line in a block contains three physical pages (e.g., a lower page, an upper page, and an extra page), and the word line typically belongs to a specific layer in the z dimension (perpendicular to the xy plane).

[0084] For a given block formed by a grid of cells connected by word lines and bit lines, the number of word lines on the same layer is typically small. Therefore, a block can be formed by word lines from all layers 452. Furthermore, word lines and pages within the same block can reside on different layers 452. It should also be noted that a block contains more than one type of page (e.g., top page, bottom page, extra page, top page), and at least one read voltage is associated with each of these page types, as will be understood by one of those skilled in the art upon reading this description.

[0085] Furthermore, due to cycling, holding, read interference, programming interference, or other mechanisms specific to 3D NAND flash technology (e.g., floating gate or charge trap based technologies), processing technology, cell and material design, circuit and array architecture, or other specific design factors, the programmable threshold voltage distribution in a memory block can change with the relatively slow or fast writing and erasing of data (cycling), reading of data (read interference), time (holding), etc. In other words, the RBER of a flash memory block increases with time and use. Each P / E cycle performed on a memory block while it is in use results in the damage of memory cells, which in turn increases the corresponding RBER.

[0086] Block calibration is an important aspect of enhancing the durability and retention of flash memory storage systems (e.g., especially enterprise-class flash systems) by reducing the RBER experienced. This block calibration corresponds to the read voltage and refers to an algorithm that can track changes in the threshold voltage distribution and adjust the read voltage accordingly, thereby significantly reducing bit errors and improving performance consistency in the corresponding device by reducing the read tail latency that would otherwise be caused by the error recovery mechanism call.

[0087] Furthermore, an adjustment to the read voltage is applied accordingly during the read command. The threshold voltage represents the voltage associated with the transistor turning on a given flash memory cell, and its value depends on the amount of charge stored during programming. However, the read voltage is a bias voltage, and its value is typically between the threshold voltages of two adjacent logic states, for example, as described below. Figure 5 The following is a further detailed explanation.

[0088] For reference only Figure 5 The example illustrates a graph 500 showing the threshold voltage shift phenomenon. The x-axis of graph 500 represents the programmed threshold voltage V. TH The y-axis represents the cell count of a QLC NAND flash memory block. In QLC NAND flash memory, each cell stores 4 bits of information; therefore, V... TH The distribution corresponds to 16 possible discrete levels (L0, L1, ..., L15). Furthermore, each different type of page in a given block of QLCNAND flash memory has a different set of read voltages corresponding to it. According to one example (which is by no means intended to limit the invention), the lower pages correspond to read voltage V8, the upper pages correspond to read voltages V4 and V12, the additional pages correspond to read voltages V2, V6, V10, and V14, and the top page corresponds to read voltages V1, V3, V5, V7, V9, V11, V13, and V15.

[0089] The solid line distribution 502 indicates the V after programming. TH Level. The vertical solid line 504 indicates the voltage level for V. THDistribution 502 shows the optimal read voltage (V1, ..., V15). The dashed distribution 506 indicates the V voltage loss due to charge over time. TH A negative shift of the level. Due to this negative shift to a lower voltage, the read voltage 504 is no longer optimal. In fact, a negative offset must be applied to the read voltage to account for V. TH The distribution changes from 502 to 506. The vertical dashed line 508 indicates the V value in 506. TH The optimal read voltage (V1, ..., V15) is determined during the holding period of the distribution. Typically, each of the 16 levels (L0, L1, ..., L15) shown in the diagram can have a different V. TH The shifting allows each of the 15 read voltages (V1, ..., V15) to have a different optimal shift.

[0090] Therefore, the read voltage shift value (or offset value) is preferably determined periodically shortly after and / or after the block is written. The threshold voltage can be considered as an exponent of the cell programming level (i.e., L0, L1, ..., L15), as determined by measuring the source-drain current when a control gate bias is applied to the memory cell. Typically, during a read operation, one or more read voltages between adjacent nominal threshold voltage levels are used to determine the cell state. When the threshold voltage value of the memory cell changes (as described above), the read voltage applied during the read operation is preferably shifted accordingly using a set of offset values ​​to obtain optimal read conditions and minimize RBER. Subsequently, the optimal read voltage shift value can be updated periodically, for example, during a background health check, or as needed, for example, in the case of high bit error count or ECC failure.

[0091] While increases in RBER are irreparable for some blocks (e.g., those caused by prolonged P / E cycles), increases in RBER caused by events such as hold and / or read disturbances are transient in the sense that the affected block is not irreversibly damaged. This adverse increase in RBER is remedied when the corresponding memory block is recalibrated to correct the corresponding read voltage. In other methods, blocks experiencing transient RBER increases can be remedied by erasing, programming, and recalibrating. Therefore, it is clear that the RBER of a block depends on the block's state, which can be determined by the cycle state, hold state, read disturbance state, and / or any combination thereof. Block recalibration improves RBER by adjusting the read voltage, making them more resistant to permanent and / or transient effects. TH It is optimal under various distribution variations.

[0092] Ideally, the read voltage of each page in a memory block is updated individually. However, as memory capacity increases, the amount of storage consumed by maintaining the read voltage offset value for each page in each block also increases. For example, moving from 3 bits per cell in TLC NAND flash to 4 bits per cell in QLC NAND flash, each block implements 16 threshold voltage levels (instead of 8 in TLC) and 15 different read voltages (instead of 7 in TLC) to read any pages included within it. Furthermore, with improvements in vertical stacking and process technology, the number of layers in each new generation of 3-D NAND flash memory has increased. Subsequently, the number of pages in each block has also increased. For example, current 3-D QLC NAND flash memory can have more than 90 layers and more than 4,000 pages per block. Therefore, if all these 15 different read voltages in 3-D QLC NAND are calibrated independently (or individually), the amount of metadata involved in storing individual read offset value sets for each page or group of pages in a block and the number of calibration reads per page increase significantly.

[0093] As memory capacity continues to increase, so do the reliability issues associated with memory. Therefore, in addition to the increased number of read voltage offsets associated with each page in each block of memory, conventional calibration engines also experience an increase in processing overhead due to decreased memory reliability.

[0094] In stark contrast to the increasingly inefficient ways traditional memory systems manage memory performance, the various methods presented in this paper can significantly reduce calibration overhead while also improving read performance. In some methods, these improvements are achieved by reducing the number of read operations performed during memory calibration, as will be described in further detail below.

[0095] Now for reference Figure 6A A flowchart of a method 600 for calibrating the read voltage of a memory block configured in a multi-bit-per-cell mode is shown. According to the invention, method 600 can be used in... Figure 1-5 The method can be executed in any environment described herein, wherein it can be executed in various ways. For example, any process included in method 600 can be executed relative to a block of storage space in NVRAM, such as 3-D TLC NAND flash memory, 3-D QLC NAND flash memory, etc., or any other desired type of memory. Furthermore, as those skilled in the art will understand upon reading this specification, method 600 may include more than Figure 6A The specific operations described in the text may include more or fewer operations.

[0096] Each step of method 600 can be performed by any suitable component of the operating environment. For example, in various methods, method 600 can be performed partially or entirely by a controller (e.g., a flash memory controller), a processor, a computer, or some other device having one or more processors. Thus, in some methods, method 600 can be a computer-implemented method. It should also be noted that the terms computer, processor, and controller are used interchangeably with respect to any method herein, and such components are considered equivalent in many different arrangements of the invention.

[0097] Furthermore, for those methods that have a processor, the processor is, for example, a processing circuit, chip, and / or module implemented in hardware and / or software, and preferably has at least one hardware component that can be used in any device to perform one or more steps of method 600. Illustrative processors include, but are not limited to, central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations thereof, or any other suitable computing device known in the art.

[0098] like Figure 6A As shown, operation 602 of method 600 includes proceeding to the next memory block. Regarding this specification, "next memory block" can vary depending on the given method. For example, when initiating method 600, the next memory block can simply be the first memory block. In other methods, the next memory block can be the next memory logical block. Furthermore, operation 602 can be performed between memory blocks in any desired manner, such as sequentially, randomly, by usage pattern, etc. Additionally, operation 602 can be triggered periodically by a background process that checks all NAND blocks, for example, every week, or can be triggered when needed, such as when page reads in the block present a high-bit error count or an ECC failure. Furthermore, the memory preferably includes NVRAM. For example, in some methods, the memory includes 3-D TLC NAND flash memory, while in other methods, the memory includes 3-D QLC NAND flash memory.

[0099] Decision 604 also includes determining whether a given memory block should be recalibrated. In some methods, criteria can be implemented to identify when and whether a particular block should be recalibrated. For example, a block can be recalibrated after a predetermined number of P / E cycles (e.g., 500 P / E cycles), after experiencing undesirable low performance metrics (e.g., the number of bit errors exhibiting a predetermined error count threshold), after a predetermined amount of time has elapsed since the last recalibration, etc. This allows for some reduction in the amount of computational overhead experienced, for example, as those skilled in the art will understand after reading this description.

[0100] In response to determining that a given memory block should not be recalibrated for any reason, method 600 returns to operation 602, thereby proceeding to the next block, and then repeating decision 604. However, in response to determining that a given memory block should be recalibrated, method 600 proceeds to operation 606. There, operation 606 includes determining the current operating state of the given memory block.

[0101] This operational state can be determined based on various types of available information, such as statistics corresponding to the block. For example, block statistics, including P / E cycle counter values, read interference counter values, the amount of hold time maintained by a hold timer, open / closed block states (i.e., whether a given block is partially or fully programmed), the number of programmed pages in the block, operating temperature, etc., can be used to determine the current operational state of the block. An illustrative list of the current operational states that a given block of memory may be experiencing includes (but is by no means limited to) hold states, read interference states, cycle states, open and / or closed states (e.g., whether some or all pages in the block have been programmed), and / or any combination thereof.

[0102] The operating states that a given block may be experiencing can provide a description of the threshold voltage. Figure 5 The states of L0-L15 in the block and thus describe the corresponding read voltages for a given block. Figure 5 The information required for adjustments (V1-V15) is as follows. This is primarily because the threshold voltages of a given word line undergo similar loss mechanisms when exposed to the same or similar operating conditions, at least relative to each other, and therefore the corresponding read voltages require similar shifts or adjustments. In other words, each of the threshold voltages of a given word line will undergo a corresponding shift in response to experiencing a given set of operating conditions. While these shifts are not typically the same value for each threshold voltage within the same word line, the relative differences between them are predictably repeatable. For example, whenever a word line subsequently encounters the same or similar set of operating conditions, it can be predicted that the relative threshold voltage shift experienced by each corresponding threshold voltage, and the relative read voltage shift that causes the threshold voltage shift, will be the same as previously encountered.

[0103] According to one example, which is by no means intended to limit the invention, tests performed on a given block B reveal that, when in a specific operating state S1, the first read voltage experiences a shift of -4, the second read voltage experiences a shift of -8, and the third read voltage experiences a shift of -2. The relationship between each of these shift values ​​can thus be stored in memory, indicating that for operating state S1, block B reacts such that the first read voltage experiences a shift that is half the shift of the second read voltage, and the third read voltage experiences a shift that is one-quarter the shift of the second read voltage. Therefore, the next time block B experiences operating state S1, it can be predicted that the first, second, and third read voltages will experience the same relative shifts without performing any calibration, calculation, etc. Similarly, another block C having the same operating state S1 can also benefit from such a prediction that its first, second, and third read voltages will experience the same relative shifts as block B, without performing any calibration, calculation, etc.

[0104] Therefore, a block can be tested in multiple different operating states to determine the relative changes that occur for each of its read voltages. These relative changes can also be stored in memory (e.g., as a predetermined voltage mapping in a lookup table), making it easy to retrieve the read voltage shift values ​​of blocks in the same or similar operating states from memory, for example, as will be described in further detail below. Although relative read voltage shifts can be stored in memory for future use, these read voltage shifts are only represented relative to each other. Therefore, relative read voltage shifts cannot determine any actual read voltage shift values ​​that have been experienced. However, by calculating the actual read voltage shift value of one read voltage, relative read voltage shifts can be used to infer the actual read voltage shift values ​​of the remaining read voltages, for example, as will soon become apparent.

[0105] Return again Figure 6A Method 600 proceeds from operation 606 to operation 608. There, operation 608 involves proceeding to the next word line in the currently evaluated block. As previously stated, the "next word line" can vary depending on the given method. For example, during the initial iteration of operation 608, the next word line of the block could simply be the first word line. In other methods, the next word line could be the next logical word line in the block. Furthermore, operation 608 can proceed between word lines in any desired manner, such as sequentially, randomly, using a pattern, etc.

[0106] Operation 610 further includes selecting one of the read voltages associated with a given word line as a reference read voltage, while operation 612 includes calculating an absolute shift value of the reference read voltage. As described above, by calculating the actual read voltage shift value (here, the "absolute shift value") of one read voltage (the "reference read voltage"), the relative read voltage shift can be used to infer the actual read voltage shift values ​​of the remaining read voltages.

[0107] For example, depending on the desired method, any of the read voltages associated with a given word line can be selected as the reference read voltage. For instance, in some methods, the rightmost read voltage (e.g., the highest read voltage) can be selected as the reference read voltage, while in others, the leftmost read voltage (e.g., the lowest read voltage) can be selected. In other methods, a random read voltage of the word line, a read voltage predicted to experience the maximum voltage shift value of the word line, a read voltage selected by the user, etc., can be selected as the reference read voltage. The absolute shift value of the reference read voltage can also be calculated using any process that will become apparent to those skilled in the art after reading this description.

[0108] Proceeding to operation 614, method 600 includes determining a relative voltage shift value for each of the remaining read voltages associated with a given word line. As mentioned above, the relative shift value of the read voltage associated with a given word line is preferably known based on testing, modeling, analysis of past performance, etc. Thus, the absolute shift value of a reference read voltage can be used in conjunction with the relative shift value to infer the actual read voltage shift value of the remaining read voltage. In other words, the relative shift value is determined relative to a reference read voltage.

[0109] In some methods, the relative shift value is incorporated into a predetermined voltage map. For a given operating state of the primary block, the predetermined voltage map associates the relative shift value with each of the corresponding read voltages. For example, temporarily referencing... Figure 8A Table 800 depicts an illustrative voltage mapping. As shown, each operating state s1, s2, ..., sN has a plurality of relative shift values ​​(e.g., a(2, 5)). Each relative shift value is further associated with a corresponding read voltage (e.g., V5).

[0110] Therefore, in operation 614 of method 600, a predetermined voltage mapping corresponding to the current operating state of the block can be used to determine the relative shift value of the given word line for the remaining read voltage. For example, the current operating state of the block currently being calibrated can be matched with a corresponding one of a plurality of predetermined operating states, such as... Figure 8AAs seen in Table 800. Furthermore, the relative shift value can be simply extracted from a predetermined voltage map assigned to the matching predetermined operating states. This ultimately allows the voltage shift value of all read voltages associated with a given word line to be determined as a result of calculating only one of the shift values, for example, as will be described in further detail below. This significantly reduces processing overhead and performance latency while also ensuring high read performance and efficient memory usage.

[0111] Continue to refer to Figure 6A Operation 616 includes adjusting each of the read voltages associated with a given word line using each of an absolute shift value and a corresponding relative shift value. As described above, the relative shift value is an absolute shift value calculated relative to a reference read voltage. Therefore, each of the read voltages (except the reference read voltage) can be adjusted by applying the corresponding relative shift value to the absolute shift value and then applying the resulting shift value to the given read voltage.

[0112] Returning to the example presented above regarding block B, the second read voltage can be designated as the reference read voltage. As a result, an absolute shift value of -8 will be calculated for the second read voltage, indicating that a shift of -8 should be applied to its read voltage. Using this absolute shift value of -8, the relative shift value of 1 / 2 of the first read voltage and the relative shift value of 1 / 4 of the third read voltage indicate that an actual shift value of -4 should be applied to the first read voltage, while an actual shift value of -2 should be applied to the third read voltage.

[0113] In some methods, during operation 616, an absolute shift value is also applied to the reference read voltage. However, in other methods, the absolute shift value may be applied to the reference read voltage as part of the calculation performed in operation 612 above. The absolute shift value and / or other resulting shift values ​​may be applied to the corresponding read voltage in a manner that will be apparent to those skilled in the art upon reading this description. For example, in some methods, the shift value may be stored in memory, sent to a memory controller for application, used to actually adjust the corresponding read voltage, etc.

[0114] The method proceeds from operation 616 to operation 618, which includes incrementing the word line counter. As described above, method 600 is preferably used to calibrate various blocks in the memory, and to calibrate each word line in each block. Thus, the word line counter can be used to track how many word lines have been evaluated in a given block. It should also be noted that, for example, according to this method, the word line counter can be incremented in any desired unit. Furthermore, for each block calibrated, the word line counter is preferably reset to a base value (e.g., 0).

[0115] Proceeding to decision 620, a determination is made regarding whether the word line counter is greater than the number of word lines contained in the currently calibrated block. In other words, decision 620 determines whether each of the word lines in the current block has been evaluated. In response to determining that the word line counter is not greater than the number of word lines included in the block, method 600 returns to operation 608, allowing the next word line to be evaluated, for example, as described above. Thus, processes 608-620 can be repeated iteratively for each word line in the block.

[0116] Returning to decision 620, method 600 returns to operation 602 in response to determining that the word line counter is greater than the number of word lines contained in the block. In other words, method 600 returns to operation 602, allowing the next block to be calibrated. Thus, processes 602-620 can be repeated iteratively for each block in the memory. As a result, the various processes in method 600 can significantly reduce the calibration overhead experienced, especially compared to conventional processes that may experience several hundred percent more calibration overhead.

[0117] While method 600 involves calculating the absolute shift value of a reference read voltage in each word line, similar improvements can be achieved as a result of further partitioning the read voltages in a given word line based on the page type. For example, see now. Figure 6B Another method 650 for calibrating the read voltage of a memory block configured in a multi-bit-per-cell mode is shown according to one method. However, it should be noted that... Figure 6B Method 650 includes Figure 6A The method 600 is a variation that describes several exemplary configurations for the process of calibrating the read voltage of a memory block. Therefore, Figure 6B Various processes have the same Figure 6A The processes have the same numbering. Therefore, any one or more processes included in method 650 can implement any one or more methods described above with respect to those processes included in method 600.

[0118] According to the present invention, method 650 can be performed in... Figure 1-5 The method can be executed in any environment described herein, wherein it can be executed in various ways. For example, any process included in method 650 can be executed relative to a block of storage space in NVRAM, such as 3-D TLC NAND flash memory, 3-D QLC NAND flash memory, etc., or any other desired type of memory. Furthermore, as those skilled in the art will understand upon reading this specification, method 650 may include more than Figure 6B The specific operations described in the text may include more or fewer operations.

[0119] Each step of method 650 can be performed by any suitable component of the operating environment. For example, in various methods, method 650 can be performed partially or entirely by a controller (e.g., a flash memory controller), a processor, a computer, or some other device having one or more processors. Thus, in some methods, method 650 can be a computer-implemented method. It should also be noted that the terms computer, processor, and controller are used interchangeably with respect to any method herein, and such components are considered equivalent in many different arrangements of the invention.

[0120] Furthermore, for those methods that have a processor, the processor is, for example, a processing circuit, chip, and / or module implemented in hardware and / or software, and preferably has at least one hardware component that can be used in any device to perform one or more steps of method 650. Illustrative processors include, but are not limited to, central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations thereof, or any other suitable computing device known in the art.

[0121] like Figure 6B As shown, operation 602 of method 650 includes proceeding to the next memory block. As stated above, for the purposes of this specification, "next memory block" can vary depending on the given method. Method 650 proceeds from operation 602 to decision 604, which determines whether the given memory block should be recalibrated.

[0122] In response to determining that a given memory block should not be recalibrated for any reason, method 650 returns to operation 602, thereby proceeding to the next block, and then repeating decision 604. However, in response to determining that a given memory block should be recalibrated, method 650 proceeds to operation 606. There, operation 606 includes determining the current operating state of the given block of memory, for example, according to any of the methods described above. Furthermore, operation 608 includes proceeding to the next word line in the current block being evaluated. As previously stated, the “next word line” can vary depending on the given method.

[0123] Method 650 further includes grouping the read voltages corresponding to the current word line based on their respective page types. See operation 652. Preferably, the read voltages are grouped such that each read voltage in a given group corresponds to the same page type. For example, each read voltage in a first group may correspond to the top page in a given word line, while each read voltage in a second group may correspond to an additional page in a given word line. The groups can be assigned differently depending on the method. For example, in some methods, each read voltage can be assigned to a given group by setting a corresponding flag, listing the read voltages in one or more different tables, assigning an identifier to the read voltages, etc.

[0124] In response to dividing the read voltages into multiple groups based on page type, each group is preferably evaluated individually and / or in parallel before proceeding to the next word line. Therefore, operation 654 includes moving to the next group of read voltages. As mentioned above, depending on the desired method, the "next group" of read voltages can simply be the first group, the next group, the last group, a random group of these groups, etc.

[0125] Method 650 proceeds from operation 654 to operation 656, further comprising selecting one of the read voltages in a given group as a reference read voltage. As described above, for example, depending on the desired method, any one of the read voltages in a given group can be selected as the reference read voltage. For example, in some methods, the first read voltage in the group can be selected as the reference read voltage, while in other methods, the leftmost read voltage (e.g., the lowest read voltage) in the group can be selected as the reference read voltage. In other methods, a random read voltage in the group, a read voltage predicting the maximum voltage shift value experiencing the group, a read voltage selected by the user, etc., can be selected as the reference read voltage.

[0126] Operation 612 further includes calculating the absolute shift value of the reference read voltage, while operation 658 includes determining the relative voltage shift value of each of the remaining read voltages in the given group. Thus, any one or more of the methods described above with respect to operation 614 can be modified and / or implemented as is to perform operation 658 for the remaining read voltages in the given group, for example, as those skilled in the art will understand after reading this description.

[0127] For example, in a preferred method, the relative voltage shift value of each of the remaining read voltages in a given group is determined by matching the current operating state of the block and the type of the page in the given group with a corresponding one of a plurality of predetermined operating states. Furthermore, the relative shift value is preferably extracted from a predetermined voltage map assigned to the matching predetermined operating state and corresponding to the type of the page in the given group. Thus, the specific page type corresponding to the given group affects the determined relative voltage shift value. (Temporary reference) Figure 8B Tables 830, 840, 850, and 860 depict illustrative voltage mappings, each corresponding to a different page type. Thus, each of Tables 830, 840, 850, and 860 can correspond to a different set of page types for a given word line. As shown, each operating state s1, s2, ..., sN for each page type LP, UP, XP, TP has multiple corresponding relative shift values ​​(e.g., a(2, 5) in Table 860). Each of these relative shift values ​​is further associated with a corresponding read voltage (e.g., V5 in Table 860).

[0128] As described above, in operation 658 of method 650, a predetermined voltage mapping corresponding to the current operating state of the block and the page type in the given group can be used to determine the relative shift value of the pages in the given group for the remaining read voltage. For example, the current operating state of the block currently being calibrated can be matched with one of a plurality of predetermined operating states. The predetermined operating states may further have more than one voltage mapping associated with them, wherein each of the voltage mappings corresponds to a different page type in the page type, for example, such as Figure 8B This is seen in Tables 830, 840, 850, and 860. Furthermore, the relative shift value can be simply extracted from a predetermined voltage map assigned to the matching predetermined operating state and page type. This ultimately allows the voltage shift value of all read voltages associated with a given group to be determined as a result of actually calculating only one of the shift values, for example, as will be described in further detail below. This significantly reduces processing overhead and performance latency while also ensuring high read performance and efficient memory usage.

[0129] Continue to refer to Figure 6B Operation 660 includes adjusting each of the absolute shift value and the corresponding relative shift value in a given group of read voltages. As mentioned above, the relative shift value is an absolute shift value calculated relative to a reference read voltage for a given group. Therefore, each read voltage in the group (except the reference read voltage) can be adjusted by applying the corresponding relative shift value to the absolute shift value and applying the resulting shift value to the given read voltage. Again, thus, any one or more of the methods described above with respect to operation 616 can be modified and / or implemented as is to perform operation 660, for example, as those skilled in the art will understand after reading this description.

[0130] Method 650 proceeds from operation 660 to decision 662, determining whether each group corresponding to the current word line has been evaluated. In response to determining that at least one group has not yet been evaluated, method 650 returns to operation 654, allowing progress to the next group of read voltages. Thus, processes 654-662 included in method 650 can be repeated iteratively for each group in the word line.

[0131] However, in response to determining that each group corresponding to the current word line has been evaluated, method 650 proceeds to operation 618. There, operation 618 includes incrementing the word line counter. Furthermore, method 650 is preferably used to calibrate various blocks in the memory, and each word line in each calibrated block. Thus, the word line counter can be used to track how many word lines have been evaluated in a given block. Therefore, proceed to decision 620, making a determination as to whether the word line counter is greater than the number of word lines contained in the block currently being calibrated. In response to determining that the word line counter is not greater than the number of word lines contained in the block, method 650 returns to operation 608, allowing the next word line to be evaluated, for example, as described above. Thus, the processes 608-620 included in method 650 can be repeated iteratively for each word line in the block.

[0132] Referring again to decision 620, method 650 returns to operation 602 in response to determining that the word line counter is greater than the number of word lines contained in the block. In other words, method 650 returns to operation 602 so that the next block can be calibrated. Thus, the processes 602-620 included in method 650 can be repeated iteratively for each block in memory.

[0133] The various procedures in Method 650 can also significantly reduce the calibration overhead experienced, especially compared to conventional procedures that may experience several hundred percent more calibration overhead.

[0134] While methods 600 and 650 implement different levels of granularity in how they determine the read voltage shift value, in some methods, the two methods can be combined into a single process. For example, a method (not shown) may include a decision to determine whether to evaluate the read voltage at the word line level or at a specific page type level. In other words, a method may be implemented that determines, for example, based on user input, system settings, performance metrics, etc., which of the above calibration strategies should be implemented for a given block.

[0135] Now see Figure 7 As mentioned above, Table 700 presents several exemplary operational states that a given memory block may currently be experiencing (see, for example, s2). As shown, each state listed in the "State" column corresponds to a specific value for several different types of statistics. According to an example, state s... k+1 This corresponds to a block that has undergone P / E cycles between 0 and 1000, a hold time between 0 and 24 hours, 0 read disturbance cycles, and a system operating temperature of 40°C. Therefore, any block identified as having statistics matching the aforementioned range and values ​​can be identified as having s k+1The current operating state of the block. Once the current operating state of the block matches one of the predetermined operating states, the predetermined operating state can be further used to identify a predetermined relative shift value of the read voltage of the block being evaluated, for example, see below. Figures 8A to 8B As those skilled in the art will understand, Table 700 may include multiple different operating states for different values ​​or ranges of P / E cycles, hold times, readout disturbance cycles, operating temperatures, or other statistics.

[0136] Continue to refer to Figure 7 Preferably, for various block, word line, and page types in a given storage system, the number of block operation states is predetermined. For example, Figure 7 The various block operation states shown in Table 700 can be predetermined according to methods for specific types of memory, specific products, specific users, etc. Furthermore, these block operation states can be predetermined using testing, modeling, manufacturer specifications, historical performance information, etc.

[0137] As described above, each of these operating states can be further associated with a specific relative shift value of the read voltage associated with the block being evaluated. For example, see Figure 8A Table 800 includes an illustrative voltage mapping. Each of the operating states s1, s2, ..., sN can be adjusted from, for example, a predetermined operating state in response to comparing the current operating state of the block with a predetermined operating state. Figure 7 Choose from the table shown. Figure 8A Table 800 can thus be used to identify multiple relative shift values ​​(e.g., A(2, 5)) corresponding to a specific operating state that the block is undergoing. Each relative shift value is further associated with a corresponding read voltage (e.g., V5), and can thus be used, for example, to calculate the actual read voltage shift value for most read voltages according to any of the methods included herein.

[0138] Figure 8B It also includes tables 830, 840, 850, and 860, each of which includes a voltage mapping corresponding to a specific page type. Therefore, it can be used in conjunction with... Figure 8A Tables 830, 840, 850, and 860 are used in a similar manner to Table 800 to determine relative shift values ​​for various read voltages corresponding to pages of the same type (e.g., additional pages "XP"). Each of these relative shift values ​​is further correlated with a corresponding read voltage (e.g., V5 in Table 860) and can be used to calculate most of the actual read voltage shift values ​​associated with a given page type, for example, according to any of the methods included herein. For example, by comparing the current operating state of the block and the type of the page in the given group with one of a plurality of predetermined operating states (e.g., see...). Figure 7Matching is performed to determine the relative voltage shift value for each of a plurality of read voltages in a given group. Subsequently, the relative shift value is preferably extracted from a predetermined voltage map assigned to a predetermined operating state and corresponding to the type of page in the given group.

[0139] It should be noted that although a specific read voltage in the read voltages has been identified as the reference voltage “reference” in each of Tables 830, 840, 850, and 860, this is by no means intended to be limiting. As stated above, for example, any read voltage in a given group can be selected as the reference voltage according to the desired method.

[0140] Thus, as a result of actually calculating only one of the voltage shift values, the various methods included in this paper are able to determine the voltage shift values ​​of all read voltages associated with a given word line and / or page group. This significantly reduces processing overhead and performance latency while ensuring high read performance and efficient memory usage. As mentioned above, these significant improvements are achieved as a result of implementing a process that recognizes the relative offset between read voltages at certain boundaries of device operating states. Some of the methods included in this paper are also able to recognize that the absolute voltage shift value will change, but the relative shift value remains within the aforementioned boundaries. Therefore, the relative shift value can be decoupled from the absolute shift value by mapping the relative voltage shift value with a corresponding reference voltage. By determining the current operating state of the block, it can be determined whether a given block is within the aforementioned boundaries, where the relative voltage shift value is maintained. The reference voltage can also be used to periodically track changes in the absolute shift value during different operating states that the block may experience.

[0141] Based on examples of its use, it is by no means intended to limit the invention. Figure 5 The threshold voltage shift shown corresponds to a 3D QLC NAND with voltage threshold (VTH) levels of i = 0, 1, ..., 15 for a given block. Therefore, let “s” represent the state of the block (e.g., the block has undergone “x” p / e cycles, “y” hold cycles, etc.). Consequently, the change in the average value of the i-th VTH distribution at word line “w” can be expressed as: VTH(i, w, s) = VTH(i, w, 0) + Δ·a(i, w, s), where VTH(i, w, 0) is the VTH when the block is first programmed (e.g., at the start of its lifetime). Furthermore, Δ is the positive unit of the VTH shift, and a(i, w, s) represents the integer value of the shift amount of the i-th VTH distribution relative to state 0 when the block is in state s.

[0142] Therefore, for a given state of a block, the 16 VTH distributions can be represented by a set of integers: a(i, w, s), i = 0, ..., 15. Using the rightmost distribution as a reference, this set can be written as: a'(0, w, s), a'(1, w, s), ..., a'(14, w, s), a'(15, w, s), where a'(i, w, s) = a(i, w, s) / |a(15, w, s)|. This normalized set represents the relative change of the 16 VTH distributions at state s with respect to the change in VTH i = 15. For example, let s correspond to 1,000 cycles and a 1-week hold, such that the following Equation 1 holds:

[0143] {a'(0,w,s),a'(1,w,s),...,a'(14,w,s),a'(15,w,s)}={-0.1,-0.2,...,-0.8,-1} Equation 1

[0144] Therefore, Equation 1 provides a representation of the shift in the average value of the VTH distribution, which is correlated with a similar shift in the corresponding read voltage to compensate for VTH variations. The previous representation of the VTH shift for word line w and block state s, a'(i, w, s), i = 0, ..., 15, is further maintained within the margin of block operation. This is because the relative shift of the 16 VTH distributions due to typical (e.g., non-instantaneous) wear mechanisms is a relatively slow process. Relative changes are typically driven by the physical mechanisms that cause VTH shifts (e.g., charge loss during hold). For example, typically, the relative changes in the VTH distribution remain the same between 0 and 1 weeks of holding, but can vary between 1 and 2 weeks of holding, etc., such that {a'(0, w, s1 = 1,000 cycles and 0-1 week holding), a'(1, w, s1), ..., a'(14, w, s1), a'(15, w, s1)} = {-0.1, -0.2, -0.2, ..., -0.8, -1}. Furthermore, {a'(0, w, s2 = 1,000 cycles and 1-2 week holding), a'(1, w, s2), ..., a'(14, w, s2), a'(15, w, s2)} = {-0.2, -0.3, -0.3, ..., -0.9, -1}.

[0145] On the other hand, the absolute shift of the 16 VTH distributions can be a relatively fast process (e.g., at least relative to typical wear mechanisms), and it can also vary between different parts of the block (e.g., different layers or groups of word lines) due to processing variations, materials, or other technology-specific variability issues. Thus, {a'(0, w1, s in the lower layer), a'(1, w1, s), ..., a'(14, w1, s), a'(15, w1, s)} = {a'(0, w2 in the higher layer), a'(1, w2, s), ..., a'(14, w2, s), a'(15, w2, s)}, however a(15, w1, s) = -4 and a(15, w2, s) = -5.

[0146] Therefore, the various methods included in this paper can calibrate the read voltage at any given state s by identifying the current state s of the block, determining the absolute shift of these reference voltages using one or more reference read voltages, and then determining a mapping of the relative shift of the remaining voltage relative to the reference voltage at the given state s. Furthermore, the remaining non-reference read voltages can be adjusted based on the absolute offset, relative offset, and current value (e.g., before calibration) of the corresponding read voltage.

[0147] It should also be noted that the specific configurations included in any of the methods included herein are not limiting. For example, the number and / or type of pages in a given word line and / or memory block, the number and / or values ​​of read voltages, the number and / or values ​​of threshold voltage levels, the number of common and / or independent read voltage offset values ​​corresponding to each calibration scheme, etc., included in any of the methods herein are by no means intended to be limiting, but are presented only by way of example.

[0148] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0149] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0150] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device.

[0151] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing the status information of the computer-readable program instructions.

[0152] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0153] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0154] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0155] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be implemented as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0156] Furthermore, systems according to various embodiments may include a processor and logic integrated with and / or integrateable with the processor, the logic being configured to perform one or more of the process steps described herein. The processor may be any configuration as described herein, such as a discrete processor or processing circuitry including many components such as processing hardware, memory, I / O interfaces, etc. "Integrated with" means that the processor has logic embedded therewith as hardware logic, such as application-specific integrated circuits (ASICs), FPGAs, etc. "Executable by the processor" means that the logic is hardware logic; software logic, such as firmware, part of an operating system, part of an application; etc., or some combination of hardware and software logic that is accessible to the processor and configured to cause the processor to perform a certain function when executed by the processor. The software logic may be stored on local and / or remote memory of any memory type, as is known in the art. Any processor known in the art may be used, such as software processor modules and / or hardware processors, such as ASICs, FPGAs, central processing units (CPUs), integrated circuits (ICs), graphics processing units (GPUs), etc.

[0157] Figure 9 A network architecture 900 based on one method is shown. For example... Figure 9 As shown, multiple remote networks 902 are provided, including a first remote network 904 and a second remote network 906. A gateway 901 may be coupled between the remote network 902 and a neighboring network 908. In the context of this network architecture 900, networks 904 and 906 may each take any form, including but not limited to LANs, WANs such as the Internet, public switched telephone networks (PSTN), internal telephone networks, etc.

[0158] In use, gateway 901 serves as the entry point from remote network 902 to neighboring network 908. Thus, gateway 901 can function as a router capable of routing a given data packet to gateway 901, and as a switch providing the actual path for a given packet to and from gateway 901.

[0159] The system further includes at least one data server 914 coupled to a neighboring network 908, which is accessible from a remote network 902 via a gateway 901. It should be noted that the data server 914 may include any type of computing device / component. Multiple user devices 916 are coupled to each data server 914. Such user devices 916 may include desktop computers, laptop computers, handheld computers, printers, and / or any other type of logically-containing device. It should be noted that in some methods, user devices 911 may also be directly coupled to any other device in the network.

[0160] Peripheral device 920, or a series of peripheral devices 920, such as fax machines, printers, scanners, hard drives, networking and / or local data storage units or systems, may be coupled to one or more of networks 904, 906, and 908. It should be noted that databases and / or additional components may be used with or integrated into any type of network element coupled to networks 904, 906, and 908. In the context of this specification, a network element may refer to any component of the network.

[0161] According to some methods, the methods and systems described herein can be implemented using virtual systems and / or emulate one or more other systems, and / or on virtual systems and / or emulate one or more other systems, such as UNIX systems that virtually host a Microsoft Windows environment. In some methods, this virtualization and / or emulation can be enhanced by using VMware software.

[0162] In other approaches, one or more networks 904, 906, 908 can represent a cluster of systems commonly referred to as a "cloud." In cloud computing, shared resources such as processing power, peripherals, software, data, servers, etc., are provided to any system in the cloud on an on-demand basis, thereby allowing access to and distribution of services across many computing systems. Cloud computing typically involves internet connectivity between systems operating in the cloud; however, other technologies for connecting systems can also be used, as is known in the art.

[0163] Figure 10 It shows a method and Figure 9 A representative hardware environment associated with user equipment 916 and / or server 914. Figure 10A typical hardware configuration of a processor system 1000 according to a method is shown, the processor system having a central processing unit 1010 such as a microprocessor and a plurality of other units interconnected via a system bus 1012. In some methods, the central processing unit 1010 may include the above-referenced Figure 2 Any method described by one or more processors 210.

[0164] Figure 10 The processor system 1000 shown includes RAM 1014, read-only memory (ROM) 1016, and I / O adapter 1018. According to some methods, and in no way intended to limit the invention, the I / O adapter 1018 may include the above-referenced components. Figure 2 Any method described in the I / O adapter 218. Still refer to Figure 10 In the processor system 1000, the aforementioned components 1014, 1016, and 1018 can be used to connect peripheral devices, such as the storage subsystem 1020, to the bus 1012. In some methods, the storage subsystem 1020 may include... Figure 2 The data storage system 220 has a similar and / or identical configuration. According to one example, which is by no means intended to limit the invention, the storage subsystem 1020 may include non-volatile data storage cards, for example, in addition to... Figure 2 In addition to the RAID controller shown, it also has NVRAM memory cards, RAM, ROM and / or some other known types of non-volatile memory.

[0165] Continue to refer to Figure 10 User interface adapter 1022 is used to connect keyboard 1024, mouse 1026, speaker 1028, microphone 1032 and / or other user interface devices such as touch screen, digital camera (not shown) to bus 1012.

[0166] The processor system 1000 also includes a communication adapter 1034 for connecting the processor system 1000 to a communication network 1035 (e.g., a data processing network) and a display adapter 1036 for connecting a bus 1012 to a display device 1038.

[0167] The processor system 1000 may have an operating system residing on it, such as Microsoft Windows operating system (OS), Mac OS, UNIX OS, etc. It should be understood that the preferred method can also be implemented on platforms and operating systems other than those mentioned. The preferred method can be written using JAVA, XML, C and / or C++, or other programming languages ​​along with object-oriented programming methods. Object-oriented programming (OOP), which has become increasingly used for developing complex applications, can be used.

[0168] also, Figure 11 A storage system 1100 is shown that implements a higher-level (e.g., SSD) storage layer in combination with a lower-level (e.g., magnetic tape) storage layer according to a method. Note that, according to various methods, Figure 11 Some of the components shown can be implemented as hardware and / or software. Storage system 1100 may include a storage system manager 1112 for communicating with multiple media on at least one higher storage layer 1102 and at least one lower storage layer 1106. However, in other approaches, storage system manager 1112 may communicate with multiple media on at least one higher storage layer 1102 but not on a lower storage layer. The higher storage layer (one or more) 1102 preferably includes one or more random access and / or direct access media 1104, such as hard disks, non-volatile memory (NVM), NVRAM, solid-state memory in SSDs, flash memory, SSD arrays, flash memory arrays, etc., and / or other media mentioned herein or known in the art. According to the illustrative example, Figure 3 -4 illustrates an exemplary architecture that can be used as an SSD system for a higher storage tier 1102, depending on the desired approach.

[0169] Still referencing Figure 11 The lower storage layer 1106 preferably includes one or more lower-performance storage media 1108, including sequential access media such as magnetic tape and / or optical media in a magnetic tape drive, slower access HDDs, slower access SSDs, etc., and / or other media described herein or known in the art. One or more additional storage layers 1116 may include any combination of storage memory media desired by the designer of the system 1100. Therefore, in some methods, one or more additional storage layers 1116 may include... Figure 1-2 The SSD system architectures shown are similar or identical.

[0170] Storage system manager 1112 can be accessed via network 1110, for example... Figure 11The storage area network (SAN) or some other suitable network type shown communicates with storage media 1104, 1108 on the higher storage tier 1102 and the lower storage tier 1106. The storage system manager 1112 can also communicate with one or more host systems (not shown) via a host interface 1114, which may or may not be part of the storage system manager 1112. The storage system manager 1112 and / or any other component of the storage system 1100 can be implemented in hardware and / or software and can utilize processors (not shown) for executing commands of types known in the art, such as central processing units (CPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc. Of course, any arrangement of the storage system can be used, as will be apparent to those skilled in the art upon reading this specification.

[0171] In other methods, storage system 1100 may include any number of data storage layers, and each storage layer may include the same or different storage media. For example, each data storage layer may include the same type of storage media, such as HDD, SSD, sequential access media (tape in a tape drive, optical disc in an optical disc drive, etc.), direct access media (CD-ROM, DVD-ROM, etc.), or any combination of media storage types. In such a configuration, higher storage layer 1102 may primarily include SSD storage media for storing data in a higher-performance storage environment, and the remaining storage layers, including lower storage layer 1106 and additional storage layer 1116, may include any combination of SSDs, HDDs, tape drives, etc., for storing data in a lower-performance storage environment. Thus, data accessed more frequently, data with higher priority, data requiring faster access, etc., can be stored in higher storage layer 1102, while data without any of these attributes can be stored in additional storage layer 1116, which includes lower storage layer 1106. Of course, those skilled in the art, upon reading this specification, can design many other combinations of storage media types to implement different storage schemes based on the methods presented herein.

[0172] According to some methods, a storage system (such as 1100) may include logic configured to receive a request to open a dataset, logic configured to determine whether the requested dataset is stored in a plurality of associated portions in a lower storage layer 1106 of the hierarchical data storage system 1100, logic configured to move each associated portion of the requested dataset to a higher storage layer 1102 of the hierarchical data storage system 1100, and logic configured to combine the requested dataset from the associated portions onto the higher storage layer 1102 of the hierarchical data storage system 1100.

[0173] Of course, according to various embodiments, this logic can be implemented as a method or computer program product on any device and / or system.

[0174] It is clear that the various features of the aforementioned systems and / or methods can be combined in any way, resulting in multiple combinations from the description presented above.

[0175] It should also be understood that embodiments of the present invention may be provided in the form of services deployed on behalf of customers in order to provide services on demand.

[0176] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method for calibrating read voltages of a memory block, comprising: determining a current operating state of the block, wherein the block contains one or more word lines therein, wherein one or more read voltages are associated with each of the word lines; and for each given word line of the word lines in the block: selecting one of the read voltages associated with the given word line as a reference read voltage, computing an absolute shift value of the reference read voltage, determining a relative shift value of each of the remaining read voltages associated with the given word line, wherein the relative shift value is determined relative to the reference read voltage, and using each of the absolute shift value and the relative shift value to adjust each of the read voltages associated with the given word line.

2. The computer-implemented method of claim 1, wherein the relative shift value of the remaining read voltages is determined using a predetermined voltage map corresponding to the current operating state of the block.

3. The computer-implemented method of claim 2, wherein determining the relative shift value of each of the remaining read voltages associated with the given word line comprises: matching the current operating state of the block to a corresponding one of a plurality of predetermined operating states; and extracting the relative shift value from the predetermined voltage map assigned to the matched predetermined operating state. the current operating state of the block is determined using one or more statistics corresponding to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: cycle count, read disturb count, and retention time.

4. The computer-implemented method of claim 1, wherein, 5. The computer-implemented method of claim 1, wherein the memory is a non-volatile random access memory (NVRAM).

6. The computer-implemented method of claim 5, wherein the NVRAM comprises a three-dimensional triple-level-cell (TLC) NAND flash memory.

7. The computer-implemented method of claim 5, wherein the NVRAM comprises a three-dimensional quad-level-cell (QLC) NAND flash memory.

8. A computer program product for calibrating read voltages of a memory block, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and / or executable by a processor to cause the processor to: determine, by the processor, a current operating state of the block, wherein the block contains one or more word lines therein, wherein one or more read voltages are associated with each of the word lines; and for each given word line of the word lines in the block: select, by the processor, one of the read voltages associated with the given word line as a reference read voltage, compute, by the processor, an absolute shift value of the reference read voltage, ​ determining, by the processor, a relative shift value for each of the remaining read voltages associated with the given word line, wherein, The relative shift value is determined relative to the reference read voltage, and each of the read voltages associated with the given word line is adjusted by the processor using the absolute shift value and each of the relative shift values.

9. The computer program product of claim 8, wherein the relative shift value of the remaining read voltages is determined using a predetermined voltage map corresponding to the current operating state of the block.

10. The computer program product of claim 9, wherein determining the relative shift value of each of the remaining read voltages associated with the given word line includes: matching the current operating state of the block to a corresponding one of a plurality of predetermined operating states; and extracting the relative shift value from the predetermined voltage map assigned to the matched predetermined operating state.

11. The computer program product of claim 8, wherein the current operating state of the block is determined using one or more statistics corresponding to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: cycle count, read disturb count, and retention time.

12. The computer program product of claim 8, wherein the memory is a non-volatile random access memory (NVRAM).

13. The computer program product of claim 12, wherein the NVRAM includes a three-dimensional triple-level-cell NAND flash memory.

14. The computer program product of claim 12, wherein the NVRAM includes a three-dimensional quad-level-cell NAND flash memory.

15. A system for calibrating read voltages of memory blocks, comprising: a plurality of non-volatile random access memory (NVRAM) blocks configured to store data; a processor; and logic integrated with and / or integratable by the processor, the logic configured to, for each given block of the blocks: determine, by the processor, a current operating state of the given block, wherein the given block includes one or more word lines therein, wherein one or more read voltages are associated with each of the word lines; and for each given word line of the word lines in the given block: select, by the processor, one of the read voltages associated with the given word line as a reference read voltage, calculate, by the processor, an absolute shift value of the reference read voltage, determine, by the processor, a relative shift value of each of the remaining read voltages associated with the given word line, wherein the relative shift value is determined relative to the reference read voltage, and each of the read voltages associated with the given word line is adjusted by the processor using the absolute shift value and each of the relative shift values.

16. The system of claim 15, wherein the relative shift value of the remaining read voltages is determined using a predetermined voltage map corresponding to the current operating state of the block. ​ 17. The system of claim 16, wherein determining the relative shift value for each of the remaining read voltages associated with the given word line includes: matching the current operating state of the block to a corresponding one of a plurality of predetermined operating states; and extracting the relative shift value from the predetermined voltage mapping assigned to the matched predetermined operating state.

18. The system of claim 15, wherein the current operating state of the block is determined using one or more statistics corresponding to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: cycle count, read disturb count, and retention time.

19. The system of claim 15, wherein at least some of the NVRAM blocks are included in a three-dimensional triple-level-cell NAND flash.

20. The system of claim 15, wherein at least some of the NVRAM blocks are included in a three-dimensional quad-level-cell NAND flash.

21. A computer-implemented method for calibrating read voltages of a memory block, comprising: determining a current operating state of the block, wherein the block contains more than one type of page therein, wherein at least one read voltage is associated with each of the page types; for each given word line in the block: dividing the read voltages into groups based on the respective page types; and for each given group of read voltages in the given word line: selecting one of the read voltages in the given group as a reference read voltage, computing an absolute shift value of the reference read voltage, determining a relative shift value for each of the remaining read voltages in the given group, wherein the relative shift value is determined relative to the reference read voltage, and using each of the absolute shift value and the relative shift value to adjust each of the read voltages in the given group. each of the read voltages in a given group corresponds to the same page type.

22. The computer-implemented method of claim 21, wherein, 23. The computer-implemented method of claim 21, wherein the relative shift values for the remaining read voltages in the given group are determined using a predetermined voltage mapping corresponding to the current operating state of the block and the type of page in the given group. determining the relative shift value for each of the remaining read voltages in the given group includes:

24. The computer-implemented method of claim 23, wherein, matching the current operating state of the block and the page type in the given group to a corresponding one of a plurality of predetermined operating states; and extracting the relative shift value from the predetermined voltage mapping assigned to the matched predetermined operating state and corresponding to the page type in the given group. the current operating state of the block is determined using one or more statistics corresponding to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: cycle count, read disturb count, and retention time. ​ 25. The computer-implemented method of claim 21, wherein, ​

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