Three-dimensional memory device and method of forming the same

Abstract

A three-dimensional (3D) memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to international application No. PCT / CN2021 / 114050 entitled “THREE-DIMENSIONAL MEMORYDEVICES AND METHODS FOR FORMING THE SAME”, filed on August 23, 2021, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Embodiments of this disclosure relate to a three-dimensional (3D) storage device and a method of manufacturing the same.

[0004] Planar memory cells have been miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is nearing its upper limit. Furthermore, with the increasing number of 3D memory layers, controlling the channel profile becomes increasingly difficult. Summary of the Invention

[0005] This article discloses embodiments of 3D storage devices and methods for forming the same.

[0006] In one aspect, a 3D memory device is disclosed. The 3D memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure along a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film above the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

[0007] In another aspect, a 3D memory device is disclosed. The 3D memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a dielectric core, a semiconductor channel above the dielectric core, and a memory film above the semiconductor channel. The dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and a first diameter of the dielectric core at the bottom of the channel structure is smaller than a second diameter of the dielectric core at the top of the channel structure.

[0008] In another aspect, a system is disclosed. The system includes a 3D storage device configured to store data, and a storage controller coupled to the 3D storage device and configured to control the operation of the 3D storage device. The 3D storage device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D storage device at its bottom. The channel structure includes a semiconductor channel and a storage film above the semiconductor channel. The storage film includes a first angular structure, and a first diameter of the storage film at its bottom below the first angular structure is smaller than a second diameter of the storage film at its upper portion above the first angular structure.

[0009] In another aspect, a system is disclosed. The system includes a 3D storage device configured to store data, and a storage controller coupled to the 3D storage device and configured to control the operation of the 3D storage device. The 3D storage device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D storage device at its bottom. The channel structure includes a dielectric core, a semiconductor channel above the dielectric core, and a storage film above the semiconductor channel. The dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and a first diameter of the dielectric core at the bottom of the channel structure is smaller than a second diameter of the dielectric core at the top of the channel structure.

[0010] In another aspect, a method for forming a 3D memory device is disclosed. A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate. A second stacked structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stacked structure. A channel hole penetrating the second and first stacked structures along a first direction is formed to expose the substrate. An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel hole. The channel hole has a first width at a first portion having a third dielectric layer formed on the sidewalls and a second width at a second portion not having a third dielectric layer formed on the sidewalls, and the first width is less than the second width. A memory film is conformally formed in the channel hole. A semiconductor channel is formed in the channel hole and over the memory film. The semiconductor channel completely fills the channel hole at the first portion. The substrate and the first dielectric layer are removed to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel. An interconnect structure in contact with the semiconductor channel is formed.

[0011] In another aspect, a method for forming a 3D memory device is disclosed. A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate. A second stacked structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stacked structure. A channel hole penetrating the second and first stacked structures along a first direction is formed to expose the substrate. An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel hole. The channel hole has a first width at a first portion having a third dielectric layer formed on the sidewalls and a second width at a second portion not having a third dielectric layer formed on the sidewalls, and the first width is less than the second width. A memory film and a semiconductor channel are conformally formed in the channel hole. A dielectric core is formed in the channel hole and over the semiconductor channel. The dielectric core completely fills the channel hole at the first portion. The substrate and the first dielectric layer are removed to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel. An interconnect structure in contact with the semiconductor channel is formed. Attached Figure Description

[0012] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the description, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0013] Figure 1 A cross-section of an exemplary 3D storage device according to some aspects of this disclosure is shown.

[0014] Figure 2 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0015] Figure 3 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0016] Figure 4-20 Cross-sections of exemplary 3D storage devices at different stages of the manufacturing process are shown, according to some aspects of this disclosure.

[0017] Figure 21 A flowchart illustrating an exemplary method for forming a 3D storage device according to some aspects of this disclosure is shown.

[0018] Figure 22 A cross-section of an exemplary 3D storage device according to some aspects of this disclosure is shown.

[0019] Figure 23 A cross-section of another exemplary 3D storage device according to some aspects of this disclosure is shown.

[0020] Figure 24A cross-section of an exemplary 3D storage device according to some aspects of this disclosure is shown.

[0021] Figure 25 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0022] Figure 26 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0023] Figure 27 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0024] Figure 28 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0025] Figures 29-40 Cross-sections of exemplary 3D storage devices at different stages of the manufacturing process are shown, according to some aspects of this disclosure.

[0026] Figure 41 A flowchart illustrating an exemplary method for forming a 3D storage device according to some aspects of this disclosure is shown.

[0027] Figure 42 A cross-section of an exemplary 3D storage device according to some aspects of this disclosure is shown.

[0028] Figure 43 A cross-section of the bottom of the channel structure according to some aspects of this disclosure is shown.

[0029] Figure 44-52 Cross-sections of exemplary 3D storage devices at different stages of the manufacturing process are shown, according to some aspects of this disclosure.

[0030] Figure 53 A flowchart illustrating an exemplary method for forming a 3D storage device according to some aspects of this disclosure is shown.

[0031] Figure 54 A block diagram of an exemplary system having a storage device according to some aspects of this disclosure is shown.

[0032] Figure 55A An illustration of an exemplary memory card having a storage device according to some aspects of this disclosure is shown.

[0033] Figure 55B An illustration of an exemplary solid-state drive (SSD) having a storage device according to some aspects of this disclosure is shown.

[0034] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0035] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other in a manner not specifically depicted in the drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0036] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0037] It should be readily understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” not only means directly “on” something, but also includes the meaning of being “on” something with an intermediate feature or layer in between, and that “above” or “on top” not only means being “above” or “on top” something, but can also include the meaning of being “above” or “on top” something without an intermediate feature or layer in between (i.e., directly on something).

[0038] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or feature relative to another element (or more) element or feature as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted similarly accordingly.

[0039] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0040] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0041] As used herein, the term “3D memory device” refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0042] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and vertically interconnecting them, so that the resulting structure acts as a single device, thereby achieving performance improvements with reduced power and a smaller footprint compared to conventional planar processes. However, as the number of 3D memory layers continues to increase, controlling the channel profile becomes increasingly difficult.

[0043] Figure 1 A cross-section of an exemplary 3D storage device 100 according to some aspects of this disclosure is shown. For example... Figure 1As shown, the 3D storage device 100 includes a stacked structure 111 and a channel structure 118 extending through the stacked structure 111 in the y-direction. The stacked structure 111 may include staggered conductive layers 105 and dielectric layers 107, and the stacked conductive / dielectric layer pairs are also referred to as a storage stack. In some embodiments, the dielectric layer 107 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer 105 may form word lines and may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof.

[0044] The channel structure 118 may extend through the stacked structure 111, and the bottom of the channel structure 118 may contact the source of the 3D memory device 100. In some embodiments, the channel structure 118 may include a semiconductor channel 132 and a memory film 125 formed over the semiconductor channel 132. The term "over" here, in addition to the above explanation, should also be interpreted as "above" something from the top side or from the lateral side. In some embodiments, the channel structure 118 may also include a dielectric core 129 located at the center of the channel structure 118. In some embodiments, the memory film 125 may include a tunneling layer 130 over the semiconductor channel 132, a memory layer 128 over the tunneling layer 130, and a barrier layer 126 over the memory layer 128.

[0045] According to some embodiments, the dielectric core 129, semiconductor channel 132, tunneling layer 130, storage layer 128, and barrier layer 126 are arranged radially from the center of the channel structure 118 outwards in this order. In some embodiments, the tunneling layer 130 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage layer 128 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the barrier layer 126 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film may comprise a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0046] like Figure 1 As shown, the dummy channel structure 124 can be formed in the stacked structure 111 extending along the y-direction. In some embodiments, the contact structure 134 can be formed in the stacked structure 111 extending along the y-direction. It is understood that in an actual structure, the stacked structure 111 and the stepped region (including the dummy channel structure 124 and / or the contact structure 134) may not be seen in the same cross-section. For better description of this disclosure, cross-sections of the stacked structure 111 and the stepped region are shown in the same figure of this disclosure, and... Figure 1The coordinates in the x and z directions are marked to show the perpendicularity of the cross-sections of the stacked structure 111 and the stepped region.

[0047] Figure 2 A cross-section of the bottom of the channel structure 118 of a 3D storage device 100 according to some aspects of this disclosure is shown. For example... Figure 2 As shown, the bottom of the channel structure 118 may include a curved structure of a semiconductor channel 132, a tunneling layer 130, and a memory layer 128. In some embodiments, the barrier layer 126 located at the bottom of the channel structure 118 may have a different thickness compared to the barrier layer 126 located at the top of the channel structure 118. In some embodiments, the barrier layer 126 may have a thickness W1 at the bottom of the channel structure 118, and the barrier layer 126 may have a thickness W2 at the top of the channel structure 118, and W1 is greater than W2, such as... Figure 2 As shown.

[0048] In some embodiments, the barrier layer 126 may include a dielectric material obtained by forming the channel structure storage film 125 and a dielectric material obtained by forming the fifth dielectric layer 116, which will be described later. In other words, the thickness W1 or the thickness W2 of the barrier layer 126 may include a dielectric material formed along the x-direction between the storage layer 128 and the sidewalls of the stacked structure 111.

[0049] The conductive layer 136 can be disposed below the stacked structure 111, such as... Figure 1 and Figure 2 As shown. In some embodiments, the conductive layer 136 may be a polysilicon layer. In some embodiments, the conductive layer 136 is in direct contact with the semiconductor channel 132. In some embodiments, the conductive layer 136 is in direct contact with a portion of the bottom surface and side surface of the semiconductor channel 132 at the bottom of the channel structure 118. In some embodiments, the bottom surface of the storage film 125, including the barrier layer 126, the storage layer 128, and the tunneling layer 130, is above the bottom surface of the semiconductor channel 132, such as... Figure 2 As shown.

[0050] Figure 3 A cross-section of the bottom of the channel structure 118 of a 3D storage device 100 according to some aspects of this disclosure is shown. In some embodiments, the channel structure 118 is a circular structure in a plan view of the 3D storage device 100. In some embodiments, the dielectric core 129, semiconductor channel 132, tunneling layer 130, storage layer 128, and barrier layer 126 are arranged radially from the center of the channel structure 118 toward the outer surface. Figure 3As shown, the semiconductor channel 132 located at the bottom of the channel structure 118 can have a different diameter compared to the semiconductor channel 132 located at the upper part of the channel structure 118. In some embodiments, in the plan view of the 3D storage device 100, the semiconductor channel 132 may have an outer diameter W3 at the bottom of the channel structure 118, and the semiconductor channel 132 may have an outer diameter W4 at the upper part of the channel structure 118, and W3 is smaller than W4. In some embodiments, the semiconductor channel 132 may be formed as an angled structure 131 in the cross-section of the bottom of the channel structure 118. For example, as Figure 3 As shown, the semiconductor channel 132 can be formed as two right-angled structures. In some embodiments, the semiconductor channel 132 can be formed as an obtuse-angled structure, an acute-angled structure, a right-angled structure, an arc-angled structure, or any combination of these angular structures. The outer diameter W3 of the semiconductor channel 132 at the bottom of the channel structure 118 below the angular structure is smaller than the outer diameter W4 of the semiconductor channel 132 at the top of the channel structure 118 above the angular structure.

[0051] Figure 4-20 Cross sections of a 3D storage device 100 at different stages of the manufacturing process according to some aspects of this disclosure are shown. Figure 21 A flowchart illustrating an exemplary method 2100 for forming a 3D storage device 100 according to some aspects of this disclosure is shown. For a better description of this disclosure, it will be discussed together. Figure 4-20 The cross-section of the 3D storage device 100 in the middle and Figure 21 Method 2100. It is understood that the operations shown in Method 2100 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously, or in different sequences. Figure 4-20 and Figure 21 Execute in the order shown.

[0052] like Figure 4 and Figure 21As shown in operation 2102, a first stacked structure 101, including a first dielectric layer 104, a first conductive layer 106, a second dielectric layer 108, and a second conductive layer 110, is formed on a substrate 102. In some embodiments, the substrate 102 may be a doped semiconductor layer. In some embodiments, the conductive layer 106 may be a polysilicon layer, and the conductive layer 110 may be a polysilicon layer. In some embodiments, the first dielectric layer 104 and / or the second dielectric layer 108 may include a silicon oxide layer. In some embodiments, the first conductive layer 106 may include a doped polysilicon layer. In some embodiments, the first conductive layer 106 may include a p-doped polysilicon layer. In some embodiments, the second conductive layer 110 may include an undoped polysilicon layer. In some embodiments, the first dielectric layer 104, the first conductive layer 106, the second dielectric layer 108, and the second conductive layer 110 may be deposited sequentially by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some implementations, the first stacked structure 101 may include only one polysilicon layer, such as the first conductive layer 106.

[0053] In some embodiments, during the formation of the first stack structure 101, the first conductive layer 106 and the second conductive layer 110 may be treated with ammonia (NH3). In some embodiments, the NH3 treatment may be performed on the top surfaces of the first conductive layer 106 and the second conductive layer 110. In some embodiments, performing the NH3 treatment on the top surfaces of the first conductive layer 106 and the second conductive layer 110 can prevent the formation of oxide layers along the x-direction on the first conductive layer 106 and the second conductive layer 110 during subsequent oxidation processes.

[0054] like Figure 5 and Figure 21 As shown in operation 2104, a second stacked structure 103 comprising a plurality of alternately arranged third dielectric layers 107 and a plurality of sacrificial layers 109 is formed on a first stacked structure 101. The dielectric / sacrificial layer pair may comprise staggered third dielectric layers 107 and sacrificial layers 109 extending in a plane along the x-direction and perpendicular to the y-direction. In some embodiments, each third dielectric layer 107 may comprise a silicon oxide layer, and each sacrificial layer 109 may comprise a silicon nitride layer. The second stacked structure 103 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0055] Further reference Figure 5 and Figure 21In operation 2106, a channel hole 112 is formed in the second stacked structure 103 and the first stacked structure 101 along a first direction (y-direction). In some embodiments, the channel hole 112 may penetrate the second stacked structure 103 and extend to the top surface of the first conductive layer 106. In some embodiments, the channel hole 112 may extend to the middle of the first conductive layer 106, such as... Figure 20 As shown. In some embodiments, the channel via 112 can penetrate the second stacked structure 103 and the first conductive layer 106 and expose the substrate, such as... Figure 5 As shown. Figure 5 As shown, the first dielectric layer, the first conductive layer 106, the second dielectric layer, and the second conductive layer 110 are exposed by the sidewalls of the channel via 112. In some embodiments, the fabrication process for forming the channel via 112 may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE). In some embodiments, the channel via 112 may further extend into the top of the substrate.

[0056] like Figure 6 and Figure 21 As shown in operation 2108, an oxidation operation is performed to form a fourth dielectric layer 114 on the first conductive layer 106 exposed by the sidewalls of the channel hole 112. In some embodiments, because an NH3 treatment is performed on the top surfaces of the first conductive layer 106 and the second conductive layer 110 during the formation of the first stack structure, the fourth dielectric layer 114 may be formed along the x-direction (which is a plane perpendicular to the y-direction) on the first conductive layer 106 exposed by the sidewalls of the channel hole 112.

[0057] In a plan view of the 3D storage device 100, the channel hole 112 may be circular, and the exposed sidewalls are circular circumferences. In some embodiments, the fourth dielectric layer 114 is formed starting from the circumference of a circle on the first conductive layer 106 and then extending to the center of the circle.

[0058] In some embodiments, based on the formation rate of the fourth dielectric layer 114, the fourth dielectric layer 114 formed on one side of the first conductive layer 106 in the channel hole 112 can contact the fourth dielectric layer 114 formed on the other side of the first conductive layer 106. In some embodiments, the fourth dielectric layer 114 formed on one side of the first conductive layer 106 in the channel hole 112 can be separated from the fourth dielectric layer 114 formed on the other side of the first conductive layer 106 by a gap. It is understood that the description of one side or the other side of the channel hole 112 herein is from a cross-sectional view. In the actual structure, from a plan view, the channel hole 112 can be a hole, and the fourth dielectric layer 114 formed on the first conductive layer 106 can be formed from the periphery towards the center. In some embodiments, in a plan view, the fourth dielectric layer 114 formed on the first conductive layer 106 can cover the entire channel hole 112. In some embodiments, in a plan view, the fourth dielectric layer 114 formed on the first conductive layer 106 may have a gap (hole) at the center of the channel via 112. In some embodiments, the width of the gap can be controlled during the formation operation, and the size of the gap can further lead to various structures of the memory film formed in subsequent processes. In some embodiments, the width of the gap can be controlled so that a portion or the entire memory film fills the gap. For example, a barrier layer can be formed to fill the gap.

[0059] In some embodiments, the fifth dielectric layer 116 may be formed on the second conductive layer 110 exposed by the sidewalls of the channel via 112. Because the first conductive layer 106 comprises doped polysilicon and the second conductive layer 110 comprises undoped polysilicon, the formation rate of the fourth dielectric layer 114 can be higher than that of the fifth dielectric layer 116. Therefore, the area of ​​the fourth dielectric layer 114 can be larger than the area of ​​the fifth dielectric layer 116. It can be understood that in Figure 6 In the cross-sectional view, the fifth dielectric layer 116 is formed from both sides of the second conductive layer 110. However, in the plan view of the structure, the fifth dielectric layer 116 is formed from the periphery to the center on the second conductive layer 110.

[0060] like Figure 7 and Figure 21As shown in operation 2110, a channel structure 118 may be formed in a channel hole 112. The channel structure 118 may include a storage film 125 and a semiconductor channel 132. In some embodiments, the channel structure 118 may also include a dielectric core 129 at the center of the channel structure 118. In some embodiments, the storage film 125 is a composite layer including a tunneling layer 130, a storage layer 128 (also referred to as a "charge trap layer"), and a barrier layer 126. The channel structure 118 may have a cylindrical shape (e.g., a pillar shape), and the bottom of the cylindrical shape may taper at a portion having a fifth dielectric layer 116 formed on the sidewall of the channel hole 112. In some embodiments, the channel structure 118 may be tapered, and the bottom of the tapered shape is smaller than the top of the tapered shape. In this case, the bottom of the tapered shape may taper at a portion having a fifth dielectric layer 116 formed on the sidewall of the channel hole 112.

[0061] According to some embodiments, the dielectric core 129, semiconductor channel 132, tunneling layer 130, storage layer 128, and barrier layer 126 are arranged radially from the center of the pillar toward the outer surface in this order. In some embodiments, the tunneling layer 130 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage layer 128 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the barrier layer 126 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 125 may comprise a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0062] like Figure 7 As shown, a gate slot opening 120 can also be formed along the y-direction in the second stacked structure 103 and the first stacked structure 101. The gate slot opening 120 can be formed by performing dry etching, wet etching, or other suitable processes. In some embodiments, the gate slot opening 120 can extend to the substrate 102.

[0063] like Figure 8 As shown, a polysilicon oxidation operation can be further performed in the gate slot opening 120 to form an oxide layer 121 on the first conductive layer 106 and an oxide layer 123 on the second conductive layer 110 exposed by the gate slot opening 120. The oxide layers 121 and 123 formed on the first conductive layer 106 and the second conductive layer 110 can protect the first conductive layer 106 and the second conductive layer 110 during subsequent etching processes of the word line replacement operation.

[0064] like Figure 9 As shown, a word line replacement operation is performed, and sacrificial layer 109 can be removed and replaced with word line 105. Word line 105 is... Figure 1 The conductive layer 105 is located within the cavity. For example, the sacrificial layer 109 can be removed by dry etching, wet etching, or other suitable processes to form multiple cavities. Word lines 105 can be formed in the cavities by sequentially depositing a gate dielectric layer made of a high-k dielectric material, an adhesion layer including titanium / titanium nitride (Ti / TiN) or tantalum / tantalum nitride (Ta / TaN), and a gate conductor made of tungsten. After the word line replacement operation, a stacked structure 111 is formed, such as... Figure 9 As shown.

[0065] like Figure 10 As shown, a removal process can be performed to clean the gate slot opening 120. The removal process can remove residues from previous processes from the gate slot opening 120. For example, high-k dielectric material can be removed from the gate slot opening 120.

[0066] like Figure 11 As shown, a gate gap 133 may be formed in the gate gap opening 120. In some embodiments, the gate gap 133 may include a dielectric layer. In some embodiments, the gate gap 133 may also include one or more conductive layers, such as polysilicon, tungsten (W), or a combination of polysilicon and W.

[0067] like Figure 12 As shown, the dummy channel structure 124 can be formed in the stacked structure 111 extending in the y-direction. In some embodiments, the contact structure 134 can be formed in the stacked structure 111 extending in the y-direction. In some embodiments, the contact structure 134 can contact the second conductive layer 110.

[0068] In some embodiments, the gate gap 133 may be formed prior to the word line replacement operation. In some embodiments, after the gate gap 133, the dummy channel structure 124, and the contact structure 134 are formed on the substrate 102, one or more interconnect layers may also be formed on the memory array. Furthermore, peripheral circuitry may be formed on another substrate and bonded to the memory array in a subsequent process.

[0069] like Figure 13 and Figure 21As shown in operation 2112, a substrate removal operation is performed. In some embodiments, the substrate 102 can be removed by wet etching, dry etching, or other suitable processes until stopped by the first dielectric layer 104. When the substrate 102 is removed using wet etching, the bottom surface of the channel structure 118 is higher than the bottom surfaces of the gate gap 133 and the dummy channel structure 124; therefore, in the final structure, the bottom surface of the semiconductor channel 132 is higher than the bottom surfaces of the gate gap 133 and the dummy channel structure 124. In some embodiments, the substrate 102 can be removed by a chemical mechanical polishing (CMP) process, and the bottom of the gate gap 133 and the dummy channel structure 124 can be removed together, such as... Figure 22 and Figure 23 As shown.

[0070] In some embodiments, substrate 102 can be stripped. In some embodiments where substrate 102 comprises silicon and the stop layer (first dielectric layer 104) comprises a dielectric layer such as silicon oxide or silicon nitride, silicon CMP can be used to remove substrate 102, and the silicon CMP can automatically stop when a stop layer with a material other than silicon is reached, i.e., it acts as a back-side CMP stop layer. In some embodiments, wet etching with tetramethylammonium (TMAH) is used to remove substrate 102, and the wet etching automatically stops when a stop layer with a material other than silicon is reached, i.e., it acts as a back-side etching stop layer.

[0071] Then, as Figure 14 and Figure 21 As shown in operation 2114, the first dielectric layer 104 and the fourth dielectric layer 114 are removed. In some embodiments, the first dielectric layer 104 and the fourth dielectric layer 114 can be removed by wet etching, dry etching, CMP, or other suitable processes. After the first dielectric layer 104 and the fourth dielectric layer 114 are removed, the bottom of the channel structure 118 is exposed. In some embodiments, the bottom of the dielectric layer of the gate gap 133 is also removed. In some embodiments, a portion of the barrier layer 126 may also be removed together with the fourth dielectric layer 114.

[0072] Because the channel structure 118 is formed on the fourth dielectric layer 114, such as Figure 7 As shown, a fourth dielectric layer 114 is formed through a polysilicon oxidation operation, as... Figure 6As shown, before removing the first dielectric layer 104 and the fourth dielectric layer 114, the bottom of the channel structure 118 (which is the bottommost position of the barrier layer 126) can be controlled to be coplanar with or slightly higher than the top surface of the first conductive layer 106. After removing part of the memory film in a subsequent process, the bottom surface of the semiconductor channel 132 can be above the first conductive layer 106, coplanar with the bottom surface of the second conductive layer 110, coplanar with the top surface of the second conductive layer 110, between the bottom and top surfaces of the second conductive layer 110, coplanar with the bottom surface of the bottommost layer in the third dielectric layer 107, or above the bottom surface of the bottommost layer in the third dielectric layer 107. Therefore, by using the polysilicon oxidation operation performed on the first conductive layer 106, the depth of the channel structure 118 can be controlled within a predetermined range, and the depth or bottom profile of the channel structure 118 is not affected by the residue formed in the channel via 112. This improves the control of the channel profile.

[0073] Then, as Figure 15 and Figure 21 As shown in operation 2112, the first conductive layer 106 is removed. In some embodiments, the first conductive layer 106 can be removed by wet etching, dry etching, CMP, or other suitable processes.

[0074] like Figure 16 As shown, the second dielectric layer 108 is removed to expose the second conductive layer 110, and portions of the memory film are removed to expose portions of the tunneling layer 130, the memory layer 128, and the barrier layer 126. In some embodiments, portions of the memory film and the second dielectric layer 108 are removed by a single etching process. In some embodiments, portions of the memory film and the second dielectric layer 108 are removed by multiple etching processes. For example, the second dielectric layer 108 may be removed first. The memory layer 128, including silicon nitride, is selectively removed using wet etching with a suitable etchant (e.g., phosphoric acid) without etching the second conductive layer 110. The etching of the memory layer 128 can be controlled by controlling the etching time and / or etching rate so that the etching does not continue to affect the remaining portions of the memory layer 128 surrounded by the memory stack. The barrier layer 126, including silicon oxide, and the tunneling layer 130, are then selectively removed using wet etching with a suitable etchant (e.g., hydrofluoric acid) without etching the second conductive layer 110, including polysilicon, and the semiconductor channel 132. The etching of the barrier layer 126 and tunneling layer 130 can be controlled by controlling the etching time and / or etching rate, so that the etching does not continue to affect the remaining portions of the barrier layer 126 and tunneling layer 130 surrounded by the memory stack. In some embodiments, after the portion of the memory film is removed, the bottom surfaces of the exposed portions of the tunneling layer 130, memory layer 128, and barrier layer 126 are above the bottom surface of the semiconductor channel 132.

[0075] In some embodiments, the removal order of the first dielectric layer 104, the fourth dielectric layer 114, and the first conductive layer 106 in operation 2112 may be different. In some embodiments, the removal order may vary. Figure 13 After the substrate 102 is shown, the first dielectric layer 104 can be removed separately while the fourth dielectric layer 114 remains. Then, the first conductive layer 106 surrounding the fourth dielectric layer 114 is removed. Subsequently, the fourth dielectric layer 114 and the second dielectric layer 108 can be removed in the same process.

[0076] Because during the formation of the channel structure 118, the fifth dielectric layer 116 forms a protrusion along the x-direction on the sidewall of the channel hole 112, the cylindrical bottom of the channel structure 118 is affected by the fifth dielectric layer 116 and forms a contraction structure or depression, such as Figure 7 As shown. After removing the bottom of the storage membrane, in some embodiments, the exposed portions of the tunneling layer 130 and the storage layer 128 may have a smaller critical dimension (or diameter as seen in plan view) than that of the tunneling layer 130 and the storage layer 128 located at the top of the channel structure 118, such as... Figure 16 As shown. Furthermore, in some embodiments, the exposed portion of the semiconductor channel 132 at the bottom of the channel structure 118 also has a smaller critical dimension (or diameter as seen in plan view) than the semiconductor channel 132 at the top of the channel structure 118, such as... Figure 16 As shown.

[0077] In some embodiments, the second dielectric layer 108 can be removed by a CMP process, and the bottom surface of the gate gap 133 and the bottom surface of the dummy channel structure 124 can be coplanar or substantially coplanar with the bottom surface of the second conductive layer 110, such as... Figure 22 or Figure 23 As shown.

[0078] Because the fifth dielectric layer 116 is formed on the second conductive layer 110 through a polysilicon oxidation operation, such as Figure 6 As shown, and subsequently a storage film is formed on the fifth dielectric layer 116, the barrier layer 126, storage layer 128, and tunneling layer 130 may not be a straight structure along the y-direction. The width W1 of the bottom of the barrier layer 126 may be greater than the width W2 of the top of the barrier layer 126, as shown. Figure 16 As shown. In addition, the storage layer 128 and the tunneling layer 130 may form angular structures at the bottom of the storage membrane.

[0079] like Figure 17As shown, a third conductive layer 136 is formed over the exposed channel structure 118 and the second conductive layer 110. In some embodiments, the third conductive layer 136 may be a polysilicon layer. In some embodiments, the third conductive layer 136 may be formed by CVD, PVD, ALD, or other suitable processes.

[0080] like Figure 18 As shown, through-silicon contacts (TSCs) are formed to expose the contact structure. For example... Figure 19 As shown, contact pads 138 are formed that are in contact with contact structure 134 or with the third conductive layer 136.

[0081] Figure 22 A cross-section of another exemplary 3D storage device 200 according to some aspects of this disclosure is shown. Figure 22 The 3D storage device 200 shown includes a channel structure 118, a gate gap 133, and a dummy channel structure 124. The bottom of the gate gap 133 and the bottom of the dummy channel structure 124 may be coplanar or substantially coplanar with the bottom surface of the second conductive layer 110. In some embodiments, the bottom of the gate gap 133 and the bottom of the dummy channel structure 124 may be coplanar or substantially coplanar with the bottom surface of the semiconductor channel 132. For example, in some embodiments, during the removal operation of the first dielectric layer 104, the first conductive layer 106, and / or the second dielectric layer 108, the bottom of the gate gap 133 and the bottom of the dummy channel structure 124 may be removed together with the channel structure 118. In some embodiments, the bottom surface of the gate gap 133 and the bottom surface of the dummy channel structure 124 may be coplanar with or slightly higher than the bottom surface of the second conductive layer 110, such as... Figure 22 As shown.

[0082] Figure 23 A cross-section of yet another exemplary 3D storage device 300 according to some aspects of this disclosure is shown. The bottom surface of the channel structure 118, such as the bottom surface of the semiconductor channel 132, may be above the top surface of the second conductive layer 110, such as... Figure 23 As shown. In some embodiments, the bottom surface of the channel structure 118, such as the bottom surface of the semiconductor channel 132, may be coplanar with the top surface of the second conductive layer 110. In some embodiments, the bottom surface of the channel structure 118, such as the bottom surface of the semiconductor channel 132, may be below the top surface of the second conductive layer 110, such as... Figure 22 As shown.

[0083] By forming a fourth dielectric layer 114 on the first conductive layer 106 exposed by the sidewalls of the via 112, the via 112 can be completely or partially filled by the fourth dielectric layer 114. Therefore, the bottom of the channel structure 118 can be defined by the positions of the fourth dielectric layer 114 and the first conductive layer 106. The bottom of the channel structure 118 is not affected by the via etching trench, and thus the process window for via formation is greatly increased.

[0084] Figure 24 A cross-section of an exemplary 3D storage device 400 according to some aspects of this disclosure is shown. For example... Figure 24 As shown, the 3D storage device 400 includes a stacked structure 402 and a channel structure 404 extending through the stacked structure 402 in the y-direction. The stacked structure 402 may include interleaved conductive and dielectric layers, similar to the stacked structure 111 of the 3D storage device 100. In some embodiments, the formation and materials of the stacked structure 402 may be similar to those of the stacked structure 111.

[0085] Figure 25 A cross-section of the bottom of a channel structure 404 of a 3D memory device 400 according to some aspects of the present disclosure is shown. The channel structure 404 may extend through a stacked structure 402, and the bottom of the channel structure 404 may contact the source of the 3D memory device 400. In some embodiments, the channel structure 404 may include a semiconductor channel 132 and a memory film 125 formed over the semiconductor channel 132, similar to the channel structure 118 of the 3D memory device 100. However, the structure of the bottom of the channel structure 404 differs from that of the channel structure 118. In some embodiments, the channel structure 404 may also include a dielectric core 129 located at the center of the channel structure 404. In some embodiments, the memory film 125 may include a tunneling layer 130 over the semiconductor channel 132, a memory layer 128 over the tunneling layer 130, and a barrier layer 126 over the memory layer 128.

[0086] like Figure 25 As shown, the bottom 412 of the channel structure 404 may include a curved structure of the barrier layer 126, the tunneling layer 130, and the storage layer 128. In some embodiments, in the plan view of the 3D storage device 400, the bottom 412 of the channel structure 404 may have an outer diameter W5, and the upper portion 414 of the channel structure 404 may have an outer diameter W6. In some embodiments, W5 is smaller than W6. In some embodiments, the storage film 125 may include an angular structure 422, and the outer diameter W5 of the storage film 125 at the bottom below the angular structure 422 is smaller than the outer diameter W6 of the storage film 125 at the upper portion above the angular structure 422. For example, as Figure 25As shown, the storage film 125 can be formed as two right-angled structures. In some embodiments, the storage film 125 can be formed as an obtuse-angled structure, an acute-angled structure, a right-angled structure, an arc-angled structure, or any combination of these angular structures.

[0087] In some embodiments, in a plan view of the 3D storage device 400, the semiconductor channel 132 in the bottom 412 of the channel structure 404 may have an outer diameter W7, and the semiconductor channel 132 in the upper 414 of the channel structure 404 may have an outer diameter W8. In some embodiments, W7 is smaller than W8. In some embodiments, the semiconductor channel 132 may include a corner structure 424, and the outer diameter W7 of the semiconductor channel 132 at the bottom of the channel structure 404 below the corner structure 424 is smaller than the outer diameter W8 of the semiconductor channel 132 at the upper part of the channel structure 404 above the corner structure 424. For example, as Figure 25 As shown, the semiconductor channel 132 can be formed as a right-angled structure. In some embodiments, the semiconductor channel 132 can be formed as an obtuse-angled structure, an acute-angled structure, a right-angled structure, an arc-angled structure, or any combination of these angular structures.

[0088] The 3D storage device 400 may further include a conductive layer 406 in direct contact with the stacked structure 402, and a doped conductive layer 408 disposed below the conductive layer 406. In some embodiments, the conductive layer 406 may be a polysilicon layer, and the doped conductive layer 408 may be a doped polysilicon layer. In some embodiments, the 3D storage device 400 may further include a dielectric layer 410 disposed between the conductive layer 406 and the bottom 412 of the channel structure 404. In a plan view of the 3D storage device 400, the dielectric layer 410 may surround the bottom 412 of the channel structure 404, and the conductive layer 406 may surround the dielectric layer 410. The doped conductive layer 408 is disposed below the conductive layer 406, the dielectric layer 410, and the channel structure 404. In some embodiments, the doped conductive layer 408 may be in direct contact with the bottom surface of the storage film 125 and the semiconductor channel 132. In some embodiments, the dielectric core 129 is formed only in the upper portion 414 of the channel structure 404.

[0089] Figure 26 A cross-section of the bottom of another channel structure 504 of a 3D storage device 500 according to some aspects of this disclosure is shown. The channel structure 504 (including the upper portion 514) of the 3D storage device 500 is similar to the channel structure 404 of the 3D storage device 400, but the bottom 512 of the channel structure 504 is different. Figure 26As shown, a portion of the doped conductive layer 408 extends into the conductive layer 406. The extended portion of the doped conductive layer 408 surrounds the bottom 512 of the channel structure 504. The conductive layer 406 further surrounds the extended portion of the doped conductive layer 408. In some embodiments, the bottom surface of the storage film 125 is in direct contact with the doped conductive layer 408. In some embodiments, the top surface of the polysilicon layer 406 is coplanar with the top surface of the doped polysilicon layer 408 and the bottom surface of the storage film 125.

[0090] Figure 27 A cross-section of the bottom of the channel structure 604 of a 3D memory device 600 according to some aspects of this disclosure is shown. In some embodiments, the channel structure 604 of the 3D memory device 600 may be similar to the channel structure 404 of the 3D memory device 400, but the 3D memory device 600 does not include a doped polysilicon layer beneath the conductive layer 406. In some embodiments, the channel structure 604 of the 3D memory device 600 may be directly coupled to an interconnect structure. For example, the channel structure 604 of the 3D memory device 600 may be directly coupled to a pad lead-out structure without forming a doped polysilicon layer beneath the channel structure.

[0091] Figure 28 A cross-section of the bottom of the channel structure 704 of a 3D storage device 700 according to some aspects of this disclosure is shown. In some embodiments, the channel structure 704 of the 3D storage device 700 may be similar to the channel structure 504 of the 3D storage device 500, but the doped conductive layer 408 of the 3D storage device 700 may not be formed below the conductive layer 406. For example... Figure 28 As shown, the doped conductive layer 408 of the 3D memory device 700 may surround the bottom 512 of the channel structure 704. A conductive layer 406 further surrounds the doped conductive layer 408. In some embodiments, the channel structure 704 of the 3D memory device 700 may be directly coupled to an interconnect structure. For example, the channel structure 704 of the 3D memory device 700 may be directly coupled to a pad lead-out structure without forming a doped polysilicon layer beneath the conductive layer 406.

[0092] Figures 29-40 Cross sections of a 3D storage device 400 at different stages of the manufacturing process according to some aspects of this disclosure are shown. Figure 41 A flowchart illustrating an exemplary method 4100 for forming a 3D storage device 400 according to some aspects of this disclosure is shown. To better describe this disclosure, it will be discussed together. Figures 29-40 The cross-section of the 3D storage device 400 in the middle and Figure 41 Method 4100. It is understood that the operations shown in method 4100 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figures 29-40 and Figure 41 The different execution sequences are shown.

[0093] like Figure 29 and Figure 41 As shown in operation 4102, a stacked structure 452 including a dielectric layer 456 and a conductive layer 406 is formed on a substrate 458. In some embodiments, the substrate 458 may be a doped semiconductor layer. In some embodiments, the dielectric layer 456 may include a silicon oxide or silicon nitride layer. In some embodiments, the conductive layer 406 may include a doped polysilicon layer or an undoped polysilicon layer. In some embodiments, the dielectric layer 456 and the conductive layer 406 may be deposited sequentially using one or more thin-film deposition processes, as described above. Figure 14 and Figure 21 The operations shown in 2114 include, but are not limited to, CVD, PVD, ALD, or any combination thereof.

[0094] Then, as Figure 29 and Figure 41 As shown in operation 4104, a stacked structure 454 comprising a plurality of alternately arranged dielectric layers 462 and a plurality of sacrificial layers 460 is formed on the stacked structure 452. The dielectric / sacrificial layer pair may comprise staggered dielectric layers 462 and sacrificial layers 460 extending in a plane along the x-direction and perpendicular to the y-direction. In some embodiments, each dielectric layer 462 may comprise a silicon oxide layer, and each sacrificial layer 460 may comprise a silicon nitride layer. The stacked structure 454 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0095] like Figure 30 and Figure 41 As shown in operation 4106, a channel via 464 is formed that penetrates the stacked structures 454 and 452 along the y-direction, and the substrate 458 is exposed by the channel via 464. In some embodiments, the fabrication process for forming the channel via 464 may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE).

[0096] Then, as Figure 30 and Figure 41 As shown in operation 4108, an oxidation operation is performed to form a dielectric layer 410 on the conductive layer 406 exposed by the sidewalls of the channel via 464. In some embodiments, the dielectric layer 410 is further formed on the bottom of the channel via 464 on the substrate 458. In some embodiments, the dielectric layer 410 is further formed on the dielectric layer 456. In some embodiments, the dielectric layer 410 is formed on the conductive layer 406 along the x-direction. Figure 30As shown, after the dielectric layer 410 is formed, the channel hole 464 has a width W9 (or diameter in the plan view) at the portion having the dielectric layer 410 formed on the sidewall, and a width W10 at the portion not having the dielectric layer 410 formed on the sidewall. In some embodiments, the width W9 is smaller than the width W10.

[0097] like Figure 31 and Figure 41 As shown in operation 4110, a channel structure 404 may be formed in a channel via 464. The channel structure 404 may include a storage film 125 and a semiconductor channel 132. In some embodiments, the storage film 125 is a composite layer including a tunneling layer 130, a storage layer 128 (also referred to as a "charge trapping layer"), and a barrier layer 126, such as... Figure 25 As shown. The channel structure 404 may have a cylindrical shape (e.g., a pillar shape), and the bottom of the cylindrical shape may taper at a portion having a dielectric layer 410 formed on the sidewalls of the channel hole 464. The formation of the channel structure 404 may include conformally forming a storage film 125 in the channel hole 464, and then forming a semiconductor channel 132 in the channel hole 464 above the storage film 125, as shown. Figure 41 As shown in operation 4112. Figure 31 As shown, because the channel hole 464 has a smaller width W9 at the portion having the dielectric layer 410 formed on the sidewall, the semiconductor channel 132 can completely fill the channel hole 464 at the portion having the dielectric layer 410 formed on the sidewall.

[0098] like Figure 32 As shown, a polysilicon etch-back operation can be performed on the thin semiconductor channel 132, and a dielectric core 129 can be formed at the center of the channel structure 404. According to some embodiments, the dielectric core 129, semiconductor channel 132, tunneling layer 130, storage layer 128, and barrier layer 126 are arranged radially from the center of the pillar toward the outer surface in this order. Because the semiconductor channel 132 can completely fill the channel hole 464 at the portion of the channel hole having a dielectric layer 410 formed on the sidewalls, the dielectric core 129 can be formed over the completely filled portion of the semiconductor channel 132. In some embodiments, the tunneling layer 130 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage layer 128 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the barrier layer 126 may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 125 may include a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0099] like Figure 33As shown, a gate slot 466 can be formed. An opening slot extending vertically through stacked structures 454 and 452 can be formed first. In some embodiments, the fabrication process for forming the slot may include wet etching and / or dry etching, such as DRIE. A gate replacement process can then be performed through the slot to replace the sacrificial layer 460 with a word line structure. An insulating structure may be completely or partially filled in the slot (with or without an air gap) to form the gate slot 466 using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0100] After forming the gate gap 466, local contacts including channel local contacts 468 and word line local contacts 470, as well as peripheral contacts 472, are formed. A local dielectric layer can be formed on the stacked structure 402 by depositing a dielectric material such as silicon oxide or silicon nitride on top of the stacked structure 402 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Contact openings can be etched through the local dielectric layer (and any other interlayer dielectric (ILD) layer) using wet etching and / or dry etching (e.g., RIE), and then the contact openings are filled with a conductive material using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the channel local contacts 468, word line local contacts 470, and peripheral contacts 472.

[0101] like Figure 34 As shown, a bonding layer 474 is formed over the channel local contact 468, the word line local contact 470, and the peripheral contact 472. The bonding layer 474 may include bonding contacts electrically connected to the channel local contact 468, the word line local contact 470, and the peripheral contact 472. Then, as... Figure 35 As shown, the storage stack and peripheral circuitry 476 are bonded face-to-face. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding.

[0102] like Figure 36 and Figure 41As shown in operation 4114, substrate 458 is removed to expose dielectric layer 456. In some embodiments, substrate 458 can be completely removed using CMP, polishing, dry etching, and / or wet etching. In some embodiments, substrate 458 is stripped. In some embodiments where substrate 458 comprises silicon, dielectric layer 456 can be used as a stop layer, such as silicon nitride, which automatically stops when silicon CMP is used to remove substrate 458, i.e., acts as a back-side CMP stop layer, upon reaching dielectric layer 456 containing materials other than silicon. In some embodiments, substrate 458 (silicon substrate) is removed using wet etching with tetramethylammonium (TMAH), which automatically stops when reaching dielectric layer 456 containing materials other than silicon, i.e., acts as a back-side etching stop layer. Dielectric layer 456 can ensure complete removal of substrate 458 without concern for thickness uniformity after thinning.

[0103] like Figure 37 and Figure 41 As shown in operation 4114, in some embodiments, after removing the substrate 458, a planarization operation, such as CMP, may be further performed to remove the dielectric layer 456, a portion of the storage film 125, and a portion of the semiconductor channel 132. In some embodiments, after removing the dielectric layer 456, the upper surface of the conductive layer 406 is coplanar with the top surface of the dielectric layer 410, the storage film 125, and the semiconductor channel 132.

[0104] like Figure 38 As shown, an implantation operation can be performed on the semiconductor channel 132 to dope the top of the polysilicon material of the semiconductor channel 132, and then a doped conductive layer 408 can be formed on the conductive layer 406, the dielectric layer 410, the storage film 125, and the semiconductor channel 132. In some embodiments, an activation operation, such as a laser activation operation, can be further performed on the doped conductive layer 408. In some embodiments, the doped conductive layer 408 is in direct contact with the dielectric layer 410, the storage film 125, and the semiconductor channel 132.

[0105] like Figure 39 and Figure 41 As shown in operation 4116, an interconnect structure is formed that contacts the semiconductor channel 132. An ILD layer 480 can be formed on the doped conductive layer 408, and then source contact openings can be formed in the ILD layer 480. Source contacts 478 are formed in the source contact openings. In some embodiments, contacts 482 are formed extending through the ILD layer 480 and contacting peripheral contacts. Figure 40 As shown, the redistribution layer 484 is formed on the source contact 478 and contact 482.

[0106] Figure 42A cross-section of an exemplary 3D storage device 800 according to some aspects of this disclosure is shown. For example... Figure 42 As shown, the 3D storage device 800 includes a stacked structure 802 and a channel structure 804 extending through the stacked structure 802 in the y-direction. The stacked structure 802 may include interleaved conductive and dielectric layers, similar to the stacked structure 111 of the 3D storage device 100. In some embodiments, the formation and materials of the stacked structure 802 may be similar to those of the stacked structure 111.

[0107] Figure 43 A cross-section of the bottom of a channel structure 804 of a 3D memory device 800 according to some aspects of the present disclosure is shown. The channel structure 804 may extend through a stacked structure 802, and the bottom of the channel structure 804 may contact the source of the 3D memory device 800. In some embodiments, the channel structure 804 may include a semiconductor channel 132 and a memory film 125 formed on the semiconductor channel 132, the semiconductor channel 132 being similar to the channel structure 118 of the 3D memory device 100. However, the structure of the bottom of the channel structure 804 differs from that of the channel structure 118. In some embodiments, the channel structure 804 may also include a dielectric core 129 located at the center of the channel structure 804. In some embodiments, the memory film 125 may include a tunneling layer 130 over the semiconductor channel 132, a memory layer 128 over the tunneling layer 130, and a barrier layer 126 over the memory layer 128.

[0108] like Figure 43 As shown, the bottom 812 of the channel structure 804 may include a curved structure of the barrier layer 126, the tunneling layer 130, and the storage layer 128. In some embodiments, in the plan view of the 3D storage device 800, the bottom 812 of the channel structure 804 may have a diameter W11, and the upper portion 814 of the channel structure 804 may have a diameter W12. In some embodiments, W11 is smaller than W12. In some embodiments, in the plan view of the 3D storage device 800, the dielectric core 129 may have a diameter W13 in the bottom 812 of the channel structure 804, and the dielectric core 129 may have a diameter W14 in the upper portion 814 of the channel structure 804. In some embodiments, W13 is smaller than W14.

[0109] The 3D storage device 800 may further include a conductive layer 806 in direct contact with the stacked structure 802, and a doped conductive layer 808 disposed below the conductive layer 806. In some embodiments, the conductive layer 806 may be a polysilicon layer, and the doped conductive layer 808 may be a doped polysilicon layer. In some embodiments, a portion of the doped conductive layer 808 may extend into the conductive layer 806. Figure 43As shown, the bottom of the semiconductor channel 132 can extend into an extension of the doped conductive layer 808, and the extension of the doped conductive layer 808 surrounds the bottom 812 of the semiconductor channel 132. The conductive layer 806 further surrounds the extension of the doped conductive layer 808. In some embodiments, the bottom surface of the storage film 125 is in direct contact with the doped conductive layer 808. In some embodiments, the top surface of the conductive layer 806 is coplanar with the top surface of the doped conductive layer 808 and the bottom surface of the storage film 125.

[0110] The difference between the channel structure 804 of the 3D storage device 800 and the channel structure 404 of the 3D storage device 400 lies in the structure at the bottom of the channel structure. For example... Figure 43 As shown, the dielectric core 129 can fill the spaces between semiconductor channels 132 at the narrow portion (bottom 812) of the channel structure 804; however, the dielectric core 129 can also be formed above the semiconductor channels 132 at the narrow portion (bottom 412) of the channel structure 804. This difference may be due to the formation processes of the memory film 125 and the semiconductor channels 132. When the semiconductor channel 132 is formed to completely fill the narrow portion of the channel hole, the subsequently formed dielectric core 129 can be formed above the semiconductor channel 132. When the semiconductor channel 132 is formed to partially fill the narrow portion of the channel hole, the subsequently formed dielectric core 129 can fill the spaces between the semiconductor channels 132.

[0111] By forming a dielectric layer 410 on the conductive layer 406 exposed by the sidewalls of the channel hole 464, the bottom of the channel structure 404 can be defined by the positions of the dielectric layer 410 and the conductive layer 406. The bottom of the channel structure 404 will not be affected by the etching trench of the channel hole, thus greatly increasing the process window for channel hole formation.

[0112] Figure 44-52 Cross sections of a 3D storage device 800 at different stages of the manufacturing process according to some aspects of this disclosure are shown. Figure 53 A flowchart illustrating an exemplary method 5300 for forming a 3D storage device 800 according to some aspects of this disclosure is shown. To better describe this disclosure, it will be discussed together. Figure 44-52 The cross-section of the 3D storage device 800 in the middle and Figure 53 Method 5300. It is understood that the operations shown in Method 5300 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously, or in different sequences. Figure 44-52 and Figure 53 Execute in the order shown.

[0113] like Figure 44 and Figure 53As shown in operation 5302, a stacked structure 852 comprising a dielectric layer 856 and a conductive layer 806 is formed on a substrate 858. In some embodiments, the substrate 858 may be a doped semiconductor layer. In some embodiments, the dielectric layer 856 may comprise a silicon oxide or silicon nitride layer. In some embodiments, the conductive layer 806 may comprise a doped polysilicon layer or an undoped polysilicon layer. In some embodiments, the dielectric layer 856 and the conductive layer 806 may be deposited sequentially using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0114] Then, as Figure 44 and Figure 53 As shown in operation 5304, a stacked structure 854 comprising a plurality of alternately arranged dielectric layers 862 and a plurality of sacrificial layers 860 is formed on the stacked structure 852. The dielectric / sacrificial layer pair may comprise staggered dielectric layers 862 and sacrificial layers 860 extending in a plane along the x-direction and perpendicular to the y-direction. In some embodiments, each dielectric layer 862 may comprise a silicon oxide layer, and each sacrificial layer 860 may comprise a silicon nitride layer. The stacked structure 854 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0115] like Figure 44 and Figure 53 As shown in operation 5306, a channel via 864 is formed that penetrates the stacked structures 854 and 852 along the y-direction, and the substrate 858 is exposed by the channel via 864. In some embodiments, the fabrication process for forming the channel via 864 may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE).

[0116] Then, as Figure 44 and Figure 53 As shown in operation 5308, an oxidation operation is performed to form a dielectric layer 810 on the conductive layer 806 exposed by the sidewalls of the channel via 864. In some embodiments, the dielectric layer 810 is further formed on the bottom of the channel via 864 on the substrate 858. In some embodiments, the dielectric layer 810 is further formed on the dielectric layer 856. In some embodiments, the dielectric layer 810 is formed on the conductive layer 806 along the x-direction. Figure 44 As shown, after the dielectric layer 810 is formed, the channel hole 864 has a width W15 (or diameter in the plan view) at the portion having the dielectric layer 810 formed on the sidewall, and a width W16 at the other portion not having the dielectric layer 810 formed on the sidewall. In some embodiments, the width W15 is smaller than the width W16.

[0117] like Figure 45 and Figure 53 As shown in operation 5310, a channel structure 804 may be formed in a channel via 864. The channel structure 804 may include a storage film 125 and a semiconductor channel 132. In some embodiments, the storage film 125 is a composite layer including a tunneling layer 130, a storage layer 128 (also referred to as a "charge trapping layer"), and a barrier layer 126, such as... Figure 43 As shown. The channel structure 804 may have a cylindrical shape (e.g., a pillar shape), and the bottom of the cylindrical shape may taper at a portion having a dielectric layer 810 formed on the sidewalls of the channel hole 864. The formation of the channel structure 804 may include conformally forming a storage film 125 in the channel hole 864, and then forming a semiconductor channel 132 in the channel hole 864 above the storage film 125, as shown. Figure 53 The operation is shown in 5312. Figure 45 As shown, because the channel hole 864 has a smaller width W15 at the portion having a dielectric layer 810 formed on the sidewall, the semiconductor channel 132 can completely fill the channel hole 864 at the portion having a dielectric layer 810 formed on the sidewall.

[0118] A polysilicon etch-back operation can be performed on the thin semiconductor channel 132, and a dielectric core 129 can be formed at the center of the channel structure 804. Because the semiconductor channel 132 can completely fill the channel hole 864 at the portion of the channel hole having a dielectric layer 810 formed on the sidewalls, the dielectric core 129 can completely fill the center of the channel structure 804 at the portion of the channel hole having a dielectric layer 810 formed on the sidewalls, such as... Figure 53 The operation 5312 is shown in the diagram. According to some embodiments, the dielectric core 129, semiconductor channel 132, tunneling layer 130, storage layer 128, and barrier layer 126 are arranged radially from the center of the pillar toward the outer surface in this order. In some embodiments, the tunneling layer 130 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage layer 128 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the barrier layer 126 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 125 may comprise a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0119] like Figure 46As shown, a gate gap 866 can be formed, and then a gate replacement can be performed to replace the sacrificial layer 860 with a word line structure. An insulating structure can be completely or partially filled in the gap (with or without an air gap) to form the gate gap 866 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0120] After forming the gate gap 866, local contacts including channel local contacts 868 and word line local contacts 870, as well as peripheral contacts 872, are formed. A local dielectric layer can be formed on the stacked structure 802 by depositing a dielectric material such as silicon oxide or silicon nitride on top of the stacked structure 802 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Contact openings can be etched through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the channel local contacts 868, word line local contacts 870, and peripheral contacts 872.

[0121] A bonding layer 874 is formed over the channel local contact 868, the word line local contact 870, and the peripheral contact 872. The bonding layer 874 may include bonding contacts electrically connected to the channel local contact 868, the word line local contact 870, and the peripheral contact 872. Then, as... Figure 47 As shown, the storage stack and peripheral circuitry 876 are bonded face-to-face. In some embodiments, a processing technique (e.g., plasma treatment, wet processing, and / or heat treatment) is applied to the bonding surfaces prior to bonding.

[0122] like Figure 48 and Figure 53 As shown in operation 5314, substrate 858 is removed to expose dielectric layer 856. In some embodiments, substrate 858 can be completely removed using CMP, polishing, dry etching, and / or wet etching. In some embodiments, substrate 858 is stripped. In some embodiments where substrate 858 comprises silicon, dielectric layer 856 can be used as a stop layer, such as silicon nitride, which can automatically stop when silicon CMP is used to remove substrate 458 and reaches dielectric layer 856, which has a material other than silicon, i.e., acts as a back-side CMP stop layer. In some embodiments, substrate 858 (silicon substrate) is removed using wet etching via TMAH, which automatically stops when dielectric layer 856, which has a material other than silicon, is reached, i.e., acts as a back-side etching stop layer. Dielectric layer 856 can ensure complete removal of substrate 858 without concern for thickness uniformity after thinning.

[0123] like Figure 49 and Figure 53 As shown in operation 5314, in some embodiments, after removing the substrate 858, a planarization operation, such as CMP, may be further performed to remove the dielectric layer 856, a portion of the storage film 125, and a portion of the semiconductor channel 132. In some embodiments, after removing the dielectric layer 856, the top surface of the conductive layer 806 is coplanar with the top surfaces of the dielectric layer 810, the storage film 125, and the semiconductor channel 132.

[0124] Then, as Figure 50 As shown, portions of the storage film 125 and the dielectric layer 810 can be removed to form a recess exposing the side surfaces of the semiconductor channel 132. In some embodiments, portions of the storage film 125 (including silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO)) and the dielectric layer 810 can be removed by dry etching, wet etching, or other suitable processes. An implantation operation can be performed on the semiconductor channel 132 to dope the top of the polysilicon material of the semiconductor channel 132, and then a doped conductive layer 808 can be formed on the conductive layer 806 and in the recess. In some embodiments, an activation operation, such as a laser activation operation, can be further performed on the doped conductive layer 808. In some embodiments, the doped conductive layer 808 is in direct contact with the storage film 125 and the semiconductor channel 132.

[0125] like Figure 52 and Figure 53 As shown in operation 5316, an interconnect structure is formed that contacts the semiconductor channel 132. An ILD layer 880 can be formed on the doped conductive layer 808, and then source contact openings can be formed in the ILD layer 880. Source contacts 878 are formed in the source contact openings. In some embodiments, contacts 882 are formed that extend through the ILD layer 880 and contact peripheral contacts. Figure 52 As shown, a redistribution layer 884 can be formed on the source contact 878 and contact 882.

[0126] By forming a dielectric layer 810 on the conductive layer 806 exposed by the sidewalls of the channel hole 864, the bottom of the channel structure 804 can be defined by the positions of the dielectric layer 810 and the conductive layer 806. The bottom of the channel structure 804 will not be affected by the etching trench of the channel hole, thus greatly increasing the process window for channel hole formation.

[0127] Figure 54A block diagram of an exemplary system 900 having a storage device according to some aspects of this disclosure is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 54 As shown, system 900 may include a host 908 and a memory system 902 having one or more storage devices 904 and a storage controller 906. The host 908 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 908 may be configured to send data to or receive data from storage device 904.

[0128] Storage device 904 can be any storage device disclosed herein. As detailed above, storage device 904, such as a NAND flash memory device, can have a controlled and predefined discharge current during the bit-line discharge operation. According to some embodiments, storage controller 906 is coupled to storage device 904 and host 908 and is configured to control storage device 904. Storage controller 906 can manage data stored in storage device 904 and communicate with host 908. For example, storage controller 906 can be coupled to storage device 904, such as 3D storage devices 100, 200, 300, 400, 500, 600, 700, or 800 as described above, and storage controller 906 can be configured to control the operation of channel structures 118, 404, 504, 604, 704, or 804 via peripheral devices. By forming a dielectric layer on the polysilicon layer exposed by the sidewalls of the channel hole, the bottom of the channel structure will not be affected by the etch trench of the channel hole, and thus the process window for forming 3D memory devices of 100, 200, 300, 400, 500, 600, 700 or 800 will be greatly increased.

[0129] In some embodiments, the storage controller 906 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the storage controller 906 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The storage controller 906 can be configured to control the operation of the storage device 904, such as read, erase, and program operations. The storage controller 906 can also be configured to manage various functions for data that has been stored or will be stored in the storage device 904, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the storage controller 906 is also configured to process error correction codes (ECC) for data read from or written to the storage device 904. Storage controller 906 may also perform any other suitable function, such as formatting storage device 904. Storage controller 906 may communicate with external devices (e.g., host 908) according to specific communication protocols. For example, storage controller 906 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0130] The storage controller 906 and one or more storage devices 904 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 902 can be implemented and packaged into different types of end electronic products. Figure 55A In one example shown, the storage controller 906 and a single storage device 904 can be integrated into the memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1002 may also include a connection between the memory card 1002 and a host (e.g., Figure 18The memory card connector 1004 is coupled to the host 908. In such a... Figure 55B In another example shown, the storage controller 906 and multiple storage devices 904 can be integrated into the SSD 1006. The SSD 1006 may also include a connection between the SSD 1006 and a host (e.g., Figure 18 The SSD connector 1008 is coupled to the host 908 in the memory card 1002. In some embodiments, the storage capacity and / or operating speed of the SSD 1006 is greater than that of the memory card 1002.

[0131] According to one aspect of this disclosure, a 3D memory device is disclosed. The 3D memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film above the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

[0132] In some embodiments, the semiconductor channel includes a second angular structure, and the third diameter of the semiconductor channel at the bottom of the channel structure below the second angular structure is smaller than the fourth diameter of the semiconductor channel at the upper portion of the channel structure above the second angular structure. In some embodiments, the semiconductor channel below the second angular structure includes a solid pillar structure. In some embodiments, the semiconductor channel above the second angular structure includes a hollow structure. In some embodiments, the storage film at the bottom of the channel structure and the storage film at the upper portion of the channel structure have the same thickness.

[0133] In some embodiments, the 3D storage device further includes a polysilicon structure disposed below the stacked structure. The polysilicon structure is in direct contact with the semiconductor channel. In some embodiments, the polysilicon structure includes a polysilicon layer in direct contact with the stacked structure and a doped polysilicon layer disposed below the polysilicon layer. In some embodiments, the polysilicon layer surrounds the bottom of the channel structure, and the doped polysilicon layer is disposed below the bottom of the channel structure.

[0134] In some embodiments, the 3D storage device further includes a second dielectric layer disposed between the polysilicon layer and the bottom of the channel structure. The second dielectric layer surrounds the bottom of the channel structure, and the polysilicon layer surrounds the second dielectric layer.

[0135] In some embodiments, a doped polysilicon layer is disposed beneath the polysilicon layer, the second dielectric layer, and the channel structure. In some embodiments, a portion of the doped polysilicon layer extends into the polysilicon layer, a portion of the doped polysilicon layer surrounds the bottom of the channel structure, and the polysilicon layer surrounds a portion of the doped polysilicon layer. In some embodiments, the bottom surface of the storage film is in direct contact with the doped polysilicon layer.

[0136] According to another aspect of this disclosure, a 3D memory device is disclosed. The 3D memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a dielectric core, a semiconductor channel above the dielectric core, and a memory film above the semiconductor channel. The dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and a first diameter of the dielectric core at the bottom of the channel structure is smaller than a second diameter of the dielectric core at the top of the channel structure.

[0137] In some embodiments, the semiconductor channel includes a first angular structure, and a third diameter of the semiconductor channel at the bottom of the channel structure below the first angular structure is smaller than a fourth diameter of the semiconductor channel at the upper portion of the channel structure above the first angular structure. In some embodiments, the memory film includes a second angular structure, and a fifth diameter of the memory film at the bottom of the second angular structure below the second angular structure is smaller than a sixth diameter of the memory film at the upper portion of the second angular structure above the second angular structure.

[0138] In some embodiments, the 3D storage device further includes a polysilicon structure disposed beneath the stacked structure. The polysilicon structure is in direct contact with the semiconductor channel and the dielectric core. In some embodiments, the polysilicon structure includes a polysilicon layer in direct contact with the stacked structure and a doped polysilicon layer disposed beneath the polysilicon layer.

[0139] In some embodiments, a portion of the doped polysilicon layer extends into the polysilicon layer, and a semiconductor channel extends into said portion of the doped polysilicon layer. In some embodiments, the doped polysilicon layer is in direct contact with the dielectric core, the semiconductor channel, and the memory film.

[0140] According to another aspect of this disclosure, a system is disclosed. The system includes a 3D storage device configured to store data, and a storage controller coupled to the 3D storage device and configured to control the operation of the 3D storage device. The 3D storage device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D storage device at its bottom. The channel structure includes a semiconductor channel and a storage film above the semiconductor channel. The storage film includes a first angular structure, and a first diameter of the storage film at its bottom below the first angular structure is smaller than a second diameter of the storage film at its upper portion above the first angular structure.

[0141] According to another aspect of this disclosure, a system is disclosed. The system includes a 3D storage device configured to store data, and a storage controller coupled to the 3D storage device and configured to control the operation of the 3D storage device. The 3D storage device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D storage device at its bottom. The channel structure includes a dielectric core, a semiconductor channel above the dielectric core, and a storage film above the semiconductor channel. The dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and a first diameter of the dielectric core at the bottom of the channel structure is smaller than a second diameter of the dielectric core at the top of the channel structure.

[0142] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate. A second stacked structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stacked structure. A channel via penetrating the second and first stacked structures along a first direction is formed to expose the substrate. An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel via. The channel via has a first width at a first portion having a third dielectric layer formed on the sidewalls and a second width at a second portion not having a third dielectric layer formed on the sidewalls, and the first width is less than the second width. A memory film is conformally formed in the channel via. A semiconductor channel is formed in the channel via and over the memory film. The semiconductor channel completely fills the channel via at the first portion. The substrate and the first dielectric layer are removed to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel. An interconnect structure in contact with the semiconductor channel is formed.

[0143] In some embodiments, an oxidation operation is performed to form a third dielectric layer on the first polysilicon layer along a second direction perpendicular to the first direction. In some embodiments, a dielectric core is formed in the channel via, above a fully filled portion of the semiconductor channel. In some embodiments, a semiconductor channel is formed in the channel via to completely fill a first portion of the channel via and to form voids in a second portion of the channel via.

[0144] In some embodiments, the substrate is removed, and a planarization operation is performed to remove the first dielectric layer, a portion of the memory film, and the semiconductor channel. In some embodiments, the first polysilicon layer is coplanar with the third dielectric layer, the memory film, and the semiconductor channel.

[0145] In some embodiments, an implantation operation is performed on the semiconductor channel to form a second polysilicon layer over the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel. In some embodiments, the second polysilicon layer includes a doped polysilicon layer.

[0146] In some embodiments, a gate slot structure is formed that extends along a first direction through the second stack structure. In some embodiments, multiple word lines replace multiple sacrificial layers.

[0147] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate. A second stacked structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stacked structure. A channel via penetrating the second and first stacked structures along a first direction is formed to expose the substrate. An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel via. The channel via has a first width at a first portion having a third dielectric layer formed on the sidewalls and a second width at a second portion not having a third dielectric layer formed on the sidewalls, and the first width is less than the second width. A memory film and a semiconductor channel are conformally formed in the channel via. A dielectric core is formed in the channel via and over the semiconductor channel. The dielectric core completely fills the channel via at the first portion. The substrate and the first dielectric layer are removed to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel. An interconnect structure in contact with the semiconductor channel is formed.

[0148] In some embodiments, an oxidation operation is performed to form a third dielectric layer on the first polysilicon layer along a second direction perpendicular to the first direction. In some embodiments, a dielectric core is formed in a channel via, the dielectric core having a third width at a first portion of the dielectric via and a fourth width at a second portion of the channel via, wherein the third width is less than the fourth width.

[0149] In some embodiments, the substrate is removed, and a planarization operation is performed to remove the first dielectric layer, a portion of the memory film, and the semiconductor channel. In some embodiments, the first polysilicon layer is coplanar with the third dielectric layer, the memory film, and the semiconductor channel.

[0150] In some embodiments, the third dielectric layer and a portion of the memory film, as well as the dielectric core, are removed to expose the semiconductor channel. A second polysilicon layer is formed over the first polysilicon layer and the exposed semiconductor channel. In some embodiments, the second polysilicon layer includes a doped polysilicon layer.

[0151] In some embodiments, a gate slot structure is formed that extends along a first direction through the second stack structure. In some embodiments, multiple word lines replace multiple sacrificial layers.

[0152] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance set forth herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0153] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) storage device, comprising: A stacked structure comprising interleaved conductive layers and a first dielectric layer; as well as A channel structure extending through the stacked structure in a first direction and contacting the source electrode of the 3D memory device at the bottom of the channel structure, the channel structure including a semiconductor channel and a memory film above the semiconductor channel. The storage film includes a first angular structure at the bottom of the channel structure, and the first diameter of the storage film at the bottom below the first angular structure is smaller than the second diameter of the storage film at the upper part above the first angular structure.

2. The 3D storage device according to claim 1, wherein, The semiconductor channel includes a second angular structure, and the third diameter of the semiconductor channel at the bottom of the channel structure below the second angular structure is smaller than the fourth diameter of the semiconductor channel at the top of the channel structure above the second angular structure.

3. The 3D storage device according to claim 2, wherein, The semiconductor channel beneath the second angular structure comprises a solid pillar structure.

4. The 3D storage device according to claim 2, wherein, The semiconductor channel above the second angular structure includes a hollow structure.

5. The 3D storage device according to any one of claims 1-4, wherein, The storage film at the bottom of the channel structure and the storage film at the top of the channel structure have the same thickness.

6. The 3D storage device according to any one of claims 1-4, further comprising: The polycrystalline silicon structure disposed below the stacked structure The polycrystalline silicon structure is in direct contact with the semiconductor channel.

7. The 3D storage device according to claim 6, wherein, The polycrystalline silicon structure includes a polycrystalline silicon layer in direct contact with the stacked structure, and a doped polycrystalline silicon layer disposed below the polycrystalline silicon layer.

8. The 3D storage device according to claim 7, wherein, The polysilicon layer surrounds the bottom of the channel structure, and the doped polysilicon layer is disposed below the bottom of the channel structure.

9. The 3D storage device according to claim 8, further comprising: A second dielectric layer is disposed between the polysilicon layer and the bottom of the channel structure. The second dielectric layer surrounds the bottom of the channel structure, and the polysilicon layer surrounds the second dielectric layer.

10. The 3D storage device according to claim 9, wherein, The doped polysilicon layer is disposed below the polysilicon layer, the second dielectric layer, and the channel structure.

11. The 3D storage device according to claim 7, wherein, A portion of the doped polysilicon layer extends into the polysilicon layer, the portion of the doped polysilicon layer surrounds the bottom of the channel structure, and the polysilicon layer surrounds the portion of the doped polysilicon layer.

12. The 3D storage device according to any one of claims 7-11, wherein, The bottom surface of the storage film is in direct contact with the doped polycrystalline silicon layer.

13. A three-dimensional (3D) storage device, comprising: A stacked structure comprising interleaved conductive layers and a first dielectric layer; as well as A channel structure extending through the stacked structure in a first direction and contacting the source electrode of the 3D memory device at the bottom of the channel structure, the channel structure comprising a dielectric core, a semiconductor channel above the dielectric core, and a memory film above the semiconductor channel. The dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and the first diameter of the dielectric core at the bottom of the channel structure is smaller than the second diameter of the dielectric core at the top of the channel structure.

14. The 3D storage device according to claim 13, wherein, The semiconductor channel includes a first angular structure, and the third diameter of the semiconductor channel at the bottom of the channel structure below the first angular structure is smaller than the fourth diameter of the semiconductor channel at the upper part of the channel structure above the first angular structure.

15. The 3D storage device according to claim 14, wherein, The storage film includes a second angular structure, and the fifth diameter of the storage film at the bottom below the second angular structure is smaller than the sixth diameter of the storage film at the upper part above the second angular structure.

16. The 3D storage device according to any one of claims 13-15, further comprising: The polycrystalline silicon structure disposed below the stacked structure The polycrystalline silicon structure is in direct contact with the semiconductor channel and the dielectric core.

17. The 3D storage device according to claim 16, wherein, The polycrystalline silicon structure includes a polycrystalline silicon layer in direct contact with the stacked structure, and a doped polycrystalline silicon layer disposed below the polycrystalline silicon layer.

18. The 3D storage device according to claim 17, wherein, A portion of the doped polysilicon layer extends into the polysilicon layer, and the semiconductor channel extends into the portion of the doped polysilicon layer.

19. The 3D storage device according to claim 18, wherein, The doped polycrystalline silicon layer is in direct contact with the dielectric core, the semiconductor channel, and the memory film.

20. A system comprising: A three-dimensional (3D) storage device configured to store data, the 3D storage device comprising: A stacked structure comprising interleaved conductive layers and a first dielectric layer; and A channel structure extending through the stacked structure in a first direction and contacting the source electrode of the 3D memory device at the bottom of the channel structure, the channel structure including a semiconductor channel and a memory film above the semiconductor channel. Wherein, the storage film includes a first angular structure at the bottom of the channel structure, and the first diameter of the storage film at the bottom below the first angular structure is smaller than the second diameter of the storage film at the upper part above the first angular structure; and A storage controller, which is coupled to the 3D storage device and configured to control the operation of the 3D storage device.

21. A system comprising: A three-dimensional (3D) storage device configured to store data, the 3D storage device comprising: A stacked structure comprising interleaved conductive layers and a first dielectric layer; and A channel structure extending through the stacked structure in a first direction and contacting the source electrode of the 3D memory device at the bottom of the channel structure, the channel structure comprising a dielectric core, a semiconductor channel above the dielectric core, and a memory film above the semiconductor channel. Wherein, the dielectric core is surrounded by the semiconductor channel at the bottom of the channel structure, and the storage film includes a corner structure at the bottom of the channel structure, such that a first diameter of the dielectric core at the bottom of the channel structure is smaller than a second diameter of the dielectric core at the top of the channel structure; and A storage controller, which is coupled to the 3D storage device and configured to control the operation of the 3D storage device.

22. A method for forming a three-dimensional (3D) storage device, comprising: A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate; A second stack structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stack structure; A channel hole is formed along a first direction to penetrate the second stacked structure and the first stacked structure to expose the substrate; An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel hole, wherein the channel hole has a first width at a first portion having the third dielectric layer formed on the sidewalls and a second width at a second portion not having the third dielectric layer formed on the sidewalls, and the first width is less than the second width. A storage film is conformally formed in the channel holes; A semiconductor channel is formed in the channel hole and over the storage film, wherein the semiconductor channel completely fills the channel hole at the first portion of the channel hole; Remove the substrate and the first dielectric layer to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel; and An interconnect structure is formed that contacts the semiconductor channel.

23. The method according to claim 22, wherein, Performing the oxidation operation to form the third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel via further includes: The oxidation operation is performed to form the third dielectric layer on the first polysilicon layer along a second direction perpendicular to the first direction.

24. The method according to claim 22 or 23, further comprising: A dielectric core is formed in the channel hole above the fully filled portion of the semiconductor channel.

25. The method according to claim 22 or 23, wherein, Forming the semiconductor channel in the channel hole and on the storage film further includes: The semiconductor channel is formed in the channel hole to completely fill the first portion of the channel hole and to form a void in the second portion of the channel hole.

26. The method according to claim 22 or 23, wherein, Removing the substrate and the first dielectric layer to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel further includes: Remove the substrate; and A planarization operation is performed to remove the first dielectric layer, a portion of the memory film, and the semiconductor channel.

27. The method according to claim 26, wherein, The first polysilicon layer is coplanar with the third dielectric layer, the memory film, and the semiconductor channel.

28. The method according to claim 22 or 23, wherein, The interconnect structure forming contact with the semiconductor channel further includes: An implantation operation is performed on the semiconductor channel; and A second polysilicon layer is formed on the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel.

29. The method according to claim 28, wherein, The second polysilicon layer includes a doped polysilicon layer.

30. The method according to claim 22 or 23, further comprising: A gate slot structure is formed that extends through the second stacked structure along the first direction.

31. The method according to claim 22 or 23, further comprising: Replace the multiple sacrificial layers with multiple word lines.

32. A method for forming a three-dimensional (3D) storage device, comprising: A first stacked structure comprising a first dielectric layer and a first polysilicon layer is formed on a substrate; A second stack structure comprising a plurality of alternately arranged second dielectric layers and a plurality of sacrificial layers is formed on the first stack structure; A channel hole is formed along a first direction to penetrate the second stacked structure and the first stacked structure to expose the substrate; An oxidation operation is performed to form a third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel hole, wherein the channel hole has a first width at a first portion having the third dielectric layer formed on the sidewalls and a second width at a second portion not having the third dielectric layer formed on the sidewalls, and the first width is less than the second width. A memory film and a semiconductor channel are coherently formed in the channel aperture; A dielectric core is formed in the channel hole and over the semiconductor channel, wherein the dielectric core completely fills the channel hole at the first portion of the channel hole; Remove the substrate and the first dielectric layer to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel; and An interconnect structure is formed that contacts the semiconductor channel.

33. The method according to claim 32, wherein, Performing the oxidation operation to form the third dielectric layer on the first polysilicon layer exposed by the sidewalls of the channel via further includes: The oxidation operation is performed to form the third dielectric layer on the first polysilicon layer along a second direction perpendicular to the first direction.

34. The method according to claim 32 or 33, wherein, Forming the dielectric core in the channel hole and over the semiconductor channel further includes: A dielectric core is formed in the channel hole, the dielectric core having a third width at the first portion of the dielectric hole and a fourth width at the second portion of the channel hole, wherein the third width is smaller than the fourth width.

35. The method according to claim 32 or 33, wherein, Removing the substrate and the first dielectric layer to expose the third dielectric layer, the first polysilicon layer, the memory film, and the semiconductor channel further includes: Remove the substrate; and A planarization operation is performed to remove the first dielectric layer, a portion of the memory film, and the semiconductor channel.

36. The method according to claim 35, wherein, The first polysilicon layer is coplanar with the third dielectric layer, the memory film, and the semiconductor channel.

37. The method according to claim 32 or 33, wherein, The interconnect structure forming contact with the semiconductor channel further includes: Remove the third dielectric layer and a portion of the memory film and the dielectric core to expose the semiconductor channel; and A second polysilicon layer is formed over the first polysilicon layer and the exposed semiconductor channel.

38. The method according to claim 37, wherein, The second polysilicon layer includes a doped polysilicon layer.

39. The method according to claim 32 or 33, further comprising: A gate slot structure is formed that extends through the second stacked structure along the first direction.

40. The method according to claim 32 or 33, further comprising: Replace the multiple sacrificial layers with multiple word lines.

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