A neural electrode array with cross-size electrode points and a design method thereof

Abstract

The present invention discloses a neural electrode array with cross-size electrode points and a design method thereof. The design method of the present invention uses a multi-channel connector to design multiple identical electrode arrays, each electrode array containing multiple electrodes of different sizes. The preparation method adopts the photolithography and etching process in micro-nano processing; in the etching process step, the present invention divides the cross-size range and uses different process parameters for etching respectively. The present invention ensures the etching accuracy of the electrode points and prevents over-etching or incomplete etching.

Description

Technical Field

[0001] The present invention relates to the fields of neuroscience, medical machinery and biomedical engineering technology, and in particular to a neural electrode array with cross-size electrode points and a design method thereof. Background Art

[0002] The human brain has about tens of billions of neurons, each of which is equivalent to a binary code. Brain waves are the carriers of ideas. When a person is thinking about something, they will send out signals of 60 millivolts to 130 millivolts (no signals are sent out when silent). These signals are extracted to analyze the correspondence between brain waves and thoughts or behavior patterns to identify ideas. By finding this correspondence, people can express their thoughts or will directly through brain waves without using limbs or organs. One of the most important means of obtaining these signals is neural interface technology, which approaches neurons through extremely small electrodes to obtain signals from single neurons. However, many actions or ideas require the coordination of one or hundreds of neurons, so it is far from enough to obtain signals from only a single neuron.

[0003] Stuart F. Cogan et al. published a paper titled "The Effect of Electrode Geometry on Electrochemical PropertiesMeasured in Saline" in Annu Int Conf IEEE Eng Med Biol Soc. 2014:6850-3, which disclosed the designs of three electrodes with different geometric shapes (circular electrode, rectangular electrode, and square electrode). The size range was 0.0023 mm2 to 0.0031 mm2. The size range was small, and the number of electrodes that could be measured was relatively limited, so the research was only aimed at the signal recording of a single neuron.

[0004] In the article Impedance scaling for gold and platinum microelectrodes published in the journal J. Neural Eng. 18 (2021) 056025, Bo Fan et al. disclosed a 16-channel flexible microelectrode electrode with a radius of 3 microns to 125 microns. The size range of its design is limited to the research scope of microelectrodes, and it shares a large channel, which cannot measure a cluster of neurons in a large area.

[0005] In summary, although electrode design has been studied to some extent, most of the literature focuses on the electrode design of single neuron signals, or the design of multiple extremely small electrodes for high-density channels, ignoring the design of cross-size electrode measurement range. Summary of the invention

[0006] In view of the defects in the prior art, the purpose of the present invention is to provide a neural electrode array with cross-size electrode points and a design method thereof. The cross-size refers to the length and width or perimeter or area of ​​different geometric shapes or the ratio between the two, wherein the fixed scale is different and is not limited to the diameter (radius).

[0007] To achieve the above object, the present invention provides a design method of a neural electrode array with cross-size electrode points, which uses a multi-channel connector to design multiple identical electrode arrays, each electrode array includes multiple electrodes of different sizes, and the electrode points of different sizes are used to record single or multiple neuron signals and stimulate single or multiple neurons; the specific design process is as follows:

[0008] The first step is to determine the number of channels, select connectors, and clarify the relationship between the corresponding channels; determine the size of the electrode points (etching layer) according to the research purpose and estimate the number of neurons that each electrode can contact; determine the distribution position of the electrode points and the line width of the wire connection;

[0009] The second step is to use design tools to design the layout design of the conductor layer and etching layer of the mask according to the determined requirements and produce the mask;

[0010] The third step is to make the designed electrodes and prepare the electrode array through micro-nano processes such as photolithography and etching.

[0011] In the present invention, the number of channels of the connector selected in the first step ranges from 16 to 64, and at least one channel is used as a grounding point to form a safety loop in the test environment.

[0012] In the present invention, the size of the electrode points in the first step ranges from 5 microns to 1000 microns, and this range can also be appropriately adjusted according to the existing process level. The sizes of adjacent electrode points are increasing and are arranged in sequence to form an electrode array. The number of neurons measured by each electrode is in a different range, and the number of neurons measured by each electrode is estimated; the line width of the wire is 5 microns to 100 microns, and a size can be selected according to the process level and research requirements. The line width cannot be too small to ensure that the process level can be achieved and it is not easy to break when connecting large-size electrodes; the line width cannot be too large, which will lead to a reduction in integration density.

[0013] In the present invention, in the second step, the size of the electrode points of the wire layer is larger than that of the electrode points of the etching layer: if the diameter of the electrode points of the etching layer is below 20 microns, the diameter of the electrode points of the wire layer can be a fixed size in the range of 20 microns to 30 microns; if the diameter of the electrode points of the etching layer is greater than 20 microns and less than 100 microns, the diameter of the electrode points of the wire layer is more than 20% larger than that of the electrode points of the etching layer; if the diameter of the electrode points of the etching layer is greater than 100 microns, the diameter of the electrode points of the wire layer is more than 10% larger than that of the electrode points of the etching layer.

[0014] In the present invention, the wire width at the connection between the electrode point of the wire layer and the wire in the second step is slightly larger than the wire width at other positions. For example, the angle between the point intersecting the circular electrode point and the center of the circle is greater than 60 degrees to avoid breakage at the connection.

[0015] In the present invention, during etching in the third step, the cross-size electrodes are divided into four ranges, namely, an ultra-micro size range of less than 15 microns; a micro size range of greater than 20 microns and less than 50 microns; a small size range of greater than 50 microns and less than 100 microns; and a large size range of greater than 100 microns; different process parameters are used to etch the electrode points in the four size ranges to expose the electrode points.

[0016] The present invention also provides a neural electrode array having cross-size electrode points obtained based on the above design method.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention provides a method and classification standard for the systematic study of cross-size electrode points. Compared with a single-size electrode array, each cross-size electrode array contains multiple electrodes of different sizes. Electrode points of different sizes are used to record single or multiple neuron signals and stimulate single or multiple neurons. Different process parameters are used for etching electrode points of different ranges. Compared with the method of using only a single etching mask and process, the etching accuracy of the electrode points is guaranteed to prevent over-etching or incomplete etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0020] Figure 1 The conductor layer layout design of a neural electrode array with cross-sized electrode points according to an embodiment of the present invention.

[0021] Figure 2 This is the etching layer layout design (divided into four masks) of a neural electrode array with cross-sized electrode points according to an embodiment of the present invention.

[0022] Figure 3 This is a design diagram of the electrode point arrangement of a neural electrode array with cross-sized electrode points according to an embodiment of the present invention.

[0023] Figure 4 This is a design diagram of a single device of a neural electrode array with cross-sized electrode points according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0025] Example 1

[0026] This embodiment provides a neural electrode array with cross-sized electrode points, and the specific preparation process is as follows:

[0027] (1) Determine the 64-channel connector, 16 cross-size electrode points form an array, including 4 arrays. The selected connector corresponds to two points, one has two suspended points, and the other two are grounded points;

[0028] (2) Determine the size of the 16 electrode points and calculate the number of neurons that can be contacted, as shown in Table 1;

[0029] (3) Determine the distribution position and spacing of the electrodes, such as Figure 3 As shown; the line width of the wire is 50 microns, such as Figure 4 As shown;

[0030] (4) Draw the corresponding points of the connector and the determined electrode points, lay out the wires (the wires should be drawn longer to facilitate process manufacturing), and try to gather them in the middle (the edges are easily damaged when preparing electrodes). The connection between the electrode points and the wires should be based on 60 degrees;

[0031] (5) Draw the electrode points and connection points of the etching layer corresponding to the wire layer, draw the outer frame to surround the entire device, and complete the design of a single device;

[0032] (6) Select a 4-inch silicon wafer as the substrate, draw the corresponding shape and size of the silicon wafer, distribute four identical devices, and draw alignment marks on the edge for alignment during overlay; the rectangular white alignment mark is used for coarse alignment, and the cross and T-shaped alignment marks in the square block are used for fine alignment;

[0033] (7) Check details and make masks, Figure 1 , Figure 2 This is the mask rendering;

[0034] (8) Depositing a layer of Parylene-C with a thickness of 2 μm on the silicon wafer by chemical vapor deposition;

[0035] (9) Spray the positive photoresist and use the conductor layer mask as a patterning template for patterning, sputter or evaporate the electrode conductive layer, use the lift-off process to remove the photoresist, and the metal layer forms the conductive structure of the electrode. Use chemical vapor deposition to deposit the second layer of Parylene-C with a thickness of 2 microns;

[0036] (10) Spin the positive resist and use the first etching layer mask (less than 20 μm) as a patterning template for patterning, and use reactive ion etching to etch the Parylene-C for the first time to expose electrode points less than 15 μm;

[0037] (11) Spin the positive resist and use the second etching layer mask (larger than 20 microns and less than 50 microns) as a patterning template for patterning, and use reactive ion etching to etch Parylene-C for the second time to expose electrode points in the range of larger than 20 microns and less than 50 microns;

[0038] (12) Spin the positive resist and use the third etching layer mask (greater than 50 microns and less than 100 microns) as a patterning template for patterning, and use reactive ion etching to etch the Parylene-C for the third time to expose the electrode points in the range of greater than 50 microns and less than 100 microns;

[0039] (13) Spin the positive resist and use the fourth etching layer mask (greater than 100 μm) as a patterning template for patterning, and use reactive ion etching to etch Parylene-C for the fourth time to expose electrode points larger than 100 μm;

[0040] (14) After cleaning off the residual photoresist, directly encapsulate the connector of the electrode.

[0041] Table 1 Electrode processing dimensions and the corresponding number of neurons measured

[0042]

[0043] In summary, the present invention provides a neural electrode array with cross-size electrode points and a preparation method thereof, and divides the size range, which can be used as a division standard for preparation.

[0044] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A method for designing a neural electrode array with cross-sized electrode points, characterized in that: It uses a multi-channel connector to design multiple identical electrode arrays, each electrode array contains multiple electrodes of different sizes, and the electrode points of different sizes are used to record single or multiple neuron signals and stimulate single or multiple neurons; the specific steps are as follows: The first step is to determine the number of channels, select connectors, and clarify the relationship between the corresponding channels; determine the size of the electrode points in the etching layer according to the research purpose and estimate the number of neurons that each electrode can contact; Determine the distribution position of electrode points and the line width of wire connections; The second step is to use the design tool to design the layout design drawings of the conductor layer and etching layer of the mask according to the requirements determined in the first step, and to produce the mask of the etching layer divided according to the different sizes of the electrode points; The third step is to make the designed electrodes, and then use different etching processes to etch the electrode points of different size ranges, expose the electrode points, and prepare the electrode array; wherein: In the first step, the size of the electrode points ranges from 5 microns to 1000 microns, the sizes of adjacent electrode points increase, and they are arranged in sequence to form an electrode array, and the line width of the wire is 5 microns to 100 microns; In the third step, during etching, the cross-size electrodes are divided into four size ranges, with diameter ranges of less than or equal to 20 microns, greater than 20 microns and less than or equal to 50 microns, greater than 50 microns and less than or equal to 100 microns, and greater than 100 microns.

2. The design method according to claim 1, characterized in that: In the first step, the number of channels of the connector ranges from 16 to 64, and at least one channel serves as a ground point.

3. The design method according to claim 1, characterized in that: In the second step, the size of the electrode points of the wire layer is larger than that of the electrode points of the etching layer: when the diameter of the electrode points of the etching layer is below 20 microns, the diameter of the electrode points of the wire layer is between 20 microns and 30 microns; when the diameter of the electrode points of the etching layer is larger than 20 microns and smaller than 100 microns, the diameter of the electrode points of the wire layer is more than 20% larger than that of the electrode points of the etching layer; when the diameter of the electrode points of the etching layer is larger than 100 microns, the diameter of the electrode points of the wire layer is more than 10% larger than that of the electrode points of the etching layer.

4. The design method according to claim 1, characterized in that: In the second step, the center spacing distance of the cross-size electrode points is determined according to the sum of the radius sizes of adjacent electrode points and the size of the substrate material.

5. The design method according to claim 1, characterized in that: In the second step, the wire width at the connection between the electrode point of the wire layer and the wire is slightly larger than the wire width at other positions.

6. A neural electrode array having cross-sized electrode points obtained according to the design method of any one of claims 1-5.

Images