Memory system and control method

Abstract

One embodiment of the present invention provides a memory system and a control method capable of reducing the amount of required memory resources. A controller receives a first command for sequentially writing data to a first area from a host. When there is a first buffer to which the first area is allocated, the controller saves the first data to the first buffer. When there is no first buffer and there is an idle buffer, the controller allocates the first area to the idle buffer and saves the first data to the idle buffer to which the first area is allocated. When there is no first buffer and there is no idle buffer, the controller additionally allocates the first area to a buffer that is the earliest updated among a plurality of buffers in order to store the last data, and saves the first data to the buffer to which the first area is additionally allocated.

Description

[0001] Related Application:

[0002] This application claims priority from Japanese Patent Application No. 2020-207741 (filing date: December 15, 2020) as a prior application, and this application incorporates all the contents of the prior application by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system including a nonvolatile memory and a method for controlling the nonvolatile memory. Background Art

[0004] In recent years, memory systems including nonvolatile memories have become widespread. As one of such memory systems, a solid-state drive (SSD) including a NAND flash memory is known.

[0005] NVM Express is a known standard for a logical interface for communication between a memory system such as an SSD and a host. TM (NVMe TM ). In the interface of the NVMe specification, a partition namespace is specified. In the partition namespace, the logical address range of the memory system is divided into multiple zones.

[0006] In a memory system, in order to buffer data to be written to different areas, buffers equal in number to the number of areas are sometimes prepared. In this case, if the number of areas to be managed in the memory system is large, a large amount of memory resources is consumed for these areas.

[0007] Therefore, in a memory system, a new technology capable of reducing the amount of required memory resources is required. Summary of the invention

[0008] An object of one embodiment of the present invention is to provide a memory system and a control method capable of reducing the amount of required memory resources.

[0009] According to an embodiment, a memory system comprises: a nonvolatile memory; and a controller, which is electrically connected to the nonvolatile memory and controls the nonvolatile memory using a partition namespace divided into a plurality of zones specified by a nonvolatile memory host controller interface specification NVM express. The controller manages a plurality of buffers. The number of the plurality of buffers is less than the number of the plurality of zones. The controller receives a first command associated with the first data from the host, the first command being a command for sequentially writing data to the first zone among the plurality of zones. The controller saves the first data to the first buffer in the case where there is a first buffer to which the first zone is allocated among the plurality of buffers according to the situation of receiving the first command. The controller allocates the first zone to the free buffer in the case where there is no first buffer among the plurality of buffers and there is an idle buffer to which no zone is allocated among the plurality of buffers according to the situation of receiving the first command, and saves the first data to the idle buffer to which the first zone is allocated. In response to receiving the first command, if the first buffer does not exist among the multiple buffers and there is no free buffer to which no area is allocated among the multiple buffers, the controller allocates the first area to the buffer that was last updated earliest among the multiple buffers in order to save the data, and saves the first data in the buffer to which the first area is additionally allocated. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing a configuration example of an information processing system including a memory system according to an embodiment.

[0011] Figure 2 This is a diagram showing an example of the structure of a partition namespace specified by the NVMe specification.

[0012] Figure 3 It is a diagram showing an update operation of a write pointer executed in the memory system according to the embodiment.

[0013] Figure 4 It is a diagram showing a buffer process executed in a memory system according to a comparative example.

[0014] Figure 5 FIG. 2 is a diagram showing another buffering process executed in the memory system according to the comparative example.

[0015] Figure 6 The diagram shows the relationship among a plurality of buffers, a data / buffer allocation control unit, and a data / area allocation control unit provided in the memory system according to the embodiment.

[0016] Fig. 7A This is a diagram showing a first process of the buffering process executed in the memory system according to the embodiment.

[0017] Figure 7B FIG. 1 is a diagram showing a second process of the buffering process executed in the memory system according to the embodiment.

[0018] Figure 7C FIG. 1 is a diagram showing a third process of the buffering process executed in the memory system according to the embodiment.

[0019] Fig.7D This is a diagram showing a fourth process of the buffering process executed in the memory system according to the embodiment.

[0020] Fig. 8A This is a diagram showing a first process of the transcendence process executed in the memory system according to the embodiment.

[0021] Figure 8B FIG. 1 is a diagram showing a second process of the transcendence process executed in the memory system according to the embodiment.

[0022] Figure 8C FIG. 1 is a diagram showing a third process of the transcendence process executed in the memory system according to the embodiment.

[0023] Fig.8D This is a diagram showing a fourth process of the transcendence process executed in the memory system according to the embodiment.

[0024] Fig. 8E This is a diagram showing a fifth process of the transcendence process executed in the memory system according to the embodiment.

[0025] Fig. 9 This is a flowchart showing a procedure of command processing executed in the memory system according to the embodiment.

[0026] Fig.10 This is a flowchart showing the procedure of data / buffer allocation processing executed in the memory system according to the embodiment.

[0027] Fig.11 This is a flowchart showing a procedure of a override process executed in a memory system according to an embodiment.

[0028] Description of Reference Numerals

[0029] 1...information processing system, 2...host, 3...SSD, 4...controller, 5...NAND flash memory, 6...DRAM, 10...bus, 11...host interface, 12...CPU, 13...NAND interface, 14...DRAM interface, 15...DMAC, 16...buffer circuit, 17...ECC encoding / decoding unit, 21...data / buffer allocation control unit, 22...data / area allocation control unit, 31...L2P table, 32...buffer update history management table. DETAILED DESCRIPTION

[0030] The following describes embodiments with reference to the drawings.

[0031] Figure 1 1 is a block diagram showing a configuration example of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and an SSD 3 .

[0032] The memory system is a semiconductor storage device configured to write data to and read data from a nonvolatile memory. The memory system can be realized as an SSD 3 including a NAND flash memory 5, for example.

[0033] The SSD 3 may also be connected to the host 2 via a cable or a network. Alternatively, the SSD 3 may be built into the host 2. As a specification of a logical interface for connecting the host 2 and the SSD 3, the NVMe specification may be used.

[0034] The host computer 2 is an information processing device configured to control the SSD 3. Examples of the host computer 2 include a personal computer, a server computer, a portable terminal, and an in-vehicle device.

[0035] The host 2 includes a processor 101 and a memory 102. The processor 101 is a CPU (Central Processing Unit) configured to control the operation of each component in the host 2. The processor 101 executes software (host software) loaded from other storage devices connected to the host 2 or from the SSD 3 into the memory 102. The host software includes an operating system, a file system, a device driver, an application program, and the like.

[0036] The memory 102 is a main memory provided in the host 2. The memory 102 is implemented by a random access memory such as a DRAM (Dynamic Random Access Memory). A portion of the storage area of ​​the memory 102 is used to store one or more SQ / CQ pairs. Each SQ / CQ pair includes one or more subtask queues (SQ) and a completion queue (CQ) associated with the one or more subtask queues (SQ).

[0037] The subtask queue (SQ) is a queue used to issue commands to the SSD 3. The completion queue (CQ) is a queue used to receive command completion information indicating the status of completed commands from the SSD 3.

[0038] The host 2 sends various commands to the SSD 3 via one or more subtask queues (SQ) included in each SQ / CQ pair.

[0039] SSD3 is configured to perform communication with host 2 in accordance with the NVMe specification.

[0040] The NVMe specification interface includes PCI express TM (PCIe TM ) bus interface (NVMe over PCIe), and via Ethernet TM The interface standard of such a network (NVMe over Fabrics: NVMe-oF). The interface specification that SSD3 is based on can be either NVMe over PCIe or NVMe-oF.

[0041] In the NVMe specification, multiple namespaces can be used. Multiple namespaces are independent logical address ranges. The logical address is an address used by the host 2 to logically specify an address in the memory space of the SSD 3. As the logical address, a logical block address can be used. Each namespace is used by the host 2 to access the SSD 3. By using multiple namespaces, one storage device can act like multiple storage devices.

[0042] Furthermore, the NVMe specification defines a partition namespace. A partition namespace is a namespace that is divided into multiple zones. Each zone contains consecutive logical addresses.

[0043] SSD3 supports the partition namespace specified by the NVMe specification. SSD3 is configured to sequentially write data to each of the multiple zones included in the partition namespace.

[0044] The SSD 3 includes a controller 4 and a nonvolatile memory (eg, a NAND flash memory 5 ). The SSD 3 may further include a random access memory such as a DRAM 6 .

[0045] The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a flash memory with a two-dimensional structure or a flash memory with a three-dimensional structure.

[0046] The memory cell array of the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 includes a plurality of pages (here, pages P0 to Py-1). Each page includes a plurality of memory cells connected to the same word line. Each of the blocks BLK0 to BLKx-1 is a unit for a data deletion operation for deleting data. Each of the pages P0 to Py-1 is a unit for a data write operation and a data read operation.

[0047] The controller 4 may also be implemented by a circuit such as a System-on-a-chip (SoC).

[0048] The controller 4 controls the NAND flash memory 5 to control data writing and data reading. The data writing operation writes data received from the host 2 to the NAND flash memory 5, and the data reading operation reads the read target data requested by the host 2 from the NAND flash memory 5. The controller 4 is electrically connected to the NAND flash memory 5 via a NAND interface 13 based on a Toggle NAND flash memory interface or an Open NAND Flash Interface (ONFI), but is not limited thereto. The controller 4 operates as a memory controller configured to control the NAND flash memory 5.

[0049] The controller 4 can function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5 .

[0050] The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) processing for hiding the constraints of the NAND flash memory 5 (for example, read / write operations in page units and delete operations in block units). The physical address corresponding to a certain logical address indicates the physical storage location in the non-volatile memory 5 where the data corresponding to the logical address is written. The controller 4 manages the correspondence between each logical address and each physical address using a logical-to-physical address translation table (L2P table) 31. As described above, a logical block address (LBA) can be used as a logical address.

[0051] Furthermore, the controller 4 is configured to control the NAND flash memory 5 using a partition namespace defined by the NVMe specification.

[0052] Figure 2 This is a diagram showing an example of the structure of a partition namespace specified by the NVMe specification.

[0053] The logical block address range of each partition namespace starts at LBA 0. For example, Figure 2 The logical block address range of the partition namespace includes z consecutive LBAs from LBA 0 to LBAz-1. The partition namespace is divided into k+1 zones from zone 0 to zone k. Each of these zones contains consecutive non-repeating logical block addresses.

[0054] In more detail, zone 0, zone 1, ..., zone k are allocated to the partition namespace. LBA0 represents the smallest LBA of zone 0, and LBAz-1 represents the largest LBA of zone k. Zone 1 includes LBAm, LBA m+1, ..., LBAn-2, LBAn-1. LBA m represents the smallest LBA of zone 1, and LBA n-1 represents the largest LBA of zone 1.

[0055] The controller 4 may manage, for example, mappings between each of the plurality of storage areas (physical storage areas) and each of the plurality of zones in the NAND flash memory 5. In this case, the controller 4 may also allocate at least one of the plurality of blocks included in the NAND flash memory 5 as a physical storage area for one zone.

[0056] When the controller 4 receives a command requesting to write data to a specific area from the host 2, the controller 4 sequentially writes data to a specific physical storage area in the NAND flash memory 5 that is allocated to the area specified by the received command, i.e., the specific area. As a result, data corresponding to consecutive LBAs included in the specific area is written to consecutive physical storage locations in the specific physical storage area allocated to the specific area.

[0057] Therefore, when sequentially reading data corresponding to consecutive LBAs included in a certain zone, the controller 4 can efficiently perform the sequential reading of the data simply by performing read access to at least one block of the physical storage area allocated for the zone.

[0058] Figure 3 This is a diagram showing the update action of the write pointer performed in SSD3.

[0059] The controller 4 of the SSD 3 manages a plurality of write pointers corresponding to a plurality of zones. Each write pointer indicates the next writable LBA in the zone corresponding to the write pointer. If data is sequentially written to a zone, the controller 4 increases the value of the write pointer corresponding to the zone by an amount corresponding to the number of logical blocks to which the data is written.

[0060] Here, the update action of the write pointer is described by taking zone 1 as an example. Zone 1 includes the logical block address range from LBA m to LBA n-1. LBA m is the smallest logical block address of zone 1, that is, the zone start logical block address (ZSLBA) of zone 1.

[0061] When zone 1 is in an empty state containing no valid data, the write pointer corresponding to zone 1 indicates LBA m, which is the zone start logical block address of zone 1. When the write destination position (start LBA) specified by the command for writing data to zone 1 is equal to the write pointer of zone 1 (here, LBAm), the controller 4 writes data to the LBA range starting from the specified start LBA, for example, LBA m and LBA m+1. The controller 4 updates the write pointer of zone 1 so that the value of the write pointer of zone 1 increases by an amount corresponding to the number of logical blocks to which the data is written. For example, when data is written to LBA m and LBA m+1, the controller 4 updates the value of the write pointer to LBA m+2. LBA m+2 indicates the smallest LBA among the unwritten LBAs in zone 1, that is, the next writable LBA in zone 1.

[0062] return Figure 1The controller 4 includes not only the above-mentioned NAND interface 13, but also a host interface 11, a CPU 12, a DRAM interface 14, a direct memory access controller (DMAC) 15, a buffer circuit 16, and an ECC (Error Correction Code) encoding / decoding unit 17. These host interface 11, CPU 12, NAND interface 13, DRAM interface 14, DMAC 15, buffer circuit 16, and ECC encoding / decoding unit 17 are connected to each other via a bus 10.

[0063] The host interface 11 is a host interface circuit configured to perform communication with the host 2. The host interface 11 is, for example, a PCIe controller. Alternatively, when the SSD 3 has a built-in network interface controller, the host interface 11 may be implemented as a part of the network interface controller.

[0064] The host interface 11 performs communication with the host 2 according to the NVMe specification. The host interface 11 includes an arbitration mechanism. The arbitration mechanism is a mechanism for selecting a subtask queue that should obtain a command from multiple subtask queues existing on the memory 102 of the host 2. The arbitration mechanism can be a polling arbitration mechanism or a weighted polling arbitration mechanism.

[0065] The host interface 11 receives (acquires) various commands from the host 2. These commands include a partition namespace command set specified by the NVMe specification. The partition namespace command set includes multiple types of commands, which are used to enable the host 2 to control the SSD 3 using the partition namespace.

[0066] The plurality of types of commands include a command for sequentially writing data to an area, and the command includes at least a parameter for specifying an area to which data should be written.

[0067] For example, the address-specific write command specified by the partition namespace command set of the NVMe specification specifies both the area where the data should be written and the write destination position (start LBA) in the area. Examples of address-specific write commands include write commands, write zero commands, and copy commands.

[0068] For example, a write command used as an address-specific write command is a command (write request) for writing data (user data) to be written to the NAND flash memory 5. The write command includes: a namespace identifier that specifies the namespace to which the data should be written, a start LBA, the size of the data (the number of logical blocks to be written), and a data pointer (buffer address) indicating the location in the memory 102 of the host 2 where the data is stored. The write command does not include a dedicated parameter (field) for specifying the zone start logical block address (ZSLBA), so the start LBA included in the write command is used as a parameter for both the zone to which the data should be written and the write destination position within the zone. In this case, the high-order bit portion of the start LBA included in the write command is used as the ZSLBA of the zone to which the write data associated with the write command should be written. The low-order bit portion of the start LBA included in the write command indicates the write destination position within the zone. Hereinafter, the write command used as an address-specific write command will be referred to as a write command.

[0069] When the start LBA specified by the write command requesting writing to the zone 1 is not equal to the LBA indicated by the write pointer of the zone 1, the controller 4 terminates the processing of the write command. In this case, the controller 4 returns a command completion indicating an error in the write processing corresponding to the write command to the host 2. Thus, it is possible to prevent non-sequential write processing from being performed in each zone.

[0070] When host 2 issues a write command to SSD3 requesting writing to a certain area, it cannot issue the next write command to the same area as the area until the command corresponding to the write command is received from SSD3. This is because the NVMe specification allows storage devices to execute commands in any order, so if the order in which multiple write commands are processed is changed by the storage device, errors may occur in the write processing within the area.

[0071] Next, the zone attachment commands specified by the partition namespace command set of the NVMe specification are explained.

[0072] Like the write command, the area addition command is a command (write request) for writing data (user data) to be written into the NAND flash memory 5. However, unlike the write command, the area addition command only specifies the area where data should be written, but does not specify the write destination position within the area.

[0073] The write destination position in the zone is automatically determined by the controller 4 of the SSD 3 so that the write in the zone is performed sequentially. The host 2 is allowed to simultaneously issue multiple zone addition commands designating the same zone to the SSD 3. Therefore, the write performance can be improved compared to the case of using a write command.

[0074] The zone add command includes, for example, a namespace identifier that specifies the namespace to which data should be written, a zone start logical block address (ZSLBA) that indicates the minimum LBA of the zone to which data should be written, the size of the data (the number of logical blocks to be written), and a data pointer (buffer address) indicating the location of the data in the memory 102 of the host 2. The host 2 can simultaneously issue multiple zone add commands that specify the same zone to the SSD 3 via one or more subtask queues.

[0075] When a certain zone addition command is received from the host 2, the controller 4 refers to the write pointer corresponding to the zone specified by the received zone addition command. Then, the controller 4 determines the next writable logical block address indicated by the write pointer as the write destination position in the specified zone. The controller 4 writes the data associated with the received zone addition command to the determined write destination position in the specified zone. Then, the controller 4 sends a command completion including information indicating the write destination position (LBA) to which the data is written to the host 2. The controller 4 thus notifies the host 2 of the LBA to which the data associated with the received zone addition command is written.

[0076] In the following description, the case of using the area addition command as the command for sequentially writing data to the area is mainly described. In addition, instead of the area addition command, a write command that specifies both the area and the write destination position in the area can be used as the command for sequentially writing data to the area.

[0077] The NAND interface 13 is a NAND controller configured to control the NAND flash memory 5 under the control of the CPU 12. When the NAND flash memory 5 is composed of a plurality of NAND flash memory chips (NAND flash memory particles), the NAND interface 13 may be connected to each of these NAND flash memory chips via a plurality of channels (Ch).

[0078] The buffer circuit 16 includes a plurality of buffers (buffer #0, buffer #1, ..., buffer #q). Buffers #0 to #q are, for example, SRAMs (static random access memories). Buffers #0 to #q are allocated in the storage area of ​​the buffer circuit 16. Alternatively, buffers #0 to #q may be allocated in the storage area of ​​the DRAM 6.

[0079] The number of buffers #0 to #q may be set to be smaller than the number of extents included in the partition namespace. Each buffer #0 to #q is used to temporarily store data to be written to one or more arbitrary extents.

[0080] The DRAM interface 14 is a DRAM controller configured to control the DRAM 6 under the control of the CPU 12 .

[0081] A part of the storage area of ​​DRAM 6 can also be used as an area for storing L2P table 31 and buffer update history table 32. Buffer update history table 32 is used to manage history information. History information indicates the order in which buffers #0 to #q are updated to store data.

[0082] Under the control of the CPU 12 , the DMAC 15 executes data transfer between the memory 102 of the host 2 and each of the buffers # 0 to #q.

[0083] When data is to be written to the NAND flash memory 5, the ECC encoding / decoding unit 17 encodes the data (data to be written) to thereby add an error correction code (ECC) as a redundant code to the data. When data is read from the NAND flash memory 5, the ECC encoding / decoding unit 17 uses the ECC added to the read data to perform error correction on the data.

[0084] The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, the DRAM interface 14, the DMAC 15, the buffer circuit 16, and the ECC encoding / decoding unit 17. The CPU 12 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the DRAM 6, and performs various processes by executing the firmware.

[0085] The CPU 12 can function as a data / buffer allocation control unit 21 and a data / area allocation control unit 22. Part or all of the data / buffer allocation control unit 21 and the data / area allocation control unit 22 may be implemented by dedicated hardware in the controller 4.

[0086] When the controller 4 receives a region addition command from the host 2, the data / buffer allocation control unit 21 determines a buffer (storage destination buffer) to be used for temporarily storing data associated with the received region addition command. In this case, the data / buffer allocation control unit 21 performs the following processing in order to distribute the data in the buffers #0 to #q without biasing the data to a specific buffer and to store the data to be written to the same region in the same buffer.

[0087] When there is no buffer among buffers #0 to #q to which the area specified by the received area addition command has been allocated, and there is an idle buffer among buffers #0 to #q, the data / buffer allocation control unit 21 determines the idle buffer as the storage destination buffer, and allocates the area specified by the received area addition command to the idle buffer. The idle buffer is a buffer to which no area is allocated. Then, the data / buffer allocation control unit 21 obtains data associated with the received area addition command from the memory 102 of the host 2, and saves the obtained data to the idle buffer determined as the storage destination buffer.

[0088] If there is a buffer among the buffers #0 to #q to which the area specified by the received area addition command is already allocated, the data / buffer allocation control unit 21 determines the buffer as the save destination buffer. Then, the data / buffer allocation control unit 21 obtains data associated with the received area addition command from the memory 102 of the host 2, and stores the obtained data in the buffer determined as the save destination buffer.

[0089] When each buffer #0 to #q has been allocated an area, and there is no buffer among buffers #0 to #q to which the area specified by the received area addition command has been allocated, the data / buffer allocation control unit 21 determines the buffer among buffers #0 to #q that was last updated earliest to save the data as the destination buffer to which the data associated with the received area addition command should be saved. Here, the buffer that was last updated earliest to save the data means the buffer among buffers #0 to #q that has passed the longest time since the last update for saving the data. The data / buffer allocation control unit 21 additionally allocates the area specified by the received area addition command to the determined destination buffer. Then, the data / buffer allocation control unit 21 obtains the data associated with the received area addition command from the memory 102 of the host 2, and saves the obtained data to the determined destination buffer.

[0090] The data / area allocation control unit 22 selects (i) an area in which the total size of data stored in one of the buffers #0 to #q is greater than the write unit (hereinafter referred to as the write unit) to the NAND flash memory 5, or (ii) an area in which the total size of corresponding data is the largest among all areas in the buffer in a full state, as the flush object area.

[0091] Here, a buffer in a full state is a buffer in which the entire buffer is filled with data. If a certain amount of data corresponding to the size of the buffer is accumulated in one of the buffers #0 to #q, the buffer becomes a buffer in a full state. The flushing target area means an area to be flushed. The flushing process is a process of reading the data stored in the buffer from the buffer and writing it to the NAND flash memory 5.

[0092] The write unit can be set to a size that is a multiple of the page size, for example. The page size indicates the size of data that can be stored in one page. The write unit can be set to the same size as the page size, to a size that is twice the page size, or to a size that is three times or more the page size.

[0093] Alternatively, the write unit may be set to a multiple of the block size, for example. The block size indicates the size of data that can be stored in one block. The write unit may be set to the same size as the block size, to twice the block size, or to more than three times the block size.

[0094] The size of each buffer #0 to #q is set to be larger than the write unit. When the total size of data in a certain area stored in a certain buffer becomes larger than the write unit, the data / area allocation control unit 22 selects the area as the flush target area.

[0095] When the size of data in any area of ​​a buffer is less than the write unit, the buffer may become full. In this case, the data / area allocation control unit 22 selects the area with the largest total size of corresponding data from among all areas stored in the full buffer as the clearing target area.

[0096] After selecting the clearing target area, the data / area allocation control unit 22 extracts only the data of the clearing target area from the data of all areas stored in the buffer storing the data of the selected clearing target area. In this case, the data / area allocation control unit 22 extracts only the data of the clearing target area while maintaining the data of other areas other than the clearing target area in the buffer. Then, the data / area allocation control unit 22 writes the extracted data to the specific physical storage area in the NAND flash memory 5 allocated to the clearing target area.

[0097] In order to realize the process of extracting only the data in the clearing object area while maintaining the data in other areas in the buffer, each buffer #0~#q can also be realized as a first-in-first-out buffer (FIFO buffer) with an override control function.

[0098] The FIFO buffer with an override function includes, for example, an input port for inputting data, an output port for outputting data, and a path for connecting the output port to the input port, which is also called a loop path.

[0099] When a certain FIFO buffer is full, or when the total size of data in a specific area stored in a certain FIFO buffer exceeds the write unit, the data / area allocation control unit 22 determines whether the next data that can be read from the FIFO buffer is data in the clearing target area. The next data that can be read from the FIFO buffer means the oldest data among the data stored in the FIFO buffer.

[0100] When the next data that can be read from the FIFO buffer is data of other areas other than the clearing target area, the data / area allocation control unit 22 performs processing for writing the data of other areas back to the FIFO buffer. In this case, the data / area allocation control unit 22 performs the reading operation and the writing operation for the FIFO buffer while the loop path of the FIFO buffer is enabled. Thus, the data / area allocation control unit 22 performs the operation of reading the data of other areas from the FIFO buffer and the operation of writing the read data of the other areas back to the FIFO buffer in parallel.

[0101] When the next data that can be read from the FIFO buffer is data in the flush target area, the data / area allocation control unit 22 does not write the data in the flush target area back to the FIFO buffer, but performs a normal read operation for reading the data in the flush target area from the FIFO buffer. In this case, the data / area allocation control unit 22 performs a read operation in a state where the loop path of the FIFO buffer is disabled, thereby reading the data in the flush target area from the FIFO buffer.

[0102] Until all the data in the flush target area is read from the FIFO buffer, the data / area allocation control unit 22 selectively executes the above-mentioned process for writing back and the above-mentioned normal reading process as necessary.

[0103] In this way, by enabling or disabling the loop path of the FIFO buffer, the data / area allocation control unit 22 can execute processing (override processing) of reading only the data of the clearing target area from the FIFO buffer in a state where data older than the data of the clearing target area is maintained in the FIFO buffer. Through this override processing, only the data of the clearing target area can be extracted from the FIFO buffer in a state where data of other areas other than the clearing target area is maintained in the FIFO buffer.

[0104] Next, the buffering process of the present embodiment will be described in detail. Before describing the buffering process of the present embodiment in detail, the buffering process according to the comparative example will be described first.

[0105] Figure 4 Here, as the buffering process performed in the memory system (SSD) according to the comparative example, a buffering process using the same number of buffers as the number of zones will be described.

[0106] like Figure 4 As shown, in the comparative example, a plurality of zones correspond to a plurality of buffers one by one. The zones managed in the SSD involved in the comparative example are k+1 zones from zone 0 to zone k. In this case, k+1 buffers from buffer #0 to buffer #k need to be prepared in the SSD involved in the comparative example.

[0107] Buffer #0 is used to store only data that should be written to zone 0. Buffer #1 is used to store only data that should be written to zone 1. Buffer #2 is used to store only data that should be written to zone 2. Buffer #3 is used to store only data that should be written to zone 3. Buffer #k is used to store only data that should be written to zone k.

[0108] If a region add command designating region 0 is issued from the host to the SSD involved in the comparative example, the input control unit of the SSD involved in the comparative example saves the data associated with the region add command in buffer #0. Similarly, if a region add command designating region 1 is issued from the host to the SSD, the input control unit saves the data associated with the region add command in buffer #1. If a predetermined amount of data or more is accumulated in one of the buffers #0 to #k, sequential writing to the region corresponding to the buffer is started.

[0109] exist Figure 4 In the buffer processing of the comparative example shown, the same number of buffers as the number of zones is required. Therefore, when the number of zones to be managed in the SSD is large, a large number of buffers, that is, a large number of memory resources, are required.

[0110] Next, a buffering process in the case of adopting a configuration in which the number of buffers to be prepared in the SSD is simply reduced will be described as another buffering process according to a comparative example. Figure 5 Another buffering process executed in the memory system according to the comparative example is shown.

[0111] like Figure 5As shown, in the comparative example, the areas managed in the SSD are area 0 to area k+1 areas. The buffers prepared in the SSD are four buffers, buffer #0 to buffer #3. Here, the number of buffers (=4) is set to be less than the number of areas (k+1). Therefore, each buffer #0 to #3 is shared by several areas.

[0112] As methods for enabling each buffer #0 to #3 to be shared by several zones, there is a first method of writing the data of each zone to the NAND flash memory in smaller units, and a second method of waiting until a specified amount of data is accumulated in the buffer and then writing the data of each zone to the NAND flash memory in units of the specified amount of data.

[0113] In the first method, for example, when the data of areas 0 to 3 are respectively stored in buffers #0 to #3, when an area addition command is received from the host 2 specifying an area other than areas 0 to 3 (for example, area #k), it is necessary to perform a clearing process on the data stored in one of the buffers #0 to #3.

[0114] For example, when the data of area #k should be stored in buffer #0, the output control unit performs a clearing process for the data of area 0 already stored in buffer #0. In this case, even if the size of the data of area 0 already stored in buffer #0 is relatively small, the data of area 0 is read from buffer #0. Then, the read data of area 0 is written to the block in the NAND flash memory 5 allocated to area 0.

[0115] In the first method, it is possible to prevent data from different areas from being mixed in one buffer. However, in the first method, data from each area is written to the block of the NAND flash memory in smaller units. Therefore, it may take a long time from the start of writing to a block until the entire block is filled with data. If the block is partially written for a long time, the reliability of the data written in the block may be reduced. In addition, if the number of blocks in the partially written state increases, there is a concern that the blocks that can be used as new write destination blocks will be exhausted.

[0116] In the second method, after a predetermined amount of data is accumulated in each buffer, the data is written to the NAND flash memory. Therefore, data from different areas are mixed in one buffer. In this case, the mixed existence of data from different areas may cause fragmentation in which the data of the same area is dispersed in various different locations in one buffer. If such fragmentation occurs, the output control unit needs to write the data of each area to the NAND flash memory in smaller units, as in the first method.

[0117] Next, the buffering process according to the embodiment will be described. Figure 6It is a diagram showing the buffering process executed in the SSD 3 involved in the embodiment.

[0118] exist Figure 6 In FIG. 1 , the zones managed by SSD3 are 8 zones 0 to 7. The buffers prepared in SSD3 are 4 buffers 0 to 3. The number of zones and the number of buffers shown here are examples, and the number of zones and the number of buffers can be larger or smaller than the number shown here. The number of buffers is less than the number of zones.

[0119] Buffer #0 includes a first-in-first-out (FIFO) buffer 201, a flush control unit 202, and an allocation management table 203. Similarly, buffer #1 includes a FIFO buffer 211, a flush control unit 212, and an allocation management table 213. Buffer #2 includes a FIFO buffer 221, a flush control unit 222, and an allocation management table 223. Buffer #3 includes a FIFO buffer 231, a flush control unit 232, and an allocation management table 233.

[0120] Each of the FIFO buffers 201 to 231 is used to temporarily store data to be written to any one or more of the areas 0 to 7. Each of the FIFO buffers 201 to 231 can be realized as a FIFO buffer with an override function.

[0121] Each flush control unit 202 to 232 executes flush processing for writing data stored in the FIFO buffer to the NAND flash memory 5 together with the data / area allocation control unit 22. In the present embodiment, when the total size of data in one area stored in any one of the buffers #0 to #3 becomes larger than the write unit, that is, when the total size of data in one area stored in any one of the FIFO buffers 201 to 231 included in the buffers #0 to #3 becomes larger than the write unit, the flush processing is started.

[0122] The flushing process is also executed when any of the buffers #0 to #3 is full, that is, when any of the FIFO buffers 201 to 231 included in the buffers #0 to #3 is full. That is, when any of the FIFO buffers is full, the data of the area with the largest total size of the corresponding data among all the areas of data stored in the FIFO buffer is written to the NAND flash memory 5.

[0123] Each flush control unit 202-232 can determine whether the corresponding buffer among buffers #0-#3 satisfies the flush start condition. In this embodiment, when the total size of data in one area stored in a buffer among buffers #0-#3 is greater than the write unit, the buffer is determined to have satisfied the flush start condition. In addition, when a buffer among buffers #0-#3 is in a full state with data as a whole, the buffer is also determined to have satisfied the flush start condition.

[0124] In addition, each buffer #0 to #3 is configured to store data in the FIFO buffer included in the buffer, so the state of each buffer #0 to #3 is the same as the state of each FIFO buffer 201 to 231 included in the buffer #0 to #3. Therefore, the process of judging whether each buffer #0 to #3 satisfies the flushing condition can also be performed by judging whether each FIFO buffer 201 to 231 satisfies the flushing condition. The following mainly illustrates the case where each flushing control unit 202 to 232 judges whether the corresponding FIFO buffer among the FIFO buffers 201 to 231 satisfies the flushing start condition, to explain the buffering process of this embodiment.

[0125] That is, each flush control unit 202-232 determines whether the corresponding FIFO buffer satisfies the flush start condition. In this embodiment, when the total size of data in a zone stored in a certain FIFO buffer is greater than the write unit, the FIFO buffer is judged to satisfy the flush start condition. In addition, when a certain FIFO buffer is in a full state where the entire FIFO buffer is filled with data, the FIFO buffer is also judged to satisfy the flush start condition.

[0126] Each allocation management table 203 to 233 is a management table for managing identifiers of one or more areas allocated to the corresponding FIFO buffer. For example, if the FIFO buffer 201 is determined as the storage destination buffer to which the data of area 0 should be stored, area 0 is allocated to the FIFO buffer 201. Then, the identifier indicating area 0 is stored in the allocation management table 203 corresponding to the FIFO buffer 201.

[0127] In the initial state, each buffer #0 to #3 is an idle buffer. That is, each FIFO buffer 201 to 231 included in the buffer #0 to #3 is an idle FIFO buffer. An idle FIFO buffer is a FIFO buffer to which no area is allocated.

[0128] When each FIFO buffer 201 to 231 is idle, that is, when each buffer #0 to #3 is idle, when the controller 4 receives a zone addition command that specifies a specific zone from the host 2, the data / buffer allocation control unit 21 determines a certain idle buffer, for example, buffer #0, as the storage destination buffer to which the data of the specific zone should be stored. The data / buffer allocation control unit 21 allocates the specific zone to buffer #0. Then, the data / buffer allocation control unit 21 stores the data associated with the received zone addition command in the FIFO buffer 201 of buffer #0. Furthermore, the data / buffer allocation control unit 21 stores an identifier indicating the specific zone in the allocation management table 203 of buffer #0. Furthermore, the data / buffer allocation control unit 21 stores information indicating the buffer that was last updated to store data (here, the identifier indicating buffer #0) in the buffer update history management table 32.

[0129] When the controller 4 receives a new area addition command specifying another specific area from the host 2, the data / buffer allocation control unit 21 determines a certain free buffer, such as buffer #1, as the destination buffer to which the data of the other specific area should be saved. The data / buffer allocation control unit 21 allocates the other specific area to buffer #1. Then, the data / buffer allocation control unit 21 saves the data associated with the received new area addition command to the FIFO buffer 211 of buffer #1. Furthermore, the data / buffer allocation control unit 21 saves the identifier representing the other specific area to the allocation management table 213 of buffer #1. Furthermore, the data / buffer allocation control unit 21 saves the information representing the buffer that was last updated to save data (here, the identifier representing buffer #1) to the buffer update history management table 32.

[0130] In this way, the four areas are respectively allocated to the four buffers #0 to #3, that is, the four FIFO buffers 201 to 231.

[0131] When the controller 4 receives an area addition command from the host 2 that specifies a specific area that has been allocated to one of the buffers #0 to #3, the data / buffer allocation control unit 21 saves the data associated with the received area addition command to the FIFO buffer of the buffer to which the specific area has been allocated.

[0132] For example, when the controller 4 receives from the host 2 an area add command designating the same area as the area already allocated to the buffer #0, the data / buffer allocation control unit 21 stores the data associated with the received area add command in the FIFO buffer 201 of the buffer #0. Then, the data / buffer allocation control unit 21 stores, in the buffer update history management table 32, information indicating the buffer that was last updated to store the data (here, the identifier indicating the buffer #0).

[0133] When the controller 4 receives an area add command designating a new area different from the four areas already allocated to the four buffers #0 to 3 from the host 2, the data / buffer allocation control unit 21 determines the buffer that was last updated the earliest to store data by referring to the buffer update history table 32. The data / buffer allocation control unit 21 additionally allocates the new area to the determined buffer.

[0134] For example, when the buffer that was last updated the earliest to store data is buffer #0, the data / buffer allocation control unit 21 allocates the new area to buffer #0. Then, the data / buffer allocation control unit 21 stores the data associated with the received area addition command in the FIFO buffer 201 of buffer #0. Furthermore, the data / buffer allocation control unit 21 stores the identifier indicating the new area in the allocation management table 203 of buffer #0. Furthermore, the data / buffer allocation control unit 21 stores the information indicating the buffer that was last updated to store data (here, the identifier indicating buffer #0) in the buffer update history management table 32.

[0135] In this way, by allocating a new area to the buffer that was last updated the earliest to store data, it is possible to prevent the buffer used to store data from being biased towards a specific buffer, and as a result, data to be written to areas 0 to 7 can be distributed among buffers #0 to #3.

[0136] When one of the FIFO buffers 201 to 231 satisfies the flush start condition, the data / area allocation control unit 22 extracts only the data of the flush object area from the data stored in the FIFO buffer while maintaining the data of the areas other than the flush object area stored in the FIFO buffer. The data of the flush object area is write data associated with one or more area addition commands that specify the flush object area. Then, the data / area allocation control unit 22 writes the extracted data, i.e., the write data associated with several area addition commands that specify the flush object area, to the logical block range starting from the next writable LBA of the flush object area. Thus, sequential writing is performed on the flush object area.

[0137] As described above, one of the physical storage areas in the NAND flash memory 5 is allocated to each of the areas 0 to 7. Therefore, in the write operation to the clearing target area, the data / area allocation control unit 22 first determines the physical storage area allocated to the clearing target area and the write destination position in the physical storage area. Then, the data / area allocation control unit 22 writes the write data to the continuous physical storage positions starting from the write destination position in the physical storage area so that the data associated with these area addition commands are arranged on the physical storage area in the same order as the order in which these area addition commands are issued.

[0138] Next, refer to Figure 7A to Figure 7D , an example of buffer processing involved in the implementation mode is described. Figure 6 Similarly, the buffer processing involved in the embodiment is described by taking as an example a case where the areas managed by SSD3 are eight areas from area 0 to area 7 and the buffers prepared in SSD3 are four buffers from buffer #0 to buffer #3.

[0139] Fig. 7A This is a diagram showing the first process of the buffering process executed in SSD3.

[0140] Here, it is assumed that the controller 4 has received two area addition commands designating area 1 , three area addition commands designating area 0 , one area addition command designating area 3 , and one area addition command designating area 4 in sequence from the host 2 .

[0141] The data / buffer allocation control unit 21 allocates the first four areas designated by the received area addition commands, namely, area 1, area 0, area 3, and area 4, to buffer #0, buffer #1, buffer #2, and buffer #3, respectively.

[0142] In more detail, the controller 4 first receives the first zone addition command for specifying zone 1 from the host 2. There is no buffer to which zone 1 has been allocated. Therefore, the data / buffer allocation control unit 21 allocates zone 1 to buffer #0 to which no zone has been allocated. The data / buffer allocation control unit 21 adds an identifier representing zone 1 to the allocation management table 203 of buffer #0. Then, the data / buffer allocation control unit 21 obtains the data "zone1-D1" associated with the first zone addition command for specifying zone 1 from the memory 102 of the host 2, and saves the obtained data "zone1-D1" to the FIFO buffer 201. Thereafter, the data / buffer allocation control unit 21 adds information representing the buffer that was last updated to save data (here, the identifier representing buffer #0) to the buffer update history table 32.

[0143] The controller 4 receives a second zone addition command for specifying zone 1 from the host 2. Since zone 1 has been allocated to buffer #0, the data / buffer allocation control unit 21 determines buffer #0 as the destination buffer for storing the data associated with the second zone addition command for specifying zone 1. The data / buffer allocation control unit 21 obtains the data "zone1-D2" associated with the second zone addition command for specifying zone 1 from the memory 102 of the host 2, and stores the obtained data "zone1-D2" in the FIFO buffer 201. At this time, the identifier of the buffer last added to the buffer update history table 32 is the identifier of buffer #0. Therefore, the process of adding the identifier of buffer #0 storing the data "zone1-D2" to the buffer update history table 32 can be omitted here.

[0144] Furthermore, even when the identifier of the buffer last updated to save data is the same as the identifier of the buffer last added to the buffer update history table 32, the identifier of the buffer last updated to save data may be added to the buffer update history table 32. The following assumes, but is not limited to, a case where the identifier of the buffer last updated to save data is added to the buffer update history table 32 only when the identifier of the buffer last updated to save data is different from the identifier of the buffer last added to the buffer update history table 32.

[0145] The controller 4 receives the first zone addition command specifying zone 0 from the host 2. Since there is no buffer to which zone 0 has been allocated, the data / buffer allocation control unit 21 allocates zone 0 to buffer #1 to which no zone has been allocated. The data / buffer allocation control unit 21 adds an identifier representing zone 0 to the allocation management table 213 of buffer #1. Then, the data / buffer allocation control unit 21 obtains the data "zone0-D1" associated with the first zone addition command specifying zone 0 from the memory 102 of the host 2, and saves the obtained data "zone0-D1" to the FIFO buffer 211. Thereafter, the data / buffer allocation control unit 21 adds information indicating the buffer that was last updated to save data (here, the identifier representing buffer #1) to the buffer update history table 32.

[0146] The controller 4 receives the second zone addition command specifying zone 0 from the host 2. Zone 0 has already been assigned to buffer #1, so the data / buffer allocation control unit 21 determines buffer #1 as the storage destination buffer for the data associated with the second zone addition command specifying zone 0. The data / buffer allocation control unit 21 obtains the data "zone0-D2" associated with the second zone addition command specifying zone 0 from the memory 102 of the host 2, and stores the obtained data "zone0-D2" in the FIFO buffer 211.

[0147] The controller 4 receives the third zone addition command specifying zone 0 from the host 2. Zone 0 has already been assigned to buffer #1, so the data / buffer allocation control unit 21 determines buffer #1 as the storage destination buffer for the data associated with the third zone addition command specifying zone 0. The data / buffer allocation control unit 21 obtains the data "zone0-D3" associated with the third zone addition command specifying zone 0 from the memory 102 of the host 2, and stores the obtained data "zone0-D3" in the FIFO buffer 211.

[0148] The controller 4 receives the first zone addition command specifying zone 3 from the host 2. Since there is no buffer to which zone 3 has been allocated, the data / buffer allocation control unit 21 allocates zone 3 to buffer #2 to which no zone has been allocated. The data / buffer allocation control unit 21 adds an identifier representing zone 3 to the allocation management table 223 of buffer #2. Then, the data / buffer allocation control unit 21 obtains data "zone3-D1" associated with the first zone addition command specifying zone 3 from the memory 102 of the host 2, and saves the obtained data "zone3-D1" to the FIFO buffer 221. Thereafter, the data / buffer allocation control unit 21 adds information representing the buffer that was last updated to save data (here, the identifier representing buffer #2) to the buffer update history table 32.

[0149] The controller 4 receives the first zone addition command for specifying zone 4 from the host 2. There is no buffer to which zone 4 has been allocated, so the data / buffer allocation control unit 21 allocates zone 4 to buffer #3 to which no zone has been allocated. The data / buffer allocation control unit 21 adds an identifier representing zone 4 to the allocation management table 233 of buffer #3. Then, the data / buffer allocation control unit 21 obtains data "zone4-D1" associated with the first zone addition command for specifying zone 4 from the memory 102 of the host 2, and saves the obtained data "zone4-D1" to the FIFO buffer 231. Thereafter, the data / buffer allocation control unit 21 adds information representing the buffer that was last updated to save data (here, the identifier representing buffer #3) to the buffer update history table 32.

[0150] Figure 7B It is a diagram showing the second process of the buffering process according to the embodiment.

[0151] Here, imagine the following situation: after receiving Fig. 7A After the seven area addition commands described in , the controller 4 receives from the host 2 one area addition command designating area 1, one area addition command designating area 3, one area addition command designating area 4, and one area addition command designating area 3 in sequence.

[0152] Area 1, area 3 and area 4 have been allocated to buffer #0, buffer #2 and buffer #3 respectively. Therefore, the data / buffer allocation control unit 21 executes Fig. 7A The data "zone1-D3" associated with the zone addition command for specifying zone 1, the data "zone3-D2" associated with the zone addition command for specifying zone 3, the data "zone4-D2" associated with the zone addition command for specifying zone 4, and the data "zone3-D3" associated with the zone addition command for specifying zone 3 are stored in the FIFO buffer 201 of buffer #0, the FIFO buffer 221 of buffer #2, the FIFO buffer 231 of buffer #3, and the FIFO buffer 221 of buffer #2, respectively. Then, the data / buffer allocation control unit 21 adds the identifier of buffer #0, the identifier of buffer #2, the identifier of buffer #3, and the identifier of buffer #2 to the buffer update history table 32 in sequence.

[0153] Next, it is assumed that the controller 4 receives the first area addition command designating area 2 from the host 2 .

[0154] There is no buffer to which area 2 has been allocated, and there is no free buffer. Therefore, the data / buffer allocation control unit 21 determines the buffer that was last updated the earliest to store data by referring to the buffer update history table 32. The buffer update history table 32 stores information indicating that "the buffer that was last updated the earliest is buffer #1, the buffer that was last updated the second earliest is buffer #0, the buffer that was last updated the second earliest is buffer #3, and the buffer that was last updated the latest is buffer #2" as history information.

[0155] Therefore, the data / buffer allocation control unit 21 allocates zone 2 to the buffer #1, which is the buffer that was last updated the earliest to store data. In this case, the data / buffer allocation control unit 21 adds an identifier indicating zone 2 to the allocation management table 213 of buffer #1. Then, the data / buffer allocation control unit 21 stores the data "zone2-D1" associated with the first zone addition command that specifies zone 2 in the FIFO buffer 211. Thereafter, the data / buffer allocation control unit 21 adds information indicating the buffer that was last updated to store data (here, the identifier indicating buffer #1) to the buffer update history table 32.

[0156] Next, it is assumed that the controller 4 receives a second area addition command designating area 2 from the host 2 .

[0157] Zone 2 has already been allocated to buffer #1. Therefore, the data / buffer allocation control unit 21 determines buffer #1 as the destination buffer for storing the data associated with the second zone addition command that specifies zone 2. The data / buffer allocation control unit 21 obtains the data "zone2-D2" associated with the second zone addition command that specifies zone 2 from the memory 102 of the host 2, and stores the obtained data "zone2-D2" in the FIFO buffer 211.

[0158] Figure 7C It is a diagram showing a third process of the buffering process according to the embodiment.

[0159] Here, imagine the following situation: after receiving Fig. 7A The seven districts described in the additional orders and Figure 7B After the six area addition commands described in , the controller 4 first receives two area addition commands specifying area 1, two area addition commands specifying area 4, and one area addition command specifying area 2 from the host 2 in sequence.

[0160] Zone 1, zone 4, and zone 2 have been allocated to buffer #0, buffer #3, and buffer #1, respectively. Therefore, the data / buffer allocation control unit 21 stores the data "zone1-D4" and the data "zone1-D5" respectively associated with the two zone addition commands for specifying zone 1 in the FIFO buffer 201 of buffer #0, stores the data "zone4-D3" and the data "zone4-D4" respectively associated with the two zone addition commands for specifying zone 4 in the FIFO buffer 231 of buffer #3, and stores the data "zone2-D3" associated with one zone addition command for specifying zone 2 in the FIFO buffer 211 of buffer #1. Then, the data / buffer allocation control unit 21 sequentially adds the identifier of buffer #0, the identifier of buffer #3, and the identifier of buffer #1 to the buffer update history table 32.

[0161] Next, it is assumed that the controller 4 receives the first area addition command designating the area 5 from the host 2 .

[0162] There is no buffer that has been allocated with area 5, and there is no free buffer. Therefore, the data / buffer allocation control unit 21 determines the buffer that was last updated earliest to store data by referring to the buffer update history table 32. The buffer that was last updated earliest to store data is buffer #2.

[0163] Therefore, the data / buffer allocation control unit 21 allocates zone 5 to the buffer #2, which is the buffer that was last updated the earliest to store data. In this case, the data / buffer allocation control unit 21 adds the identifier indicating zone 5 to the allocation management table 223 of buffer #2. Then, the data / buffer allocation control unit 21 stores the data "zone5-D1" associated with the first zone addition command that specifies zone 5 in the FIFO buffer 221. Thereafter, the data / buffer allocation control unit 21 adds information indicating the buffer that was last updated to store data (here, the identifier indicating buffer #2) to the buffer update history table 32.

[0164] Next, the controller 4 receives a second area add command designating the area 5 , and a third area add command designating the area 5 from the host 2 .

[0165] Zone 5 has been allocated to buffer #2. Therefore, the data / buffer allocation control unit 21 stores the data "zone5-D2" associated with the second zone addition command specifying zone 5 and the data "zone5-D3" associated with the third zone addition command specifying zone 5 in the FIFO buffer 221.

[0166] Next, it is assumed that the controller 4 receives two area addition commands designating area 0 from the host 2 .

[0167] Zone 0 has already been allocated to buffer #1. Therefore, the data / buffer allocation control unit 21 stores the data "zone0-D4" and "zone0-D5" respectively associated with the two zone addition commands that specify zone 0 in the FIFO buffer 211. Thereafter, the data / buffer allocation control unit 21 adds information indicating the buffer that was last updated to store data (here, the identifier indicating buffer #1) to the buffer update history table 32.

[0168] Since the data "zone0-D5" is stored in the FIFO buffer 221 of the buffer #1, the FIFO buffer 221 becomes full and cannot store any more data. Since the FIFO buffer 221 becomes full, the FIFO buffer 221 satisfies the flush start condition.

[0169] Fig.7D It is a diagram showing the fourth process of the buffering process according to the embodiment.

[0170] The data / area allocation control unit 22 selects an area to be cleared from the buffer #1, and extracts only data associated with the area to be cleared from among all the data stored in the buffer #1.

[0171] In buffer #1 (i.e., FIFO buffer 221), data "zone0-D1" to "zone0-D5" associated with zone 0 and data "zone2-D1" to "zone2-D3" associated with zone 2 are stored. In buffer #1, zone 0 is the zone with the largest total size of associated data. Therefore, the data / zone allocation control unit 22 determines zone 0 as the zone to be cleared.

[0172] The data / area allocation control unit 22 extracts only the data associated with zone 0 from buffer #1. At this time, the data / area allocation control unit 22 controls so that the data associated with zones other than the clearing target zone is maintained in buffer #1. That is, the data / area allocation control unit 22 extracts the data "zone0-D1" to "zone0-D5" from buffer #1 while the data "zone2-D1" to "zone2-D3" are maintained in buffer #1. Then, the data / area allocation control unit 22 determines the zone of the write destination, and sequentially writes the data "zone0-D1" to "zone0-D5" to the determined write destination zone (here, zone 0). If the data of zone 0 disappears from buffer #1, the data / area allocation control unit 22 deletes the identifier of zone 0 from the allocation management table 213. As a result, the allocation of zone 0 to buffer #1 is released.

[0173] Therefore, when an area add command specifying area 0 is received after the data of area 0 disappears from buffer #1, there is no buffer already allocated with area 0. Therefore, the data / buffer allocation control unit 21 refers to the buffer update history table 32 to determine the buffer that was last updated the earliest in order to store the data, and stores the data associated with the received area add command in the determined buffer.

[0174] Next, refer to Figure 8A to Figure 8E , illustrating an example of override processing for extracting data associated with area 0 from buffer #1.

[0175] Fig. 8A This is a diagram showing the first process of the overtaking process executed in SSD3.

[0176] The FIFO buffer 211 of the buffer #1 includes an input port 211A, an output port 211B, a loop path 211C, an input selector 211D, and an output selector 211E. The loop path 211C is a path connecting the output port 211B of the FIFO buffer 211 and the input port 211A of the FIFO buffer 211. The input selector 211D and the output selector 211E are switch circuits for enabling or disabling the loop path 211C.

[0177] The input port 211A of the FIFO buffer 211 is connected to the input selector 211D. The output port 211B of the FIFO buffer 211 is connected to the output selector 211E. The input selector 211D selects either the external input or the loop path 211C, and connects the selected external input or the loop path 211C to the input port 211A. The output selector 211E selects either the loop path 211C or the external output, and connects the output port 211B to the selected loop path 211C or the external output. The external output is transmitted via Figure 1 The NAND interface 13 is connected to the NAND flash memory 5.

[0178] When the next data that can be read from the FIFO buffer 211, that is, the oldest data in the FIFO buffer 211, is data of an area other than the flush target area, the data / area allocation control unit 22 controls the input selector 211D and the output selector 211E to enable the loop path 211C and connect the output port 211B to the input port 211A. When the next data that can be read from the FIFO buffer 211 is data of the flush target area, the data / area allocation control unit 22 controls the output selector 211E to disable the loop path 211C and connect the output port 211B to the external output. In this case, the data / area allocation control unit 22 may control the input selector 211D to connect the input port 211A to the loop path 211C.

[0179] When starting the cleanup process, Fig. 8A As shown, the data / area allocation control unit 22 first controls the input selector 211D to disconnect the input port 211A from the external input and connect the input port 211A to the loop side, that is, the loop path 211C, in order to prevent new data from being stored in the FIFO buffer 211.

[0180] Figure 8B This is a diagram showing a second process of the transcendence process according to the embodiment.

[0181] The data / area allocation control unit 22 determines whether the next data that can be read from the FIFO buffer 211 is data of the clearing target area. Until the reading of the data "zone0-D1" to "zone0-D3" is completed, the next data that can be read is the data associated with the zone 0 that is the clearing target area. Therefore, the data / area allocation control unit 22 controls the output selector 211E to connect the output port 211B to the external output, thereby invalidating the loop path 211C. Thereafter, the data / area allocation control unit 22 reads the data "zone0-D1", the data "zone0-D2", and the data "zone0-D3" from the FIFO buffer 211.

[0182] Figure 8C This is a diagram showing a third process of the transcendence process according to the embodiment.

[0183] After the data "zone0-D1" to "zone0-D3" are read, the next data that can be read from the FIFO buffer 211 is not data of the clearing target area until the data "zone2-D1" to "zone2-D3" are read from the FIFO buffer 211. Therefore, the data / area allocation control unit 22 controls the output selector 211E to connect the output port 211B to the loop path 211C, thereby making the loop path 211C effective.

[0184] In the state where the loop path 211C is enabled, the data / area allocation control unit 22 performs a read operation of reading data from the FIFO buffer 211 and a write operation of writing data to the FIFO buffer 211. Thus, an operation of reading the data "zone2-D1" to "zone2-D3" from the output port 211B of the FIFO buffer 211 and an operation of writing the read data "zone2-D1" to "zone2-D3" back to the FIFO buffer 211 via the loop path 211C and the input port 211A are performed in parallel. As a result, the data "zone2-D1" to "zone2-D3" are maintained in the FIFO buffer 211.

[0185] Fig.8D This is a diagram showing the fourth process of the transcendence process according to the embodiment.

[0186] After the data "zone2-D1" to "zone2-D3" are read, the next data that can be read from the FIFO buffer 211 is the data of the clearing target area.

[0187] Since the next data that can be read from the FIFO buffer 211 is data of the clearing target area, the data / area allocation control unit 22 controls the output selector 211E to disable the loop path 211C and connect the output port 211B to the external output. Thereafter, the data / area allocation control unit 22 controls the FIFO buffer 211 to read the data "zone0-D4" and the data "zone0-D5" from the output port 211B.

[0188] Fig. 8E This is a diagram showing a fifth process of the transcendence process according to the embodiment.

[0189] The data / area allocation control unit 22 confirms that no data in the clearing target area remains in the FIFO buffer 211. If it is known that no data in the clearing target area remains in the FIFO buffer 211, the data / area allocation control unit 22 controls the input selector 211D to connect the input port 211A to the external input. As a result, the FIFO buffer 211 becomes capable of receiving new data from the external input.

[0190] By the overriding process described here, the data / area allocation control unit 22 extracts only the data of the flush target area from the buffer # 1. In addition, the data associated with the area other than the flush target area is maintained in the state of being stored in the buffer # 1.

[0191] Here, the override process executed when a certain buffer becomes full is described, but when the total size of data in a specific area stored in a certain buffer becomes larger than the write unit, the override process of extracting only data in the specific area is executed in the same procedure.

[0192] Fig. 9 This is a flowchart showing the procedure of command processing executed in the SSD 3 involved in the embodiment.

[0193] This command processing is used to execute a command to sequentially write data to any area among multiple areas in the partition namespace. This command can be either an area addition command or a write command used as an address specific write command. The following illustrates the processing of the area addition command and explains the process of the command processing.

[0194] First, the controller 4 receives a region addition command from the host 2 (step S11). The controller 4 determines the destination buffer to which the data associated with the received region addition command should be saved through the data / buffer allocation control unit 21, and saves the data to the determined destination buffer (step S12). The detailed process of the data / buffer allocation processing performed by the data / buffer allocation control unit 21 is described in detail in Fig.10 is described in.

[0195] The controller 4 updates the buffer update history table 32 (step S13). In step S13, the controller 4 adds the identifier of the storage destination buffer determined in step S12 as information indicating the buffer last updated to store data to the buffer update history table 32. In addition, at this time, if the identifier to be added to the buffer update history table 32 is the same as the identifier of the buffer last added to the buffer update history table, the process of adding the buffer identifier to the buffer update history table 32 may be omitted.

[0196] The controller 4 determines whether a certain buffer is full or whether the total size of data in a certain area in a certain buffer exceeds the write unit (step S14). In other words, the controller 4 determines whether there is a buffer that satisfies the flush start condition.

[0197] If there is no full buffer and no buffer in which the total size of data in a certain area exceeds the write unit (step S14 : No), the controller 4 waits until receiving the next area add command from the host 2 .

[0198] In the case where there is a full buffer, or a buffer in which the total size of data in a certain area is larger than the write unit (step S14: yes), the controller 4 extracts only the data in the clearing object area from all the data stored in the buffer through override processing (step S15). In the case where the buffer is full, the area with the largest total size of associated data is determined as the clearing object area. In the case where there is a buffer in which the total size of data associated with a certain area is larger than the write unit, the area with the total size of associated data larger than the write unit is determined as the clearing object area. The detailed process of the override processing is described in Fig.11 is described in.

[0199] The controller 4 determines the physical storage area of ​​the writing destination of the data extracted in step S15 through the data / area allocation control unit 22 (step S16). The physical storage area of ​​the writing destination is a specific storage area in the NAND flash memory 5 allocated to the determined clear target area.

[0200] Thereafter, the controller 4 writes the data of the clear target area extracted from the buffer into the physical storage area of ​​the write destination, that is, a specific storage area (physical storage area) in the NAND flash memory 5 allocated to the clear target area (step S17).

[0201] If the data of the clearing object area is written to a specific storage area in the NAND flash memory 5, the processing of one or more area addition commands corresponding to the written data is completed. In step S17, the controller 4 can send the command completion corresponding to each completed area addition command to the host 2. In addition, the controller 4 does not necessarily need to wait for the command completion to be sent before the data is written to the NAND flash memory 5 in step S17. Only when the Force Unit Access (FUA) included in the received area addition command is set to 1, it is necessary to wait for the command completion to be sent until the data is written to the NAND flash memory 5. When the FUA included in the received area addition command is 0, the controller 4 can send the command completion corresponding to the received area addition command to the host 2 without waiting before the data associated with the received area addition command is written to the NAND flash memory 5. For example, the controller 4 can send the command completion corresponding to the received area addition command to the host 2 when the data associated with the received area addition command has been saved in the buffer. Each command completion includes information indicating a write destination position (LBA) in the zone to which data associated with the zone addition command corresponding to the command completion is written.

[0202] Fig.10 1 is a flowchart showing the process of data / buffer allocation processing involved in the embodiment. The data / buffer allocation processing described here is Fig. 9 The details of the processing of step S12 in .

[0203] like Fig. 9 As described in step S11 of FIG. 1 , the controller 4 receives the area addition command from the host 2 .

[0204] The data / buffer allocation control unit 21 determines whether there is a buffer to which the area specified by the area addition command received in step S11 has been allocated, by referring to the allocation management table provided in each of the plurality of buffers (step S21 ).

[0205] When there is no buffer to which the area specified by the received area addition command has been allocated (step S21: No), the data / buffer allocation control unit 21 determines whether there is a free buffer by referring to the allocation management table provided in each of the plurality of buffers (step S22).

[0206] If there is no free buffer (step S22: No), the data / buffer allocation control unit 21 determines the buffer that was last updated earliest to store the data as the storage destination buffer (step S23). The data / buffer allocation control unit 21 refers to the buffer update history table 32 to determine the buffer that was last updated earliest to store the data. The storage destination buffer is the buffer to which the data associated with the received area addition command should be stored.

[0207] The data / buffer allocation control unit 21 allocates the area specified by the area addition command received in step S11 to the storage destination buffer (step S24). The data / buffer allocation control unit 21 adds an identifier indicating the area specified by the area addition command to the allocation management table provided in the storage destination buffer, thereby additionally allocating the area to the storage destination buffer.

[0208] The controller 4 stores the data associated with the area addition command received in step S11 in the determined storage destination buffer (step S28). That is, the data / buffer allocation control unit 21 obtains the data associated with the area addition command received in step S11 from the memory 102 of the host 2, and stores the obtained data in the determined storage destination buffer. Thereafter, the process proceeds to Fig. 9 In step S13 , the controller 4 updates the buffer update history table 32 .

[0209] When there are one or more free buffers (step S22 : Yes), the data / buffer allocation control unit 21 selects an arbitrary buffer from the free buffers and determines it as the storage destination buffer (step S25 ).

[0210] The data / buffer allocation control unit 21 allocates the area designated by the area addition command received in step S11 to the storage destination buffer (step S26 ).

[0211] Thereafter, the process proceeds to step S28 , and the controller 4 stores the data associated with the area addition command received in step S11 in the determined storage destination buffer.

[0212] If there is a buffer to which the area specified by the area addition command received in step S11 has been allocated (step S21 : Yes), the data / buffer allocation control unit 21 determines the buffer as the storage destination buffer (step S27 ).

[0213] Thereafter, the process proceeds to step S28 , and the controller 4 stores the data associated with the area addition command received in step S11 in the determined storage destination buffer.

[0214] Fig.11 is a flowchart showing the process of transcending processing involved in the implementation mode. Fig. 9 The details of the processing of step S15 in are described below.

[0215] When a certain buffer (FIFO buffer) satisfies the flush start condition, the data / area allocation control unit 22 determines an area to be flushed from among the areas allocated to the FIFO buffer (step S31).

[0216] The data / area allocation control unit 22 determines whether the area associated with the next data to be read from the FIFO buffer satisfying the flush start condition (ie, the next readable data in the FIFO buffer) is a flush target area (step S32).

[0217] When the area associated with the next readable data is not the clearing target area (step S32: No), the data / area allocation control unit 22 enables the loop path of the FIFO buffer and controls the input port and output port of the FIFO buffer to be connected to the loop side (step S33).

[0218] If the area corresponding to the next readable data is a clearing target area (step S32: Yes), the data / area allocation control unit 22 controls to release the connection if the input port and output port of the FIFO buffer are connected to the loopback side (step S34).

[0219] The data / area allocation control unit 22 reads the next readable data from the FIFO buffer (step S35). The data / area allocation control unit 22 determines whether data in the clearing target area remains among the data stored in the FIFO buffer (step S36).

[0220] When data in the clearing target area remains among the data stored in the FIFO buffer (step S36: Yes), the processing of the data / area allocation control unit 22 moves to step S32 again to read the next readable data.

[0221] If there is no data in the clearing target area remaining among the data stored in the FIFO buffer (step S36: No), the data / area allocation control unit 22 deletes the identifier indicating the clearing target area from the allocation management table of the FIFO buffer (step S37). As a result, the allocation of the clearing target area to the FIFO buffer is released.

[0222] As described above, according to the present embodiment, when there is a buffer to which the area specified by the received area addition command is allocated, the controller 4 determines the buffer as the storage destination buffer to which the data associated with the received area addition command should be stored. In addition, when there is no buffer to which the area specified by the received area addition command is allocated, but there is an idle buffer, the controller 4 determines any buffer among the idle buffers as the storage destination buffer. In addition, when there is no buffer to which the area specified by the received area addition command is allocated, and there is no idle buffer, the controller 4 determines the buffer that was last updated the earliest to store the data as the storage destination buffer.

[0223] Through these processes, data is not biased toward a specific buffer, but the storage destination of data can be dispersed among a plurality of buffers. Furthermore, data to be written to the same area can be stored in the same buffer.

[0224] In addition, the controller 4 selects, as the clearing target area, an area in which the total size of data stored in one of the plurality of buffers is greater than the write unit, or an area in which the total size of data corresponding to all areas stored in the buffer whose corresponding data is full, and in which the total size of data corresponding to the area is the largest. Thus, an area with a relatively large amount of data accumulated in the buffer can be selected as the clearing target area, and thus the efficiency of sequential writing can be improved compared to the case where the data of each area is written to the NAND flash memory 5 in smaller units.

[0225] Furthermore, the controller 4 extracts only the data of the clearing target area while the data of the area other than the clearing target area is maintained in the buffer. Thus, even if the data of the same area is fragmented to various different positions in one buffer, for example, it is not necessary to perform clearing processing on the data of the area other than the clearing target area, but it is possible to perform clearing processing on only the data of the clearing target area. Therefore, it is not necessary to write the data in the buffer to the NAND flash memory 5 in small units, but it is possible to write only the data of the clearing target area having a relatively large amount of data to the NAND flash memory 5.

[0226] As described above, in this embodiment, the data to be written to different zones can be efficiently buffered using a buffer whose number is smaller than the number of zones included in the partition namespace. Furthermore, in this embodiment, only the data of the clearing target zone can be written to the NAND flash memory 5 from the buffer where the data of different zones are mixed. Thus, compared with a configuration in which the same number of buffers as the number of zones are used, the amount of memory resources in the SSD 3 required for controlling a plurality of zones can be reduced.

[0227] Furthermore, when receiving a write command used as an address-specific write command from the host 2 , the controller 4 may transmit a command completion of the write command to the host 2 when storing data associated with the write command in the buffer.

[0228] Thus, the host 2 can issue the next write command that specifies the same area as the area specified by the write command to the SSD 3. As a result, before the processing of the write command that specifies a certain area is actually completed, that is, before the writing of the data associated with the write command to the NAND flash memory 5 is completed, the next write command that specifies the same area as the area can be received from the host 2. Thus, even in the case where each write command requests to write data of a small size, the write processing can be started after a certain amount of data associated with the same area is accumulated in the same buffer, and the writing efficiency to the NAND flash memory 5 can be improved.

[0229] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations and the modes included in the scope or subject matter of the invention are all included in the invention described in the claims and their equivalents.

Claims

1. A memory system, wherein: have: Non-volatile memory; as well as A controller is configured to be electrically connected to the non-volatile memory and to control the non-volatile memory using a partition namespace divided into a plurality of regions as specified by the non-volatile memory host controller interface specification NVM express, The controller is composed of: managing a plurality of buffers, the number of the plurality of buffers being less than the number of the plurality of regions, In response to receiving from the host a first command for sequentially writing data into a first area among the plurality of areas and associated with the first data, When there is a first buffer to which the first area is allocated among the plurality of buffers, the first data is stored in the first buffer, When the first buffer does not exist among the plurality of buffers and there is an idle buffer to which no area is allocated among the plurality of buffers, the first area is allocated to the idle buffer, and the first data is stored in the idle buffer to which the first area is allocated. When the first buffer does not exist among the multiple buffers and there is no free buffer to which any area is not allocated among the multiple buffers, the first area is additionally allocated to the buffer that was last updated earliest among the multiple buffers in order to save the data, and the first data is saved in the buffer to which the first area is additionally allocated.

2. The memory system of claim 1, wherein: The controller is composed of: managing history information indicating the order in which the plurality of buffers are updated to store data, When the first buffer does not exist among the plurality of buffers and when there is no free buffer to which any area is not allocated among the plurality of buffers, the buffer that was last updated earliest to store data among the plurality of buffers is determined by referring to the history information.

3. The memory system of claim 1, wherein: The controller is also configured as follows: In a case where a second buffer among the plurality of buffers stores second data associated with a second area among the plurality of areas and third data associated with a third area among the plurality of areas that is different from the second area, and a size of the second data is larger than a write unit to the nonvolatile memory, extracting the second data from the second buffer while the third data is maintained in the second buffer, The extracted second data is written into a storage area in the nonvolatile memory allocated to the second area.

4. The memory system of claim 3, wherein: The controller is also configured as follows: In a case where a third buffer among the plurality of buffers that is in a full state stores fourth data associated with a fourth area among the plurality of areas and fifth data associated with a fifth area among the plurality of areas that is different from the fourth area, and the size of the fourth data is larger than the size of the fifth data, extracting the fourth data from the third buffer while the fifth data is maintained in the third buffer, The extracted fourth data is written into a storage area in the nonvolatile memory allocated to the fourth zone.

5. The memory system of claim 3, wherein: Each of the plurality of buffers comprises: a first-in-first-out buffer, an input port for inputting data into the first-in-first-out buffer, an output port for outputting data from the first-in-first-out buffer, and a path for connecting the output port to the input port, The controller is also configured as follows: In a case where the next data that can be read from the first-in-first-out buffer of the second buffer is the third data, the path is made valid, and an action of reading the third data from the first-in-first-out buffer of the second buffer and an action of writing the read third data back to the first-in-first-out buffer of the second buffer are performed, thereby maintaining the third data in the second buffer.

6. The memory system of claim 5, wherein: The controller is also configured as follows: When the next data that can be read from the FIFO buffer of the second buffer is the second data, the path is invalidated, and a read operation from the FIFO buffer of the second buffer is performed, thereby extracting the second data from the second buffer.

7. The memory system of claim 3, wherein: The nonvolatile memory includes a plurality of blocks, each of the plurality of blocks includes a plurality of pages, each of the plurality of blocks is a unit of data deletion operation, and each of the plurality of pages is a unit of data writing operation and data reading operation, The write unit is a multiple of a size of each of the plurality of pages or a multiple of a size of each of the plurality of blocks.

8. The memory system of claim 1, wherein: The first command is a region addition command specified in the non-volatile memory host controller interface specification NVM express.

9. The memory system of claim 1, wherein: The first command is an address specific write command specified in the non-volatile memory host controller interface specification NVM express.

10. A control method, wherein: Controls non-volatile memory using a partition namespace divided into multiple zones as specified by the non-volatile memory host controller interface specification NVM express, with: managing a plurality of buffers less in number than the plurality of regions; receiving, from the host, a first command for sequentially writing data into a first area among the plurality of areas and associated with first data; When there is a first buffer to which the first area is allocated among the plurality of buffers, storing the first data in the first buffer; When the first buffer does not exist among the plurality of buffers and there is an idle buffer to which no area is allocated among the plurality of buffers, the first area is allocated to the idle buffer, and the first data is stored in the idle buffer to which the first area is allocated; When the first buffer does not exist among the plurality of buffers and there is no idle buffer to which any area is not allocated among the plurality of buffers, the first area is additionally allocated to a buffer that is updated earliest among the plurality of buffers for storing data, and the first data is stored in the buffer to which the first area is additionally allocated; When a second buffer among the plurality of buffers stores second data associated with a second area among the plurality of areas and third data associated with a third area among the plurality of areas that is different from the second area, and a size of the second data is larger than a write unit to the nonvolatile memory, extracting the second data from the second buffer while the third data is maintained in the second buffer, and writing the extracted second data to a storage area in the nonvolatile memory allocated to the second area; In a case where a third buffer among the multiple buffers that is in a full state stores fourth data associated with a fourth area among the multiple areas and fifth data associated with a fifth area among the multiple areas that is different from the fourth area, and a size of the fourth data is larger than a size of the fifth data, the fourth data is extracted from the third buffer while the fifth data is maintained in the third buffer, and the extracted fourth data is written to a storage area in the non-volatile memory allocated to the fourth area.

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