Charge elimination circuit module, MRAM storage unit readout circuit and storage system

Abstract

The present invention discloses a charge elimination circuit module, an MRAM storage unit readout circuit and a storage system. The readout circuit includes a first bit line capacitor, a second bit line capacitor, a bit line charge elimination module, a coupling amplification module, a coupling charge elimination module and a comparison latch module. The bit line charge elimination module can discharge two bit lines to be compared to the same low level or charge them to the same high level. The coupling amplification module can not only discharge its two input terminals to the same low level, but also amplify the signal of the input terminal. The coupling charge elimination module can discharge the two output terminals of the coupling amplification module to the same low level or charge them to the same high level, thereby preventing the charge difference on the two node capacitors after precharging, the mismatch error of the two branches connecting the two node capacitors and the residual charge on the node capacitor after the last readout is completed from affecting the readout accuracy.

Description

Technical Field

[0001] The present invention relates to the field of MRAM reading and writing technology, and in particular to a charge elimination circuit module, an MRAM storage unit readout circuit and a storage system. Background Art

[0002] The core structure of the MRAM (Magnetoresistive Random Access Memory) storage unit is the Magnetic Tunneling Junction (MTJ), which is composed of two magnetic layers sandwiched by an extremely thin non-magnetic isolation layer. The two magnetic layers are the free layer and the fixed layer. The fixed layer has a strong coercive force and its magnetic moment will not change, while the magnetic moment of the free layer will change under the influence of external current. MTJ mainly has two states: high resistance and low resistance. When the directions of the magnetic moments of the free layer and the fixed layer are consistent, electrons can easily pass through the two magnetic layers, and MTJ shows a low resistance state. At this time, we believe that the stored data is '0'. When the directions of the magnetic moments of the free layer and the fixed layer are opposite, electrons are scattered between the two layers and it is not easy to pass through the two magnetic layers. MTJ shows a high resistance state. At this time, we believe that the stored data is '1'.

[0003] For MRAM storage cells, the most basic operations are data writing and reading. The existing readout circuit is a charge-type sensitive amplifier, which includes two node capacitors of the same size, one end of which is connected to the bit lines of the unit to be read and the reference unit respectively, so that one bit line can control the release of charge of a node capacitor, and the other end is connected to the two input ends of the comparison circuit respectively. By setting the node capacitance, the DC path of the sensitive amplifier can be eliminated. In addition, by comparing the size of the node capacitance voltage, the data of the unit to be read can be read.

[0004] Specifically, this type of sensitive amplifier needs to precharge the two node capacitors to the same voltage before the bit line signal is connected. Then the bit line signal is connected, so that the charges stored on the corresponding node capacitors are discharged through the two bit lines, and when the voltage difference between the two node capacitors expands to a certain extent, the comparison circuit generates a comparison result, and the comparison result is connected to the latch for latch output, thereby completing the reading of the data of the cell to be read.

[0005] Although this sensitive amplifier can achieve comparison latching without a DC path and low read voltage, it is too dependent on the amount of charge. The charge difference on the two node capacitors after pre-charging, the mismatch error of the two branches connecting the two node capacitors, and the residual charge on the node capacitor after the previous readout are all great influences on the next readout, thus causing errors in the readout results. Summary of the invention

[0006] The present invention provides a charge elimination circuit module, an MRAM storage unit readout circuit and a storage system, which are used to overcome the technical problems existing in the above-mentioned prior art and improve the accuracy of the MRAM storage unit readout result.

[0007] The present invention provides a charge elimination circuit module, which is used to eliminate the voltage difference between the first end and the second end of the circuit module, and includes: a charge zeroing unit and a charge averaging unit.

[0008] The charge zeroing unit is composed of three MOS transistors, and is used to pull the voltage of the first end and the second end to the same low level when the three gates controlled by the discharge signal are turned on;

[0009] The charge averaging unit is composed of three transmission gates, and is used to raise the voltages of the first terminal and the second terminal to the same high level when the transmission gate control signal is enabled.

[0010] The present invention also provides an MRAM storage unit readout circuit, comprising: a first bit line capacitor, a second bit line capacitor, a bit line charge elimination module, a coupling amplification module, a coupling charge elimination module, and a comparison latch module; the bit line charge elimination module and the coupling charge elimination module both include the above-mentioned charge elimination circuit module; the first end of the bit line charge elimination module is connected to the to-be-read unit bit line and the positive electrode of the first bit line capacitor to obtain the to-be-read bit line signal from the to-be-read unit bit line, and the second end of the bit line charge elimination module is connected to the reference unit bit line and the positive electrode of the second bit line capacitor to obtain the reference bit line signal from the reference unit bit line signal; the bit line charge elimination module includes a first charge zeroing unit and a first precharge charge averaging unit, the first charge zeroing unit is used to discharge the positive electrode of the first bit line capacitor and the positive electrode of the second bit line capacitor to the same low level; the first precharge charge averaging unit is used to charge the positive electrode of the first bit line capacitor and the positive electrode of the second bit line capacitor to the same high level; the first input end of the coupling amplification module is connected to the negative electrode of the first bit line capacitor, the second input end of the coupling amplification module is connected to the negative electrode of the second bit line capacitor, and the coupling amplification module is used to amplify the to-be-read bit line signal. The first end of the coupling charge elimination module and the first input end of the comparison latch module are connected to the first output end of the coupling amplification module, and the second end of the coupling charge elimination module and the second input end of the comparison latch module are connected to the second output end of the coupling amplification module. The coupling charge elimination module includes a second charge zeroing unit and a second precharge charge averaging unit. The second charge zeroing unit is used to discharge the first output end and the second output end of the coupling amplification module to the same low level. The second precharge charge averaging unit is used to charge the first output end and the second output end of the coupling amplification module to the same high level. The comparison latch module is used to compare the third signal obtained from the first output end of the coupling amplification module and the fourth signal obtained from the second output end of the coupling amplification module, and then generate and latch a comparison result positive signal and a comparison result negative signal. The first output end of the comparison latch module is used to output the comparison result positive signal, and the second output end of the comparison latch module is used to output the comparison result negative signal.

[0011] Further, the bit line charge elimination module includes: a first NMOS transistor, a second NMOS transistor and a third NMOS transistor constituting the first charge zeroing unit, and a first transmission gate, a second transmission gate and a third transmission gate constituting the first precharge charge averaging unit; the drain of the first NMOS transistor, the output end of the second transmission gate, the drain of the third NMOS transistor and the input end of the first transmission gate are connected to the first end of the bit line charge elimination module; the output end of the first transmission gate, the output end of the third transmission gate, the source of the third NMOS transistor and the drain of the second NMOS transistor are connected to the second end of the bit line charge elimination module; the sources of the first NMOS transistor and the second NMOS transistor are grounded; the input ends of the second transmission gate and the third transmission gate are connected to the bit line precharge voltage; the positive control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected to the precharge control signal, and the negative control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected to the inverted signal of the precharge control signal; the gates of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are connected to the charge zeroing signal.

[0012] Furthermore, the coupling amplification module includes a coupling charge zeroing unit, which is used to discharge the negative electrode of the first bit line capacitor and the negative electrode of the second bit line capacitor to the same low level.

[0013] Optionally, the coupled charge zeroing unit includes: a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; the drain of the fourth NMOS transistor and the drain of the sixth NMOS transistor are connected to the first input terminal of the coupled amplification module; the source of the sixth NMOS transistor and the drain of the fifth NMOS transistor are connected to the second input terminal of the coupled amplification module; the source of the fourth NMOS transistor and the fifth NMOS transistor are grounded.

[0014] Furthermore, the coupling amplification module also includes a seventh NMOS transistor, an eighth NMOS transistor, a first node capacitor and a second node capacitor; the source of the seventh NMOS transistor is connected to the first input terminal of the coupling amplification module, and the source of the eighth NMOS transistor is connected to the second input terminal of the coupling amplification module; the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor, the positive electrode of the second node capacitor and the second output terminal of the coupling amplification module are connected; the gate of the eighth NMOS transistor, the drain of the seventh NMOS transistor, the positive electrode of the first node capacitor and the first output terminal of the coupling amplification module are connected; and the negative electrodes of the first node capacitor and the second node capacitor are grounded.

[0015] Optionally, the coupling charge elimination module includes: a ninth NMOS transistor, a tenth NMOS transistor and an eleventh NMOS transistor constituting the second charge zeroing unit, and a fourth transmission gate, a fifth transmission gate and a sixth transmission gate constituting the second precharge charge averaging unit; the drain of the ninth NMOS transistor, the output end of the fifth transmission gate, the drain of the eleventh NMOS transistor and the input end of the fourth transmission gate are connected to the first end of the coupling charge elimination module; the output end of the fourth transmission gate, the output end of the sixth transmission gate, the source of the eleventh NMOS transistor and the drain of the tenth NMOS transistor are connected to the second end of the coupling charge elimination module; the sources of the ninth NMOS transistor and the tenth NMOS transistor are grounded; the input ends of the fifth transmission gate and the sixth transmission gate are connected to the coupling precharge voltage; the positive control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected to the precharge control signal, and the negative control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected to the inverted signal of the precharge control signal; the gates of the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor are connected to the charge zeroing signal.

[0016] Optionally, the comparison latch module includes: a comparison latch unit, a positive output buffer unit and a negative output buffer unit; the first input end of the comparison latch unit is connected to the first input end of the comparison latch module, and the second input end of the comparison latch unit is connected to the second input end of the comparison latch module, and is used to compare the third signal obtained from the first output end of the coupling amplification module and the fourth signal obtained from the second output end of the coupling amplification module to generate a fifth signal and an inverted signal of the fifth signal; the input end of the positive output buffer unit is connected to the first output end of the comparison latch unit, and is used to buffer the fifth signal and output a positive signal of the comparison result from the output end of the positive output buffer unit; the input end of the negative output buffer unit is connected to the second output end of the comparison latch unit, and is used to buffer the inverted signal of the fifth signal and output a negative signal of the comparison result from the output end of the negative output buffer unit.

[0017] Further, the comparison latch unit includes: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor and a seventeenth NMOS transistor; the gate of the fifteenth NMOS transistor is connected to the first input terminal of the comparison latch unit, and the gate of the seventeenth NMOS transistor is connected to the second input terminal of the comparison latch unit; the source of the fifteenth NMOS transistor and the source of the seventeenth NMOS transistor are connected to the drain of the twelfth NMOS transistor; the source of the twelfth NMOS transistor is grounded; the drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the drain of the seventeenth NMOS transistor is connected to the sixteenth NMOS transistor. The source of the OS transistor; the gate of the fourteenth NMOS transistor, the gate of the third PMOS transistor, the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor and the drain of the sixteenth NMOS transistor are connected to the second output end of the comparison latch unit; the gate of the sixteenth NMOS transistor, the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the drain of the second PMOS transistor and the drain of the fourteenth NMOS transistor are connected to the first output end of the comparison latch unit; the sources of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are connected to the comparison latch voltage; the gates of the second PMOS transistor, the fifth PMOS transistor and the twelfth NMOS transistor are connected to the output control signal.

[0018] Optionally, the positive output buffer unit includes: a first PMOS transistor and a thirteenth NMOS transistor; the gates of the first PMOS transistor and the thirteenth NMOS transistor are connected to the input end of the positive output buffer unit; the drains of the first PMOS transistor and the thirteenth NMOS transistor are connected to the output end of the positive output buffer unit; the source of the first PMOS transistor is connected to the comparison latch voltage, and the source of the thirteenth NMOS transistor is grounded.

[0019] Optionally, the negative output buffer unit includes: a sixth PMOS transistor and an eighteenth NMOS transistor; the gates of the sixth PMOS transistor and the eighteenth NMOS transistor are connected to the input end of the negative output buffer unit; the drains of the sixth PMOS transistor and the eighteenth NMOS transistor are connected to the output end of the negative output buffer unit; the source of the sixth PMOS transistor is connected to the comparison latch voltage, and the source of the eighteenth NMOS transistor is grounded.

[0020] The present invention also provides an MRAM storage system, comprising the above-mentioned MRAM storage unit readout circuit and an MRAM storage array composed of a plurality of MRAM storage units.

[0021] In the circuit provided by the embodiment of the present invention, the bit line charge elimination module can charge the positive electrodes of the bit line capacitors respectively connected to the bit line of the unit to be read and the bit line of the reference unit to the same high level or discharge them to the same low level. At the same time, the coupling charge zeroing unit connected to the negative electrodes of the two bit line capacitors can discharge the negative electrodes of the two bit line capacitors to the same low level. The same high level or low level makes the charge difference on the two bit line capacitors zero, and the mismatch error of the two branches connecting the two bit line capacitors will not affect the charge on the bit line capacitors. The discharge also eliminates the residual charge after the last readout is completed, so that the bit line signal to be read and the reference bit line signal accurately form the first signal and the second signal through the bit line capacitor, and are respectively transmitted to the coupling amplification module for amplification processing to generate the third signal and the fourth signal.

[0022] Moreover, the first output terminal and the second output terminal of the coupling amplifier module are connected to a coupling charge elimination module, and the two output terminals of the coupling amplifier module can be charged to the same high level or discharged to the same low level. Similarly, the same high level or low level makes the charge difference on the two output terminals zero, and the mismatch error of the two branches connecting the two output terminals will not affect the charge on the output terminals. The residual charge after the last readout is also eliminated by discharge, so that the amplified third signal and the fourth signal are accurately transmitted to the comparison latch module to generate and latch an accurate comparison result, and finally improve the accuracy of the readout result of the MRAM storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 A schematic diagram of the structure of a charge elimination circuit module provided by an embodiment of the present invention;

[0025] Figure 2 A structural block diagram of an MRAM storage unit readout circuit provided by an embodiment of the present invention;

[0026] Figure 3 A circuit diagram of a bit line charge elimination module provided by an embodiment of the present invention;

[0027] Figure 4 A circuit diagram of a coupling amplification module provided by an embodiment of the present invention;

[0028] Figure 5 A circuit diagram of a coupling charge elimination module provided by an embodiment of the present invention;

[0029] Figure 6 A circuit diagram of a comparison latch module provided by an embodiment of the present invention;

[0030] Figure 7 for Figure 3 to Figure 6 Circuit diagram of MRAM memory cell readout circuits connected together. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] To make the technical solution of the present invention clearer, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram of a charge elimination circuit module structure provided by an embodiment of the present invention is shown in FIG. Figure 1 The circuit module of the present embodiment shown is used to eliminate the voltage difference between two endpoints, that is, to eliminate the voltage difference between the first end 30 and the second end 40 of the circuit module. The circuit module of the present embodiment includes: a charge zeroing unit 10 and a charge averaging unit 20. The charge zeroing unit 10 is composed of three MOS transistors, and is used to pull the voltage of the first end and the second end to the same low level when the three gates controlled by the discharge signal are turned on; the charge averaging unit 20 is composed of three transmission gates, and is used to raise the voltage of the first end and the second end to the same high level when the transmission gate control signal is enabled.

[0034] In this embodiment, the three MOS transistors constituting the charge zeroing unit 10 may all be NMOS transistors, or all be PMOS transistors, or some may be NMOS transistors and others may be PMOS transistors. To simplify the control signal, the three MOS transistors may be of the same type. Figure 1 In the example, all three MOS transistors are NMOS transistors, and the following embodiments are also described in this way.

[0035] When the three MOS transistors of the charge zeroing unit 10 are all NMOS transistors, the gates of the three NMOS transistors are connected to the same discharge signal DISCH, wherein the drains of the two NMOS transistors are connected to the first end 30 and the second end 40 respectively, the sources are both grounded, and the source and drain of the other NMOS transistor are connected to the first end and the second end respectively. In this embodiment, through the charge zeroing unit, when the discharge signal DISCH is at a high level, the three NMOS transistors are all turned on, so that the voltages of the first end 30 and the second end 40 are pulled to the same low level ground, that is, the voltage difference between the two ends is eliminated. When the transmission gate control signal of the charge averaging unit 20, that is, the enable signals PRE and PRE_P are valid, the three transmission gates are all opened, so that the voltages of the first end 30 and the second end 40 are both pulled up to VDD, and the voltage difference between the two ends is also eliminated. In practical applications, the voltage between the first end and the second end can be maintained by the charge of the capacitor, so eliminating the voltage difference between the two ends means eliminating the charge difference on the capacitors at the two ends. By eliminating the charge difference between the two ends, the memory cell readout circuit can be refreshed to avoid the residual charge after the previous readout affecting the current readout. At the same time, it also avoids the errors caused by the mismatch of the circuits at the two ends, which is beneficial to improve the accuracy of the readout results.

[0036] Figure 2 A structural block diagram of an MRAM storage unit readout circuit provided by an embodiment of the present invention, Figure 3 A circuit diagram of a bit line charge elimination module provided by an embodiment of the present invention; Figure 4 A circuit diagram of a coupling amplification module provided by an embodiment of the present invention; Figure 5 A circuit diagram of a coupling charge elimination module provided by an embodiment of the present invention; Figure 6 A circuit diagram of a comparison latch module provided by an embodiment of the present invention; Figure 7 for Figure 3 to Figure 6 Circuit diagram of MRAM memory cell readout circuit connected together. Figure 2 -, the MRAM storage unit readout circuit includes: a first bit line capacitor 11, a second bit line capacitor 12, a bit line charge elimination module 13, a coupling amplification module 14, a coupling charge elimination module 15, and a comparison latch module 16. The bit line charge elimination module 13 and the coupling charge elimination module 15 can adopt the above Figure 1 The charge elimination circuit structure of the embodiment shown.

[0037] Among them, the first end 131 of the bit line charge elimination module 13 is connected to the to-be-read unit bit line 132 and the positive electrode of the first bit line capacitor 11 to obtain the to-be-read bit line signal VBL from the to-be-read unit bit line 132, and the second end 133 of the bit line charge elimination module 13 is connected to the reference unit bit line 134 and the positive electrode of the second bit line capacitor 12 to obtain the reference bit line signal VB from the reference unit bit line 134.

[0038] The bit line charge elimination module 13 includes a first charge zeroing unit 135 and a first precharged charge averaging unit 136. The first charge zeroing unit 135 is used to discharge the positive electrode of the first bit line capacitor 11 and the positive electrode of the second bit line capacitor 12 to the same low level; the first precharged charge averaging unit 136 is used to charge the positive electrode of the first bit line capacitor 11 and the positive electrode of the second bit line capacitor 12 to the same high level.

[0039] The first input terminal 141 of the coupling amplifier module 14 is connected to the negative electrode of the first bit line capacitor 11, and the second input terminal 142 of the coupling amplifier module 14 is connected to the negative electrode of the second bit line capacitor 12. The coupling amplifier module is used to amplify the difference between the first signal X1 after the to-be-read bit line signal VBL passes through the first bit line capacitor 11 and the second signal X2 after the reference bit line signal VB passes through the second bit line capacitor 12, so as to generate a third signal INBL and a fourth signal INB with a larger difference. The coupling amplifier module 14 includes a coupling charge zeroing unit 143, which is used to discharge the negative electrode of the first bit line capacitor 11 and the negative electrode of the second bit line capacitor 12 to the same low level.

[0040] The first end 151 of the coupling charge elimination module 15 and the first input end 161 of the comparison latch module 16 are connected to the first output end 144 of the coupling amplifier module 14, and the second end 152 of the coupling charge elimination module 15 and the second input end 162 of the comparison latch module 16 are connected to the second output end 145 of the coupling amplifier module 14. The coupling charge elimination module 15 includes a second charge zeroing unit 153 and a second pre-charged charge averaging unit 154, and the second charge zeroing unit 153 is used to discharge the first output end 144 and the second output end 145 of the coupling amplifier module 14 to the same low level; the second pre-charged charge averaging unit 154 is used to charge the first output end 144 and the second output end 145 of the coupling amplifier module 14 to the same high level.

[0041] The comparison latch module 16 is used to compare the third signal INBL obtained from the first output terminal 144 of the coupling amplification module 14 and the fourth signal INB obtained from the second output terminal 145 of the coupling amplification module 14, and generate and latch a comparison result positive signal QB and a comparison result negative signal QBL. The first output terminal 163 of the comparison latch module 16 is used to output the comparison result positive signal QB, and the second output terminal 164 of the comparison latch module 16 is used to output the comparison result negative signal QBL.

[0042] When the above-mentioned MRAM storage unit readout circuit is working, the to-be-read unit bit line 132 and the reference unit bit line 134 that need to be compared pass through the bit line charge elimination module 13 and are connected to the coupling amplifier module 14 through the first bit line capacitor 11 and the second bit line capacitor 12. The bit line charge elimination module 13 includes a first precharge charge averaging unit 136 and a first charge zeroing unit 135. The first precharge charge averaging unit 136 is used to ensure that the two bit lines maintain the same precharge voltage during precharge, and the first charge zeroing unit 135 is used to ensure that the two bit lines can be pulled to the same and sufficiently small voltage during discharge.

[0043] The coupling amplifier module 14 includes a coupling charge zeroing unit to ensure that the charge stored in the device of the coupling amplifier module 14 can be completely discharged to the ground during discharge. The voltage signal (the third signal INBL and the fourth signal INB) amplified by the coupling amplifier module 14 is connected to the comparison latch module 16 after passing through the coupling charge elimination module 15. The coupling charge elimination module 15 is also divided into a second pre-charge charge averaging unit 154 and a second charge zeroing unit 153. The second pre-charge charge averaging unit 154 is used to ensure that the two output nodes of the coupling amplifier module 14 maintain the same pre-charge voltage during pre-charge, and the second charge zeroing unit 153 is used to ensure that the two output nodes of the coupling amplifier module 14 can be pulled to the same and sufficiently small voltage during discharge.

[0044] The comparison latch module 16 is mainly used to receive the two output voltage signals (the third signal INBL and the fourth signal INB) of the coupling amplifier module 14, compare and obtain the result and latch the result. The result is divided into positive and negative (comparison result positive signal QB and comparison result negative signal QBL) output.

[0045] In the MRAM storage unit readout circuit provided by the embodiment of the present invention, the bit line charge elimination module 13 can charge the positive electrodes of the bit line capacitors respectively connected to the to-be-read unit bit line 132 and the reference unit bit line 134 to the same high level or discharge them to the same low level. At the same time, the coupling charge zeroing unit 143 connected to the negative electrodes of the two bit line capacitors can discharge the negative electrodes of the two bit line capacitors to the same low level. The same high level or low level makes the charge difference on the two bit line capacitors zero, and the mismatch error of the two branches connecting the two bit line capacitors will not affect the charge on the bit line capacitors. The discharge also eliminates the residual charge after the last readout is completed, so that the to-be-read bit line signal VBL and the reference bit line signal VB accurately form the first signal X1 and the second signal X2 through the bit line capacitors, and transmit them to the coupling amplification module for amplification processing to generate the third signal INBL and the fourth signal INB.

[0046] Moreover, the first output terminal 144 and the second output terminal 145 of the coupling amplifier module 14 are connected to the coupling charge elimination module 15, and the two output terminals of the coupling amplifier module 14 can be charged to the same high level or discharged to the same low level. Similarly, the same high level or low level makes the charge difference on the two output terminals zero, and the mismatch error of the two branches connecting the two output terminals will not affect the charge on the output terminals. The residual charge after the last readout is also eliminated by discharge, so that the amplified third signal INBL and the fourth signal INB are accurately transmitted to the comparison latch module 16 to generate and latch an accurate comparison result, thereby finally improving the accuracy of the readout result of the MRAM storage unit.

[0047] In the above-mentioned MRAM storage unit readout circuit, the bit line charge elimination module 13 adopts Figure 1 The charge elimination circuit structure shown in FIG. 1 is a bit line charge elimination module 13. Figure 3 As shown, it includes: a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3 constituting a first charge zeroing unit 135, and a first transmission gate T1, a second transmission gate T2 and a third transmission gate T3 constituting a first pre-charge charge averaging unit 136;

[0048] Among them, the drain of the first NMOS transistor N1, the output end of the second transmission gate T2, the drain of the third NMOS transistor N3 and the input end of the first transmission gate T1 are connected to the first end 131 of the bit line charge elimination module 13; the output end of the first transmission gate T1, the output end of the third transmission gate T3, the source of the third NMOS transistor N3 and the drain of the second NMOS transistor N2 are connected to the second end 133 of the bit line charge elimination module 13.

[0049] The sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded GND; the input terminals of the second transmission gate N2 and the third transmission gate T3 are connected to the bit line precharge voltage VBL_RD; the positive control terminals of the first transmission gate T1, the second transmission gate T2, and the third transmission gate T3 are connected to the precharge control signal PRE, and the negative control terminals of the first transmission gate T1, the second transmission gate T2, and the third transmission gate T3 are connected to the inverted signal PRE_P of the precharge control signal; the gates of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected to the charge zeroing signal DISCH.

[0050] When the bit line charge elimination module 13 is working, the to-be-read cell bit line 132 and the reference cell bit line 134 are connected to the cell to be read and the reference cell, respectively. The embodiment of the present application does not limit the connection between the bit line and the MRAM cell by the name of the bit line. If the data stored in the cell connected to the to-be-read cell bit line 132 on the left needs to be read, the reference cell is connected to the reference cell bit line 134 on the right. If the data stored in the cell connected to the reference cell bit line 134 on the right needs to be read, the reference cell is connected to the to-be-read cell bit line 132 on the left.

[0051] The to-be-read cell bit line 132 and the reference cell bit line 134 are also connected to the bit line charge elimination module 13, which is divided into a first precharge charge averaging unit 136 and a first charge zeroing unit 135. The "first" here is to distinguish the charge zeroing unit and the precharge charge averaging unit in the coupling charge elimination module 15 described below.

[0052] In this bit line charge elimination module 13, the first precharge charge averaging unit 136 is composed of three CMOS transmission gates, which are respectively connected to two bit lines, the to-be-read unit bit line 132 and the bit line precharge voltage VBL_RD, the reference unit bit line 134 and the bit line precharge voltage VBL_RD, and are controlled by the precharge control signal PRE and its inverted signal PRE_P. When PRE is at a high level, the module is turned on and the bit line is precharged to a preset voltage value. The first charge zeroing unit 135 is composed of three NMOS transistors, which are respectively connected to two bit lines, the to-be-read unit bit line 132 and the ground GND, the reference unit bit line 134 and the ground GND, and are controlled by the charge zeroing signal DISCH. When DISCH is at a high level, the module is turned on and discharges.

[0053] The to-be-read cell bit line 132 and the reference cell bit line 134 are also connected to one end of two bit line capacitors. The two bit line capacitors are used to store and discharge the charges of the two connected MRAM storage cells while isolating the DC paths of the two bit lines.

[0054] In the above-mentioned MRAM storage unit readout circuit, the coupling amplifier module 14 can be as follows Figure 4 As shown, the coupling zeroing unit 143 includes: a fourth NMOS transistor N4, a fifth NMOS transistor N5 and a sixth NMOS transistor N6; the drain of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6 are connected to the first input terminal 141 of the coupling amplifier module 14; the source of the sixth NMOS transistor N6 and the drain of the fifth NMOS transistor N5 are connected to the second input terminal 142 of the coupling amplifier module 14; the source of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are grounded GND.

[0055] The coupling amplification module 14 can be Figure 4As shown, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a first node capacitor C1 and a second node capacitor C2 are also included.

[0056] The source of the seventh NMOS transistor N7 is connected to the first input terminal 141 of the coupling amplifier module 14, and the source of the eighth NMOS transistor N8 is connected to the second input terminal 142 of the coupling amplifier module 14; the gate of the seventh NMOS transistor N7, the drain of the eighth NMOS transistor N8, the positive electrode of the second node capacitor C2 and the second output terminal 145 of the coupling amplifier module 14 are connected; the gate of the eighth NMOS transistor N8, the drain of the seventh NMOS transistor N7, the positive electrode of the first node capacitor C1 and the first output terminal 144 of the coupling amplifier module 14 are connected. The negative electrodes of the first node capacitor C1 and the second node capacitor C2 are grounded GND.

[0057] When the coupling amplifier module 14 is working, the input end (the first input end 141 and the second input end 142) is connected to the negative electrode of the bit line capacitor, and is also connected to the source end of the cross-coupled transistor 146 (the seventh NMOS transistor N7 and the eighth NMOS transistor N8). The input end is also connected to the coupling charge zeroing unit 143. The unit is composed of three NMOS transistors, which are respectively connected to the two input ends of the coupling amplifier module 14, the first input end 141 and the ground GND, and the second input end and the ground GND. It is controlled by the charge zeroing signal DISCH. When DISCH is at a high level, the unit is turned on and discharged.

[0058] The gates of a pair of cross-coupled NMOS transistors in the coupling amplifier module 14 are respectively connected to the drain terminal of another NMOS transistor, that is, the output terminal (the first output terminal 144 and the second output terminal 145) of the coupling amplifier module 14, and the source terminals are connected to the first input terminal 141 and the second input terminal 142. In order to increase the charge storage capacity of the first output terminal 144 and the second output terminal 145 of the coupling amplifier module 14 and balance the speed of discharging the charge, a node capacitor (a first node capacitor C1 and a second node capacitor C2) is added to the first output terminal 144 and the second output terminal 145, respectively.

[0059] The MRAM storage unit readout circuit and the coupling charge elimination module 15 can also be configured as follows: Figure 1 The charge elimination circuit structure shown in FIG. 1 , the coupled charge elimination module 15 can be specifically as follows Figure 5 As shown, it includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10 and an eleventh NMOS transistor N11 constituting a second charge zeroing unit 153, and a fourth transmission gate T4, a fifth transmission gate T5 and a sixth transmission gate T6 constituting a second pre-charge charge averaging unit 154.

[0060] Among them, the drain of the ninth NMOS transistor N9, the output end of the fifth transmission gate T5, the drain of the eleventh NMOS transistor N11 and the input end of the fourth transmission gate T4 are connected to the first end 151 of the coupling charge elimination module 15; the output end of the fourth transmission gate T4, the output end of the sixth transmission gate T6, the source of the eleventh NMOS transistor N11 and the drain of the tenth NMOS transistor N10 are connected to the second end 152 of the coupling charge elimination module 15.

[0061] The sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 are grounded GND; the input terminals of the fifth transmission gate T5 and the sixth transmission gate T6 are coupled to the pre-charge voltage VDD1; the positive control terminals of the fourth transmission gate T4, the fifth transmission gate T5 and the sixth transmission gate T6 are connected to the pre-charge control signal PRE, and the negative control terminals of the fourth transmission gate T4, the fifth transmission gate T5 and the sixth transmission gate T6 are connected to the inverted signal PRE_P of the pre-charge control signal; the gates of the ninth NMOS transistor N9, the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are connected to the charge zeroing signal DISCH.

[0062] When the coupling charge elimination module 15 is working, the first output terminal 144 and the second output terminal 145 of the coupling amplifier module 14 are connected to the coupling charge elimination module 15, and the module is divided into a second precharge charge averaging unit 154 and a second charge zeroing unit 153. In this module, the second precharge charge averaging unit 154 is composed of three CMOS transmission gates, which are respectively connected to the two output terminals of the coupling amplifier module 14, the first output terminal 144 of the coupling amplifier module 14 and the coupling precharge voltage VDD1, and the second output terminal 145 of the coupling amplifier module 14 and the coupling precharge voltage VDD1, and are controlled by the precharge control signal PRE and its inverted signal PRE_P. When PRE is at a high level, the module is turned on and precharge is performed.

[0063] The second charge zeroing unit 153 is composed of three NMOS transistors, which are respectively connected to the two output ends of the coupling amplifier module 14, the first output end 144 of the coupling amplifier module 14 and the ground GND, and the second output end 145 of the coupling amplifier module 14 and the ground GND. It is controlled by the charge zeroing signal DISCH. When DISCH is at a high level, the module is turned on and discharged.

[0064] In the above-mentioned MRAM storage unit readout circuit, the comparison latch module 16 can be as follows Figure 6As shown, it includes: a comparison latch unit 51, a positive output buffer unit 52 and a negative output buffer unit 53; the first input terminal 511 of the comparison latch unit 51 is connected to the first input terminal 161 of the comparison latch module 16, and the second input terminal 512 of the comparison latch unit 51 is connected to the second input terminal 162 of the comparison latch module 16, which is used to compare the third signal INBL obtained from the first output terminal 144 of the coupling amplifier module 14 and the fourth signal INB obtained from the second output terminal 145 of the coupling amplifier module 14 to generate a fifth signal Q1 and an inverted signal Q2 of the fifth signal.

[0065] The input terminal 521 of the positive output buffer unit 52 is connected to the first output terminal 513 of the comparison latch unit 51 for buffering the fifth signal Q1 and outputting a comparison result positive signal QB from the output terminal of the positive output buffer unit 52 , ie, the first output terminal 163 of the comparison latch module 16 .

[0066] The input terminal 531 of the negative output buffer unit 53 is connected to the second output terminal 514 of the comparison latch unit 51 for buffering the inverted signal Q2 of the fifth signal and outputting the comparison result negative signal QBL from the output terminal of the negative output buffer unit 53 , i.e., the second output terminal 164 of the comparison latch module 16 .

[0067] The comparison latch unit 51 includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a twelfth NMOS transistor N12, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16 and a seventeenth NMOS transistor N17.

[0068] The gate of the fifteenth NMOS transistor N15 is connected to the first input terminal 511 of the comparison latch unit 51, and the gate of the seventeenth NMOS transistor N17 is connected to the second input terminal 512 of the comparison latch unit 51; the source of the fifteenth NMOS transistor N15 and the source of the seventeenth NMOS transistor N17 are connected to the drain of the twelfth NMOS transistor N12; the source of the twelfth NMOS transistor N12 is grounded GND.

[0069] The drain of the fifteenth NMOS transistor N15 is connected to the source of the fourteenth NMOS transistor N14, and the drain of the seventeenth NMOS transistor N17 is connected to the source of the sixteenth NMOS transistor N16; the gate of the fourteenth NMOS transistor N14, the gate of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5 and the drain of the sixteenth NMOS transistor N16 are connected to the second output terminal 514 of the comparison latch unit 51; the gate of the sixteenth NMOS transistor N16, the gate of the fourth PMOS transistor P4, the drain of the third PMOS transistor P3, the drain of the second PMOS transistor P2 and the drain of the fourteenth NMOS transistor N14 are connected to the first output terminal 513 of the comparison latch unit 51.

[0070] The sources of the second PMOS transistor P2 , the third PMOS transistor P3 , the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected to the comparison latch voltage VDD2 ; the gates of the second PMOS transistor P2 , the fifth PMOS transistor P5 and the twelfth NMOS transistor N12 are connected to the output control signal SAEN.

[0071] The above-mentioned positive output buffer unit 52 includes: a first PMOS transistor P1 and a thirteenth NMOS transistor N13; the gates of the first PMOS transistor P1 and the thirteenth NMOS transistor N13 are connected to the input terminal 521 of the positive output buffer unit 52; the drains of the first PMOS transistor P1 and the thirteenth NMOS transistor N13 are connected to the output terminal of the positive output buffer unit 52, that is, the first output terminal 163 of the comparison latch module 16; the source of the first PMOS transistor P1 is connected to the comparison latch voltage VDD2, and the source of the thirteenth NMOS transistor N13 is grounded GND.

[0072] The above-mentioned negative output buffer unit 53 includes: a sixth PMOS transistor P6 and an eighteenth NMOS transistor N18; the gates of the sixth PMOS transistor P6 and the eighteenth NMOS transistor N18 are connected to the input terminal 531 of the negative output buffer unit 53; the drains of the sixth PMOS transistor P6 and the eighteenth NMOS transistor N18 are connected to the output terminal of the negative output buffer unit 53, that is, the second output terminal 164 of the comparison latch module 16; the source of the sixth PMOS transistor P6 is connected to the comparison latch voltage VDD2, and the source of the eighteenth NMOS transistor N18 is grounded GND.

[0073] When the above-mentioned comparison latch module 16 is working, the two output terminals of the coupling amplifier module 14 are connected to the comparison latch module 16, which includes a comparison latch unit 51 and a positive and negative inverter used as an output buffer unit. The main structure of the comparison latch unit 51 is a pair of pseudo-differential tubes and a pair of complementary connected inverters, and is controlled by the output control signal SAEN. When SAEN is high, the comparison latch unit 51 is turned on, and the fifth signal Q1 and its inverted signal Q2 are compared, and the final positive and negative comparison results (QB, QBL) are output through the left and right inverters.

[0074] Based on the above MRAM storage unit readout circuit, the circuit can be operated in discharge-to-zero mode, pre-charge mode, coupling amplification mode and comparison latch mode through circuit timing control. Each operating mode is described in detail below.

[0075] The main working process of the MRAM storage unit readout circuit provided by the embodiment of the present invention is as follows:

[0076] 1. Discharge to zero mode

[0077] The charge zeroing signal DISCH is set to a high level, the pre-charge control signal PRE is set to a low level, the output control signal SAEN is set to a low level, the positive and negative electrodes of the first bit line capacitor 11 and the second bit line capacitor are grounded, and the two output ends (144 and 145) of the coupling amplifier circuit 14 are grounded, and the left and right nodes are connected to ensure that they are all at the same low level to minimize the error between the left and right nodes.

[0078] 2. Precharge Mode

[0079] The charge zeroing signal DISCH is set to a low level, the precharge control signal PRE is set to a high level, the output control signal SAEN is set to a low level, the positive electrodes of the two bit line capacitors are connected to the bit line precharge voltage VBL_RD, the two output terminals of the coupling amplifier module 14 are connected to the coupling precharge voltage VDD1, and the negative electrodes of the two bit line capacitors are not fixed voltages, which are used to store the threshold voltage mismatch of the left and right cross-coupled transistors (N4 and N5). At the same time, the nodes of the left and right paths are connected to minimize the error between the left and right nodes.

[0080] 3. Coupling Amplification Mode

[0081] The charge zeroing signal DISCH is set to a low level, the pre-charge control signal PRE is set to a low level, and the output control signal SAEN is set to a low level. At this time, if the MRAM cell resistance connected to the to-be-read unit bit line 132 is smaller than the MRAM cell resistance connected to the reference unit bit line 134, the charge stored in the first bit line capacitor 11 is discharged faster, the voltage at the negative electrode of the first bit line capacitor 11 drops faster, and the gate-source voltage difference of the seventh NMOS transistor N7 is larger, so the seventh NMOS transistor N7 on the left is turned on first, and the charge stored in the first output terminal 144 of the coupling amplifier module 14 is discharged to the first bit line capacitor 11, thereby causing the voltage of the first output terminal 144 to drop, and finally obtaining the result that the third signal INBL voltage is less than the fourth signal INB voltage.

[0082] If the MRAM cell resistance connected to the to-be-read cell bit line 132 is greater than the MRAM cell resistance connected to the reference cell bit line 134, the charge stored in the second bit line capacitor 12 is discharged faster, the voltage at the negative electrode of the second bit line capacitor drops faster, and the gate-source voltage difference of the eighth NMOS transistor N8 on the right side is larger, so the eighth NMOS transistor N8 on the right side is turned on first, and the charge stored in the second output terminal 145 of the coupling amplifier module 14 is discharged to the second bit line capacitor 12, thereby causing the voltage of the second output terminal 145 to drop, and finally obtaining the result that the fourth signal INB voltage is less than the third signal INBL voltage.

[0083] 4. Comparison latch mode

[0084] The charge zeroing signal DISCH is set to a low level, the pre-charge control signal PRE is set to a low level, the output control signal SAEN is set to a high level, the voltage information stored at the first output terminal 144 and the second output terminal 145 of the coupling amplifier module 14 is input into the comparison latch module 16 and the comparison latch unit 51 is turned on, and the comparison result is output through the inverter.

[0085] When the voltage of the third signal INBL is greater than the voltage of the fourth signal INB, the current on the left side of the pseudo differential pair of the comparison latch unit 51 is greater than the current on the right side, and the voltage drops faster. The output end of the left inverter used for latching (i.e., the first output end 513 of the comparison latch unit 51) compares and latches the result to a low level, and outputs a high-level comparison result positive signal QB through the positive output buffer unit 52. At this time, the comparison result negative signal QBL is a low level.

[0086] When the voltage of the third signal INBL is less than the voltage of the fourth signal INB, the current on the left side of the pseudo differential pair of the comparison latch unit 51 is less than the current on the right side, and the voltage drops more slowly. The output end of the left inverter for latching (i.e., the first output end 513 of the comparison latch unit 51) compares and latches the result to a high level, and outputs a low-level comparison result positive signal QB through the positive output buffer unit 52. At this time, the comparison result negative signal QBL is a high level.

[0087] According to the above working process, the comparison result positive signal QB is a high level, which means that the MRAM cell resistance connected to the left side to-be-read cell bit line 132 is greater than the MRAM cell resistance connected to the right side reference cell bit line 134. The comparison result positive signal QB is a low level, which means that the MRAM cell resistance connected to the left side to-be-read cell bit line 132 is less than the MRAM cell resistance connected to the right side reference cell bit line 134.

[0088] It should be noted that the coupling pre-charge voltage VDD1 and the comparison latch voltage VDD2 can be the same voltage to reduce circuit complexity and thus save costs.

[0089] The settings of the control signals in each working process of the above-mentioned MRAM storage unit readout circuit are shown in the following table.

[0090]

[0091] Among them, '0' represents a low level and '1' represents a high level.

[0092] The embodiment of the present invention also provides an MRAM storage system, including the MRAM storage unit readout circuit in the above embodiment and an MRAM storage array composed of multiple MRAM storage units. In the large-scale reading process of the MRAM storage array, the above-mentioned one readout circuit can be connected to multiple MRAM storage units for reading, that is, the readout circuits of multiple storage units can be refreshed at one time through one readout circuit. In the actual reading process, since the refresh charge elimination can be performed each time the readout is performed, even if the resistance value of the high-resistance state of the magnetic tunnel junction changes greatly with the temperature, it will not affect the yield of the reading. That is, the MRAM storage system in the embodiment of the present invention can effectively eliminate the charge error between the left and right branches caused by voltage fluctuations and device mismatch during charge zeroing and voltage precharging, thereby improving the yield of the readout circuit, and can withstand the mismatch caused by process angle changes and temperature fluctuations; it can also effectively eliminate the charges of different sizes remaining in the node capacitance and bit line capacitance in the circuit in the previous reading operation, thereby improving the accuracy of continuous reading at various process angles and temperatures.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charge elimination circuit module, used to eliminate the voltage difference between a first end and a second end of a circuit module, characterized in that: include: Charge zeroing unit and charge averaging unit, The charge zeroing unit is composed of three MOS transistors, and is used to pull the voltage of the first end and the second end to the same low level when the three gates controlled by the discharge signal are turned on; The charge averaging unit is composed of three transmission gates, which are used to raise the voltage of the first end and the second end to the same high level when the transmission gate control signal is enabled; the positive control ends of the three transmission gates are connected to the control signal, and the negative control ends are connected to the inverted signal of the control signal, wherein the input ends of two transmission gates are connected to the high level, and the output ends are correspondingly connected to the first end and the second end, and the input end and the output end of another transmission gate are correspondingly connected to the first end and the second end; The three MOS transistors are all NMOS transistors, and the gates of the three NMOS transistors are connected to the same discharge signal. The drains of two NMOS transistors are correspondingly connected to the first end and the second end, and the sources are grounded. The source and drain of the other NMOS transistor are correspondingly connected to the first end and the second end.

2. An MRAM storage cell readout circuit, characterized in that: include: A first bit line capacitor, a second bit line capacitor, a bit line charge elimination module, a coupling amplification module, a coupling charge elimination module, and a comparison latch module; The bit line charge elimination module and the coupling charge elimination module both include the charge elimination circuit module as claimed in claim 1; The first end of the bit line charge elimination module is connected to the to-be-read unit bit line and the positive electrode of the first bit line capacitor to obtain the to-be-read bit line signal from the to-be-read unit bit line, and the second end of the bit line charge elimination module is connected to the reference unit bit line and the positive electrode of the second bit line capacitor to obtain the reference bit line signal from the reference unit bit line; the bit line charge elimination module includes a first charge zeroing unit and a first precharge charge averaging unit, the first charge zeroing unit is used to discharge the positive electrode of the first bit line capacitor and the positive electrode of the second bit line capacitor to the same low level; the first precharge charge averaging unit is used to charge the positive electrode of the first bit line capacitor and the positive electrode of the second bit line capacitor to the same high level; The first input end of the coupling amplification module is connected to the negative electrode of the first bit line capacitor, and the second input end of the coupling amplification module is connected to the negative electrode of the second bit line capacitor. The coupling amplification module is used to amplify the difference between a first signal after the to-be-read bit line signal passes through the first bit line capacitor and a second signal after the reference bit line signal passes through the second bit line capacitor, so as to generate a third signal and a fourth signal; The first end of the coupling charge elimination module and the first input end of the comparison latch module are connected to the first output end of the coupling amplification module, the second end of the coupling charge elimination module and the second input end of the comparison latch module are connected to the second output end of the coupling amplification module, the coupling charge elimination module includes a second charge zeroing unit and a second pre-charge charge averaging unit, the second charge zeroing unit is used to discharge the first output end and the second output end of the coupling amplification module to the same low level; the second pre-charge charge averaging unit is used to charge the first output end and the second output end of the coupling amplification module to the same high level; The comparison latch module is used to generate and latch a comparison result positive signal and a comparison result negative signal after comparing the third signal obtained from the first output end of the coupling amplification module and the fourth signal obtained from the second output end of the coupling amplification module. The first output end of the comparison latch module is used to output the comparison result positive signal, and the second output end of the comparison latch module is used to output the comparison result negative signal.

3. The MRAM memory cell readout circuit according to claim 2, characterized in that: The bit line charge elimination module comprises: a first NMOS transistor, a second NMOS transistor and a third NMOS transistor constituting the first charge zeroing unit, and a first transmission gate, a second transmission gate and a third transmission gate constituting the first pre-charge charge averaging unit; The drain of the first NMOS transistor, the output of the second transmission gate, the drain of the third NMOS transistor and the input of the first transmission gate are connected to the first end of the bit line charge elimination module; the output of the first transmission gate, the output of the third transmission gate, the source of the third NMOS transistor and the drain of the second NMOS transistor are connected to the second end of the bit line charge elimination module; The sources of the first NMOS transistor and the second NMOS transistor are grounded; the input terminals of the second transmission gate and the third transmission gate are connected to the bit line precharge voltage; The positive control terminals of the first transmission gate, the second transmission gate, and the third transmission gate are connected to a pre-charge control signal, and the negative control terminals of the first transmission gate, the second transmission gate, and the third transmission gate are connected to an inverted signal of the pre-charge control signal; the gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected to a charge zeroing signal.

4. The MRAM storage cell readout circuit according to claim 2 or 3, characterized in that: The coupling amplification module includes a coupling charge zeroing unit, which is used to discharge the negative electrode of the first bit line capacitor and the negative electrode of the second bit line capacitor to the same low level.

5. The MRAM memory cell readout circuit according to claim 4, characterized in that: The coupled charge zeroing unit includes: a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; the drain of the fourth NMOS transistor and the drain of the sixth NMOS transistor are connected to the first input end of the coupled amplification module; the source of the sixth NMOS transistor and the drain of the fifth NMOS transistor are connected to the second input end of the coupled amplification module; the source of the fourth NMOS transistor and the fifth NMOS transistor are grounded.

6. The MRAM memory cell readout circuit according to claim 4, characterized in that: The coupling amplification module further includes a seventh NMOS transistor, an eighth NMOS transistor, a first node capacitor and a second node capacitor; The source of the seventh NMOS transistor is connected to the first input terminal of the coupling amplification module, and the source of the eighth NMOS transistor is connected to the second input terminal of the coupling amplification module; the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor, the positive electrode of the second node capacitor and the second output terminal of the coupling amplification module are connected; the gate of the eighth NMOS transistor, the drain of the seventh NMOS transistor, the positive electrode of the first node capacitor and the first output terminal of the coupling amplification module are connected; Negative electrodes of the first node capacitor and the second node capacitor are grounded.

7. The MRAM memory cell readout circuit according to claim 2, characterized in that: The coupling charge elimination module includes: a ninth NMOS transistor, a tenth NMOS transistor and an eleventh NMOS transistor constituting the second charge zeroing unit, and a fourth transmission gate, a fifth transmission gate and a sixth transmission gate constituting the second pre-charge averaging unit; The drain of the ninth NMOS transistor, the output end of the fifth transmission gate, the drain of the eleventh NMOS transistor and the input end of the fourth transmission gate are connected to the first end of the coupling charge elimination module; the output end of the fourth transmission gate, the output end of the sixth transmission gate, the source of the eleventh NMOS transistor and the drain of the tenth NMOS transistor are connected to the second end of the coupling charge elimination module; The sources of the ninth NMOS transistor and the tenth NMOS transistor are grounded; the input terminals of the fifth transmission gate and the sixth transmission gate are coupled to a precharge voltage; The positive control terminals of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected to the pre-charge control signal, and the negative control terminals of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected to the inverted signal of the pre-charge control signal; the gates of the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor are connected to the charge zeroing signal.

8. The MRAM memory cell readout circuit according to claim 2, characterized in that: The comparison latch module comprises: A comparison latch unit, a positive output buffer unit and a negative output buffer unit; the first input end of the comparison latch unit is connected to the first input end of the comparison latch module, and the second input end of the comparison latch unit is connected to the second input end of the comparison latch module, and is used to compare the third signal obtained from the first output end of the coupling amplification module and the fourth signal obtained from the second output end of the coupling amplification module to generate a fifth signal and an inverted signal of the fifth signal; The input end of the positive output buffer unit is connected to the first output end of the comparison latch unit, and is used to buffer the fifth signal and then output a comparison result positive signal from the output end of the positive output buffer unit; The input end of the negative output buffer unit is connected to the second output end of the comparison latch unit, and is used to buffer the inverted signal of the fifth signal and then output a negative signal of the comparison result from the output end of the negative output buffer unit.

9. The MRAM memory cell readout circuit according to claim 8, characterized in that: The comparison latch unit includes: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor and a seventeenth NMOS transistor; The gate of the fifteenth NMOS transistor is connected to the first input terminal of the comparison latch unit, and the gate of the seventeenth NMOS transistor is connected to the second input terminal of the comparison latch unit; the source of the fifteenth NMOS transistor and the source of the seventeenth NMOS transistor are connected to the drain of the twelfth NMOS transistor; the source of the twelfth NMOS transistor is grounded; The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the drain of the seventeenth NMOS transistor is connected to the source of the sixteenth NMOS transistor; the gate of the fourteenth NMOS transistor, the gate of the third PMOS transistor, the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor and the drain of the sixteenth NMOS transistor are connected to the second output terminal of the comparison latch unit; the gate of the sixteenth NMOS transistor, the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the drain of the second PMOS transistor and the drain of the fourteenth NMOS transistor are connected to the first output terminal of the comparison latch unit; The sources of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are connected to the comparison latch voltage; the gates of the second PMOS transistor, the fifth PMOS transistor and the twelfth NMOS transistor are connected to the output control signal.

10. The MRAM memory cell readout circuit according to claim 8, characterized in that: The positive output buffer unit comprises: a first PMOS transistor and a thirteenth NMOS transistor; The gates of the first PMOS transistor and the thirteenth NMOS transistor are connected to the input end of the positive output buffer unit; the drains of the first PMOS transistor and the thirteenth NMOS transistor are connected to the output end of the positive output buffer unit; the source of the first PMOS transistor is connected to the comparison latch voltage, and the source of the thirteenth NMOS transistor is grounded.

11. The MRAM memory cell readout circuit according to claim 8, characterized in that: The negative output buffer unit comprises: a sixth PMOS transistor and an eighteenth NMOS transistor; The gates of the sixth PMOS transistor and the eighteenth NMOS transistor are connected to the input end of the negative output buffer unit; the drains of the sixth PMOS transistor and the eighteenth NMOS transistor are connected to the output end of the negative output buffer unit; the source of the sixth PMOS transistor is connected to the comparison latch voltage, and the source of the eighteenth NMOS transistor is grounded.

12. An MRAM storage system, characterized in that: An MRAM storage array comprising an MRAM storage cell readout circuit as claimed in any one of claims 2 to 11 and a plurality of MRAM storage cells.

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