Data integrity check based on voltage profile metrics

Abstract

This application relates to data integrity checks based on voltage distribution metrics. Systems and methods including a memory device and a processing device operatively coupled to the memory device are disclosed. The processing device is capable of performing operations including: determining a value of a data state metric of a memory page; determining a value of a voltage distribution metric associated with the page in response to the data state metric satisfying a first threshold criterion; and performing media management operations relative to a block associated with the page in response to the voltage distribution metric value satisfying a second threshold criterion.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to data integrity checks based on voltage distribution metrics. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to one aspect of this application, a system is provided. The system includes: a memory device; and a processing device operatively coupled to the memory device to perform operations including: determining a value of a data state metric of a memory page; determining a value of a voltage distribution metric associated with the page in response to the data state metric value satisfying a first threshold criterion; and performing media management operations relative to a block associated with the page in response to the voltage distribution metric value satisfying a second threshold criterion.

[0004] According to another aspect of this application, a method is provided. The method includes: determining a value of a data state metric of a memory page; determining a plurality of voltage distribution metrics associated with the page in response to the data state metric satisfying a first threshold criterion; applying a second voltage distribution metric to a third threshold criterion in response to the determination that a first voltage distribution metric value of the plurality of voltage distribution metrics fails to satisfy a second threshold criterion; and performing media management operations relative to a block associated with the page in response to the second voltage distribution metric value satisfying the third threshold criterion.

[0005] According to another aspect of this application, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing means operatively coupled to a memory, perform operations including: determining a value of a data state metric of a memory page associated with a block; determining a value of a voltage distribution metric associated with the page in response to the data state metric satisfying a first threshold criterion; and performing media management operations relative to the block associated with the page in response to the voltage distribution metric value satisfying a second threshold criterion. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This illustration schematically depicts data degradation caused by slow charge loss exhibited by a three-level memory cell according to some embodiments of the present disclosure.

[0009] Figure 3 The diagram illustrates an example of programming distribution valley degradation according to some embodiments of this disclosure.

[0010] Figure 4 The illustration illustrates the determination of the programming distribution valley line metric according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart of an example method for performing data integrity checks based on a programmed distribution valley line metric, according to some embodiments of this disclosure.

[0012] Figure 6 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] Various aspects of this disclosure relate to data integrity checks based on voltage distribution metrics. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die comprising one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane comprises a set of physical blocks. Each block comprises a set of pages. A “block” will be referred to herein as a set of contiguous or non-contiguous memory pages. An example of a “block” is an “erasable block,” which is the smallest erasable unit of memory, while a “page” is the smallest writable unit of memory. Each page comprises a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values. For example, a single-level cell (SLC) can store only one bit per memory element, while a multi-level cell (MLC) is a memory element that can store more than a single bit of information.

[0015] The memory cell can be programmed (written) by applying a voltage to it, which causes the charge to be retained by the memory cell, thereby determining the voltage signal V. CG The voltage signal V CG A control electrode must be applied to the cell to open it to inter-cell current between the source and drain electrodes. More specifically, for each individual memory cell (with the charge Q stored therein), a threshold control gate voltage V may exist. T (also referred to in this paper as the "threshold voltage" or simply the "threshold"), so that for V CG <V T The source-drain current is low. Once the control gate voltage exceeds the threshold voltage, V CG >V T The current generally increases. Because the actual geometry of the electrodes and gate varies between memory cells, the threshold voltage V... T Even cells implemented on the same die can be different. Therefore, a memory cell can be characterized as a distribution of threshold voltage P, P(Q,V). T )=dW / dV T Where dW represents the threshold voltage of any given cell in the interval [V] when charge Q is placed on the memory cell. T V T +dV T The probability within ] .

[0016] Memory devices may have a narrower distribution P(Q,V) compared to the operating range of the control voltages allowed by the cells of the device. T Therefore, multiple non-overlapping distributions P(Q) k V T (The "valley line" or "programmed distribution valley line") can be placed within the working range, thereby allowing the storage and reliable detection of multiple values ​​Q of the charge. k k = 1, 2, 3… The term “valley” can refer to the shape of a graph generated by multiple non-overlapping distributions, which can be represented as a function that is monotonically decreasing when its independent variable is below the global minimum and monotonically increasing when its independent variable is above the global minimum, and the graph depicting said function is symmetrical about the vertical axis of the independent variable whose horizontal axis is equal to the global minimum. The distributions (valleys) are interspersed with voltage intervals (valley tolerances), in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, such valley tolerances can be used to separate various charge states Q. k - The corresponding threshold voltage V of the unit can be detected during the read operation. TThe logic state of a cell is determined by which two valley tolerances it exists between. This effectively allows a single memory cell to store multiple bits of information: a memory cell with 2N-1 well-defined valley tolerances and 2N valley operations can reliably store N bits of information. Specifically, this can be achieved by comparing the measured threshold voltage V exhibited by the memory cell. T Read operations are performed with one or more reference voltage levels (read levels) corresponding to a known valley tolerance (e.g., the center of the tolerance) of the memory device.

[0017] A higher number of possible states reduces the amount of tolerance required to separate those states (e.g., valley tolerance). The memory device may include a three-level-cell (TLC) memory. In a TLC memory, each memory cell stores three information bits with eight total voltage states. The memory device may include a four-level-cell (QLC) memory. In a QLC memory, each memory cell may store four information bits with sixteen voltage states. For example, in a QLC memory, a memory cell may store four data bits (e.g., 1111, 0000, 1101, etc.) corresponding to data received from a host system using sixteen voltage states. It can be noted that the operations described herein can be applied to any multi-bit memory cell.

[0018] Furthermore, each bit of a memory cell is stored in a different part of the memory cell (hereinafter also referred to as a "logical page"). Various read level thresholds are available for various logical page types (hereinafter also referred to as "page types"): SLC page type is the lower logical page (LP), MLC page type is LP and upper logical page (UP), TLC page type is LP, UP, and extra logical page (XP), and QLC page type is LP, UP, XP, and top logical page (TP). For example, a QLC memory cell may have a total of four logical pages, including a lower logical page (LP), an upper logical page (UP), an extra logical page (XP), and a top logical page (TP), where each logical page stores one data bit. For example, a bit may be represented by each of the four logical pages of the memory cell. In a memory cell used for QLC memory, each combination of the four bits may correspond to a different voltage level (hereinafter also referred to as a "level"). For example, the first level of the memory cell may correspond to 1111, the second level may correspond to 0111, and so on. Because a QLC memory cell consists of 4 data bits, there are a total of 16 possible combinations of four data bits. Therefore, a QLC memory cell can be programmed into one of 16 different levels.

[0019] When data is written to a memory cell in the memory subsystem for storage, the memory cell can degrade. Therefore, each memory cell in the memory subsystem can have a finite number of write operations performed on the memory cell before it can no longer reliably store data. Furthermore, data stored in the memory cell can be read from the memory device and transferred to the host system. During a read operation, a read reference voltage is applied to the word line containing the data to be read, while a pass voltage is applied to the word line of the unread memory cell. The pass voltage is a read reference voltage higher than any of the stored threshold voltages. However, when data is read from a memory cell in the memory subsystem, adjacent or neighboring word lines can experience degradation via, for example, read interference, slow charge loss, etc. Read interference is a phenomenon in NAND memory where reading data from a memory cell can cause the threshold voltage of unread memory cells in the same block to shift to a different value. Slow charge loss is a phenomenon where the threshold voltage of a memory cell changes over time as the charge of the memory cell is degrading; this is called "time voltage shift" (due to the degradation charge causing the programming distribution to shift along the voltage axis towards a lower voltage level). The threshold voltage changes rapidly at first (immediately after the memory cell is programmed), and then slows down approximately logarithmically with respect to the time elapsed since the cell programming event. Therefore, failure to mitigate the time-voltage shift caused by slow charge loss can lead to an increased bit error rate in read operations.

[0020] The memory subsystem may perform data integrity checks (also referred to herein as “scans” or “scan operations”) to verify that data stored at a block can be reliably read. In an example, the memory subsystem controller may select a block and perform data integrity checks on some to all pages of the block. During the data integrity check, information about the error rate associated with the data is measurable and collected, and values ​​for data state metrics are determined for the data stored at the block. As used herein, “data state metric” refers to a quantity measured or inferred from the state of data stored on the memory device. Specifically, a data state metric may reflect the state of time-voltage shifts, the degree of read interference, and / or other measurable features of the data state. Composite data state metrics are functions of a set of component state metrics (e.g., weighted sums). One example of a data state metric is the Bit Error Count (BEC). Another example of a data state metric is the Residual Bit Error Rate (RBER). RBER corresponds to the number of bit errors experienced per unit time by the data stored at the data block (e.g., BEC / total bit reads).

[0021] If a data state metric exceeds a threshold criterion (e.g., BEC or RBER is above a threshold), indicating a high error rate associated with data stored at an expired block, then the block can be "refreshed" by performing a media management operation (e.g., a folding operation) to relocate the data stored at a word line or the entire block to a new block in the memory subsystem. Folding data stored at a word line or block to another block may involve writing the data stored at the word line or said block to another block to refresh the data stored by the memory subsystem.

[0022] However, determining block data integrity based on a single data state metric (e.g., RBER or BEC) is not always an accurate indicator of a block's "health." This can lead to over- or under-flushing of blocks by the memory subsystem. Over-flushing blocks can increase program / erase cycles (PECs), resulting in greater use of memory subsystem resources and consequently, reduced memory subsystem controller performance due to fewer resources available for other read or write operations. Under-flushing blocks, due to higher error rates, can cause reliability issues, leading to defective and corrupted data.

[0023] The present disclosure addresses the above and other deficiencies by implementing a memory subsystem controller capable of performing data integrity checks based on programmed distribution valley metrics. In an illustrative example, the memory subsystem controller may initiate a data integrity check of a block and select pages associated with the block for scanning. The scan may estimate selected data state metrics (e.g., error counts) associated with the data stored at the page. If the value of a data state metric (e.g., BEC value, RBER value, etc.) obtained during the scan is below a threshold, the memory subsystem controller may perform a read operation on the page to obtain data that can be used to generate an error count distribution. The memory subsystem controller may then determine one or more programmed distribution valley metrics (e.g., valley metrics) based on the error count distribution generated by the read operation. In embodiments, valley metrics include valley tolerance, valley bottom, and valley center. If one or more valley metrics exceed a refresh threshold criterion, the memory subsystem controller may perform media management operations on the block, such as a folding operation. For example, the memory subsystem controller may perform a folding operation if at least one of the following conditions is met: the collapse of the valley width meets a threshold criterion, the shift in the valley center meets a threshold criterion, and / or the rise in the valley bottom meets a threshold criterion.

[0024] The advantages of this disclosure include, but are not limited to, improved memory subsystem performance by reducing or eliminating over-refreshing or under-refreshing blocks by the memory subsystem controller. The reduced number of unnecessary refresh operations also reduces the amount of resources the memory subsystem devotes to data integrity scanning. This can lead to improved memory subsystem performance and reduced power consumption. Furthermore, reliability issues attributable to higher error rates are reduced. Although embodiments are described using memory cells of NAND flash memory, aspects of this disclosure are applicable to other types of memory subsystems.

[0025] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or such computing device including memory and processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without the intervention of the components), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays for bit storage based on changes in volume resistance. Furthermore, crosspoint non-volatile memory allows for in-place write operations, unlike many flash-based memories, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0037] In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device including a raw memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] In one embodiment, memory subsystem 110 includes media manager component 113, which can be used to implement block scan operation strategies according to embodiments of the present disclosure. In some embodiments, memory subsystem controller 115 includes at least a portion of media manager component 113. In some embodiments, media manager component 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of media manager component 113 and is configured to perform the functionality described herein. Media manager component 113 can communicate directly with memory devices 130 and 140 via a synchronization interface. Furthermore, data transfer between memory devices 130 and 140 can be completed within memory subsystem 110 without accessing host system 120. Media manager component 113 can determine metrics associated with programming distribution valleys, as described in more detail below.

[0043] Figure 2 This describes a time-voltage shift caused, at least in part, by the slow charge loss exhibited by the three-level memory cells, according to embodiments of the present disclosure. Although Figure 2 The illustrative example utilizes a three-level cell, but the same observations can be made, and therefore the same remedy can be applied to a single-level cell and any memory cell with multiple levels.

[0044] A memory cell can be programmed (written into) by applying a voltage (e.g., a programming voltage) to it, thereby generating the charge stored in the memory cell. Precise control over the amount of charge stored in a memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. (With 2...) n A memory cell operating at different threshold voltage levels can store n bits of information.

[0045] Each illustration in Figures 210 and 230 shows a programming distribution 220A to 220N (also referred to herein as a “voltage distribution” or “distribution” or “programming distribution valley” or “valley”) of a memory cell programmed to encode the corresponding logic level (“000” to “111” in the case of TLC) by a corresponding write level (which may be assumed to be located at the midpoint of the programming distribution). Programming distributions 220A to 220N illustrate the range of threshold voltages (e.g., a normal distribution of threshold voltages) used for programming memory cells at corresponding write levels (e.g., programming voltages). As shown, a three-level memory cell may have seven programming distribution valleys (e.g., valley 1 (220A), valley 2 (220B)... valley 7 (220N)). To distinguish adjacent distributions (corresponding to two different logic levels), a read threshold voltage level (shown by a vertical dashed line) is defined such that any measured voltage below the read threshold level is associated with one of a pair of adjacent programming distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other of a pair of adjacent distributions.

[0046] In Figure 210, eight states of the memory cell are shown below the corresponding programming distribution (except for the state marked ER, which is the erased state and its distribution is not shown). Each state corresponds to a logic level. Threshold voltage levels are marked Va to Vh. As shown, any measured voltage below Va is associated with the ER state. States marked P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 220A to 220N, respectively.

[0047] The time after programming (TAP) will refer herein to the time since a cell was written and is the primary driver of time-to-time voltage shift (TVS). TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., based on the controller clock). Cells, blocks, pages, block families, etc., are new (or relatively new) if they have a (relatively) small TAP, and old (or relatively old) if they have a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be performed (e.g., reference calibration 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes). In various embodiments of this disclosure, metrics associated with each of the programming distribution valleys can be measured and used to determine whether a block is refreshed by performing a media management operation (e.g., a folding operation).

[0048] As can be seen from the comparison of example graphs 210 and 230, which respectively reflect the time after programming (TAP) 0 (immediately following programming) and T hours TAP (where T is the number of hours), the programming distribution changes over time primarily due to slow charge loss. To reduce the read bit error rate, the corresponding read threshold voltage is adjusted to compensate for the shift in the programming distribution, as shown by the vertical dashed line. In various embodiments of this disclosure, the time voltage shift is selectively tracked for the die group based on measurements taken at one or more representative dies of the die group. Based on measurements characterizing the time voltage shift and operating temperature of the dies in the die group, taken at representative dies of the die group, the read threshold voltage offset for reading the memory cells of the dies in the die group is updated and applied to the base read threshold level for read operations.

[0049] Figure 3 Graph 300 illustrates an example curve depicting the type of programming distribution valley degradation. (As shown in the image...) Figure 3 To illustrate, valley line 310 shows the instance programming distribution of recently programmed data (e.g., TAP = 0). The x-axis represents the voltage offset from the ideal read position (or level) in 10 mV steps, and the y-axis represents the RBER of a 2kb page (used as an example), where the y-axis ranges from 0 bit errors to 100 bit errors.

[0050] In the first instance of data degradation, as shown at 350, valley 310 undergoes an increase in the valley bottom and a decrease in the valley tolerance, resulting in the distribution shown by valley 320. This valley tolerance can refer to the relative width or relative tolerance between adjacent programming distribution pairs. For example, a valley tolerance associated with a specific logical page type can indicate the relative width between programming distribution pairs associated with that specific logical page type. The valley bottom indicates the distance of the valley center from the x-axis (e.g., RBER or BEC = 0). As shown, the valley bottom increases from 10 bits of RBER to approximately 32 bits. In the second instance of data degradation, as shown at 360, valley 310 undergoes a shift of two steps (e.g., 20 mV) from the center of the ideal read position (hereinafter “valley center”), resulting in the distribution shown by valley 330. The shift in the valley center (hereinafter “valley shift”) can increase the bit error rate. In the third instance of data degradation, as shown at 370, valley line 310 experiences a collapse of the valley line tolerance, while the valley line bottom and valley line center do not change, resulting in the distribution shown by valley line 340.

[0051] In various embodiments of this disclosure, the media manager component 113 may determine the programming distribution valley metrics (e.g., valley tolerance, valley floor, and valley shift) of pages in each block of the memory subsystem 110. It should be noted that valley lines 1 and 7 may be more susceptible to degradation than valley lines 2 through 6. For example, valley line 1 (210A) may have a higher crash rate than valley lines 2 through 7 because valley line 1 has less charge than valley lines 2 through 7, and is therefore more susceptible to read and programming interference. Valley line 7 (210N) may experience a larger voltage shift than valley lines 1 through 6 because valley line 7 has more charge than valley lines 2 through 7, and is therefore more susceptible to data retention and charge loss. Therefore, in some embodiments, the media manager component 113 may scan only valley lines 1 and / or valley lines 7 or the page types associated with valley lines 1 and / or valley lines 7 (e.g., valley line 1 may be associated with LP pages, and valley line 7 may be associated with XP pages).

[0052] Figure 4 This illustration provides a more detailed explanation of determining the programming distribution valley metric (also known as the voltage distribution metric). Specifically, Figure 4 Example graphs 410 and 420 illustrate programming distribution valleys 430A to B, which correlate the error count of a memory page (shown along the y-axis) with the read location (level) used in memory operations on the memory cell group of memory subsystem 110 (shown along the x-axis). Programming distribution valleys 430A to B (e.g., valleys) may be based on error count data corresponding to multiple read operations on the memory cell group. For example, pages may be selected and sampled, and the error count may be determined using read levels corresponding to the programming distribution level of the memory page. The media manager component 113 may generate programming distribution valleys 430A to B after multiple read memory operations. Programming distribution valleys 430A to B may be based on page type (e.g., LP, UP, and / or XP for TLC type memory cells), word line group (WLG), valley level (e.g., valley 1 to valley 7 for TLC type memory cells), or any combination thereof.

[0053] In some embodiments, the media manager component 113 uses a vectorized read level calibration (vRLC) procedure to determine the valley tolerance, valley floor, and valley shift of the programmed distribution valleys. For example, the media manager component 113 may first sample the read set to determine a center result 440 based on an error count of data read using read level 432A corresponding to a specific page type for an individual memory page, a left result 442 based on an error count using left offset 434A, and a right result 444 based on an error count using right offset 436A. For example, the left result 442 is sampled at a threshold voltage offset by a predetermined voltage amount from read level 432A in the negative voltage direction. The right result 444 is sampled at a threshold voltage offset by a predetermined voltage amount from read level 432A of center result 440 in the positive voltage direction, as illustrated by right offset 436A. Left offset 434A and right offset 436A may have predetermined values ​​measured on a scale. The scale can be adjusted for the minimum threshold voltage of the memory subsystem 110 (e.g., 10mV, 20mV, etc.). In some embodiments, the left offset of 434A is equal to the right offset of 436A, making the offset symmetrical. In other embodiments, the first and second offset values ​​may be different (e.g., the offsets are asymmetrical).

[0054] Media manager component 113 may then generate a left vector (vector A) from center result 440 and left result 442, and a right vector (vector B) from center result 440 and right result 444. The vectors can provide a state indicating whether calibration is required after exiting 432A. In some embodiments, the first component of each of vectors A and B (referred to herein as "Ay" and "By", respectively) is based on valley characteristics (e.g., width, depth, slope, symmetry, etc.) of the error distribution associated with the valley, and the second component of each of vectors A and B (referred herein as "Ax" and "Bx", respectively) is based on a sample offset. For example, media manager component 113 may calculate the Ax component of vector A based on the difference between the x-coordinate of center result 440 and the left result, and the Ay component of vector A based on the value of the left offset 434A. Similarly, media manager component 113 may calculate the Bx component of vector B based on the difference between the value of center result 440 and the value of right result 444, and the By component of vector B based on the value of the right offset 436A. Therefore, equation A can be used to... m =(Ax 2 +Ay 2 ) 1 / 2 Determine the magnitude of vector A, and this can be achieved through equation B. m =(Bx 2 +By 2 ) 1 / 2 Determine the value of vector B.

[0055] Media manager component 113 can determine whether the current read level of the valley line is optimized (e.g., in a calibrated state) based on a comparison of vector A and vector B. For example, if vectors A and B satisfy a predetermined relationship, then media manager component 113 can determine that the current read level is at an optimal threshold level (e.g., at the center of the valley line). In some embodiments, the predetermined relationship may be that the magnitudes of vectors A and B are equal within a predetermined limit. In some embodiments, the current read level is optimized when the phase angles of vectors A and B must satisfy a threshold criterion (e.g., a predetermined relationship). For example, the predetermined relationship may be that the phase angles of vectors A and B relative to the central axis are equal and opposite within a predetermined limit, as seen in graph 420.

[0056] If vectors A and B fail to satisfy a predetermined relationship with each other (e.g., not in a calibrated state), then media manager component 113 may calibrate the read level. In an embodiment, the media manager component may estimate a read level fine-tuning or offset (hereinafter “estimated offset”) to be applied to the read level to produce an updated read level. The estimated offset provides the magnitude and direction for shifting the read level from its current voltage value to an updated read level value that minimizes the error count of read operations on a set of memory cells corresponding to an error distribution. To calculate the estimated offset, media manager component 113 may receive and use information associated with vectors A and B, including component information. For example, media manager component 113 may compare the magnitudes of vectors A and B and / or the phase angles of vectors A and B (and / or their components) and estimate the offset (magnitude and direction) by which the read level should be shifted. In another embodiment, media manager component 113 may shift the read level by a predetermined voltage offset. Once a new read level is determined (e.g., a new center result 450), the media manager component 113 can determine a new left result 452 and a new right result 454. The media manager component 113 can then determine new vectors A and B based on the new center result 450, the new left result 452, the new right result 454, and the right offset 436B, and determine whether the new vectors A and B satisfy a predetermined relationship. The media manager component 113 can continue this calibration procedure until the vectors satisfy a predetermined relationship.

[0057] Once calibrated, the media manager component 113 can perform three additional read operations (e.g., final center read, final left read, and final right read). Based on these values, the media manager component 113 can determine the valley tolerance, valley floor, and valley shift of the programmed distribution valley line. For example, the media manager component 113 can determine the heights of the final left and final right reads to determine the valley tolerance by determining the distance between the two points. The media manager component 113 can use the final center read as the valley floor. The media manager component 113 determines the valley shift by determining the offset value between the initial valley center position and the final center read.

[0058] In some embodiments, the media manager component 113 may use a curve fitting model to determine the valley metric. Specifically, the media manager component 113 may perform multiple read operations on a page. The media manager component 113 may then apply the voltage values ​​(e.g., voltage offset values ​​associated with the x-axis) and error count values ​​(e.g., RBER values ​​associated with the y-axis) obtained from the read operations to the following equation: RBER = Valley width * (X - Valley center) 2 +Valleyline bottom limit. In this example, three read operations are sufficient to resolve the values ​​of valleyline center, valleyline bottom limit, and valleyline tolerance. The valleyline shift can be obtained by offsetting the initial valleyline center position to the value between the solution for the valleyline center. In other embodiments, other mathematical methods can be used, such as an asymmetric exponential model (y = valleyline bottom limit + 2). -L(x-谷线中心) +2 -R(x-谷线中心) ), asymmetric parabolic models (e.g., split parabola equations), etc.

[0059] Figure 5 This is a flowchart of an example method 500 for data integrity checking based on a programmable distribution valley metric, according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The media manager component 113 performs the process. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 510, the processing logic of the memory subsystem controller 115 initiates a data integrity check (e.g., a scan operation) of the block and selects pages associated with the block for scanning. Pages may be selected randomly. The scan operation or other data integrity check verifies that the data stored at the page does not contain any errors, or that the number of errors is appropriately low. During the scan operation, the processing logic identifies one or more data state metrics, such as the Bit Error Count (BEC) or Raw Bit Error Rate (RBER), which represents the number of bit errors experienced by the data stored at the data block per unit time. In some embodiments, during the scan operation, the processing logic reads a raw codeword (i.e., a fixed number of bits) from the page. The processing logic may apply the codeword to an Error Correction Code (ECC) decoder to produce a decoded codeword and compare the decoded codeword with the original codeword. The processing logic may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER.

[0061] At operation 520, the processing logic determines whether the value of a data state metric (e.g., BEC value, RBER value, etc.) meets a threshold criterion (e.g., meets or exceeds a threshold). For example, the processing logic may determine whether the RBER value or BEC value exceeds a threshold. In response to the data state metric value meeting the criterion, the processing logic continues at operation 530 and performs one or more read operations on the page. The data obtained from the read operations can be used to generate an error count distribution (e.g., a valley line). Otherwise, the processing logic continues at operation 570 and selects a new page associated with the block for scanning.

[0062] In some embodiments, multiple threshold criteria may be used. For example, in response to an RBER or BEC value below a first threshold, the processing logic may continue at operation 570, select a new page to scan, and proceed to operation 520. In response to an RBER or BEC value between the first and second thresholds, the processing logic may continue at operation 530 and perform multiple read operations on the page. In response to an RBER or BEC value exceeding the second threshold, the processing logic may continue at operation 560 and perform media management operations, such as a folding operation. In some embodiments, the threshold criteria may be adjusted based on one or more parameters. For example, the correlation between RBER and valley tolerance may be determined for each block. Based on the relevant data, each RBER value may be associated with a valley tolerance. Therefore, the associated RBER value may be used as a threshold criterion based on the lowest acceptable valley tolerance.

[0063] At operation 540, the processing logic determines one or more values ​​of one or more programmed distribution valley metrics (e.g., voltage distribution metrics or valley metrics) based on the error count distribution generated by one or more read operations. For example, the processing logic may determine one or more of the following: a valley tolerance value associated with a page, a valley floor associated with a page, and a valley center associated with a page. (The above is in...) Figure 4 It describes in detail the determination of valley tolerance, valley floor and valley center.

[0064] At operation 550, the processing logic may determine whether one or more of the valley line metrics meet the refresh threshold criteria. In response to one or more of the valley line metrics meeting the refresh threshold criteria, the processing logic may continue at operation 560 and trigger a media management operation (e.g., a folding operation). For example, the media management operation may write data stored at a word line associated with a page to another block to refresh the data stored by memory subsystem 110. In another instance, the media management operation may write data stored across an entire block to another block to refresh the data stored by memory subsystem 110. Once the data has been written to the other block, the data stored in the initial word line or block is erased, and the initial block can be programmed with new data. Depending on the embodiment, the data may be relocated to another block on the same plane of the same memory device, relocated to another plane on the same memory device, or relocated to a different memory device of memory subsystem 110. In response to one or more of the valley line metrics failing to meet the refresh threshold criteria, the processing logic may continue at operation 570 and select a new page associated with said block for scanning.

[0065] Returning to operation 550, in some embodiments, the processing logic may first determine whether the value of a first valley metric (e.g., valley tolerance) satisfies a first valley metric threshold criterion (e.g., having a width between a left read value and a right read value below a threshold). In response to the first valley metric value satisfying the first valley metric criterion, the processing logic may continue at operation 560 and trigger a media management operation. In response to the first valley metric value failing to satisfy the first valley metric threshold criterion, the processing logic may determine whether the value of a second valley metric (e.g., valley shift) satisfies a second valley metric threshold criterion (e.g., the read level has shifted off a threshold voltage value). In response to the second valley metric value satisfying the first valley metric threshold criterion, the processing logic may continue at operation 560 and trigger a media management operation. In response to the second valley metric value failing to satisfy the second valley metric threshold criterion, the processing logic may determine whether the value of a third valley metric (e.g., valley bottom) satisfies a third valley metric threshold criterion (e.g., the valley bottom is above a threshold). If the third valley line metric meets the threshold criterion, the processing logic can continue at operation 560 and trigger the media management operation; otherwise, the processing logic can continue at operation 570 and select a new page.

[0066] In some embodiments, any combination of the first valley line metric, the second valley line metric, and the third valley line metric can be combined to satisfy a refresh threshold criterion. For example, in response to the first valley line metric failing to meet the first valley line metric threshold criterion, the processing logic may then determine whether the second valley line metric (e.g., valley line shift) and the third valley line metric (e.g., valley line bottom) meet the second valley line metric threshold criterion and the third valley line metric threshold criterion, respectively. If both the second valley line metric and the third valley line metric meet their respective threshold criteria, then the processing logic may trigger a media management operation. Otherwise, if only one (or neither) of the second valley line metric and the third valley line metric meets their respective threshold criteria, then the processing logic may select a new page at operation 570.

[0067] In another embodiment, the processing logic may use a neural network to determine whether one or more of the valley metrics meet refresh threshold criteria. In some embodiments, the neural network may be a binary classification neural network or a feedforward neural network. The neural network may receive three input values ​​(e.g., valley tolerance, valley center or valley shift, and valley bottom) and produce a binary output value. The output value may indicate whether a media management action is triggered or a new page is selected. The neural network may further include one or more hidden layers. The hidden layers process the input values ​​to produce the output values. In some embodiments, a supervised learning mechanism may be used to train the neural network, wherein a set of input values ​​is provided to the neural network and its output value is compared with a desired output value. The difference between the resulting output value and the desired output value can be used to adjust the weights of the neural network. The neural network may use a curve fitting model, an asymmetric exponential model, an asymmetric parabolic model, or any other model during training. In some embodiments, an unsupervised learning mechanism may be used to train the neural network. In some embodiments, other machine learning models may be used.

[0068] Figure 6 An example machine is described as representing computer system 600, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used for controller operation (e.g., executing an operating system to perform corresponding... Figure 1(Operation of the media manager component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0069] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0070] Example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630. The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communication via a network 620.

[0071] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more instruction sets 626 or software embodying any one or more methods or functions described herein. Instructions 626 may also be wholly or at least partially residing in main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage device 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0072] In one embodiment, instruction 626 includes implementing the corresponding Figure 1 The block manager component 113 contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0073] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. An algorithm herein is generally considered to be a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0074] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memories of a computer system and transform said data into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0075] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices for carrying out the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0077] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0078] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the embodiments of the present disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: Determine the value of the data status metric for the memory page; When the value of the data state metric is determined to satisfy the first threshold criterion, a first value of the first voltage distribution metric and a second value of the second voltage distribution metric associated with the page are determined. Determine whether the first value of the first voltage distribution metric satisfies the second threshold criterion; When it is determined that the first value of the first voltage distribution metric satisfies the second threshold criterion, it is then determined whether the second value of the second voltage distribution metric satisfies the third threshold criterion. as well as When the second value of the second voltage distribution metric is determined to satisfy the third threshold criterion, media management operations are performed relative to the block associated with the page.

2. The memory system of claim 1, wherein the value of the data state metric reflects the raw bit error rate (RBER) or bit error count (BER).

3. The memory system of claim 1, wherein the value of the voltage distribution metric reflects one or more of a voltage distribution tolerance, a voltage distribution floor, or a voltage distribution center.

4. The memory system of claim 1, wherein a vectorized read level calibration vRLC procedure is used to determine the value of the voltage distribution metric.

5. The memory system of claim 1, wherein a neural network is used to determine the value of the voltage distribution metric.

6. The memory system of claim 1, wherein the operation further comprises: In response to the failure of the value of the data state metric to meet the first threshold criterion or the failure of the value of the voltage distribution metric to meet the second threshold criterion, a new value of the data state metric for another memory page associated with the block is determined.

7. The memory system of claim 1, wherein the media management operation includes writing data stored at the block to a new block.

8. A method for a memory system, the method comprising: Determine the value of the data status metric for the memory page; When the value of the data state metric is determined to satisfy the first threshold criterion, a first value of the first voltage distribution metric and a second value of the second voltage distribution metric associated with the page are determined. Determine whether the first value of the first voltage distribution metric satisfies the second threshold criterion; When it is determined that the first value of the first voltage distribution metric satisfies the second threshold criterion, it is then determined whether the second value of the second voltage distribution metric satisfies the third threshold criterion. as well as When the second value of the second voltage distribution metric is determined to satisfy the third threshold criterion, media management operations are performed relative to the block associated with the page.

9. The method of claim 8, wherein the value of the data state metric reflects the raw bit error rate (RBER) or bit error count (BER).

10. The method of claim 8, wherein the value of the voltage distribution metric reflects one or more of a voltage distribution tolerance, a voltage distribution floor, or a voltage distribution center.

11. The method of claim 8, wherein the value of the voltage distribution metric is determined using a vectorized read level calibration vRLC procedure.

12. The method of claim 8, wherein a neural network is used to determine the value of the voltage distribution metric.

13. The method of claim 8, further comprising: In response to the failure of the value of the data state metric to meet the first threshold criterion or the failure of the value of the voltage distribution metric to meet the second threshold criterion, a new value of the data state metric for another memory page associated with the block is determined.

14. The method of claim 8, wherein the media management operation comprises writing data stored at the block to a new block.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a memory, perform operations including: Determine the value of the data status metric of the memory page associated with the block; When the value of the data state metric is determined to satisfy the first threshold criterion, a first value of the first voltage distribution metric and a second value of the second voltage distribution metric associated with the page are determined. Determine whether the first value of the first voltage distribution metric satisfies the second threshold criterion; When it is determined that the first value of the first voltage distribution metric satisfies the second threshold criterion, it is then determined whether the second value of the second voltage distribution metric satisfies the third threshold criterion. as well as Media management operations are performed relative to the block associated with the page when the second value of the second voltage distribution metric is determined to satisfy the third threshold criterion.

16. The non-transitory computer-readable storage medium of claim 15, wherein the value of the data state metric reflects the raw bit error rate (RBER) or bit error count (BER).

17. The non-transitory computer-readable storage medium of claim 15, wherein the value of the voltage distribution metric reflects one or more of a voltage distribution tolerance, a voltage distribution floor, or a voltage distribution center.

18. The non-transitory computer-readable storage medium of claim 15, wherein the value of the voltage distribution metric is determined using a vectorized read level calibration vRLC procedure.

19. The non-transitory computer-readable storage medium of claim 15, wherein a neural network is used to determine the value of the voltage distribution metric.

20. The non-transitory computer-readable storage medium of claim 15, wherein the operation further comprises: In response to the failure of the value of the data state metric to meet the first threshold criterion or the failure of the value of the voltage distribution metric to meet the second threshold criterion, a new value of the data state metric for another memory page associated with the block is determined.

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