Semiconductor device including ferroelectric layer and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device including a ferroelectric layer and a manufacturing method thereof. The semiconductor device according to an embodiment includes: a substrate; a bit line structure and a source line structure, each extending in a direction perpendicular to a surface of the substrate; a semiconductor layer, which is arranged between the bit line structure and the source line structure on a plane parallel to the surface of the substrate; a first ferroelectric layer, which is arranged on a first surface of the semiconductor layer; and a first gate electrode layer, which is arranged on the first ferroelectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Application No. 10-2020-0175878 filed on December 15, 2020 with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to a semiconductor device, and more particularly, to a semiconductor device including a ferroelectric layer and a method of manufacturing the same. Background Art

[0004] Generally, ferroelectric materials refer to materials that have spontaneous electric polarization in a state where no external electric field is applied. In addition, in ferroelectric materials, the electric polarization can exhibit hysteresis behavior when an external electric field is applied. Therefore, by controlling the applied external electric field, various polarizations can be reversibly realized in ferroelectric materials that follow hysteresis behavior. This feature can be applied to semiconductor devices that store signal information in a non-volatile manner. Summary of the invention

[0005] A semiconductor device according to an embodiment of the present disclosure may include: a substrate; a bit line structure and a source line structure, each extending in a direction perpendicular to the surface of the substrate; a semiconductor layer, arranged between the bit line structure and the source line structure on a plane parallel to the surface of the substrate; a first ferroelectric layer, arranged on a first surface of the semiconductor layer; and a first gate electrode layer, arranged on the first ferroelectric layer.

[0006] A semiconductor device according to another embodiment of the present disclosure may include: a substrate; a bit line structure and a source line structure, each extending in a direction perpendicular to the surface of the substrate; and a plurality of unit cell structures electrically connected to the bit line structure and the source line structure. Each of the plurality of unit cell structures may include: a semiconductor layer, which is arranged on a plane parallel to the substrate surface and in contact with the bit line structure and the source line structure; a first ferroelectric layer, which is arranged on a first surface of the semiconductor layer; and a first gate electrode layer, which is arranged on the first ferroelectric layer and is spaced apart from the bit line structure and the source line structure. The plurality of unit cell structures are arranged to be spaced apart from each other in a direction perpendicular to the substrate surface.

[0007] A method for manufacturing a semiconductor device according to another embodiment of the present disclosure is disclosed. In the method, a substrate including a base insulating layer may be provided. A first stacked structure may be formed on the base insulating layer, the first stacked structure including: a first insulating layer and a second insulating layer, both of which are arranged to be spaced apart from each other in a direction perpendicular to the surface of the substrate; and a semiconductor layer and at least one sacrificial layer, which are arranged between the first insulating layer and the second insulating layer. The first stacked structure may be selectively etched on the base insulating layer to form a second stacked structure, the second stacked structure including a first groove and a first recessed space, the first groove being formed to expose the base insulating layer, and the first recessed space being formed by selectively etching the at least one sacrificial layer in the first groove. A third stacked structure may be formed, which includes a plurality of material layers arranged in the first recessed space of the second stacked structure, the plurality of material layers including: an interface insulating layer arranged on the semiconductor layer, a ferroelectric layer at least covering the interface insulating layer, and a gate electrode layer arranged on the ferroelectric layer. A fourth stacked structure may be formed, which includes a bit line structure in the first groove of the third stacked structure arranged on the base insulating layer. The fourth stacked structure may be selectively etched on the base insulating layer to form a fifth stacked structure, the fifth stacked structure including a second trench exposing the base insulating layer, the second trench exposing the semiconductor layer, the interface insulating layer, the ferroelectric layer, the gate electrode layer, and the first insulating layer and the second insulating layer on the sidewall surface of the second trench. A sixth stacked structure may be formed, which includes a source line structure disposed in the second trench of the fifth stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2B yes Figure 2A An enlarged view of portion “A” of a semiconductor device.

[0011] Figure 3A is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0012] Figure 3B yes Figure 3A An enlarged view of portion “B” of the semiconductor device.

[0013] Figure 4A is a schematic cross-sectional view showing a semiconductor device according to still another embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A An enlarged view of portion “C” of the semiconductor device.

[0015] Figures 5 to 19 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 20 to Figure 25 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0017] Figures 26 to 30 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, in order to clearly represent the components of each device, the size of the components (e.g., the width and thickness of the components) are magnified. In general, the accompanying drawings are interpreted from the perspective of the observer, and when an element is mentioned to be located above another element, this includes all meanings that the element can be directly located above another element or that other elements can be between these elements. In multiple drawings, the same reference numerals refer to substantially the same elements.

[0019] In addition, the expression of the singular form of a word should be understood to include the plural form of the word, unless otherwise clearly applied in the context. It will be understood that the terms "comprise", "include" or "have" are intended to specify the presence of features, numbers, steps, operations, components, elements, parts or combinations thereof, and are not used to exclude the presence or possible addition of one or more other features, numbers, steps, operations, components, elements, parts or combinations thereof. In addition, when performing a method or manufacturing method, unless a specific order is clearly indicated in the context, each process constituting the method can occur differently from the specified order. That is, each process can occur in the same order specified, can be performed substantially simultaneously, or can be performed in a reverse order or a different order.

[0020] According to an embodiment of the present disclosure, a semiconductor device including a field effect transistor type unit cell structure (which has a ferroelectric layer) can be provided. The ferroelectric layer can be arranged between the channel region of the field effect transistor and the gate electrode layer. In one embodiment, the semiconductor device can be used as a non-volatile memory device. The write operation of the semiconductor device can be performed by applying a write voltage to the gate electrode layer to write different polarization states in the ferroelectric layer. After removing the write voltage, the different polarization states can be stored in the form of residual polarization. The stored residual polarization state can be used as signal information. The read operation of the semiconductor device can be performed by reading the threshold voltage of the field effect transistor, and the threshold voltage varies according to the size or orientation of the residual polarization stored in the ferroelectric layer.

[0021] Figure 1 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present disclosure. Figure 1 , the semiconductor device 1 may include a plurality of unit cells MC1, MC2, MC3, and MC4, which are disposed between a source line SL and any one of a first bit line BL1 and a second bit line BL2. Figure 1 The first to fourth unit cells MC1 , MC2 , MC3 , and MC4 are illustrated as examples of the plurality of unit cells, but the plurality of unit cells are not necessarily limited thereto, and various numbers of unit cells may be utilized.

[0022] refer to Figure 1 , the first to fourth unit cells MC1, MC2, MC3 and MC4 may be field effect transistor type memory cells having first to fourth ferroelectric layers FE1, FE2, FE3 and FE4 as gate dielectric layers, respectively. The first to fourth word lines WL1, WL2, WL3 and WL4 may be electrically connected to the first to fourth ferroelectric layers FE1, FE2, FE3 and FE4 of the first to fourth unit cells MC1, MC2, MC3 and MC4, respectively.

[0023] Source electrodes S1 and S2 of the field effect transistors constituting the first unit cell MC1 and the second unit cell MC2 may be electrically connected to the first bit line BL1 and the second bit line BL2, respectively. Drain electrodes D1 and D2 of the field effect transistors constituting the first unit cell MC1 and the second unit cell MC2 may be electrically connected to a common source line SL. That is, the first unit cell MC1 and the second unit cell MC2 may share the source line SL.

[0024] The source electrodes S3 and S4 of the field effect transistors constituting the third unit cell MC3 and the fourth unit cell MC4 may be electrically connected to the first bit line BL1 and the second bit line BL2, respectively. The drain electrodes D3 and D4 of the field effect transistors constituting the third unit cell MC3 and the fourth unit cell MC4 may be electrically connected to a common source line SL. That is, the third unit cell MC3 and the fourth unit cell MC4 may share the source line SL.

[0025] Figure 1 The circuit configuration of the semiconductor device 1 in FIG. 1 can be applied to semiconductor devices 1 a , 1 b , and 1 c according to embodiments of the present disclosure described below.

[0026] Figure 2A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 2B yes Figure 2A An enlarged view of portion “A” of a semiconductor device.

[0027] refer to Figure 2A , the semiconductor device 1a may include a substrate 101, a first bit line structure 110a and a second bit line structure 110b, a source line structure 120, and first to fourth unit cell structures UC10, UC20, UC30, and UC40. The first bit line structure 110a and the second bit line structure 110b and the source line structure 120 may extend in a first direction (i.e., z direction) perpendicular to a surface 101S of the substrate 101.

[0028] The first unit cell structure UC10 and the third unit cell structure UC30 may be disposed between the first bit line structure 110a and the source line structure 120. The first unit cell structure UC10 and the third unit cell structure UC30 may be electrically connected to the first bit line structure 110a and the source line structure 120. The first unit cell structure UC10 and the third unit cell structure UC30 may be disposed to be spaced apart from each other in a first direction (i.e., z direction). An interlayer insulating layer 190 may be disposed between the first unit cell structure UC10 and the third unit cell structure UC30.

[0029] The second unit cell structure UC20 and the fourth unit cell structure UC40 may be disposed between the second bit line structure 110b and the source line structure 120. The second unit cell structure UC20 and the fourth unit cell structure UC40 may be electrically connected to the second bit line structure 110b and the source line structure 120. The second unit cell structure UC20 and the fourth unit cell structure UC40 may be disposed to be spaced apart from each other in the first direction (i.e., the z direction). An interlayer insulating layer 190 may be disposed between the second unit cell structure UC20 and the fourth unit cell structure UC40.

[0030] Figure 2AFour unit cell structures are shown, but the present disclosure is not limited thereto. Various numbers of unit cell structures may be disposed between the first bit line structure 110a and the source line structure 120. Similarly, various numbers of unit cell structures may be disposed between the second bit line structure 110b and the source line structure 120.

[0031] refer to Figure 2A The substrate 101 may include a semiconductor material. For example, the semiconductor material may be made of silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2 ), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or a combination of two or more thereof or including silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2 ), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or a combination of two or more thereof. The semiconductor material may be doped with a dopant. As an example, the semiconductor material may be doped with an N-type dopant or a P-type dopant.

[0032] An integrated circuit may be provided on the substrate 101. As an example, the integrated circuit may include a driving circuit or a control circuit for the first to fourth unit cell structures UC10, UC20, UC30, and UC40. The integrated circuit may include at least one field effect transistor.

[0033] A base insulating layer 105 may be disposed on the substrate 101. The base insulating layer 105 may electrically insulate the first bit line 110a, the second bit line 110b, and the source line 120 from the substrate 101. The base insulating layer 105 may be made of or include an insulating material. The insulating material may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0034] The first bit line structure 110a and the second bit line structure 110b may be disposed to be spaced apart from each other on the base insulating layer 105. Each of the first bit line structure 110a and the second bit line structure 110b may extend in a first direction (ie, z direction). The first bit line structure 110a and the second bit line structure 110b may correspond to Figure 1 The first bit line BL1 and the second bit line BL2 in the circuit diagram.

[0035] Each of the first bit line structure 110a and the second bit line structure 110b may be a columnar structure. As an example, the first bit line structure 110a and the second bit line structure 110b may be a rectangular columnar structure. Each of the first bit line structure 110a and the second bit line structure 110b may be made of a conductive material or include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. In one embodiment, the first bit line structure 110a and the second bit line structure 110b may be made of substantially the same material.

[0036] The source line structure 120 may be disposed on the base insulating layer 105. The source line structure 120 may be disposed between the first bit line structure 110a and the second bit line structure 110b. The source line structure 120 may extend in a first direction (ie, z direction). The source line structure 120 may correspond to Figure 1 The source line SL in the circuit diagram.

[0037] The source line structure 120 may be a columnar structure. As an example, the source line structure 120 may be a rectangular columnar structure. The source line structure 120 may be made of or include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0038] refer to Figure 2A , the first to fourth unit cell structures UC10, UC20, UC30 and UC40 may correspond to Figure 1 Each of the first to fourth unit cell structures U10, U20, U30, and U40 may have substantially the same configuration. Figure 2BThe first unit cell structure UC10 among the first to fourth unit cell structures U10, U20, U30, and U40 is described. The configurations of the second to fourth unit cell structures U20, U30, and U40 are apparent from the configuration of the first unit cell structure UC10.

[0039] refer to Figure 2A and Figure 2B , the semiconductor layer 130 may be disposed on a plane parallel to a surface 101S common to the substrate 101 and the base insulating layer 105. As an example, the plane parallel to the surface 101S of the substrate 101 may be a plane perpendicular to the first direction (i.e., the z direction). The semiconductor layer 130 may be disposed between the first bit line structure 110a and the source line structure 120. In one embodiment, the side surfaces of the semiconductor layer 130 may be disposed to contact the first bit line structure 110a and the source line structure 120, respectively.

[0040] The semiconductor layer 130 may be made of or include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs), etc. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include a transition metal dichalcogenide (TMDC) or black phosphorus, etc. The transition metal dichalcogenide (TMDC) may include, for example, molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2 ), indium selenide (InSe) or gallium selenide (GaSe), etc. As an example, the semiconductor material may be made of or include a metal oxide, such as indium gallium zinc oxide (IGZO). The semiconductor layer 130 may be doped with an n-type or p-type dopant. The conductivity of the semiconductor layer 130 may vary depending on the amount of the dopant.

[0041] The semiconductor layer 130 may include: a source region 132, which contacts the first bit line structure 110a; a drain region 134, which contacts the source line structure 120; and a channel region 136, which is disposed between the source region 132 and the drain region 134. The source region 132 and the drain region 134 may be doped with the same type of dopant. The channel region 136 may be doped with a different type of dopant from the source region 132 and the drain region 134. As an example, the source region 132 and the drain region 134 may be doped with an n-type dopant, and the channel region 136 may be doped with a p-type dopant. As another example, the source region 132 and the drain region 134 may be doped with a p-type dopant, and the channel region 136 may be doped with an n-type dopant.

[0042] The semiconductor layer 130 may have a first surface 130S1 and a second surface 130S2 facing each other. A first interface insulating layer 140U may be disposed on the first surface 130S1 of the semiconductor layer 130. A first ferroelectric layer 150U may be disposed on the first interface insulating layer 140U. A first gate electrode layer 160U may be disposed on the first ferroelectric layer 150U.

[0043] The first interface insulating layer 140U may be made of an insulating material or include an insulating material. As an example, the first interface insulating layer 140U may be made of an oxide, a nitride, an oxynitride, or a combination of two or more thereof or include an oxide, a nitride, an oxynitride, or a combination of two or more thereof. The first interface insulating layer 140U may have an amorphous state. The first interface insulating layer 140U may be used to reduce interface defects generated when the semiconductor layer 130 and the first ferroelectric layer 150U directly form an interface. In some embodiments, when the interface stability between the semiconductor layer 130 and the first ferroelectric layer 150U is ensured, the first interface insulating layer 140U may be omitted.

[0044] The first ferroelectric layer 150U may be made of or include a ferroelectric material having a remanent polarization. The first ferroelectric layer 150U may include a crystalline metal oxide. The first ferroelectric layer 150U may include a binary metal oxide. The first ferroelectric layer 150U may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In another embodiment, the first ferroelectric layer 150U may include a ternary metal oxide or a higher metal oxide. The first ferroelectric layer 150U may include, for example, Pb(Zr,Ti)O 3 , SrBi 2 Ta 2 O 9 , (Bi,La) 4 Ti 3 O 12 ,BiFeO 3 , or a combination of two or more thereof.

[0045] The first gate electrode layer 160U may be made of or include a conductive material. The first gate electrode layer 160U may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, or a combination of two or more thereof.

[0046] Despite Figure 2A and Figure 2B1 , but in some embodiments, the first gate electrode layer 160U may extend in a second direction that is not parallel to the first direction. Specifically, the first gate electrode layer 160U may extend in a direction perpendicular to the first direction, wherein the first direction is the direction in which the first bit line structure 110a and the source line structure 120 extend. The first gate electrode layer 160U may extend in a second direction (e.g., y direction) on a plane parallel to the surface 101S of the substrate 101. For example, the first gate electrode layer 160U may be used as a word line.

[0047] Reference again Figure 2B , a first bit line insulating layer 182U and a first source line insulating layer 184U may be disposed on the first ferroelectric layer 150U. The first bit line insulating layer 182U and the first source line insulating layer 184U may be disposed on the sidewalls of the first gate electrode layer 160U. The first bit line insulating layer 182U may be disposed in a lateral direction (i.e., corresponding to Figure 2A The first source line insulating layer 184U may be electrically insulated from the first gate electrode layer 160U in the lateral direction (i.e., corresponding to the x direction). Figure 2A The first bit line insulating layer 182U and the first source line insulating layer 184U may be made of or include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0048] The first cover dielectric layer 170U may be disposed on the first gate electrode layer 160U, the first bit line insulating layer 182U, and the first source line insulating layer 184U. In one embodiment, the first cover dielectric layer 170U may be in contact with the first gate electrode layer 160U, the first bit line insulating layer 182U, and the first source line insulating layer 184U. In one embodiment, the first cover dielectric layer 170U may be made of a material substantially the same as the first ferroelectric layer 150U. That is, the first cover dielectric layer 170U may be made of or include a ferroelectric material having a residual polarization. An interlayer insulating layer 190 may be disposed on the first cover dielectric layer 170U. The interlayer insulating layer 190 may be made of or include, for example, an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0049] Reference again Figure 2B, a second interface insulating layer 140L may be disposed on the second surface 130S2 of the semiconductor layer 130. A second ferroelectric layer 150L may be disposed on the second interface insulating layer 140L. A second gate electrode layer 160L may be disposed on the second ferroelectric layer 150L. The configuration of the second interface insulating layer 140L, the second ferroelectric layer 150L, ​​and the second gate electrode layer 160L may be substantially the same as the configuration of the first interface insulating layer 140U, the first ferroelectric layer 150U, and the first gate electrode layer 160U.

[0050] In addition, a second bit line insulating layer 182L and a second source line insulating layer 184L may be provided on the sidewalls of the second gate electrode layer 160L. The second bit line insulating layer 182L may be provided in a lateral direction (ie, corresponding to Figure 2A The first bit line structure 110a is electrically insulated from the second gate electrode layer 160L in the lateral direction (i.e., corresponding to the x direction). Figure 2A The second bit line insulating layer 182L may be configured substantially the same as the first bit line insulating layer 182U, and the second source line insulating layer 184L may be configured substantially the same as the first source line insulating layer 184U.

[0051] The second capping dielectric layer 170L may be disposed on the second gate electrode layer 160L, the second bit line insulating layer 182L, and the second source line insulating layer 184L. The configuration of the second capping dielectric layer 170L may be substantially the same as that of the first capping dielectric layer 170U. An interlayer insulating layer 190 may be disposed on the second capping dielectric layer 170L.

[0052] In one embodiment, although Figure 2A and Figure 2B 101S, but the first gate electrode layer 160U and the second gate electrode layer 160L may be electrically connected to each other. As an example, the first gate electrode layer 160U and the second gate electrode layer 160L may be connected to each other by a conductive via (not shown) disposed in a direction perpendicular to the surface 101S of the substrate 101. Therefore, in the first unit cell structure UC10, the first gate electrode layer 160U and the second gate electrode layer 160L may simultaneously control the polarization of the first ferroelectric layer 150U and the second ferroelectric layer 150L by simultaneously applying the same gate voltage to the first ferroelectric layer 150U and the second ferroelectric layer 150L. Therefore, the same electrical signal may be stored in the first ferroelectric layer 150U and the second ferroelectric layer 150L. As a result, the first unit cell structure U10 may be operated as a single memory cell.

[0053] In another embodiment, the first gate electrode layer 160U and the second gate electrode layer 160L may be electrically isolated from each other. In the first unit cell structure UC10, the first gate electrode layer 160U and the second gate electrode layer 160L may control the polarization of the first ferroelectric layer 150U and the second ferroelectric layer 150L by applying gate voltages to the first ferroelectric layer 150U and the second ferroelectric layer 150L independently of each other. Therefore, separate electrical signals may be stored in the first ferroelectric layer 150U and the second ferroelectric layer 150L. As a result, the first unit cell structure U10 may operate as two memory cells.

[0054] Figure 3A is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Figure 3B yes Figure 3A An enlarged view of portion "B" of a semiconductor device. Figure 2A and Figure 2B Compared with the semiconductor device 1a of FIG. 1 , the configurations of the first to fourth unit cell structures (ie, UC11 , UC21 , UC31 , and UC41 ) of the semiconductor device 1b are different. Figure 3A Some components are related to Figure 2A Corresponding elements with the same numbers in the drawings are substantially the same, so some descriptive details may be omitted below.

[0055] refer to Figure 3A , the first to fourth unit cell structures UC11, UC21, UC31, and UC41 of the semiconductor device 1b may correspond to Figure 1 The first to fourth unit cells MC1, MC2, MC3 and MC4 in the circuit diagram of FIG. The configurations of the first to fourth unit cell structures UC11, UC21, UC31 and UC41 may be substantially the same as each other. Figure 3B The first unit cell structure UC11 among the first to fourth unit cell structures UC11 , UC21 , UC31 , and UC41 is described in detail.

[0056] refer to Figure 3A and Figure 3B , the semiconductor layer 130 may be disposed on the base insulating layer 105 on a plane parallel to the surface 101S of the substrate 101. As an example, the plane parallel to the surface 101S of the substrate 101 may be a plane perpendicular to the first direction (ie, z direction).

[0057] The semiconductor layer 130 may include a source region 132 in contact with the first bit line structure 110 a , a drain region 134 in contact with the source line structure 120 , and a channel region 136 disposed between the source region 132 and the drain region 134 .

[0058] A first interface insulating layer 140U may be disposed on the first surface 130S1 of the semiconductor layer 130. A first electric floating layer 242U may be disposed on the first interface insulating layer 140U. A first ferroelectric layer 250U may be disposed on the first electric floating layer 242U. The first ferroelectric layer 250U may have The first ferroelectric layer 250U may include a first portion 250U1, a second portion 250U2, and a third portion 250U3. The first portion 250U1 and the second portion 250U2 may be arranged to be spaced apart from each other in the z direction, and the third portion 250U3 may connect the first portion 250U1 and the second portion 250U2 to each other. The first gate electrode layer 260U may be arranged between the first portion 250U1 and the second portion 250U2 of the first ferroelectric layer 250U. The first covering conductive layer 244U may be arranged on the second portion 250U2 of the first ferroelectric layer 250U.

[0059] The first electrically floating layer 242U may have conductivity. The first electrically floating layer 242U may be made of or include a conductive material. The conductive material may include, for example, a metal, a conductive metal nitride, or a conductive metal oxide. The first electrically floating layer 242U may be electrically floating in the first unit cell structure UC11.

[0060] The first electric floating layer 242U may form an interface with the first portion 250U1 of the first ferroelectric layer 250U. On the other hand, when ferroelectric polarization is formed in the first portion 250U1 of the first ferroelectric layer 250U, the charge induced by the ferroelectric polarization may be distributed inside the first portion 250U1 adjacent to the interface of the first electric floating layer 242U. The first electric floating layer 242U may provide a sufficient number of charges of opposite polarity to the inner region of the first electric floating layer 242U adjacent to the interface. The charges in the inner region of the first electric floating layer 242U may shield the induced charges in the first portion 250U1. Therefore, the charges induced in the first ferroelectric layer 250U due to the ferroelectric polarization may be offset by the charges provided by the first electric floating layer 242U. As a result, the charges induced by the ferroelectric polarization may be prevented from generating a depolarization electric field in the first ferroelectric layer 250U. Therefore, the ferroelectric polarization of the first ferroelectric layer 250U may be prevented from being degraded due to the depolarization electric field.

[0061] The first electrically floating layer 242U may be electrically insulated from the first bit line structure 110a by the first bit line insulating layer 282U. The first electrically floating layer 242U may be electrically insulated from the source line structure 120 by the first source line insulating layer 284U.

[0062] Reference again Figure 3B, the first portion 250U1 of the first ferroelectric layer 250U can cover the first electric floating layer 242U. The first portion 250U1 can substantially perform the function of storing ferroelectric polarization as signal information. The ferroelectric polarization can be controlled by a gate voltage provided by the first gate electrode layer 260U and applied between the first gate electrode layer 260U and the semiconductor layer 130.

[0063] The second portion 250U2 of the first ferroelectric layer 250U may be disposed between the first gate electrode layer 260U and the first capping conductive layer 244U. The third portion 250U3 of the first ferroelectric layer 250U may be disposed on the sidewall surface of the source line structure 120 to connect the first portion 250U1 and the second portion 250U2 to each other. In one embodiment, the second portion 250U2 and the third portion 250U3 may not be electrically controlled by the gate voltage between the first gate electrode layer 260U and the semiconductor layer 130 provided by the first gate electrode layer 260U. Therefore, the second portion 250U2 and the third portion 250U3 may not substantially perform a storage function of storing ferroelectric polarization as signal information between the first gate electrode layer 260U and the semiconductor layer 130.

[0064] The materials constituting the first to third parts 250U1, 250U2 and 250U3 of the first ferroelectric layer 250U may be the same as those constituting the above-referenced Figure 2A and Figure 2B The material of the first ferroelectric layer 150U described is substantially the same.

[0065] The first gate electrode layer 260U may be disposed between the first portion 250U1 and the second portion 250U2 of the first ferroelectric layer 250U in the z direction. In addition, the first gate electrode layer 260U may be disposed between the first bit line insulating layer 282U and the third portion 250U3 of the first ferroelectric layer 250U in the x direction. The material constituting the first gate electrode layer 260U may be the same as that constituting the first gate electrode layer 260U. Figure 2A and Figure 2B The materials of the first gate electrode layer 160U described above are substantially the same. The first gate electrode layer 260U may be electrically insulated from the first bit line structure 110a by a first bit line insulating layer 282U.

[0066] Despite Figure 3A and Figure 3B1 , but in some embodiments, the first gate electrode layer 260U may extend in a second direction that is not parallel to the first direction (i.e., the z direction). Specifically, the first gate electrode layer 260U may extend in a direction perpendicular to the first direction, the first direction being the direction in which the first bit line structure 110a and the source line structure 120 extend. The first gate electrode layer 260U may extend in a second direction (e.g., the y direction) on a plane parallel to the surface 101S of the substrate 101. The first gate electrode layer 260U may be used as a word line.

[0067] The first covering conductive layer 244U may be arranged to contact the second portion 250U2 of the first ferroelectric layer 250U. The first covering conductive layer 244U may be made of or include a conductive material. In one embodiment, the first covering conductive layer 244U may be electrically floating. The first covering conductive layer 244U may be electrically insulated from the first bit line structure 110a by the first bit line insulating layer 282U. The first covering conductive layer 244U may be electrically insulated from the source line structure 120 by the first source line insulating layer 284U. An interlayer insulating layer 190 may be arranged on the first covering conductive layer 244U. The interlayer insulating layer 190 may be arranged to contact the first covering conductive layer 244U, the first bit line insulating layer 282U, and the first source line insulating layer 284U.

[0068] Reference again Figure 3B A second interface insulating layer 140L may be disposed on the second surface 130S2 of the semiconductor layer 130. A second electric floating layer 242L may be disposed on the second interface insulating layer 140L. A second ferroelectric layer 250L may be disposed on the second electric floating layer 242L. The second ferroelectric layer 250L may have The second ferroelectric layer 250L may include a first portion 250L1, a second portion 250L2, and a third portion 250L3. The first portion 250L1 and the second portion 250L2 may be arranged to be spaced apart from each other in the z direction, and the third portion 250L3 may connect the first portion 250L1 and the second portion 250L2 to each other. The second gate electrode layer 260L may be arranged between the first portion 250L1 and the second portion 250L2 of the second ferroelectric layer 250L. The second covering conductive layer 244L may be arranged on the second portion 250L2 of the second ferroelectric layer 250L.

[0069] A second bit line insulating layer 282L may be disposed between the first bit line structure 110a and each of the second electrical floating layer 242L, the second gate electrode layer 260L, and the second capping conductive layer 244L. A second source line insulating layer 284L may be disposed between the source line structure 120 and each of the second electrical floating layer 242L and the second capping conductive layer 244L.

[0070] An interlayer insulating layer 190 may be disposed on the second capping conductive layer 244L. The interlayer insulating layer 190 may be disposed in contact with the second capping conductive layer 244L, the second bit line insulating layer 282L, and the second source line insulating layer 284L.

[0071] The configuration of the second interface insulating layer 140L, the second electrical floating layer 242L, the second ferroelectric layer 250L, the second gate electrode layer 260L, the second covering conductive layer 244L, the second bit line insulating layer 282L and the second source line insulating layer 284L can be basically the same as the configuration of the first interface insulating layer 140U, the first electrical floating layer 242U, the first ferroelectric layer 250U, the first gate electrode layer 260U, the first covering conductive layer 244U, the first bit line insulating layer 282U and the first source line insulating layer 284U.

[0072] In one embodiment, although Figure 3A and Figure 3B Although not shown in the figure, the first gate electrode layer 260U and the second gate electrode layer 260L may be electrically connected to each other. As an example, the first gate electrode layer 260U and the second gate electrode layer 260L may be connected to each other through a conductive via (not shown) disposed in a direction perpendicular to the surface 101S of the substrate 101. The first gate electrode layer 260U and the second gate electrode layer 260L provide the same gate voltage to simultaneously control the polarization of the first ferroelectric layer 250U and the second ferroelectric layer 250L, so that the first unit cell structure UC11 can be operated as a single memory cell.

[0073] In another embodiment, the first gate electrode layer 260U and the second gate electrode layer 260L can be electrically isolated from each other. The first gate electrode layer 260U and the second gate electrode layer 260L each provide a gate voltage to independently control the polarization of the corresponding first ferroelectric layer 250U and the second ferroelectric layer 250L, so that the first unit cell structure UC11 can operate as two memory cells.

[0074] Figure 4A is a schematic cross-sectional view showing a semiconductor device according to still another embodiment of the present disclosure. Figure 4B yes Figure 4A An enlarged view of a portion "C" of a semiconductor device. Figure 2A and Figure 2B Compared to the semiconductor device 1a, the semiconductor device 1c is different in the configuration of the first to fourth unit cell structures (ie, UC12, UC22, UC32, and UC42). Figure 4A Some components are related to Figure 2A Corresponding elements with the same numbers in the drawings are substantially the same, so some descriptive details may be omitted below.

[0075] refer to Figure 4A, the first to fourth unit cell structures UC12, UC22, UC32, and UC42 of the semiconductor device 1c may correspond to Figure 1 The first to fourth unit cells MC1, MC2, MC3 and MC4 in the circuit diagram of FIG. The configurations of the first to fourth unit cell structures UC12, UC22, UC32 and UC42 may be substantially the same as each other. Figure 4B The first unit cell structure UC12 among the first to fourth unit cell structures UC12 , UC22 , UC32 , and UC42 is described in detail.

[0076] refer to Figure 4B , the first unit cell structure UC12 may include an interface insulating layer 140, a ferroelectric layer 150, a gate electrode layer 160, and a covering dielectric layer 170 disposed on the first surface 130S1 of the semiconductor layer 130. In addition, the first unit cell structure UC12 may include a bit line insulating layer 182 and a source line insulating layer 184, both of which are disposed on the sidewalls of the gate electrode layer 160. The bit line insulating layer 182 and the source line insulating layer 184 are disposed only on the first surface 130S1 of the semiconductor layer 130. An interlayer insulating layer 190 may be disposed on the second surface 130S2 of the semiconductor layer 130 and on the covering dielectric layer 170.

[0077] The configurations of the interface insulating layer 140, the ferroelectric layer 150, the gate electrode layer 160, the capping dielectric layer 170, the bit line insulating layer 182, and the source line insulating layer 184 may be the same as those described in reference Figure 2A and Figure 2B The configurations of the described first interface insulating layer 140U, the first ferroelectric layer 150U, the first gate electrode layer 160U, the first capping dielectric layer 170U, the first bit line insulating layer 182U, and the first source line insulating layer 184U are substantially the same.

[0078] As described above, in various embodiments of the present disclosure, each semiconductor device may include a unit cell structure disposed between a bit line structure and a source line structure extending in a vertical direction perpendicular to a substrate surface. The unit cell structure may be implemented as a field effect transistor type ferroelectric device on a plane parallel to the surface of the substrate.

[0079] Because the field effect transistor type ferroelectric device is arranged on a plane parallel to the substrate surface, the height of the unit cell structure in the direction perpendicular to the substrate surface can be reduced. Therefore, the density of the unit cell structure vertically stacked in a fixed volume on the surface of the substrate can be increased. In addition, as the height of the unit cell structure is reduced, when multiple unit cell structures are stacked on the substrate, the stress of the substrate can be reduced because the stress of the substrate depends on the height of the multiple unit cell structures.

[0080] Figures 5 to 19 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 5 to 19 The described method can be applied to reference Figure 2A and Figure 2B A method for manufacturing a semiconductor device 1a is described.

[0081] In one embodiment, a method for manufacturing a semiconductor device may include: forming a first stacked structure 10 ( Figure 5 ), forming a second stacked structure 20 ( Figure 6 and Figure 7 ), forming a third stacked structure 30( Figures 8 to 13 ), forming a fourth stacked structure 40 ( Fig.14 ), forming a fifth stacked structure 50 ( Fig.15 ), and forming a sixth stacked structure 60 ( Figures 16 to 19 ).

[0082] refer to Figure 5 , a substrate 1001 may be provided. The substrate 1001 may be the same as that described above. Figure 2A and Figure 2B The described substrate 101 is substantially the same.

[0083] Next, a base insulating layer 1005 may be formed on the substrate 1001. The base insulating layer 1005 may be formed as described above. Figure 2A and Figure 2B The base insulating layer 1005 described above is basically the same. The base insulating layer 1005 can be formed by applying, for example, a chemical vapor deposition method, a sputtering method, or an atomic layer deposition method.

[0084] Subsequently, a first insulating layer 1010a may be formed on the base insulating layer 1005. The first insulating layer 1010a may be formed of or include an insulating material. The insulating material may include, for example, oxide, nitride, or oxynitride. The first insulating layer 1010a may be formed by applying, for example, chemical vapor deposition, sputtering, or atomic layer deposition.

[0085] Subsequently, a first sub-structure 1000a may be formed on the first insulating layer 1010a. The first sub-structure 1000a may include: a first sacrificial layer 1020 formed on the first insulating layer 1010a; a semiconductor layer 1030 formed on the first sacrificial layer 1020; and a second sacrificial layer 1040 formed on the semiconductor layer 1030.

[0086] In one embodiment, the configurations of the first sacrificial layer 1020 and the second sacrificial layer 1040 may be substantially the same as each other. For example, each of the first sacrificial layer 1020 and the second sacrificial layer 1040 may have an etching selectivity relative to the base insulating layer 1005, the first insulating layer 1010a, and the semiconductor layer 1030. Each of the first sacrificial layer 1020 and the second sacrificial layer 1040 may be formed of, for example, an oxide, a nitride, or an oxynitride or include, for example, an oxide, a nitride, or an oxynitride. The first sacrificial layer 1020 and the second sacrificial layer 1040 may be formed by applying a chemical vapor deposition method, a sputtering method, an atomic layer deposition method, or the like.

[0087] In one embodiment, the semiconductor layer 1030 may be formed of or include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs), etc. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include a transition metal dichalcogenide (TMDC) or black phosphorus, etc. The transition metal dichalcogenide (TMDC) may include, for example, molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2 ), indium selenide (InSe) or gallium selenide (GaSe), etc. The semiconductor material may include, for example, a metal oxide, such as indium gallium zinc oxide (IGZO). The semiconductor layer 1030 may be doped with an n-type dopant or a p-type dopant. The conductivity of the semiconductor layer 1030 may vary depending on the amount of the dopant. The semiconductor layer 1030 may be formed by applying, for example, a chemical vapor deposition method, a sputtering method, or an atomic layer deposition method. In one embodiment, when the first insulating layer 1010a is an oxide layer, the first sacrificial layer 1020 and the second sacrificial layer 1040 may be nitride layers, and the semiconductor layer 1030 may be a semiconductor material layer doped with a dopant.

[0088] Next, a second insulating layer 1010b may be formed on the first substructure 1000a. The configuration and manufacturing method of the second insulating layer 1010b may be substantially the same as those of the first insulating layer 1010a.

[0089] Therefore, a second substructure 1000b may be formed on the second insulating layer 1010b. The configuration of the second substructure 1000b may be substantially the same as that of the first substructure 1000a. The second substructure 1000b may include: a first sacrificial layer 1020 formed on the second insulating layer 1010b; a semiconductor layer 1030 formed on the first sacrificial layer 1020; and a second sacrificial layer 1040 formed on the semiconductor layer 1030. The manufacturing method of the second substructure 1000b may be substantially the same as that of the first substructure 1000a.

[0090] Subsequently, a third insulating layer 1010c may be formed on the second substructure 1000b. The configuration and manufacturing method of the third insulating layer 1010c may be substantially the same as the configuration and manufacturing method of the first insulating layer 1010a. Figure 5 The first stacked structure 10 is formed by the related processes.

[0091] refer to Figure 6 , by selectively etching the base insulating layer 1005 Figure 5 The first stack structure 1000 may be formed by forming first trenches T1 exposing the base insulating layer 1005. The first trenches T1 may be formed by applying an anisotropic etching process. In one embodiment, each of the first trenches T1 may be a hole-shaped pattern.

[0092] refer to Figure 7 The first sacrificial layer 1020 and the second sacrificial layer 1040 may be selectively etched in the first trench T1 to form first recessed spaces R1a and R1b. The first recessed spaces R1a and R1b may include a first side space R1a formed by etching the first sacrificial layer 1020 and a second side space R1b formed by etching the second sacrificial layer 1040.

[0093] In one embodiment, the first recessed spaces R1a and R1b may be formed by providing an etchant into the first trench T1 to isotropically etch the first sacrificial layer 1020 and the second sacrificial layer 1040. The isotropic etching may be performed using the etching selectivity of the first sacrificial layer 1020 and the second sacrificial layer 1040 relative to the base insulating layer 1005, the semiconductor layer 1030, and the first to third insulating layers 1010a, 1010b, and 1010c. Figure 6 and Figure 7 The second stacked structure 20 is formed by the related processes.

[0094] refer to Figure 8 , an interface insulating material layer 1100 may be formed on the semiconductor layer 1030. The interface insulating material layer 1100 may be formed of, for example, an oxide, a nitride, or an oxynitride, or include, for example, an oxide, a nitride, or an oxynitride, etc. In one embodiment, the interface insulating material layer 1100 may be formed by chemical vapor deposition, sputtering, or atomic layer deposition, etc. In some embodiments, the interface insulating material layer 1100 may be formed by oxidizing the semiconductor layer 1030.

[0095] refer to Fig. 9, a ferroelectric layer 1200 may be formed along the inner surface of the first trench T1. The ferroelectric layer 1200 may be formed of or include a ferroelectric material. In one embodiment, the ferroelectric material may include a binary metal oxide. As an example, the binary metal oxide may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In another embodiment, the ferroelectric material may include a ternary metal oxide or a higher metal oxide. The ternary or higher metal oxide may include, for example, Pb(Zr,Ti)O 3 , SrBi 2 Ta 2 O 9 , (Bi,La) 4 Ti 3 O 12 ,BiFeO 3 , or a combination of two or more thereof. The ferroelectric layer 1200 may be formed by, for example, chemical vapor deposition or atomic layer deposition.

[0096] Subsequently, a gate electrode layer 1300 may be formed on the ferroelectric layer 1200. The gate electrode layer 1300 may be formed of, for example, a conductive material or include a conductive material. The conductive material may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, or a combination of two or more thereof. The gate electrode layer 1300 may be formed by, for example, chemical vapor deposition or atomic layer deposition.

[0097] refer to Fig.10 , the interface insulating material layer 1100, the ferroelectric layer 1200, and the gate electrode layer 1300 in each first trench T1 may be selectively removed by applying an anisotropic etching method. Therefore, the interface insulating material layer 1100, the semiconductor layer 1030, the ferroelectric layer 1200, the gate electrode layer 1300, and the first to third insulating layers 1010a, 1010b, and 1010c may be exposed to the sidewall surface T1S of the first trench T1.

[0098] refer to Fig.11 , the gate electrode layer 1300 exposed on the sidewall surface T1S of the first trench T1 may be selectively etched to form a second recessed space R2. The second recessed space R2 may be formed by applying an isotropic etching method. In addition, a portion of the semiconductor layer 1030 exposed to the sidewall surface T1S of the first trench T1 may be doped to form a first semiconductor doping region 1030a. The first semiconductor doping region 1030a may be formed by implanting an n-type dopant or a p-type dopant using an ion implantation method.

[0099] refer to Fig.12 , the second recess space R2 and the first trench T1 may be filled with an insulating material 1400. Fig.13 , the insulating material 1400 inside the first trench T1 can be removed by applying an anisotropic etching method. Therefore, the insulating material 1400 can remain in the second recessed space R2. Figures 8 to 13 The third stacked structure 30 is formed by the related processes.

[0100] refer to Fig.14 , can be filled with conductive material Fig.13 The first trench T1 in the gate electrode layer 1300 is formed to form a bit line structure 1500. The bit line structure 1500 may be disposed to be spaced apart from the gate electrode layer 1300. For example, the bit line structure 1500 and the gate electrode layer 1300 may be electrically insulated from each other by the insulating material 1400. Fig.14 The fourth stacked structure 40 is formed by the related processes. The fourth stacked structure 40 includes a bit line structure 1500 disposed inside the first trench T1.

[0101] refer to Fig.15 , can be selectively etched Fig.14 The fourth stack structure 40 is etched to form a second trench T2 exposing the base insulating layer 1005. Specifically, the fourth stack structure 40 may be selectively etched using an anisotropic etching method. The second trench T2 may be disposed to be spaced apart from the bit line structure 1500.

[0102] The method of etching the fourth stack structure 40 by an anisotropic etching method may include removing a portion of each of the first to third insulating layers 1010a, 1010b, and 1010c, the first sacrificial layer 1020, the second sacrificial layer 1040, and the semiconductor layer 1030, and removing Fig.14 A portion of the interface insulating layer 1100 and the ferroelectric layer 1200 are shown.

[0103] refer to Fig.15 The second trench T2 may expose the semiconductor layer 1030, the interface insulating layer 1100, the ferroelectric layer 1200, the gate electrode layer 1300, and the first to third insulating layers 1010a, 1010b, and 1010c on the sidewall surface T2S of the second trench T2. As described above, the fifth stacked structure 50 may be formed by performing the Fig.15 Related processes to form.

[0104] refer to Fig.16 The gate electrode layer 1300 exposed on the sidewall surface T2S of the second trench T2 may be selectively etched to form a third recessed space R3. The third recessed space R3 may be formed by applying an isotropic etching method.

[0105] refer to Fig.17 , can be filled with insulating material 1600 Fig.16 The third recessed space R3 and the second groove T2 are shown. Fig.18 ,exist Fig.17 The insulating material 1600 in the second trench T2 shown in FIG. 1 can be removed by applying an anisotropic etching method. Therefore, the insulating material 1600 can remain in the third recessed space ( Fig.16 In addition, the second semiconductor doping region 1030b may be formed by doping a portion of the semiconductor layer 1030 exposed on the sidewall surface T2S of the second trench T2. As an example, the second semiconductor doping region 1030b may be formed by implanting n-type or p-type dopants using an ion implantation method.

[0106] refer to Fig.19 , can be filled with conductive material Fig.18 The second trench T2 is formed to form a source line structure 1700. The source line structure 1700 may be disposed to be spaced apart from the gate electrode layer 1300. For example, the source line structure 1700 and the gate electrode layer 1300 may be electrically insulated from each other by the insulating material 1600. Figures 16 to 19 The sixth stacked structure 60 is formed by the related processes. As a result, the semiconductor device according to the embodiment of the present disclosure can be manufactured.

[0107] Figure 20 to Figure 25 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Figure 20 to Figure 25 The described method can be used as a reference Figure 3A and Figure 3B In the method for manufacturing the semiconductor device 1b described.

[0108] First, you can execute the above reference Figures 5 to 8 As a result, it is possible to manufacture Fig. 20 The stacked structure shown. Fig. 20 The stacked structure may be a structure in which Figure 7 After the first recessed spaces R1 a and R1 b are formed in the second stacked structure 20 , an interface insulating material layer 1100 is formed on the semiconductor layer 1030 .

[0109] refer to Fig.21 , a conductive material layer 2100 may be formed along the inner surface of the first trench T1. Subsequently, a ferroelectric layer 2200 may be formed on the conductive material layer 2100. A gate electrode layer 2300 may be formed on the ferroelectric layer 2200.

[0110] The conductive material layer 2100 may be formed of or include, for example, a metal, a conductive metal nitride, or a conductive metal oxide. The ferroelectric layer 2200 and the gate electrode layer 2300 may be respectively the same as those described above. Figures 5 to 19 The ferroelectric layer 1200 and the gate electrode layer 1300 of the described method are substantially the same. The conductive material layer 2100, the ferroelectric layer 2200 and the gate electrode layer 2300 may be formed by applying, for example, chemical vapor deposition, sputtering or atomic layer deposition.

[0111] refer to Fig. 22 , can be targeted Fig.21 The stacked structure is implemented with the above reference Fig.10 and Fig.11 The anisotropic etching method and the isotropic etching method are basically the same process. That is, the interface insulating layer 1100, the conductive material layer 2100, the ferroelectric layer 2200 and the gate electrode layer 2300 in the first trench T1 can be selectively removed by applying the anisotropic etching method. Subsequently, the conductive material layer 2100 and the gate electrode layer 2300 exposed on the sidewall surface T1S of the first trench T1 can be selectively etched by applying the isotropic etching method to form a recessed space R20. In addition, the portion of the semiconductor layer 1030 exposed on the sidewall surface T1S of the first trench T1 can be doped to form a first semiconductor doping region 1030a.

[0112] refer to Fig.23 , by sequentially executing and referencing Figure 12 to Figure 14 The process described above is basically the same process, and the recessed space R20 can be filled with an insulating material 1400, and can be Fig. 22 A bit line structure 1500 is formed inside the first trench T1.

[0113] refer to Fig.24 , can be executed sequentially with reference to Figure 15 to Figure 16 The anisotropic etching method and the isotropic etching method described are basically the same process. That is, the anisotropic etching method can be used to selectively etch Fig.23 The stacked structure is formed to form a second trench T2 exposing the base insulating layer 1005. Subsequently, the conductive material layer 2100 exposed on the sidewall surface T2S of the second trench T2 may be selectively etched by adopting an isotropic etching method to form a recessed space R30.

[0114] refer to Fig.25 , can be executed sequentially with reference to Figures 17 to 19 The process described is basically the same process. It can be filled with insulating material 1600 Fig.24The recessed space R30 and the second trench T2 are formed, and then the insulating material 1600 inside the second trench T2 can be removed by applying an anisotropic etching method. Subsequently, the portion of the semiconductor layer 1030 exposed on the sidewall surface T2S of the second trench T2 can be doped to form a second semiconductor doping region 1030b. Subsequently, a source line structure 1700 can be formed in the second trench T2. As a result, a semiconductor device according to an embodiment of the present disclosure can be manufactured.

[0115] Figures 26 to 30 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to yet another embodiment of the present disclosure. Figures 26 to 30 The described method can be applied to reference Figure 4A and Figure 4B A method for manufacturing a semiconductor device 1c is described.

[0116] refer to Fig.26 , a substrate 1001 may be provided. A base insulating layer 1005 may be formed on the substrate 1001. A first insulating layer 1010a may be formed on the base insulating layer 1005. A first substructure 3000a may be formed on the first insulating layer 1010a. The first substructure 3000a may include: a semiconductor layer 1030 formed on the first insulating layer 1010a; and a sacrificial layer 1040a formed on the semiconductor layer 1030. Figure 5 Compared with the first substructure 1000a, Fig.26 In the first substructure 3000 a , no sacrificial layer is disposed between the first insulating layer 1010 a and the semiconductor layer 1030 .

[0117] Subsequently, a second insulating layer 1010b may be formed on the first substructure 3000a. A second substructure 3000b may be formed on the second insulating layer 1010b. The configuration of the second substructure 3000b may be substantially the same as that of the first substructure 3000a. A third insulating layer 1010c may be formed on the second substructure 3000b. As a result, a first stacked structure 10a may be formed on the base insulating layer 1005.

[0118] refer to Fig. 27 , the above-referenced steps may be sequentially performed on the first stacked structure 10a. Figure 6 and Figure 7 The process described above is substantially the same as the process described above. That is, the trench T11 exposing the base insulating layer 1005 can be formed by selectively etching the first stacked structure 10a on the base insulating layer 1005. Subsequently, the sacrificial layer 1040a exposed on the sidewall surface of the trench T11 can be selectively etched to form a recessed space R11. Therefore, the second stacked structure 20a can be formed.

[0119] Since the sacrificial layer 1040a is formed only on Fig.26 On the surface of the semiconductor layer 1030 in each of the first substructure 3000a and the second substructure 3000b of the first stacked structure 10a, Fig. 27 As shown, an upper surface 1030US and a side surface 1030SS of a portion of the semiconductor layer 1030 may be exposed after forming the recess space R11 .

[0120] refer to Fig.28 , an interface insulating layer 3100 may be formed on the upper surface 1030US and the side surface 1030SS of the above-mentioned portion of the semiconductor layer 1030. The interface insulating layer 3100 may be composed of Figure 8 The interface insulating layer 1100 is formed of substantially the same material.

[0121] refer to Fig.29 , you can execute the same as above reference Fig. 9 The process described above is basically the same process. That is, it can be carried out along Fig.28 The ferroelectric layer 3200 is formed on the inner surface of the trench T11. A gate electrode layer 3300 may be formed on the ferroelectric layer 3200. The ferroelectric layer 3200 and the gate electrode layer 3300 may be respectively formed of Fig. 9 The ferroelectric layer 1200 and the gate electrode layer 1300 are made of substantially the same material.

[0122] Subsequently, the above references can be performed sequentially. Figures 10 to 19 The process described is essentially the same process. Results, such as Fig.30 As shown, a semiconductor device according to an embodiment of the present disclosure can be manufactured.

[0123] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the accompanying claims.

Claims

1. A semiconductor device, comprising: substrate; a bit line structure and a source line structure, each extending in a direction perpendicular to a surface of the substrate; a semiconductor layer disposed on a plane parallel to the surface of the substrate and between the bit line structure and the source line structure; a first ferroelectric layer disposed on an upper surface of the semiconductor layer; and a first gate electrode layer disposed on the first ferroelectric layer, Wherein, the semiconductor layer comprises: a source region in contact with the bit line structure; a drain region in contact with the source line structure; and a channel region disposed between the source region and the drain region, The source region and the drain region are both doped with the same type of dopant, and the channel region is doped with a dopant of a different type from that of the source region and the drain region.

2. The semiconductor device according to claim 1, further comprising: a second ferroelectric layer disposed on a lower surface of the semiconductor layer opposite to the upper surface; and A second gate electrode layer is disposed on the second ferroelectric layer.

3. The semiconductor device according to claim 2, wherein: The first gate electrode layer and the second gate electrode layer are connected through a conductive via.

4. The semiconductor device according to claim 2, wherein: The first gate electrode layer and the second gate electrode layer are electrically isolated from each other.

5. The semiconductor device according to claim 1, further comprising: A bit line insulating layer and a source line insulating layer are arranged on the side wall of the first gate electrode layer, The bit line insulating layer electrically insulates the bit line structure from the first gate electrode layer, and the source line insulating layer electrically insulates the source line structure from the first gate electrode layer.

6. The semiconductor device according to claim 1, further comprising: An interface insulating layer is disposed between the semiconductor layer and the first ferroelectric layer.

7. The semiconductor device according to claim 1, further comprising: an electrically floating layer, the electrically floating layer being disposed between the semiconductor layer and the first ferroelectric layer, Wherein, the electrically floating layer is conductive.

8. A semiconductor device comprising: substrate; a bit line structure and a source line structure, each extending in a direction perpendicular to a surface of the substrate; and a plurality of unit cell structures electrically connected to the bit line structure and the source line structure, Wherein, each of the plurality of unit cell structures comprises: a semiconductor layer disposed on a plane parallel to the surface of the substrate and in contact with the bit line structure and the source line structure; A first ferroelectric layer disposed on an upper surface of the semiconductor layer; and a first gate electrode layer disposed on the first ferroelectric layer and spaced apart from the bit line structure and the source line structure, wherein the plurality of unit cell structures are arranged to be spaced apart from each other in a direction perpendicular to the surface of the substrate, Wherein, the semiconductor layer comprises: a source region in contact with the bit line structure; a drain region in contact with the source line structure; and A channel region is disposed between the source region and the drain region.

9. The semiconductor device according to claim 8, further comprising: a second ferroelectric layer disposed on a lower surface of the semiconductor layer opposite to the upper surface; and A second gate electrode layer is disposed on the second ferroelectric layer and is spaced apart from the bit line structure and the source line structure.

10. The semiconductor device according to claim 8, further comprising: An interface insulating layer is disposed between the semiconductor layer and the first ferroelectric layer.

11. The semiconductor device according to claim 8, further comprising: an electrically floating layer, the electrically floating layer being disposed between the semiconductor layer and the first ferroelectric layer, Wherein, the electrically floating layer is conductive.

12. A method for manufacturing a semiconductor device, the method comprising: providing a substrate including a base insulating layer; forming a first stacked structure on the base insulating layer, the first stacked structure comprising: a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer being arranged to be spaced apart from each other in a direction perpendicular to a surface of the substrate; and a substructure arranged between the first insulating layer and the second insulating layer, wherein the substructure comprises a semiconductor layer and at least one sacrificial layer; Selectively etching the first stacked structure on the base insulating layer to form a second stacked structure, the second stacked structure comprising a first groove and a first recessed space, the first groove being formed to expose the base insulating layer, and the first recessed space being formed by selectively etching the at least one sacrificial layer in the first groove; forming a third stacked structure, the third stacked structure comprising a plurality of material layers arranged in the first recessed space of the second stacked structure, the plurality of material layers comprising: an interface insulating layer arranged on the semiconductor layer, a ferroelectric layer at least covering the interface insulating layer, and a gate electrode layer arranged on the ferroelectric layer; forming a fourth stacked structure including a bit line structure disposed on the base insulating layer and in the first trench of the third stacked structure; selectively etching the fourth stacked structure on the base insulating layer to form a fifth stacked structure, the fifth stacked structure comprising a second trench exposing the base insulating layer, the second trench exposing the semiconductor layer, the interface insulating layer, the ferroelectric layer, the gate electrode layer, and the first insulating layer and the second insulating layer on a sidewall surface of the second trench; and A sixth stacked structure is formed, which includes a source line structure disposed in the second trench of the fifth stacked structure.

13. The method according to claim 12, wherein: The step of forming a first stacked structure comprises: forming the first insulating layer on the base insulating layer; forming a first sacrificial layer on the first insulating layer; forming the semiconductor layer on the first sacrificial layer; forming a second sacrificial layer on the semiconductor layer; and forming the second insulating layer on the second sacrificial layer, Wherein, each of the first sacrificial layer and the second sacrificial layer has an etching selectivity relative to the semiconductor layer, the first insulating layer and the second insulating layer.

14. The method according to claim 12, wherein: The step of forming the first stacked structure comprises: forming the first insulating layer on the base insulating layer; forming the semiconductor layer on the first insulating layer; forming a first sacrificial layer on the semiconductor layer; and forming the second insulating layer on the first sacrificial layer, and The first sacrificial layer has an etching selectivity relative to the semiconductor layer, the first insulating layer and the second insulating layer.

15. The method according to claim 12, wherein: The step of forming the third stacked structure comprises: forming the interface insulating layer on the semiconductor layer exposed by the first recessed space; forming the ferroelectric layer along the inner surface of the first trench; forming the gate electrode layer on the ferroelectric layer; and selectively removing the interface insulating layer, the ferroelectric layer and the gate electrode layer in the first trench by adopting an anisotropic etching method, and The interface insulating layer, the semiconductor layer, the ferroelectric layer, the gate electrode layer, and the first and second insulating layers are exposed to sidewall surfaces of the first trench.

16. The method according to claim 15, further comprising: Selectively etching the gate electrode layer exposed on the sidewall surface of the first trench to form a second recessed space; as well as The second recessed space is filled with an insulating material.

17. The method according to claim 15, further comprising: A portion of the semiconductor layer exposed to the sidewall surface of the first trench is doped to form a first semiconductor doping region.

18. The method according to claim 12, in, The step of forming the fourth stacked structure includes: filling the first trench of the third stacked structure with a conductive material to form the bit line structure, and The bit line structure is arranged to be spaced apart from the gate electrode layer.

19. The method according to claim 12, in, The step of forming the fifth stack structure includes: anisotropically etching the fourth stack structure to form the second trench, the second trench being arranged to be spaced apart from the bit line structure, and Wherein, anisotropically etching the fourth stacked structure includes: removing a portion of the semiconductor layer, a portion of the interface insulating layer, a portion of the ferroelectric layer, a portion of the at least one sacrificial layer, a portion of the first insulating layer, and a portion of the second insulating layer.

20. The method of claim 12, further comprising: After forming the fifth stacked structure, selectively etching the gate electrode layer exposed to the sidewall surface of the second trench to form a second recessed space; Filling the second recessed space with an insulating material; as well as A portion of the semiconductor layer exposed to the sidewall surface of the second trench is doped to form a second semiconductor doping region.

21. The method according to claim 12, in, The step of forming the sixth stacked structure includes: filling the second trench of the fifth stacked structure with a conductive material to form the source line structure, and Wherein, the source line structure is arranged to be spaced apart from the gate electrode layer.

22. The method according to claim 12, wherein: The step of forming the third stacked structure comprises: forming the interface insulating layer on the semiconductor layer exposed by the first recessed space; forming a conductive material layer along the inner surface of the first groove; forming the ferroelectric layer on the conductive material layer; forming the gate electrode layer on the ferroelectric layer; and removing the interface insulating layer, the conductive material layer, the ferroelectric layer and the gate electrode layer in the first trench by an anisotropic etching process, and The semiconductor layer, the interface insulating layer, the conductive material layer, the ferroelectric layer, the gate electrode layer, and the first and second insulating layers are exposed to the sidewall surfaces of the first trench.

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