Array substrate and preparation method thereof, display panel, and display device

Abstract

The present invention relates to the field of display technology, and discloses an array substrate and a preparation method thereof, a display panel, and a display device. The array substrate comprises: a base substrate, a first metal layer, a metal oxide layer, and a second metal layer stacked in sequence and isolated from each other on the base substrate; the first metal layer comprises a light-shielding metal, a first electrode, and an anti-static wiring; the metal oxide layer comprises a first active layer, and the second metal layer comprises a gate line and a second electrode; the gate line and the anti-static wiring are connected through a first TFT, one of the first electrode and the second electrode forms a source and drain of the first TFT, and the other forms a gate of the first TFT; the source is electrically connected to the gate line, and the drain is electrically connected to the anti-static wiring. In the array substrate, the overall structure of the anti-static structure is simple and compact, and does not require preparation across multiple conductive layers. The anti-static structure is formed earlier, and the static electricity accumulated during dry etching or exposure during preparation is channeled from the gate line to the anti-static wiring to be consumed.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] In the existing OLED substrate structure design, an anti-static structure is set up, but the anti-static structure in the existing technology is relatively complicated, and the preparation process involves many steps. Often, the preparation can only be completed after many conductive layer steps to achieve the static electricity conduction effect. As a result, some metal layer preparation processes cannot conduct the large amount of static electricity accumulated during dry etching or exposure, which can easily cause static electricity breakdown. Summary of the invention

[0003] The present invention discloses an array substrate and a preparation method thereof, a display panel, and a display device. In the array substrate, the antistatic structure has a simple overall structure and a compact structure, with fewer preparation steps and no need to cross multiple conductive layers. When the gate line is formed, the antistatic structure is also formed, and the static electricity accumulated during the preparation process due to dry etching or exposure can be conducted from the gate line to the antistatic wiring, and the static electricity is consumed on the antistatic wiring. The phenomenon of short circuit caused by electrostatic breakdown at the intersection of the gate and the active layer in the pixel unit during the preparation process can be effectively avoided, and electrostatic breakdown in the overlapping area between the antistatic wiring and the gate line can be avoided, reducing the short circuit between the two metal layers in the overlapping area, thereby effectively reducing the bright spot phenomenon caused by the short circuit, and effectively improving the product yield.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] An array substrate comprises: a base substrate, and a first metal layer, a metal oxide layer and a second metal layer sequentially stacked and isolated from each other on the base substrate;

[0006] The first metal layer includes a light-shielding metal, a first electrode, and an anti-static wiring, and the anti-static wiring is located in a peripheral wiring area of ​​the substrate; the metal oxide layer includes a first active layer; the second metal layer includes a gate line and a second electrode;

[0007] Among them, the gate line is connected to the anti-static wiring through a first TFT, and the first electrode, the first active layer and the second electrode constitute the first TFT, one of the first electrode and the second electrode forms the source and drain of the first TFT, and the other forms the gate of the first TFT; the first active layer is connected to the source and drain of the first TFT through a conductive structure, and the distance between the surface of the conductive structure away from the substrate and the substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate and the substrate; the source of the first TFT is electrically connected to the gate line, and the drain of the first TFT is electrically connected to the anti-static wiring; and a first capacitor is formed between the gate of the first TFT and the source of the first TFT, and a second capacitor is formed between the gate of the first TFT and the drain of the first TFT.

[0008] The above-mentioned array substrate includes a base substrate, which is divided into a display area and a peripheral wiring area located on the periphery of the display area. A first metal layer is arranged on the base substrate, and the first metal layer is used to form a shading metal, a first electrode, and an anti-static wiring. The shading metal, the first electrode, and the anti-static wiring are prepared and formed by the same layer of metal. The shading metal is used to shading in the display area, and the first electrode and the anti-static wiring are arranged in the peripheral wiring area; a metal oxide layer is formed on the first metal layer, and the metal oxide layer is isolated from the first metal layer. The metal oxide layer includes a first active layer, and a second metal layer is arranged on the metal oxide layer, and the first metal layer and the metal oxide layer are isolated from each other. The material of the second metal layer can be copper or aluminum, or other conductive metals, which is not limited to this embodiment; the second metal layer is used to form a gate line and a second electrode, wherein the gate line and the anti-static wiring are The electrostatic lines are connected through the first TFT, and the first electrode, the first active layer and the second electrode constitute the first TFT. One of the first electrode and the second electrode forms the source and drain of the first TFT, that is, forms the source and drain of the first TFT, and the other forms the gate of the first TFT. The first active layer and the source and drain of the first TFT can be connected through a conductive structure. Relative to the substrate, the top surface of the conductive structure is lower than the top surface of the second metal layer, or the top surface of the conductive structure is flush with the top surface of the second metal layer. The conductive structure is a conductive layer formed before the second metal layer is formed or is a part of the second metal layer. Since the first TFT is formed by the first electrode, the first active layer and the second electrode, the conductive structure is also a part of the first TFT. The conductive structure plays a role in connecting the upper and lower layers, and the conductive structure is a part of the first active layer or the second electrode.The source of the first TFT is electrically connected to the gate line, the drain of the first TFT is electrically connected to the anti-static wiring, a first capacitor is formed between the gate of the first TFT and the first source, a second capacitor is formed between the gate of the first TFT and the drain of the first TFT, the first TFT is connected between the gate line and the anti-static wiring, when there is more static electricity on the gate line, the source of the first TFT is electrically connected to the gate line, and the voltage is the same as the gate line, the gate line accumulates more static electricity, the voltage of the gate line is higher, then the source voltage of the first TFT is higher, there is a first capacitor between the first TFT and the gate of the first TFT, then the gate of the first TFT forms a high potential, the first TFT is turned on, the source and drain of the first TFT are connected, and then the static electricity of the gate line is diverted to the anti-static wiring. In the structure of the above-mentioned array substrate, after the gate line layer is formed, the anti-static wiring in the anti-static structure and the connection between the anti-static wiring and the gate line The first TFT is formed, and the antistatic structure can form a conductive structural circuit by relying on only three conductive layers, namely, the first metal layer, the metal oxide layer and the second metal layer. The overall antistatic structure is very simple and can complete the electrostatic drainage. The antistatic structure is formed earlier in the preparation process of the array substrate, and can play a drainage role for the static electricity on the gate line; in the preparation process, the large static electricity accumulated due to etching or exposure will be drained from the gate line to the antistatic routing by the already formed antistatic structure, and the antistatic routing will consume the static electricity, thereby eliminating the static electricity, and can effectively avoid the phenomenon of short circuit caused by electrostatic breakdown at the intersection of the gate and the active layer in the sub-pixel unit during the preparation process, and can avoid electrostatic breakdown in the overlapping area of ​​the antistatic routing and the gate line, reduce the short circuit between the two metal layers with the overlapping area, and then effectively reduce the bright spot phenomenon caused by the short circuit, and effectively improve the product yield. ;

[0009] Therefore, in the above-mentioned array substrate, the overall structure of the anti-static structure is simple and compact, with fewer preparation steps and no need to cross multiple conductive layers. When the gate line is formed, the anti-static structure is also formed, and the static electricity accumulated during the preparation process due to dry etching or exposure can be conducted from the gate line to the anti-static routing. The static electricity is consumed on the anti-static routing, which can effectively avoid the phenomenon of short circuit caused by electrostatic breakdown at the intersection of the gate and the active layer in the pixel unit during the preparation process, and can avoid electrostatic breakdown in the overlapping area between the anti-static routing and the gate line, reduce the short circuit between the two layers of metal in the overlapping area, and effectively reduce the bright spot phenomenon caused by short circuit, thereby effectively improving the product yield.

[0010] Optionally, the first electrode forms a source and a drain of the first TFT, and the second electrode forms a gate of the first TFT.

[0011] Optionally, the first active layer includes a channel region opposite to the gate of the first TFT, and a first conductive region and a second conductive region respectively located on both sides of the channel region, the first conductive region and the second conductive region constitute the conductive structure, and the first conductive region is connected to the source of the first TFT, and the second conductive region is connected to the drain of the first TFT.

[0012] Optionally, the first electrode forms a gate of the first TFT, and the second electrode forms a source and drain of the first TFT.

[0013] Optionally, the first active layer includes a channel region opposite to the gate of the first TFT, and a first conductive region and a second conductive region respectively located on both sides of the channel region, and the second electrode is also formed with a first connecting metal and a second connecting metal, the first connecting metal and the second connecting metal constitute the conductive structure, the first connecting metal and the second connecting metal constitute the conductive structure, the first connecting metal is connected to the first conductive region, and the second connecting metal is connected to the second conductive region.

[0014] Optionally, the gate electrode of the first TFT partially overlaps with the source electrode of the first TFT to form the first capacitor, and the gate electrode of the first TFT partially overlaps with the drain electrode of the first TFT to form the second capacitor.

[0015] Optionally, the anti-static wiring is a ring-shaped wiring, and the anti-static wiring is arranged around the display area of ​​the array substrate.

[0016] Optionally, an orthographic projection of the gate line on the base substrate overlaps with an orthographic projection of the antistatic wiring on the base substrate, and a hollow structure is provided at a portion where the antistatic wiring overlaps with the gate line.

[0017] Optionally, the array substrate further includes:

[0018] a buffer layer disposed between the first metal layer and the metal oxide layer;

[0019] A gate insulating layer is disposed between the metal oxide layer and the second metal layer.

[0020] Optionally, the metal oxide layer further includes a second active layer located in a sub-pixel unit of the array substrate;

[0021] The second metal layer further includes a second gate located in the sub-pixel unit and corresponding to the second active layer;

[0022] An interlayer insulating layer is disposed on the second metal layer, a third metal layer is formed on the interlayer insulating layer, and the third metal layer includes a second source electrode and a second drain electrode electrically connected to the second active layer.

[0023] The present invention further provides a display panel, comprising any one of the array substrates provided by the above technical solution.

[0024] The present invention also provides a display device, comprising any display panel provided by the above technical solution.

[0025] The present invention also provides a method for preparing any one of the array substrates provided by the above technical solutions, comprising:

[0026] Forming a first metal layer on the base substrate, wherein the first metal layer includes a light-shielding metal, a first electrode, and an anti-static wiring, wherein the anti-static wiring is located in a peripheral wiring area of ​​the base substrate;

[0027] forming a metal oxide layer on the first metal layer, the metal oxide layer being isolated from the first metal layer, and the metal oxide layer comprising a first active layer;

[0028] forming a second metal layer on the first metal layer, the second metal layer and the metal oxide layer being isolated from each other, the second metal layer comprising a gate line and a second electrode;

[0029] Among them, the gate line is connected to the anti-static wiring through a first TFT, and the first electrode, the first active layer and the second electrode constitute the first TFT, one of the first electrode and the second electrode forms the source and drain of the first TFT, and the other forms the gate of the first TFT; the first active layer is connected to the source and drain of the first TFT through a conductive structure, and the distance between the surface of the conductive structure away from the substrate and the substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate and the substrate; the source of the first TFT is electrically connected to the gate line, the drain of the first TFT is electrically connected to the anti-static wiring, and a first capacitor is formed between the gate of the first TFT and the source of the first TFT, and a second capacitor is formed between the gate of the first TFT and the drain of the first TFT. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a top view structure of an array substrate provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a partial structure of an array substrate provided by an embodiment of the present invention;

[0032] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure along the AA direction;

[0033] Figure 4 A schematic diagram of a partial structure of an array substrate provided by an embodiment of the present invention;

[0034] Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the BB direction;

[0035] Figure 6 A schematic diagram of an equivalent circuit of a first TFT provided by an embodiment of the present invention;

[0036] Icon: 1-array substrate; 2-first electrode; 3-antistatic wiring; 4-gate line; 5-second electrode; 6-first TFT; 7-hollow structure; 8-first connection metal; 9-second connection metal; 10-buffer layer; 11-first active layer; 12-gate insulation layer; 13-passivation layer; 14-first conductive area; 15-second conductive area. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] like Figures 1 to 3 as well as Figure 6As shown, an embodiment of the present invention provides an array substrate, comprising: a base substrate 1; and a first metal layer, a metal oxide layer, and a second metal layer stacked in sequence and isolated from each other on the base substrate 1; the first metal layer comprises a light-shielding metal, a first electrode 2, and an anti-static wiring 3, and the anti-static wiring 3 is located in the peripheral wiring area of ​​the base substrate; the metal oxide layer comprises a first active layer 11; the second metal layer comprises a gate line 4, and a second electrode 5; wherein the gate line 4 is connected to the anti-static wiring 3 through a first TFT 6, the first electrode 2, the first active layer 11, and the second electrode 5 constitute a first TFT 6, and the first electrode 2 and the second electrode 5 constitute a first TFT 6. 5, one of them forms the source and drain of the first TFT6, and the other forms the gate of the first TFT6; the first active layer is connected to the source and drain of the first TFT through a conductive structure, and the distance between the surface of the conductive structure away from the substrate substrate and the substrate substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate substrate and the substrate substrate; the source of the first TFT6 is electrically connected to the gate line 4, and the drain of the first TFT6 is electrically connected to the anti-static wiring 3; and a first capacitor is formed between the gate of the first TFT6 and the source of the first TFT6, and a second capacitor is formed between the gate of the first TFT6 and the drain of the first TFT6.

[0039] The above-mentioned array substrate includes a base substrate, which is divided into a display area and a peripheral wiring area located on the periphery of the display area. A first metal layer is arranged on the base substrate, and the first metal layer is used to form a shading metal, a first electrode 2, and an anti-static wiring 3. The shading metal, the first electrode 2, and the anti-static wiring 3 are prepared and formed by the same layer of metal. The shading metal is used to shading in the display area, and the first electrode 2 and the anti-static wiring 3 are arranged in the peripheral wiring area; a metal oxide layer is formed on the first metal layer, and the metal oxide layer is isolated from the first metal layer. The metal oxide layer includes a first active layer 11, and a second metal layer is arranged on the metal oxide layer, and the second metal layer is isolated from the metal oxide layer. The material of the second metal layer can be copper or aluminum, or other conductive metals, which is not limited to this embodiment; the second metal layer is used to form a gate line 4 and a second electrode 5, wherein the gate line 4 and the anti-static The wirings 3 are connected through the first TFT 6, and the first electrode 2, the first active layer 11 and the second electrode 5 constitute the first TFT 6. One of the first electrode 2 and the second electrode 5 forms the source and drain of the first TFT 6, that is, forms the source and drain of the first TFT 6, and the other forms the gate of the first TFT 6. The first active layer and the source and drain of the first TFT can be connected through a conductive structure. Relative to the substrate, the top surface of the conductive structure is lower than the top surface of the second metal layer, or the top surface of the conductive structure is flush with the top surface of the second metal layer. The conductive structure is a conductive layer formed before the second metal layer is formed or is a part of the second metal layer. Since the first TFT is formed by the first electrode 2, the first active layer and the second electrode 5, the conductive structure is also a part of the first TFT. The conductive structure plays a role in connecting the upper and lower layers, and the conductive structure is a part of the first active layer or the second electrode.The source of the first TFT6 is electrically connected to the gate line 4, the drain of the first TFT6 is electrically connected to the anti-static wiring 3, a first capacitor C1 is formed between the gate of the first TFT6 and the first source, a second capacitor C2 is formed between the gate of the first TFT6 and the drain of the first TFT6, the first TFT6 is connected between the gate line 4 and the anti-static wiring 3, when there is more static electricity on the gate line 4, the source of the first TFT6 is electrically connected to the gate line 4, and the voltage of the gate line 4 is the same, the gate line 4 accumulates more static electricity, the voltage of the gate line 4 is higher, then the source voltage of the first TFT6 is higher, and the first capacitor C1 is formed between the first TFT6 and the gate of the first TFT6 , then the gate electrode GT of the first TFT6 forms a high potential, the first TFT6 is turned on, the source and drain of the first TFT6 are connected, and then the static electricity of the gate line 4 is conducted to the anti-static wiring 3. Specifically, a plurality of gate lines are arranged on the substrate, each of which is provided with a first TFT connected to the anti-static wiring. With respect to one gate line, a first TFT connected to the anti-static wiring can be arranged at both ends of the gate line, or a first TFT connected to the anti-static wiring can be arranged at one end of the gate line, or three first TFTs are arranged, each of which is used to connect the gate line and the anti-static wiring. It should be noted that a first The number and position of TFTs can be set according to actual needs, and this embodiment does not limit this. In the structure of the above-mentioned array substrate, after the gate line 4 layer is formed, the antistatic wiring 3 in the antistatic structure and the first TFT 6 connecting the antistatic wiring 3 and the gate line 4 are formed. The antistatic structure can form a conductive structural circuit by relying on only three conductive layers, namely the first metal layer, the metal oxide layer and the second metal layer. The overall antistatic structure is very simple and can conduct static electricity. The antistatic structure is simple and reliable, with fewer preparation processes. It is formed earlier in the preparation process of the array substrate and can conduct static electricity on the gate line 4. In the preparation process, due to The large static electricity accumulated by etching or exposure will be conducted from the gate line 4 to the antistatic routing line 3 by the antistatic structure that has been formed. The antistatic routing line 3 will consume the static electricity, thereby eliminating the static electricity. During the preparation process, the phenomenon of short circuit caused by static electricity breakdown at the intersection of the gate and the active layer in the sub-pixel unit can be effectively avoided, and the static electricity breakdown in the overlapping area of ​​the antistatic routing line 3 and the gate line 4 can be avoided, and the short circuit between the two layers of metal with the overlapping area can be reduced, thereby effectively reducing the bright spot phenomenon caused by the short circuit, effectively improving the product yield, and after the product is completed, the antistatic structure can play a role in electrostatic protection, forming a protective effect on the circuit routing in the product. ;

[0040] Therefore, in the above-mentioned array substrate, the overall structure of the anti-static structure is simple and compact, with fewer preparation steps and no need to cross many layers of conductive layers. When the gate line is formed, the anti-static structure is also formed, and the static electricity accumulated during the preparation process due to dry etching or exposure can be conducted from the gate line to the anti-static routing. The static electricity is consumed on the anti-static routing, which can effectively avoid the phenomenon of short circuit caused by electrostatic breakdown at the intersection of the gate and the active layer in the pixel unit during the preparation process, and can avoid electrostatic breakdown in the overlapping area between the anti-static routing and the gate line, reduce the short circuit between the two layers of metal in the overlapping area, and effectively reduce the bright spot phenomenon caused by short circuit, effectively improving the product yield.

[0041] Specifically, the array substrate further includes: a buffer layer 10 which is arranged between the first metal layer and the metal oxide layer and is stacked in sequence, and a gate insulating layer 12 which is arranged between the metal oxide layer and the second metal layer, wherein the buffer layer plays an insulating role to separate the stacked first metal layer from the metal oxide, and the gate insulating layer plays an insulating role to separate the stacked metal oxide from the second metal layer; wherein the metal oxide layer also includes a second active layer located in the sub-pixel unit, and the second metal layer also includes a second gate located in the sub-pixel unit and corresponding to the second active layer; an interlayer insulating layer is arranged on the second metal layer, and a third metal layer is formed on the interlayer insulating layer, and the material of the third metal layer can be copper or aluminum; the third metal layer includes a second source and a second drain which are electrically connected to the second active layer, and the second gate, the second active layer, the second source and the second drain constitute a second TFT, and the second TFT switch can be a pixel TFT switch in the sub-pixel circuit.

[0042] Specifically, a passivation layer 13 is disposed on the third metal layer. The material of the passivation layer 13 may be SiOx, and the thickness of the passivation layer 13 may be 3000 angstroms to 5000 angstroms.

[0043] Among them, in the above array substrate, there are multiple optional configurations for the configuration of the first electrode 2 and the second electrode 5, such as:

[0044] Method 1:

[0045] like Figure 2 and Figure 3 As shown, the first electrode 2 can be formed as the source and drain of the first TFT6, and the second electrode 5 can be formed as the gate of the first TFT6, that is, the first electrode 2 forms the source and drain of the first TFT6, the source and drain of the first TFT6 are prepared and formed in the same layer as the shading metal and the antistatic wiring 3, and the drain of the first TFT6 is electrically connected to the antistatic wiring 3; the second electrode 5 is set as the gate of the first TFT6, the gate of the first TFT6 is prepared and formed in the same layer as the gate line 4, and the gate line 4 is electrically connected to the source of the first TFT6.

[0046] Specifically, in the first embodiment, in the first TFT, the conductive structure connecting the source and drain of the first TFT and the first active layer 11 can be a part of the first active layer 11, wherein the first active layer includes a channel region opposite to the gate of the first TFT, and the channel region is provided with a first conductive region 14 and a second conductive region 15, respectively, wherein the first conductive region and the second conductive region can be provided to form the conductive structure, the first conductive region extends and is connected to the source of the first TFT 6 by extending into the first via hole, and the second conductive region extends and is connected to the drain of the first TFT by extending into the second via hole, thereby realizing the connection between the source and drain of the first active layer and the first TFT. In addition, since the source and drain of the first TFT and the antistatic wiring are prepared and formed in the same layer, the drain of the first TFT can be directly connected to the antistatic wiring when preparing the pattern of the first metal layer, which is simple and reliable; for the connection between the gate line and the source of the first TFT, the gate line 4 can be provided to be connected to the source of the first TFT 6 through the third via hole, which is simple and reliable.

[0047] Method 2:

[0048] like Figure 4 and Figure 5 As shown, the first electrode 2 forms the gate of the first TFT6, and the second electrode 5 forms the source and drain of the first TFT6, that is, the first electrode 2 is set as the gate of the first TFT6, and the gate of the first TFT6 is prepared and formed in the same layer as the shading metal and the antistatic wiring 3; the second electrode 5 is set as the source and drain of the first TFT6, and the source and drain of the first TFT6 are prepared and formed in the same layer as the gate line 4, the gate line 4 is electrically connected to the source of the first TFT6, and the antistatic wiring 3 is electrically connected to the drain of the first TFT6.

[0049] Specifically, in the above-mentioned method 2, the first active layer 11 includes a channel region opposite to the gate of the first TFT, and a first conductive region 14 and a second conductive region 14 respectively located on both sides of the channel region. A first connecting metal 8 and a second connecting metal 9 may also be formed in the second electrode 5. The first connecting metal and the second connecting metal may constitute a conductive structure connecting the first active layer and the source and drain of the first TFT, wherein the first connecting metal is directly connected to the source of the TFT, and the first connecting metal may be connected to the first conductive region of the first active layer by extending into the fourth via hole, the second connecting metal is directly connected to the drain of the first TFT, and the second connecting metal may be connected to the second conductive region of the first active layer by extending into the fifth via hole; since the gate line and the source and drain of the first TFT are prepared and formed in the same layer, the gate line may be directly connected to the source of the first TFT to achieve electrical connection, which is simple, reliable and convenient to prepare; the drain of the first TFT may be connected to the antistatic wiring through the sixth via hole, which has a simple structure and is easy to prepare.

[0050] Specifically, in the above-mentioned array substrate, a part of the projection of the gate of the first TFT6 in the direction perpendicular to the substrate can be set to overlap with a part of the projection of the source of the first TFT6 in the direction perpendicular to the substrate, that is, the gate of the first TFT6 and the source of the first TFT6 are set to partially overlap to form a first capacitor; and a part of the projection of the gate of the first TFT6 in the direction perpendicular to the substrate is set to overlap with a part of the projection of the drain of the first TFT6 in the direction perpendicular to the substrate, and the gate of the first TFT6 and the drain of the first TFT6 are set to partially overlap to form a second capacitor.

[0051] like Figure 1 As shown, in the above-mentioned array substrate, the anti-static wiring 3 is a ring wiring, and the anti-static wiring 3 is arranged around the display area of ​​the base substrate. The anti-static wiring 3 is directly arranged in a ring shape and arranged around the display area of ​​the base substrate, which can better consume and eliminate static electricity.

[0052] Specifically, Figure 2 As shown, the orthographic projection of the gate line 4 on the substrate overlaps with the orthographic projection of the anti-static wiring 3 on the substrate, and a hollow structure 7 is provided at the portion of the anti-static wiring 3 that overlaps with the gate line 4. The hollow structure 7 is provided at the portion of the anti-static wiring 3 that overlaps with the gate line 4, which can effectively avoid the generation of parasitic capacitance at the overlapping portion of the anti-static wiring 3 and the gate line 4, and effectively avoid electrostatic breakdown.

[0053] This embodiment further provides a display panel, comprising any array substrate provided by the above technical solution.

[0054] This embodiment also provides a display device, including any display panel provided by the above technical solution.

[0055] Based on the same inventive concept, Figure 1 , Figure 2 as well as Figure 3 This embodiment further provides a method for preparing any one of the array substrates provided in the above embodiments, including:

[0056] Step S101, forming a first metal layer on a base substrate, the first metal layer comprising a light shielding metal, a first electrode 2, and an anti-static wiring 3, the anti-static wiring 3 being located in a peripheral wiring area of ​​the base substrate;

[0057] Step S102, forming a metal oxide layer on the first metal layer, wherein the metal oxide layer and the first metal layer are isolated from each other, and the metal oxide layer includes a first active layer;

[0058] Step S103, forming a second metal layer on the first metal layer, the second metal layer and the first metal layer are isolated from each other, and the second metal layer includes a gate line 4 and a second electrode 5;

[0059] Among them, the gate line 4 is connected to the anti-static wiring 3 through the first TFT6, the first electrode, the first active layer and the second electrode constitute the first TFT, one of the first electrode 2 and the second electrode 5 forms the source and drain of the first TFT6, and the other forms the gate of the first TFT6; the first active layer and the source and drain of the first TFT are connected through a conductive structure, and the distance between the surface of the conductive structure away from the substrate and the substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate and the substrate; the source of the first TFT6 is electrically connected to the gate line 4, the drain of the first TFT6 is electrically connected to the anti-static wiring 3, and a first capacitor is formed between the gate of the first TFT6 and the source of the first TFT6, and a second capacitor is formed between the gate of the first TFT6 and the drain of the first TFT6.

[0060] During the preparation process of the above-mentioned preparation method, the overall structure of the anti-static structure is simple and compact, the preparation steps are relatively few, and there is no need to cross multiple conductive layers. When the gate line is formed, the anti-static structure is also formed, and the static electricity accumulated during the preparation process due to dry etching or exposure can be conducted from the gate line to the anti-static routing, and the static electricity is consumed on the anti-static routing. This can effectively avoid the phenomenon of short circuit caused by electrostatic breakdown at the intersection of the gate and the active layer in the pixel unit during the preparation process, and can avoid electrostatic breakdown in the overlapping area between the anti-static routing and the gate line, reduce the short circuit between the two layers of metal in the overlapping area, and effectively reduce the bright spot phenomenon caused by the short circuit, and effectively improve the product yield.

[0061] Specifically, refer to Figure 3 As shown, the above preparation method further includes: after forming the first metal layer and before forming the metal oxide layer, forming a buffer layer 10 on the first metal layer;

[0062] After forming the metal oxide layer and before forming the second metal layer, a gate insulating layer 12 is formed on the metal oxide layer.

[0063] Specifically, during the patterning preparation of the second metal layer, the gate line 4, the second electrode 5 and the second gate electrode can be formed simultaneously, and the second gate electrode is located in the display area.

[0064] Specifically, in the patterning preparation of the metal oxide layer, the first active layer and the second active layer can be formed simultaneously, and the second active layer is located in the sub-pixel unit, which simplifies the preparation process.

[0065] Specifically, refer to Figure 3As shown, the above preparation method further includes: after forming the second metal layer, forming an interlayer insulating layer on the second metal layer;

[0066] Then, a third metal layer is formed on the interlayer insulating layer, the third metal layer includes a second source electrode and a second drain electrode, wherein the second source electrode, the second drain electrode and the second active layer are electrically connected, the second gate electrode, the second active layer and the second source electrode and the second drain electrode can constitute a second TFT, and the second TFT can be formed as a pixel TFT switch in a pixel circuit; specifically, the material of the third metal layer can be copper or aluminum;

[0067] Next, a passivation layer 13 is formed on the third metal layer. The material of the passivation layer 13 may be SiOx, and the thickness of the passivation layer 13 may be 3000 angstroms to 5000 angstroms.

[0068] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: include: A base substrate, and a first metal layer, a metal oxide layer, and a second metal layer sequentially stacked and isolated from each other on the base substrate; The first metal layer includes a light-shielding metal, a first electrode, and an anti-static wiring, and the anti-static wiring is located in a peripheral wiring area of ​​the substrate; the metal oxide layer includes a first active layer; the second metal layer includes a gate line and a second electrode; The gate line is connected to the anti-static wiring through a first TFT, and the first electrode, the first active layer and the second electrode constitute the first TFT, the first active layer is connected to the source and drain of the first TFT through a conductive structure, and the distance between the surface of the conductive structure away from the substrate and the substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate and the substrate; the source of the first TFT is electrically connected to the gate line, and the drain of the first TFT is electrically connected to the anti-static wiring; and a first capacitor is formed between the gate of the first TFT and the source of the first TFT, and a second capacitor is formed between the gate of the first TFT and the drain of the first TFT; Wherein, the first electrode forms a source and drain of the first TFT, and the second electrode forms a gate of the first TFT; The first active layer includes a channel region opposite to the gate of the first TFT, and a first conductive region and a second conductive region respectively located on both sides of the channel region, the first conductive region and the second conductive region forming the conductive structure, and the first conductive region is connected to the source of the first TFT, and the second conductive region is connected to the drain of the first TFT; Alternatively, the first electrode forms a gate of the first TFT, and the second electrode forms a source and drain of the first TFT; The first active layer includes a channel region opposite to the gate of the first TFT, and a first conductive region and a second conductive region respectively located on both sides of the channel region. The second electrode is also formed with a first connecting metal and a second connecting metal. The first connecting metal and the second connecting metal constitute the conductive structure. The first connecting metal is connected to the first conductive region, and the second connecting metal is connected to the second conductive region.

2. The array substrate according to claim 1, characterized in that: The gate electrode of the first TFT partially overlaps with the source electrode of the first TFT to form the first capacitor, and the gate electrode of the first TFT partially overlaps with the drain electrode of the first TFT to form the second capacitor.

3. The array substrate according to claim 1, characterized in that: The anti-static wiring is a ring-shaped wiring, and the anti-static wiring is arranged around the display area of ​​the array substrate.

4. The array substrate according to claim 1, characterized in that: The orthographic projection of the gate line on the base substrate overlaps with the orthographic projection of the antistatic wiring on the base substrate, and a hollow structure is provided at the overlapping portion of the antistatic wiring and the gate line.

5. The array substrate according to claim 1, characterized in that: Also includes: a buffer layer disposed between the first metal layer and the metal oxide layer; A gate insulating layer is disposed between the metal oxide layer and the second metal layer.

6. The array substrate according to claim 5, characterized in that: The metal oxide layer also includes a second active layer located in a sub-pixel unit of the array substrate; The second metal layer further includes a second gate located in the sub-pixel unit and corresponding to the second active layer; An interlayer insulating layer is disposed on the second metal layer, a third metal layer is formed on the interlayer insulating layer, and the third metal layer includes a second source electrode and a second drain electrode electrically connected to the second active layer.

7. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 6.

8. A display device, characterized in that: Comprising the display panel as claimed in claim 7.

9. A method for preparing an array substrate according to any one of claims 1 to 6, characterized in that: include: Forming a first metal layer on the base substrate, wherein the first metal layer includes a light-shielding metal, a first electrode, and an anti-static wiring, wherein the anti-static wiring is located in a peripheral wiring area of ​​the base substrate; forming a metal oxide layer on the first metal layer, the metal oxide layer being isolated from the first metal layer, and the metal oxide layer comprising a first active layer; forming a second metal layer on the first metal layer, the second metal layer and the metal oxide layer being isolated from each other, the second metal layer comprising a gate line and a second electrode; Among them, the gate line is connected to the anti-static wiring through a first TFT, and the first electrode, the first active layer and the second electrode constitute the first TFT, one of the first electrode and the second electrode forms the source and drain of the first TFT, and the other forms the gate of the first TFT; the first active layer is connected to the source and drain of the first TFT through a conductive structure, and the distance between the surface of the conductive structure away from the substrate and the substrate is less than or equal to the distance between the surface of the second metal layer away from the substrate and the substrate; the source of the first TFT is electrically connected to the gate line, the drain of the first TFT is electrically connected to the anti-static wiring, and a first capacitor is formed between the gate of the first TFT and the source of the first TFT, and a second capacitor is formed between the gate of the first TFT and the drain of the first TFT.

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