Method and system for producing dies for wafer reconstruction

Abstract

The present invention relates to a method and system for producing die for wafer reconstitution. The method comprises the following steps: inspecting an epitaxial wafer to detect one or more defects; overlaying a scribe pattern on the epitaxial wafer having the detected defects; classifying the die in the scribe pattern as good die or bad die; dicing the epitaxial wafer into die and transferring the good die to a target wafer or a carrier wafer.

Description

Technical Field

[0001] The present invention relates to yield improvement of wafer reconstruction technology applicable to any application requiring devices manufactured using compound semiconductors tightly co-integrated with integrated circuits. Background Art

[0002] Applications that exploit the specific material properties of compound semiconductors can be light-emitting applications (e.g., LED displays, VECSEL arrays), photosensitive applications (e.g., NIR imagers, UV imagers); a combination of both (e.g., luminescence and / or photodetection for optical communications or neural stimulation), or electrical properties applications (transistors and diodes for power and / or high-frequency switching).

[0003] A possible application of the present invention is micro-LED displays for augmented reality applications. The demand for full high-definition (FHD) or higher resolution displays has increased. FHD displays require very large die sizes and very tight pixel pitches.

[0004] The assembly technology of the display is realized by using light-emitting diodes (LEDs) with direct band gap III-V, III-N or III-P materials, for example, known from EP 3667 745 A1. This document shows a light-emitting diode reconstructed on a carrier substrate. One or more LED devices are reconstructed as a compound semiconductor stack on a carrier substrate. The LED device may include an LED array or a micro-LED array. However, defects on the epitaxial wafer can significantly affect the display device made from the epitaxial wafer. Any defects or particles that cannot be removed will result in a loss of yield. The production of large bare chips requires strict yield control. This will in turn drive up costs and affect manufacturability. In addition, this is a multi-dimensional engineering challenge. Summary of the Invention

[0005] It is therefore an object of the present invention to provide a method, system and wafer for producing die for wafer reconstitution with high yield, in particular to maximize the number of usable die produced from epitaxial wafers by addressing the above limitations.

[0006] This object is achieved by the method, system, and reconstituted wafer produced using the die according to the present invention. Detailed description of the invention includes further improvements.

[0007] According to a first aspect of the present invention, a method produces die for wafer reconstruction. The method includes the step of inspecting an epitaxial wafer (also referred to as an epi wafer) to detect one or more defects. The method also includes overlaying a scribe pattern on the epitaxial wafer with the detected defects. In addition, the method includes the step of classifying the die in the scribe pattern as good die or bad die. In addition, the method includes the step of dicing the epitaxial wafer and transferring the good die to a target wafer or a carrier wafer. The present invention is intended to improve the quality of wafer-level epitaxial layers. In addition, the present invention is intended to increase the number of epitaxial layers or good die from each epitaxial wafer.

[0008] Therefore, the proposed solution solves the problem at the wafer level itself and maximizes the use of epitaxial wafers by taking into account the defects present on the epitaxial wafers.

[0009] Preferably, the method further comprises the step of adjusting the dicing pattern with respect to defects to optimize the location of the die relative to the detected defects, thereby maximizing the number of good die produced from the epitaxial wafer. The dicing pattern can be strategically positioned so that the majority of defects are located outside the die. Preferably, the defects are positioned at the edge of each die, thereby increasing the number of good die produced from each epitaxial wafer.

[0010] Advantageously, the method further comprises the step of inspecting the epitaxial wafer using optical and / or electrical techniques. Advantageously, defects can be detected using optical techniques such as spectroscopy or microscopy. Mapped images of defects on the epitaxial wafer can also be optionally used for future reference. Defect mapping on the epitaxial wafer can preferably be used for machine learning or for automation of the defect identification and classification process.

[0011] Preferably, the method includes the following steps: selecting good die based on the density of detected defects and / or the position of detected defects relative to the dicing pattern, and / or selecting good die based on the optical properties of the die measured by the optical brightness or cathode brightness of all selected die, or a combination thereof, and / or selecting good die based on film roughness, film thickness, film chemical composition, or a combination thereof. These selection criteria help improve the yield. The properties of the film (epitaxial layer) can be measured, such as roughness by AFM or interferometry, film thickness by ellipsometry, and chemical composition by Raman spectroscopy or infrared spectroscopy.

[0012] Preferably, inspection of the epitaxial wafers can be performed in two steps: one step on the epitaxial layers as received to detect defects that may no longer be visible in post-processing; and a second step after processing to detect defects on the bonding layer or composition.

[0013] Advantageously, the method further comprises the step of starting with a non-functionalized wafer, an unstructured wafer, or a blank epitaxial wafer. Advantageously, the epitaxial wafer comprises an epitaxial layer of a III-V, III-N, or III-P material on a substrate. In other words, the epitaxial wafer has no circuitry, only the epitaxial layer. Typically, the epitaxial layer is also referred to as an epi layer.

[0014] The epitaxial layer can be grown by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any suitable technique. Preferably, the substrate can be sapphire, GaAs, Ge, or more preferably silicon or any other suitable substrate. Advantageously, measuring defects on a blank epitaxial wafer will allow characterization of defects already at the wafer level. Thus, the method of the present invention allows optimization of the scribe pattern position on the epitaxial wafer with respect to detected defects to increase the number of good die per wafer.

[0015] Advantageously and preferably, the method comprises the step of dicing the epitaxial wafer by a technique such as mechanical scribing, plasma scribing, laser scribing, saw scribing, blade scribing or stealth scribing. These scribing techniques allow scribing of any scribing pattern applied to the epitaxial wafer.

[0016] Advantageously and preferably, the method further comprises the step of detecting defects on the epitaxial wafer, such as epitaxial layer defects, epitaxial pits, holes, slip lines, cracks, particles, inclusions, protrusions or combinations thereof.

[0017] Preferably, the good die includes a central area with zero defect tolerance, a peripheral area with high defect tolerance, and / or an intermediate area between the central area and the peripheral area with low defect tolerance, and preferably, the pixel pitch greater than 3μm tolerates defects in the high defect area in the range of 500nm to 5μm in size, and tolerates defects in the low defect tolerance range of 300nm to 500nm in size.

[0018] More advantageously, the method further comprises the step of transferring the good dies, either (a) individually to a target wafer, or (b) collectively via an intermediate carrier wafer.

[0019] According to the present invention, the carrier wafer is used temporarily and is not part of the reconstructed wafer. The carrier wafer is only used to transfer the good dies to the target wafer. The target wafer forms part of the reconstructed wafer.

[0020] Preferably, the method (a) includes the step of transferring each good die to a target wafer. The transfer method may be a direct pick-and-place transfer or any other suitable transfer method. The bonding layer is preferably an inorganic layer, such as SiCN or SiO2 or any known bonding material. During the transfer, additional cleaning and inspection steps may optionally be performed on each epitaxial die before bonding.

[0021] Alternatively, method (b) includes the step of collectively transferring the epitaxial die via a carrier wafer, including transferring the good die to the carrier wafer via a temporary bonding layer. Optionally, a cleaning and / or inspection step of each die can be performed before bonding. Method (b) also includes the step of collectively transferring the good die from the carrier wafer to the target wafer via the bonding layer. The carrier wafer is debonded. The good die are distributed on the target wafer to form a reconstructed wafer.

[0022] Advantageously and preferably, the method further comprises the steps of completely or partially removing the substrate of the good die at different stages (one option is when the good die is bonded to the target wafer) to expose the defect-free epitaxial layers, filling the gaps between the defect-free epitaxial layers, and planarizing to form a plurality of defect-free epitaxial dies (or also called epi-dies or dies) distributed on the wafer.

[0023] Preferably, the method further comprises the step of forming a display device on the reconstructed wafer and by wafer-to-wafer (W2W) bonding the reconstructed wafer to another wafer.

[0024] The further wafer comprises electronic components, in particular transistors, preferably CMOS transistors, for driving and / or controlling the electroluminescent diodes produced by structuring the epitaxial wafer. The further wafer can advantageously be a CMOS wafer.

[0025] Advantageously and preferably, the dicing pattern can be optimized such that good dies with zero defects are produced for the central region, while the peripheral region and / or the middle region still have limited defects according to a defectivity criterion.

[0026] Advantageously and preferably, the method further comprises the step of overlaying a dicing pattern on the epitaxial wafer. The dicing pattern can be a regular rectangular grid or an irregular pattern. In order to increase the number of good die, the location and size of the detected defects are used to optimize the dicing pattern. This can result in an irregular dicing pattern because the die are placed around the detected defects to produce more good die. Each die (based on the application to be used) is positioned in a manner that does not overlap with any detected defects or overlaps with detected defects only at the edge of the die. Based on the defect rate standard, the customized dicing pattern can produce a combination of good die with zero defects and good die with acceptable defects. Preferably, the customization of the pattern can start from the portion of the epitaxial wafer with the fewest defects, where more die can be placed in the regular pattern as a starting point. More preferably, in order to build the dicing pattern from the starting point, when a detected defect is encountered, the die can be moved to avoid overlapping or only overlap at the edge of the die. The die can be moved laterally in any direction to produce a larger number of good die. The die can be patterned continuously or discontinuously on the epitaxial layer to include the maximum number of good die. Therefore, die-by-die customization will significantly increase the yield of good die.

[0027] By selecting or customizing a suitable dicing pattern that is optimized so that most defects are located outside the die, the die yield per wafer will be significantly improved.

[0028] According to a second aspect of the present invention, a system for producing bare chips for wafer reconstruction is provided. The system includes a processing device configured to inspect an epitaxial wafer to detect one or more defects. The processing device is also configured to overlay a dicing pattern on the measured defects of the epitaxial wafer. In this case, the processing device is configured to classify the bare chips as good bare chips or bad bare chips, and the processing device is also configured to dice the epitaxial wafer using a dicing device. Preferably, the processing device is also configured to automatically perform these steps. More preferably, the processing device can self-learn to improve the inspection of defects in the epitaxial wafer, the positioning of the dicing pattern, the classification of good bare chips or bad bare chips, and the dicing of the epitaxial wafer to obtain good bare chips. Optionally, after dicing by further inspection, good bare chips can be further selected. Thus, through self-learning, the production of good bare chips can be automated and improved over time.

[0029] Preferably, the scribing device can be a saw, a laser, a plasma, or the like.

[0030] Advantageously, the processing device is configured to map defects detected on the epitaxial wafer. In addition, the processing device is configured to test the characteristics of a display device manufactured using good dies and compare the defect map with the characteristics of the display device. Advantageously, it can be determined whether the defect or defect rate criteria used during the process lead to unsatisfactory display characteristics. Thereby, the selection criteria for good dies can be further optimized. In addition, the processing device can use this information to self-learn and improve the selection criteria for good dies. In other words, if all dies that pass as good dies also perform well in the display device, the processing device can self-learn. In the event that the characteristics of the display device do not meet the expected standards, the defect map corresponding to the good dies used can be checked so that the selection criteria can be adjusted to improve the yield.

[0031] According to a third aspect of the present invention, a reconstructed wafer includes good dies and a target wafer. Good dies are selected from the epitaxial wafer, and multiple good dies are fixed to the target wafer to form the reconstructed wafer. Preferably, the good dies and / or the target wafer have a SiCN layer or other bonding material to bond them together.

[0032] Therefore, the reconstituted wafer formed of good die with improved yield manufactured in accordance with the present invention is cost-effective.

[0033] Preferably, the reconstructed wafer comprises a good die generated from an epitaxial wafer and affixed to a target wafer. The epitaxial wafer comprises an epitaxial layer on a substrate. The epitaxial layer is a III-V, III-N, or III-P layer material. Furthermore, the target wafer is a silicon wafer or other suitable material. Furthermore, the epitaxial wafer substrate may be sapphire, silicon, or any other suitable material.

[0034] Advantageously, the reconstructed wafer is suitable for wafer-to-wafer hybrid bonding with another wafer to form a display device. Preferably, the bonding is anodic bonding or fusion bonding, or preferably inter-metal bonding or any available inter-wafer bonding. This allows for large die areas with a tight pixel pitch range. Preferably, display device manufacturing using wafer-to-wafer hybrid bonding enables a pixel pitch range of less than 3 μm. Therefore, the reconstructed wafer according to the present invention meets the requirements for manufacturing FHD displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Exemplary embodiments of the present invention will now be further explained by way of example only and not limitation with reference to the accompanying drawings. In the drawings:

[0036] Figure 1 A flow chart showing possible paths for integrating LEDs with CMOS wafers;

[0037] Figure 2 (a) to (c) show Figure 2 (a) sapphire wafer, Figure 2 (b) Example of particle level of GaN-LED epilayer on silicon wafer and Figure 2 (c) Particle counts of sapphire and silicon;

[0038] Figure 3 (a) to (d) show examples of SEM images of growth defects on top of the GaN LED epilayer: Figure 3 (a) epitaxial pits, Figure 3 (b) Slip lines, Figure 3 (c) particles and Figure 3 (d) inclusions;

[0039] Figure 4 (a) to (b) show the Figure 4 (a) Brightness and Figure 4 (b) An example of a brightness image of an epitaxial wafer achieved using cathode brightness technology;

[0040] Figure 5 Examples of plots showing III-V epitaxial layer on-wafer yield versus die size for standard CMOS, GaN on Si (A+ and BB), AllnGaP on GaAs, and GaN on sapphire;

[0041] Figure 6 An exemplary embodiment of a flow chart for producing good die for wafer reconstitution and using a reconstituted wafer fabrication apparatus is shown;

[0042] Figure 7 (a) to (c) in FIG. 1 show exemplary embodiments of defect inspection of GaN on a silicon wafer: Figure 7 (a) Defect inspection diagram and classification of different types of defects, Figure 7 (b) GaN overlay dicing pattern on silicon wafer, and Figure 7 (c) in the figure marks the bad die as x;

[0043] Figure 8 (a) to (b) show exemplary embodiments of a die and a good epitaxial die covering a CMOS wafer;

[0044] Figure 9 (a) to (c) show exemplary embodiments of dicing patterns: Figure 9 (a) Standard rectangular grid, Figure 9 (b) Optimized rectangular grid, and Figure 9 (c) Irregular scribing pattern;

[0045] Figure 10 A system for producing die for wafer reconstitution is shown;

[0046] Figure 11 An exemplary embodiment of a flow chart for generating wafer reconstruction using a carrier wafer or directly on a target wafer is shown;

[0047] Figure 12 (a) to (c) show exemplary embodiments of a method for wafer reconstitution: Figure 12 (a) bonding the epitaxial die to the carrier substrate, Figure 12 (b) filling the gaps between the dies and planarizing them, and Figure 12 (c) reconstructed wafer; and

[0048] Figure 13 (a) to (f) in FIG. 5 show exemplary embodiments of integration diagrams starting from an epitaxial wafer and a carrier wafer up to a micro-LED display using wafer-to-wafer bonding. DETAILED DESCRIPTION

[0049] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, various modifications may be made to the following embodiments of the present invention, and the scope of the present invention is not limited to the following embodiments.

[0050] In the present invention, reference is made to different types of wafers as defined herein. An epitaxial wafer refers to a wafer with a cover film or a non-functionalized wafer. An epitaxial wafer may be referred to as an epi wafer. A carrier wafer refers to a wafer used to transfer a good die (or epi die) to a target wafer. A carrier wafer is a temporary wafer used in optional process steps. The carrier wafer does not form part of the reconstructed wafer. The target wafer is the final wafer to which the good die is transferred and bonded. The target wafer is part of the reconstructed wafer. The other wafer comprises electronic devices, in particular transistors, preferably CMOS transistors for driving and / or controlling electroluminescent diodes. In Figure 1 In FIG. 1 , a possible path for integrating micro LEDs with a further wafer 100 is shown, wherein the further wafer comprises electronic devices, in particular transistors, preferably a CMOS wafer.

[0051] Next-generation applications of micro-LED displays require very tight pixel pitches of 3 μm or less and very large arrays to achieve full high definition (FHD) of 1920×1280 pixels. Figure 1A possible path to implementing micro-LEDs on CMOS 101 is shown. Pixel pitches exceeding 10μm can be achieved through die-to-wafer transfer 102, with one die per pixel 103 containing RGB, and one die per display 104 containing RGB with B+RG down-conversion or via separate dies and combiners. However, FHD displays require a smaller range of pixel pitches. Pixel pitches below 10μm are achievable through full-wafer monolithic integration 105.

[0052] For example, the number of pixels required for an FHD display automatically translates to a very large die size of 6mm x 4mm (with a 3μm pitch). This in turn leads to stringent yield requirements. Therefore, inter-wafer 106 is a promising approach when using full-wafer monolithic integration. This allows for tight pixel pitches to be achieved on large die sizes (preferably 3μm or less).

[0053] Challenges faced during epitaxial wafer preparation can be due to a variety of reasons, such as growth conditions, growth methods, growth temperature or temperature gradients, which result in epitaxial wafers with inevitable defects.

[0054] Compound semiconductors used in LEDs are typically grown via epitaxial growth on closely lattice-matched foreign substrates (heteroepitaxy). The growth technique can be molecular beam epitaxy (MBE) or the more common metal organic chemical vapor deposition (MOCVD). The epitaxial wafers of the present invention can, for example, be III-V, III-N, or III-P epitaxial LED layers. The defectivity level of epitaxial layers is significantly higher than that of silicon CMOS wafers. Since defects in epitaxial wafers are unavoidable, methods are needed to address them to improve yield.

[0055] Some of the causes of defects on epitaxial wafers were discussed. The first cause of defects is the use of a less perfect substrate. Sapphire is preferred because it provides a good lattice match, but results in a large number of defects. Figure 2 Figures (a) and (b) show the defect levels of GaN LED epilayers on 150 mm sapphire wafer 201 and 200 mm silicon wafer 202, respectively. Sapphire substrates produce higher defect counts than silicon substrates. Figure 2 (c) in FIG. 2 shows a particle count graph 203 for sapphire 204 and silicon 205. The particle count for sapphire 204 is, for example, 1784, while for silicon 205 of the same size, the particle count is only about 29. Therefore, the challenge of using sapphire epitaxial wafers is to improve the yield, thereby making the option more cost-effective.

[0056] The second cause of defects may be the growth technology of the epitaxial layer, especially MOCVD. MOCVD usually still uses manual wafer loading technology, which is usually outside the clean room. In addition, MOCVD chambers are usually not optimized for defectivity but for production volume. In order to improve production volume, MOCVD has multi-wafer deposition chambers, stainless steel growth chambers, and the chamber cleaning process or clean gas is far less complex than that of advanced silicon CMOS CVD chambers. Since the deposition of a few micron thick film at a temperature of 700°C to 900°C requires a long deposition time and several hours of thermal ramp time, which makes single-wafer deposition chambers uneconomical, multi-wafer deposition is required. Therefore, growth defects on the epitaxial wafer become inevitable. In addition, during the growth process, lattice mismatch (such as epitaxial pits or slip lines) can also cause growth defects to appear. Figure 3 (a) to (d) show some examples of growth defects on top of the GaN LED epilayer. Figure 3 The SEM images in (a) to (d) are epitaxial pits 301, slip lines 302, particles 303 and inclusions 304, respectively.

[0057] The third possible reason is related to the epitaxial layer deposition uniformity, which particularly affects the final display characteristics. Epitaxial layer uniformity can affect the overall uniformity of the display device in terms of peak wavelength, internal quantum efficiency (IQE) and / or local uniformity. Figure 4 (a) to (b) are respectively obtained by Figure 4 (a) Brightness diagram 401 and Figure 4 (b) Cathode brightness graph 403 shows a uniformity measurement of the epitaxial layer. Brightness graph 401 shows characteristic emission from the epitaxial layer. The brightness graph makes it easy to identify uniformity across the epitaxial wafer. Furthermore, intensity distribution graph 402, corresponding to brightness graph 401, also reflects the uniformity of the layer. These brightness methods can be used to explore scattering, the electronic structure of the material, such as band gaps, defects, and resonance phenomena. In this case, cathode brightness graph 403 also reflects defects in the epitaxial layer.

[0058] The fourth reason for the low yield can be explained by the bonding method used to bond the CMOS wafer to the epitaxial wafer. If the CMOS wafer is bonded to the epitaxial LED wafer via wafer-to-wafer transfer, the defect density can be as low as 0.1 cm based on the standard -2 The die size assumes very high yields for CMOS wafers. However, the defect density of epitaxial wafers is 10 to 100 times higher than standard values, which means that the III-V epitaxial layers will significantly limit the yield during manufacturing.

[0059] exist Figure 5In Figure 5, the effect of high defect density on the on-wafer yield of III-V epitaxial layers is plotted against die size. It is assumed here that any particle or epitaxial defect larger than 0.3μm will create a non-working pixel. Of course, the acceptable defect rate at the pixel level for the final product may vary. The standard defect rate level for a mobile phone is zero defects per display, while in a monitor or TV, typically 3 to 6 non-working pixels per million pixels that are not lit and not clustered together are acceptable. For Figure 5 , the level of defects in using mobile phones.

[0060] exist Figure 5 In the 2018 GaN on Silicon Epiwafers (GaN on Silicon Epiwafers), even the best GaN on Silicon epiwafers show significant yield loss relative to CMOS. For FHD displays, the die area is significantly larger, and therefore, the die yield drops significantly, as shown in the figure. In fact, the defect rate is even worse because standard wafer inspection data excludes defects close to the edge (edge exclusion is 2mm to 10mm), where there are particularly high defect counts due to slip lines generated by the wafer bevel. These are not related to the individual die yield, but can cause complete failure in the inter-wafer bonding process.

[0061] The fifth factor affecting yield is the high wafer bow of III-V wafers due to intrinsic stress. III-V materials are lattice-matched by growing at very high temperatures, and when the wafer cools, the expansion coefficient of the epitaxial layer is different from that of the substrate, causing the wafer to bow. To reduce wafer bow, the thermal chuck on which the substrate wafer sits is not flat but pre-shaped to over-compensate for the stress-induced bow. This technique works very well for GaN on silicon wafers, but not very well for sapphire wafers.

[0062] Because structure dimensions are less critical, the LED industry has learned to cope with high wafer bow. However, this becomes a significant issue if III-V epitaxial wafers need to be processed in CMOS fabrication facilities, where tools will not accept wafers with bow greater than 45μm. As critical dimensions become much smaller, wafer bow standards become more stringent because wafer bow can affect the uniformity of process steps such as photolithography, CMP, and dry etching. This means that III-V epitaxial wafers need to be pre-selected, and only a certain percentage of the selected wafers can be used for further processing. Consequently, yield is affected by wafer bow.

[0063] The present invention provides a method and system for producing die for wafer reconstitution by overcoming all disadvantages and providing high yield.

[0064] According to the present invention, Figure 6A first exemplary embodiment of the method according to the first aspect is shown in an exemplary flowchart 600. The flowchart shows the steps involved in producing good die to improve yield. Starting from a blank epitaxial wafer without any electrically functional structures is highly advantageous for achieving high yield 601. The method includes a step 602 of inspecting the epitaxial wafer to detect one or more defects. The method also includes a step 603 of overlaying a scribe pattern on the epitaxial wafer with the detected defects. The method also includes a step 604 of classifying the die overlaid with the scribe pattern as good die or bad die. The method also includes a step 605 of dicing the epitaxial wafer and transferring the good die directly to a target wafer or transferring the good die to a carrier wafer and then finally to a target wafer to produce a reconstructed wafer. Therefore, the present invention provides a method for dealing with defects in epitaxial wafers at the wafer level to improve the yield of good die for wafer reconstruction.

[0065] For example, a silicon substrate is used for the target wafer provided. Preferably, a SiCN layer can be applied to the target wafer to create a bonding surface. More preferably, the selected good die can also be covered with a SiCN layer. Advantageously, SiCN provides high bonding strength between the good die and the target wafer. In addition, in order to improve the bonding strength, an annealing process after bonding can be performed. Therefore, the good die can be picked up and placed on the target wafer and bonded via the SiCN layer. Optionally, one or more SiN layers or alternative dielectric layers can be provided as an intermediate layer between the target wafer surface and the SiCN layer. In addition, optionally, the flatness and roughness can be improved by polishing these intermediate layers.

[0066] In addition to the above steps, Figure 6 Also shown is step 606 of manufacturing a device structure using the reconstructed wafer produced according to the method of the present invention. In an exemplary embodiment of the first aspect of the present invention, a non-functionalized wafer, an unstructured wafer (meaning a blank wafer), which is an epitaxial wafer having an epitaxial layer, is inspected. Thus, the yield of display devices can be improved at the beginning of the manufacturing process.

[0067] Figure 7 Figures (a) through (c) show defect inspection images of epitaxial wafer 701, with the dicing pattern overlaid on the epitaxial wafer and good die 709 sorted. Possible defects 703 and 706 on epitaxial wafers 701, 704, and 707 can be identified through inspection. For example, inspection can be performed using microscopy or spectroscopic techniques. During inspection, several defects 703 and 706, such as cracks, slip lines, epitaxial pits, or protrusions, can be identified. Alternatively or additionally, non-destructive electrical techniques can also be used.

[0068] As an example, Figure 7(a) in FIG. 1 shows a defect inspection diagram of GaN on a 200 mm silicon wafer performed by a KLA Circl inspection tool. Defects 703 are classified into different categories 702. In order to determine the good die 709, as shown in FIG. Figure 7 As shown in (b) of FIG. 7 , a scribe pattern 705 is overlaid on an epitaxial wafer 704 having detected defects 706. As an example, the scribe pattern 705 is a rectangular grid covering the silicon wafer. Figure 7 In (c), the portion of the scribe pattern 705 directly above the defects 703, 706 is classified as a bad die 708, which is marked with an "x" in this example. The squares without the "x" mark are the locations of good dies 709.

[0069] exist Figure 8 , (a) to (b) illustrate another exemplary embodiment of the method according to the first aspect of the present invention. The method for further improving the yield of good die includes adjusting the dicing pattern with respect to defects to optimize the die location relative to detected defects, thereby producing the maximum number of good die from each epitaxial wafer. In other words, the size and location of the defect on the epitaxial wafer relative to each square or rectangle of the dicing pattern are taken into account.

[0070] Figure 8 (a) to (b) show the coverage of the bare die and good epitaxial die of the CMOS wafer. The defect rate standard of the III-V epitaxial die area (also called epitaxial die) is Figure 8 ) to (b). The quality of the die will directly impact the device structure manufactured with it, such as a micro-LED display. In general, for a reconstructed wafer bonded to a CMOS wafer, the active CMOS area 801 will be larger than the epitaxial die 802 and the emission areas 803 and 804 of the epitaxial die. The area between 801 and 802 takes into account the required IO as well as additional control and computation. For most applications, very large defects should be avoided as it will affect the overall yield, especially during bonding of the reconstructed wafer to the CMOS wafer. However, depending on the application, the defect rate criteria may be different (e.g., different for areas 803 and 804).

[0071] Based on the application, the area occupied by III-V materials (ie, good die) can be segmented by considering the impact of defects on yield. Figure 8 (a) to (b) show the defect rate standard of each segment of III-V epitaxial die 802. The epitaxial die may have Figure 8The three segments shown in (b) of FIG. These segments are the central emission region 803, the intermediate emission region 804, and the peripheral region 805. The central emission region 803 of the III-V epitaxial die region must have zero defects. The intermediate emission region 804 surrounding the central emission region 803 can have a small number of defects, especially for near-eye displays. This is because the eye's resolution is better in the center and decreases toward the outside of the field of view.

[0072] Finally, the peripheral area 805 surrounding the middle area is a non-emitting exclusion zone that can tolerate a larger number of defects than the emitting area 804 located in the middle area. Therefore, any acceptable non-uniformity or acceptable good die with minor defects can be placed away from the emitting area (central area and middle area). Therefore, the defect rate standard allows good die with zero defects and some other good die to contain acceptable defects. The overlay dicing pattern makes it possible to obtain good die with zero defects, good die with defects in the range of 300nm to 500nm, and good die with defects in the range of 500nm to 5μm. Although good die with zero defects is preferred, good die with acceptable defects can still be used in the epitaxial die area. Since the defect rate standard leaves room for defects, the position of the good die relative to the detected defects can be optimized to produce the maximum number of good die from the epitaxial wafer. Therefore, it can still be economical to use a less perfect substrate (such as sapphire).

[0073] exist Figure 9 In (a) to (c), a third exemplary embodiment of the method according to the first aspect of the present invention is shown. As an example, respectively in Figure 9 (a) to (c) show different dicing patterns 902, 905, 908 covering the epitaxial wafer 901.

[0074] Figure 9 (a) in FIG. 1 shows a standard non-optimized dicing pattern 902 having a regular rectangular grid. The die 904 covering the detected defects are marked with an "x". Optimizing the dicing pattern can improve the yield of good die. For example, Figure 9 (a) in FIG. 5 shows three bad dies.

[0075] Preferably, a defectivity criterion may be used to optimize the dicing pattern. Figure 9 (b) in FIG. 1 shows a rectangular scribe grid optimized in a way that the defects are placed at the edge of the die 906 to meet the defectivity criteria. Figure 9 In (b), although die 906 covers two defects, it can still be classified as a good die because the defects will be located in the peripheral area 805 where higher defects can be tolerated. Figure 9There is only one bad die 904 in (b), while for a similar rectangular grid, the standard method will produce three bad dies. Even if defects are not allowed, Figure 9 (b) also has only two bad dies, which is still better than Figure 9 The dicing pattern used in (a) is better. Therefore, optimizing the dicing pattern improves the yield of good dies, even for the same pattern.

[0076] Furthermore, any known scribing technique (e.g., saw, high power laser, or plasma) may be used to separate the Figure 9 The rectangular scribe grid in (a) and (b) is scribed. Since saw dicing is very economical, this simple method has some advantages.

[0077] As another embodiment to increase the number of good die 903, the dicing pattern 908 is customized with respect to the defects 907 to optimize the position of the die relative to the detected defects, thereby producing the maximum number of good die 903 from the epitaxial wafer 901. This necessarily results in an irregular dicing pattern. The irregular dicing pattern 908 is preferably as follows: Figure 9 Advantageously, the defectivity criterion is taken into account while customizing the dicing pattern.

[0078] The scribing technology used for any irregular pattern is preferably plasma scribing or laser scribing. The advantage of irregular pattern is that defects on the die can be avoided, but the yield is still sufficient.

[0079] According to a second aspect of the present invention, there is provided a system for producing bare dies for wafer reconstitution. Figure 10 As shown. System 1001 includes a processing device 1002 using an inspection device 1003, the processing device 1002 being configured to inspect an epitaxial wafer 1004 using the inspection device 1003 to detect one or more defects 1005. The processing device 1002 is further configured to overlay a dicing pattern 1012 on the detected defects 1005 of the epitaxial wafer 1004. In this case, the processing device 1002 is configured to classify the dies as good dies 1009 or bad dies 1008. The processing device 1002 is further configured to dicing the good dies using a dicing device 1006. The good dies 1009 are transferred to a carrier wafer 1013 or a target wafer via a handling device 1010 to form a reconstructed wafer 1100. Optionally, after dicing, the good die verification can be repeated.

[0080] Preferably, the processing device 1002 is further configured to self-learn to detect defects 1005, overlay an appropriate dicing pattern, classify the dies as good dies 1009 or bad dies 1008, and / or dicing the good dies 1009. Thus, the production of good dies 1009 can be automated.

[0081] As another embodiment of the second aspect of the present invention, processing device 1002 is configured to store a defect rate map in memory 1007. When a final display device fails to meet standard requirements in terms of color, texture, resolution, emissivity, service life, and the like, the stored defect rate map can be used to identify any defects on epitaxial wafer 1004 that were passed as acceptable but subsequently significantly impacted the display. Thus, processing device 1002 can self-learn to improve defect detection and / or the selection of good die 1009 and / or bad die 1008. Thus, processing device 1002 can self-learn to classify good die that can also perform well in a display device.

[0082] According to an exemplary embodiment of the third aspect of the present invention, Figure 11 After the dicing pattern on the epitaxial wafer is optimized, the epitaxial wafer is diced to obtain good dies 1101. Two different methods are discussed here to transfer the good dies to the (final) target wafer.

[0083] According to the first method, the good die are transferred to a temporary carrier wafer and bonded by a temporary bonding method 1102. The carrier wafer can have a different wafer size than the epitaxial wafer. Many different integration methods can be used for the carrier wafer, such as picking up the good die and placing it on the carrier wafer. The good die are bonded to the carrier wafer by temporary bonding. The temporary bonding material holds the good die on the carrier wafer. All the die on the carrier wafer are collectively transferred to the target (final) wafer 1103. As described in step 1104, all the good die are permanently bonded to the target wafer by a bonding film such as SiCN, SiO2. The carrier wafer is debonded 1105. The permanent bonding of the good die to the target wafer can be fusion bonding, anodic bonding, dielectric bonding, metal bonding or hybrid bonding.

[0084] According to the second method, the good die is directly transferred to the target wafer 1106. The good die is bonded to the target wafer 1107 by any permanent bonding method in method (a).

[0085] According to any of these methods, the substrate material of the epitaxial wafer is fully or partially removed 1108. The removal of the substrate material of the epitaxial wafer can be performed at different stages, such as before dicing, during dicing, when the die is on the carrier wafer, or when the die is on the target wafer. The substrate removal method can be mechanical grinding, wet etching, dry etching, or a combination thereof. Finally, after the good die are placed on the target wafer by any of the above methods of forming a reconstructed wafer, the gaps between the good die are filled and planarized 1109. The reconstructed wafer can then be bonded to another wafer, such as a CMOS wafer.

[0086] According to an exemplary embodiment of the third aspect of the present invention, Figure 12 The method path of producing a reconstructed wafer using a target wafer is shown in (a) to (c). The reconstructed wafer 1200 includes an epitaxial wafer 1004 (such as Figure 10 shown) is formed and passed through Figure 10 The operation device 1010 shown transfers the good die 1201 to the target wafer 1205. Figure 10 The bonding apparatus 1011 shown in FIG2 bonds the good die 1201 to the target wafer 1205 through the bonding layer 1204. For example, the bonding layer 1204 may be a SiCN layer or a SiO2 layer on the good die 1201 and / or the target wafer 1205.

[0087] Figure 12 (a) in FIG. 1 shows a target wafer 1205 with two selected good dies 1201. The substrates 1202 of the good dies 1201 are removed by a suitable method to expose the epitaxial layer at this stage, or may be removed at a different stage. Figure 12 (b) in FIG. 1 shows a schematic diagram of the gaps between the good dies 1201 being filled with filler 1206 and planarized to form a plurality of defect-free epitaxial layers distributed on the target wafer. Figure 12 (c) in FIG. 1 shows a planarized reconstructed wafer 1207. Thus, the planarized reconstructed wafer 1207 has good, non-defective dies 1201 distributed on the target wafer 1205 ready for use with another wafer (eg, a CMOS wafer).

[0088] For example, the epitaxial wafer is a 150 mm to 200 mm silicon wafer or a sapphire wafer, and the target wafer is a 300 mm silicon wafer. Preferably, the filler for filling the gap is SiO2 or any other suitable dielectric material.

[0089] exist Figure 13 Figures (a) to (f) of FIG. 1 show an overview of the integration technology for forming a micro-LED display starting from an epitaxial wafer. This overview shows the fabrication of a reconstituted wafer according to the present invention, the transfer of the reconstituted wafer to a CMOS wafer by wafer-to-wafer transfer, and the fabrication of a micro-LED display.

[0090] Figure 13 (a) in FIG. 1 shows an epitaxial wafer 1004 and a target wafer 1205. By the method of the present invention, a maximum number of good bare chips are produced from the epitaxial wafer 1004. These good bare chips are transferred to the target wafer 1205. Figure 13 As shown in (b) of FIG. 1 , good dies are arranged on the target wafer to provide a reconstructed wafer 1200. The gaps between the good dies are filled and planarized to provide a reconstructed wafer 1200. Figure 13 The planarized reconstructed wafer 1207 is shown in (c).

[0091] Figure 13 The further method steps shown in (d) to (f) illustrate the fabrication of a micro LED display using the planarized reconstituted wafer 1207 of the present invention.

[0092] Advantageously, the planarized reconstituted wafer 1207 allows for hybrid bonding between wafers. The required precision for bonding between wafers can be achieved with the planarized reconstituted wafer 1207 of the present invention. Figure 13 As shown in (d) of FIG. , the planarized reconstructed wafer 1207 is bonded to the CMOS wafer 1301. For example, the CMOS wafer 1301 is a 300 mm CMOS wafer. Preferably, the bonding is dielectric bonding, intermetallic bonding, or hybrid bonding. Figure 13 (e) in FIG. 1 shows a micro LED display 1302 with an inter-wafer bonded LED array on a CMOS wafer. Finally, the steps of dicing, packaging, and testing are performed to achieve the following. Figure 13 The display device 1303 shown in (f) in FIG.

[0093] Although the invention has been illustrated and described with respect to one or more implementations, equivalent changes and modifications will occur to others skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, although a particular feature of the invention may be disclosed with respect to only one of a plurality of implementations, that feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

Claims

1. A method for producing a die for wafer reconstitution, the method comprising: inspecting a blank epitaxial wafer to detect one or more defects; overlaying a scribe pattern on the blank epitaxial wafer having the detected defect; adjusting the dicing pattern relative to the detected defect to optimize the position of the dies in the dicing pattern relative to the defect, thereby producing a maximum number of good dies from the blank epitaxial wafer; classifying the dies in the dicing pattern as good dies or bad dies; The blank epitaxial wafer is diced into dies and good dies are transferred to a target wafer or a carrier wafer.

2. The method according to claim 1, in, The method further comprises the step of inspecting the blank epitaxial wafer by optical technology.

3. The method according to claim 1, in, The method further comprises the steps of: selecting good die based on the density of the detected defects and / or the position of the detected defects relative to the dicing pattern, and / or Selecting good dies based on the optical characteristics of the dies as measured by the light intensity of all selected dies, and / or Good dies are selected based on film roughness, film thickness, film chemical composition, or a combination thereof.

4. The method according to claim 1, in, The method further comprises the step of starting the inspection from a non-functionalized wafer or a non-structured wafer as the blank epitaxial wafer, the blank epitaxial wafer having an epitaxial layer of III-V material on a substrate.

5. The method according to claim 1, in, The method further comprises the step of starting the inspection from a non-functionalized wafer or a non-structured wafer as the blank epitaxial wafer, the blank epitaxial wafer having an epitaxial layer of III-N material on a substrate.

6. The method according to claim 1, in, The method further comprises the step of starting the inspection from a non-functionalized wafer or a non-structured wafer as the blank epitaxial wafer, the blank epitaxial wafer having an epitaxial layer of III-P material on a substrate.

7. The method according to claim 1, in, The method further comprises the following steps: scribing the blank epitaxial wafer by plasma scribing, laser scribing, blade scribing or invisible scribing.

8. The method according to claim 1, in, The method further includes the step of detecting epitaxial layer defects, epitaxial pit defects, slip line defects, cracks, particle defects, or inclusion defects or a combination thereof.

9. The method according to claim 1, in, The method further comprises the step of fixing the good die to the target wafer or the carrier wafer by fusion bonding, direct bonding, anodic bonding, metal-to-metal bonding or adhesive bonding.

10. The method according to claim 1, in, The method further comprises the steps of: after fixing the good die to the target wafer or the carrier wafer, removing the substrate of the blank epitaxial wafer to expose the epitaxial layer, filling the gaps between the dies, and Planarization is performed to form a plurality of defect-free dies distributed on the target wafer or the carrier wafer.

11. The method according to claim 1, in, The method further comprises the steps of forming a display device by inter-wafer bonding of the reconstructed wafer to another wafer, The other wafer includes CMOS transistors for driving and / or controlling the electroluminescent diodes manufactured by wafer reconstruction.

12. The method according to claim 11, in, The die includes a central region having zero defect presence, a peripheral region having high defect presence, and / or an intermediate region between the central region and the peripheral region having low defect presence, and For a pixel pitch greater than 3 μm, the high defect existence range allows defects of 500 nm to 5 μm, and the low defect existence range allows defects of 300 nm to 500 nm.

13. The method according to claim 1, in, The scribing pattern is a regular rectangular grid, or The dicing pattern is an irregular pattern, and the irregular pattern is made so that most defects are located outside the die.

14. A system for producing die for wafer reconstitution, the system comprising: processing device, wherein the processing device is configured to inspect the blank epitaxial wafer to detect one or more defects via the inspection device; wherein the processing device is further configured to overlay a scribe pattern on the detected defects of the blank epitaxial wafer; wherein the processing device is further configured to adjust the dicing pattern relative to the detected defect to optimize the position of the dies in the dicing pattern relative to the defect, thereby generating a maximum number of good dies from the blank epitaxial wafer; wherein the processing device is further configured to classify the die into good die or bad die; and The processing device is further configured to slice the good bare die using a dicing device.

15. The system according to claim 14, in, The processing device is further configured to self-learn to detect the defects, overlay the dicing pattern, and / or classify the dies as good dies or bad dies, and / or The good bare die is diced.

16. The system according to claim 14 or 15, in, The processing device is configured to map the defects detected on the blank epitaxial wafer, The processing device is further configured to test the characteristics of a display device manufactured using the good die, and Therein, the processing means is configured to compare maps of detected defects corresponding to characteristics of the display device.

17. A reconstructed wafer, comprising: good bare chip; target wafer or carrier wafer; wherein good die are selected from blank epitaxial wafers using the method according to claim 1, and Wherein, a plurality of good bare dies are fixed or bonded on the target wafer or the carrier wafer.

18. The reconstructed wafer according to claim 17, in, The blank epitaxial wafer is a heterogeneous epitaxial wafer or a non-functionalized wafer. Wherein, the epitaxial layer on the blank epitaxial wafer is a III-V layer, and / or Wherein, the carrier wafer is a silicon wafer or a glass wafer, and / or The reconstituted wafer is suitable for inter-wafer bonding with another wafer to form a display device, wherein the bonding is fusion bonding, anodic bonding, dielectric bonding, metal-to-metal bonding, or adhesive bonding.

19. The reconstructed wafer according to claim 17, in, The blank epitaxial wafer is a heterogeneous epitaxial wafer or a non-functionalized wafer. Wherein, the epitaxial layer on the blank epitaxial wafer is a III-N layer, and / or Wherein, the carrier wafer is a silicon wafer or a glass wafer, and / or The reconstituted wafer is suitable for inter-wafer bonding with another wafer to form a display device, wherein the bonding is fusion bonding, anodic bonding, dielectric bonding, metal-to-metal bonding, or adhesive bonding.

20. The reconstructed wafer according to claim 17, in, The blank epitaxial wafer is a heterogeneous epitaxial wafer or a non-functionalized wafer. Wherein, the epitaxial layer on the blank epitaxial wafer is a III-P layer, and / or Wherein, the carrier wafer is a silicon wafer or a glass wafer, and / or The reconstituted wafer is suitable for inter-wafer bonding with another wafer to form a display device, wherein the bonding is fusion bonding, anodic bonding, dielectric bonding, metal-to-metal bonding, or adhesive bonding.

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