Stacked vertical transistor memory cells

Abstract

A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom level including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell also includes a top level including at least one top transistor, and a cross-coupling including an epi connection and a gate-to-epi connection between the top level and the bottom level.

Description

BACKGROUND

[0001] The present invention relates generally to semiconductor devices, and more particularly to stacked vertical transistor memory cells and methods of forming the same.

[0002] Vertical transistors, such as vertical field effect transistors (FETs), have been designed as a way to reduce contact poly pitch (CPP) to reduce cell size per unit and increase efficiency by orienting current vertically. In addition, the contact density per unit surface area of a vertical transistor is higher than that in a lateral transistor because the ohmic contacts and channels are aligned vertically. SUMMARY

[0003] According to an embodiment of the present invention, a semiconductor device is provided. The device includes a stacked transistor memory cell. The stacked transistor includes a bottom level including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top level including at least one top transistor, and a cross-coupling including an epi connection and a gate-to-epi connection between the top level and the bottom level.

[0004] According to another embodiment of the present invention, a semiconductor device is provided. The device includes a stacked vertical transistor memory cell. The stacked vertical transistor memory cell includes a bottom level including a plurality of bottom vertical transistors including n-type field effect transistors (nFETs) having merged top source / drain epitaxial (epi) regions and gate structures. The plurality of bottom vertical transistors includes first and second non-floating transistors and first and second floating transistors. The first and second floating transistors have at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell. The stacked vertical transistor memory cell also includes a top level including a plurality of top vertical transistors including p-type field effect transistors (pFETs) having merged bottom source / drain epi and gate structures. The plurality of top vertical transistors includes first, second, third, and fourth top vertical transistors. The stacked vertical transistor memory cell also includes a cross-coupling portion contacting the gate structures of the bottom level and the top level. The cross-coupling portion includes an epi connection formed by the merged top source / drain epi between the first non-floating and floating transistors and the second non-floating and floating transistors; an epi connection formed by the merged bottom source / drain epi between the first and third top vertical transistors and between the second and fourth top vertical transistors; a gate-to-epi connection formed by metal between the first non-floating and second floating transistors and between the second non-floating and first floating transistors; and a gate-to-epi connection formed by metal between the first and second top vertical transistors and between the third and fourth top vertical transistors.

[0005] According to yet another embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method includes forming a stacked transistor memory cell including a bottom level having a plurality of bottom transistors and a top level having at least one top transistor. The plurality of bottom transistors includes at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell. Forming the stacked transistor memory cell includes forming a cross-coupling portion including an epitaxial (epi) connection and a gate-to-epi connection between the top level and the bottom level.

[0006] These and other features and advantages will be apparent from a reading of the following detailed description of illustrative embodiments of the present invention, taken in BRIEF DESCRIPTION OF DRAWINGS

[0007] The following description will provide details of preferred embodiments referring to the following drawings in which:

[0008] Figure 1 is a schematic diagram of a memory cell according to an embodiment of the present application;

[0009] Figure 2 is a top view of a stacked vertical transistor memory cell according to an embodiment of the present application;

[0010] Figure 3 is a cross-sectional view of a memory cell according to an embodiment of the present application; Figure 2

[0011] Figure 4 is another cross-sectional view of a memory cell according to an embodiment of the present application; Figure 2

[0012] Figure 5 is a top view of a sacrificial layer etched during fabrication of a semiconductor device according to an embodiment of the present application;

[0013] Figure 6 is a cross-sectional view of a semiconductor device shown in Figure 5

[0014] Figure 7 is another cross-sectional view of a semiconductor device shown in Figure 5

[0015] Figure 8 is a cross-sectional view of a semiconductor device during fabrication of a semiconductor device to form bottom source / drain regions in a top level of the semiconductor device according to an embodiment of the present application;

[0016] Figure 9 is another cross-sectional view of a semiconductor device during fabrication of a semiconductor device to form bottom source / drain regions in a top level of the semiconductor device according to an embodiment of the present application;

[0017] Figure 10 is a cross-sectional view of a semiconductor device during fabrication of a semiconductor device to form a top transistor and an interlayer dielectric (ILD) layer according to another embodiment of the present application;

[0018] Figure 11 is another cross-sectional view of a semiconductor device during fabrication of a semiconductor device to form a top transistor and an interlayer dielectric (ILD) layer according to yet another embodiment of the present application;

[0019] Figure 12 is a cross-sectional view of an etch performed to expose a sacrificial layer during fabrication of a semiconductor device according to another embodiment of the present application;

[0020] Figure 13 ​​​​is another cross-sectional view of an etch performed to expose a sacrificial layer during fabrication of a semiconductor device according to another embodiment of the invention;

[0021] Figure 14 is a cross-sectional view of a removal of a sacrificial layer to form a cross-coupling opening during fabrication of a semiconductor device according to another embodiment of the invention;

[0022] Figure 15 is another cross-sectional view of a removal of a sacrificial layer to form a cross-coupling opening during fabrication of a semiconductor device according to another embodiment of the invention;

[0023] Figure 16 is a cross-sectional view of a formation of a conductive material in a cross-coupling opening to form a cross-coupling during fabrication of a semiconductor device according to another embodiment of the invention;

[0024] Figure 17 is another cross-sectional view of a formation of a conductive material in a cross-coupling opening to form a cross-coupling during fabrication of a semiconductor device according to an embodiment of the invention; and

[0025] Figure 18 is a block diagram / flow diagram illustrating a system / method for fabricating a semiconductor device according to another embodiment of the invention. DETAILED DESCRIPTION

[0026] Embodiments described herein provide a stacked transistor memory cell in a stacked three-dimensional (3D) transistor architecture. The stacked transistor memory cell can include floating and non-floating transistors. As used herein, a floating transistor of a memory cell is a transistor that has at least one terminal (e.g., at least one of a source / drain, a drain / source, and a gate) electrically disconnected or electrically isolated from other transistors of the memory cell, and none of which represent an external interface (e.g., a word line (WL), a bit line (BL), a power supply voltage (VDD), and a ground (GND)) of the memory cell. A non-floating transistor of a memory cell is a transistor that is not a floating transistor. That is, each of the terminals of a non-floating transistor is connected to other transistors in the memory cell, or represents an external interface of the memory cell.

[0027] A stacked transistor memory cell formed according to embodiments described herein includes a top level and a bottom level each having respective transistors. The top level can illustratively include a p-type transistor (e.g., a pFET), and the bottom level can include an n-type transistor (e.g., an nFET). For example, the top level transistor (e.g., a pFET) can be used as a pass-gate.

[0028] In one embodiment, the stacked transistor memory cell is a stacked vertical transistor memory cell. More particularly, the stacked vertical transistor memory cell can include a vertical transport FET (VTFET). A merged bottom epitaxial ("epi") in the top level can be used to connect the pass gate to the first inverter (e.g., pFET) drain. The transistor (e.g., nFET) directly under the pass gate can include a floating gate and a bottom source / drain, and can have its top epi merged to the top of the epi (drain) of the second inverter (e.g., nFET). A cross-coupled contact can connect the gates of the inverters, which can cause the pass gate bottom epi and the floating transistor top epi to be in direct contact.

[0029] According to aspects of the present application, integrating stacked transistor memory cells within a 3D monolithic scheme provides various benefits, such as benefits with respect to logic. For example, one or more of the following benefits can be realized: (1) more compact circuit packaging in order to reduce back end of line (BEOL) wire length to realize power and performance benefits; and (2) higher drive strength in a given area footprint.

[0030] Exemplary applications / uses to which the present application can be applied include, but are not limited to, manufacturing memory devices. For example, embodiments of the present application can be applied to manufacturing static random access memory (SRAM) devices formed from SRAM cells. As is known in the art, SRAM cells are composed of transistors, which can include metal oxide semiconductor FETs (MOSFETs). By way of example, in a six-transistor SRAM cell (i.e., a 6T SRAM cell), each bit is stored on four transistors that form cross-coupled inverters, and the other two transistors are access transistors that control access to the storage cells during read and write operations. In the 6T SRAM cell embodiments discussed herein, the top level can include four p-type transistors, and the bottom level can include two n-type transistors. For example, the top level can include two pass gates. However, such embodiments are not limiting. By way of example, in alternative embodiments, the top level can include n-type transistors and the bottom level can include n-type transistors.

[0031] It should be appreciated that aspects of the present application will be described in terms of a given illustrative architecture; however, other architectures, substrate materials, and process features and steps can be changed using the teachings of the present application.

[0032] It will also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0033] The embodiments can include design of integrated circuit chips created in a graphical computer programming language, and stored on computer storage media (e.g., a disk, tape, physical hard drive, or virtual hard drive such as in storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate the chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, either directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for use in the fabrication of the photolithographic masks, which can include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are then used in the fabrication of the chips.

[0034] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant in raw wafer form (i.e., as a single wafer having many unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single chip packages (e.g., plastic carriers with leads fixed to a motherboard or other higher level carrier) or in multiple chip packages (e.g., ceramic carriers with any or all of surface interconnections, tape bonded interconnections, or flip chip interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end consumer electronics to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0035] It will also be understood that material compounds will be described in terms of the elements (e.g., SiGe) that they contain. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x, where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. Compounds with additional elements will be referred to herein as alloys.

[0036] Reference throughout the specification to“one embodiment” or“an embodiment” and other variants means that a particular feature, structure, characteristic, and the like being described in connection with this embodiment is included in at least one embodiment. Therefore, the appearance of the phrases in various places throughout the specification, such as“in one embodiment” or“in an embodiment” as well as any other variations, are not necessarily all referring to the same embodiment.

[0037] It should be understood that any of the following terms such as“ / ,”“and / or,” and“at least one of” when used in the context of for example“A / B,”“A and / or B,” and“at least one of A and B” are intended to cover the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of“A, B, and / or C” and“at least one of A, B, and C,” such phrasing is intended to cover the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are chosen in the same fashion.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and / or“including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] For ease of description, spatially relative terms, such as “below”, “beneath”, “lower”, “above”, “upper” and the like, can be used herein for describing an element’s relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. The term “below” can thus include both the above and below orientations. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0040] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

[0041] Reference is now made to the drawings, wherein like numerals refer to like or similar elements throughout, and Figure 1 A schematic diagram of a memory cell 100 is provided.

[0042] The memory cell 100 includes a transistor memory cell having a stack of transistors. In an illustrative embodiment, the memory cell 100 includes a vertical transistor memory cell having a stack of vertical transistors.

[0043] The memory cell 100 can include floating and non-floating transistors. A floating transistor can have at least one terminal (e.g., at least one of a source / drain, a drain / source, and a gate) electrically disconnected from other ones of the transistors. For example, as shown, the memory cell 100 includes eight transistors, including a set of transistors 102-1 to 102-4 and a set of transistors 104-1 to 104-4. In this illustrative embodiment, the plurality of transistors can include field effect transistors (FETs). In one embodiment, the set of transistors 102-1 to 102-4 includes p-type FETs (pFETs), and the set of transistors 104-1 to 104-4 includes n-type FETs (nFETs). However, this embodiment should not be considered limiting. Transistors 140-2 and 140-3, represented by dashed lines, correspond to floating transistors (e.g., floating nFETs).

[0044] As further shown, a plurality of connections between respective ones of the plurality of transistors are shown. More particularly, cross-coupling is achieved through epi-to-epi connections and gate-to-epi connections.

[0045] More particularly, dotted line 110-1 corresponds to a merged bottom epi connection between the source / drain of transistor 102-2 and the source / drain of transistor 102-4, and dotted line 110-2 corresponds to a merged bottom epi connection (e.g., a merged pFET bottom epi connection) between the source / drain of transistor 102-1 and the source / drain of transistor 102-3.

[0046] Dotted line 120-1 corresponds to a merged top epi connection between the drain / source of transistor 104-2 and the drain / source of transistor 104-4, and dotted line 120-2 corresponds to a merged top epi connection (e.g., a merged nFET top epi connection) between the drain / source of transistor 104-1 and the drain / source of transistor 104-3.

[0047] Solid line 130-1 corresponds to a gate-epi connection of metal between the source / drain of transistor 102-2 to the gates of transistors 102-1 and 104-1, and solid line 130-2 corresponds to a gate-epi connection of metal between the drain / source of transistor 104-2 and the gates of transistors 102-1 and 104-1, solid line 140-1 corresponds to a gate-epi connection of metal between the source / drain of transistor 102-3 and the gates of transistors 102-4 and 104-4, and solid line 140-2 corresponds to a gate-epi connection of metal between the drain / source of transistor 104-3.

[0048] As further shown, memory cell 100 includes a plurality of lines. More particularly, ground (GND) line 150-1 is coupled to the source / drain of transistor 104-1, and GND line 150-2 is coupled to the source / drain of transistor 104-4. Power supply voltage (VDD) line 160-1 is coupled to the drain / source of transistor 102-1, and VDD line 160-2 is coupled to the drain / source of transistor 102-4. Word line (WL) line 170-1 is coupled to the gate of transistor 102-2, and WL line 170-2 is coupled to the gate of transistor 102-3. Bit line (BL) line 180-1 is coupled to the drain / source of transistor 102-3, and complementary bit line (~BL) line 180-2 is coupled to the drain / source of transistor 102-2.

[0049] Reference Figure 2, a top view of a stacked transistor memory cell 200 having a top tier 202 and a top tier 204 is provided. In this illustrative example, the memory cell 200 is a vertical transistor memory cell including a stack of eight transistors (e.g., FETs), although the number of transistors should not be considered limiting. The memory cell 200 can represent Figure 1 , for simplicity, Figure 2 Some components of the memory cell 200 (e.g., gate material, top and bottom epi, and sacrificial layers for forming contacts) are not shown in

[0050] The memory cell 200 can include floating and non-floating transistors. A floating transistor can have at least one terminal (e.g., at least one of source / drain, drain / source, and gate) electrically disconnected from other ones of the transistors.

[0051] For example, as shown, the memory cell 200 can include a plurality of fins corresponding to the plurality of transistors, including fins 206-2 through 206-8, which can include any suitable material according to embodiments described herein.

[0052] As further shown, the memory cell 200 can include a plurality of contacts, including GND contacts 210-1 and 210-2, VDD contacts 212-1 and 212-2, WL contacts 214-1 and 214-2, BL contact 216-1 and ~BL contact 216-2. As further shown, the memory cell 200 can include cross-coupled connections 218-1 and 218-2. As discussed above with reference to Figure 1 , the cross-coupled connections can create epi connections and metal gate-to-epi connections between the plurality of transistors. Cross-sectional views of the memory cell 200 through lines A-A' and B-B' will be described below with reference to Figure 3 and Figure 4 , respectively.

[0053] Reference is made to Figure 3 and Figure 4 , which provide cross-sectional views of the memory cell 200 of Figure 2 and Figure 3 . More particularly, Figure 3 depicts a cross-sectional view through line A-A' of Figure 2 , and Figure 4 shows a cross-sectional view through line B-B' of Figure 2 .

[0054] As shown, memory cell 200 includes a substrate 220 having a plurality of layers formed thereon. Substrate 220 can include any appropriate substrate structure, such as bulk semiconductor, semiconductor-on-insulator (SOI) substrate, etc. In one example, substrate 220 can include a silicon-containing material. Illustrative examples of silicon-containing materials suitable for substrate 220 can include, but are not limited to, Si, SiGe, SiGeC, SiC, and multilayers thereof. Although silicon is the predominant semiconductor material used in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

[0055] As described above with reference to Figure 2 Memory cell 200 also includes fins 206-1 through 206-3 and 206-5 through 206-7, VDD line 212-1, and BL line 216-1, as described above with reference to FIG. 1. Fins 206-5 through 206-7 correspond to the bottom FET, and fins 206-1 through 206-3 correspond to the top FET. Each of the FETs can also include a gate dielectric 208 and a gate conductor 209. Gate dielectric 208 and gate conductor 209 can include any appropriate materials according to the embodiments described herein.

[0056] For example, gate dielectric 208 can include a high-k dielectric material. As used herein, “high-k” refers to a dielectric material whose characteristic is a dielectric constant (k) greater than that of SiO2 at room temperature (20-25 °C) and atmospheric pressure (1 atm). In one embodiment, gate dielectric 208 can include a high-k oxide, such as HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, and mixtures thereof. Other examples of high-k dielectric materials for gate dielectric 208 include hafnium silicate, hafnium silicon oxynitride, or combinations thereof.

[0057] Examples of appropriate conductive materials for gate conductor 209 include, but are not limited to, metals, metal alloys, metal nitrides, and metal silicides, as well as stacks thereof and composites thereof. In one embodiment, gate conductor 209 can include any conductive metal including, but not limited to, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re; and gate conductor 209 can include an alloy including at least one of the aforementioned conductive elemental metals. Gate conductor 209 can also include doped polysilicon and / or polysilicon-germanium alloy materials (i.e., having a dopant concentration from 1 x 1018 dopant atoms per cubic centimeter to 1 x 1022 dopant atoms per cubic centimeter) and polycide materials (doped polysilicon / metal silicide stack materials). For example, gate conductor 209 can include a work function metal (WFM).

[0058] In one embodiment, the gate dielectric 208 and / or the gate conductor 209 can be deposited by chemical vapor deposition (CVD). Variations of CVD processes suitable for depositing at least one gate dielectric layer include, but are not limited to, APCVD, LPCVD, PECVD, MOCVD, ALD, and combinations thereof.

[0059] The memory cell 200 also includes bottom epitaxial ("epi") regions 222-1 through 222-5 corresponding to bottom source / drain regions. More particularly, the memory cell 200 includes a merged bottom epi region 222-1 corresponding to the FETs of fins 206-1 and 206-2, and bottom epi regions 222-2 through 222-5 corresponding to the FETs of fins 206-5, 206-6, 206-3, and 206-7, respectively.

[0060] The memory cell 200 also includes top epi regions 224-1 through 224-6 corresponding to top source / drain regions. More particularly, the memory cell 200 includes a merged top epi region 224-1 corresponding to the FETs of fins 206-5 and 206-6, and top epi regions 224-2 through 224-6 corresponding to the FETs of fins 206-1, 206-2, 206-5, 206-3, and 206-7, respectively.

[0061] The epi regions 222-1 through 222-5 and 224-1 through 224-6 can include any suitable material in accordance with the embodiments described herein.

[0062] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), where the grown semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms have sufficient energy to move around on the deposition surface of the semiconductor substrate as they reach the surface, enabling the depositing atoms to orient themselves to the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} oriented crystalline surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to form on semiconductor surfaces and generally does not deposit material on exposed surfaces (e.g., silicon dioxide or silicon nitride surfaces).

[0063] The source / drain epitaxy can be accomplished by ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), molecular beam epitaxy (MBE). The epitaxial material can be grown from gaseous or liquid precursors. Vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes can be used to grow the epitaxial material. Depending on the type of transistor, the epitaxial silicon, silicon germanium (SiGe), and / or carbon doped silicon (Si:C) silicon can be doped (in-situ doped) during deposition by the addition of dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium). The dopant concentration in the source / drain can be in the range of about 1 x 1019cm"3to about 2 x 1021cm"3, or preferably between 2 x 1020cm"3and 1 x 1021cm"3. When Si:C is epitaxially grown, the Si:C layer can include carbon in the range of 0.2% to 3.0%. When SiGe is epitaxially grown, the SiGe can have a germanium content in the range of 5% to 80%, or preferably between 20% to 60%.

[0064] The memory cell 200 also includes a dielectric layer 226 that isolates the pairs of top and bottom FETs. According to embodiments described herein, the dielectric layer 226 can include any suitable material (e.g., Si02).

[0065] The memory cell 200 also includes a plurality of spacer layers 228. The plurality of spacer layers 228 can include any suitable spacer material according to embodiments described herein.

[0066] The memory cell 200 also includes a shallow trench isolation (STI) region 230 and an interlayer dielectric (ILD) layer 240. The STI region 230 and the ILD layer 240 can include any suitable dielectric material according to embodiments described herein.

[0067] The memory cell 200 also includes an insulator layer 234 that provides N-P isolation. According to embodiments described herein, the insulator layer 234 can include any suitable material. For example, the insulator layer 234 can include a nitride material, for example.

[0068] The memory cell 200 also includes a GND contact 210-2, a VDD contact 212-1, a WL contact 214-2, a BL contact 216-12, and a cross-coupled connection 218-2.

[0069] The FETs corresponding to fins 206-1 can correspond to pass gate FETs, the FETs corresponding to fins 206-2 and 206-6 can correspond to inverters, and the FET corresponding to fin 206-5 can correspond to an unconnected floating FET. Thus, the merged bottom epi region 222-1 can be used to contact the pass gate FETs to the inverter FETs, the merged top epi region 224-3 can assist in cross-coupling, and the isolated bottom epi region 222-3 can correspond to an inverter ground.

[0070] Figures 5-17 A portion of a process flow for fabricating a semiconductor device 300 including a three-dimensional stacked vertical FET architecture (e.g., the device 200 described above with reference to Figures 2-4 In one embodiment, the bottom FETs include nFETs and the top FETs include pFETs.

[0071] Referring to Figures 5-7 , Figure 5 A top view of the device 300 is provided, Figure 6 A cross-sectional view of the device 300 is provided, Figure 6 through line C-C' is shown, and Figure 7 A cross-sectional view of the device 300 is provided, Figure 6 through line D-D' is shown.

[0072] As shown, the device 300 includes a substrate 302. The substrate 302 can include any appropriate substrate structure, e.g., bulk semiconductor, semiconductor-on-insulator (SOI) substrate, etc. In one example, the substrate 302 can include a silicon-containing material. Illustrative examples of Si-containing materials can include, but are not limited to, Si, SiGe, SiGeC, SiC, and multilayers thereof. Although silicon is the predominant semiconductor material used in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

[0073] Device 300 includes a plurality of top-level fin structures including top-level fins 310, a cap layer 312, and liners 314 formed on sidewalls of top-level fins 310 and cap layer 312. Liners 314 can include any suitable material for protecting top-level fins 310 during downstream processing. Device 300 also includes a plurality of bottom-level fins 316 separated from top-level fins 310 by isolation layers 318. Fins 310 and 316 and isolation layers 318 can be formed from substrate 302 according to embodiments described herein. For example, fins 310 and 316 and isolation layers 318 can be formed by etching through an SOI substrate, where top-level fins 310 are formed from a semiconductor layer, bottom-level fins 316 are formed from a base substrate layer, and isolation layers 318 are formed from an insulating layer disposed between the base substrate layer and the semiconductor layer. In one embodiment, bottom-level fins 316 can correspond to nFETs, and top-level fins 310 can correspond to pFETs. However, this embodiment should not be considered limiting.

[0074] As further shown, bottom-level fins 316 are formed on bottom-level source / drain epi regions 320, and STI regions 322 are disposed on substrate 302 between bottom-level source / drain epi regions 320. Bottom-level source / drain epi regions 320 and STI regions 322 can be formed from substrate 302 according to embodiments described herein using any suitable process.

[0075] Device 300 also includes bottom-level gate stacks 324 formed around respective regions of bottom-level fins 316, bottom-level bottom spacers 326-1, and ILD layer 308, which are similar to spacers 228 and ILD layer 240 described above with reference to device 200. In one embodiment, bottom-level gate stacks correspond to nFET gates. Bottom-level gate stacks 324 can be formed using any suitable process according to embodiments described herein. For example, bottom-level gate stacks 324 can be formed by depositing gate stack material including gate dielectric and gate conductor (e.g., high-k dielectric material and WFM), forming ILD layer 322, and etching exposed gate stack material. Bottom-level top spacers 326-2 can then be formed after bottom-level gate stacks 324 are formed. Figures 2-4

[0076] Device 300 also includes bottom-level top source / drain epi regions 328 formed around respective bottom fins 316. An implant anneal process can be performed to form junctions.​

[0077] Device 300 also includes sacrificial layers 330-1 and 330-2 for source / drain contacts. Sacrificial layers 330-1 and 330-2 can be formed by forming a sacrificial fill, forming a corresponding mask layer, and etching exposed portions of sacrificial layers 330-1 and 330-2. Sacrificial layers 330-1 and 330-2 can include any appropriate material in accordance with embodiments described herein. For example, sacrificial layers 330-1 and 330-2 can include an oxide material, for example.

[0078] Referring to Figure 8 and Figure 9 , an insulator layer 332 is formed that provides N-P isolation. Insulator layer 332 can include any appropriate material in accordance with embodiments described herein (e.g., a nitride material). As further shown, liner 314 is removed, a second liner 334 is formed, and a top-level bottom source / drain epi region 336 is formed around respective ones of top fins 310. Top-level bottom source / drain epi region 336 can be formed using any appropriate process in accordance with embodiments described herein. For example, top-level bottom source / drain epi region 336 can be formed by removing liner 314 (shown in Figure 6 and Figure 7 ), forming a sacrificial dielectric layer (not shown) on insulator layer 332, forming second liner 334 on the dielectric layer, removing the sacrificial dielectric layer, and forming top-level bottom source / drain epi region 336 adjacent to top fins 310 on insulator layer 332 underneath second liner 334. Liner 338 can then be formed.

[0079] Referring to Figure 10 and Figure 11 , portions of liner 338 are removed, and a top-level bottom spacer 340-1, an ILD layer 342, a top-level gate stack 344, a top-level top spacer 340-2, a top-level top source / drain region 346, and an ILD layer 348 are formed.

[0080] Referring to Figure 12 and Figure 13 , openings 350-1 and 350-2 are formed to liners 330-1 and 330-2, respectively. Openings 350-1 and 350-2 can be formed using any appropriate etching process in accordance with embodiments described herein (e.g., reactive ion etching (RIE)).

[0081] Referring to Figure 14 and Figure 15The liners 330-1, 330-2, and 338 are removed to form voids 352-1 and 352-2. The liners 330-1, 330-2, and 338 can be removed using any suitable process according to embodiments described herein.

[0082] Referring to Figure 16 and Figure 17 The voids 352-1 and 352-2 are filled with a conductive material to form contact portions 354-1 and 354-2, respectively. Examples of suitable conductive materials that can be used to form the contact portions 354-1 and 354-2 include, but are not limited to, Cu, W, Ru, Co, Al, etc. The contact portions 354-1 and 354-2 correspond to cross-coupled portions. In alternative embodiments, the bottom contact portions 354-1 and 354-2 are replaced with a conductive material that is deposited on the bottom of the voids 352-1 and 352-2.

[0083] Referring to Figure 18 A block diagram / flow diagram illustrating a system / method 400 for fabricating a semiconductor device including a stacked vertical transistor memory cell according to embodiments is shown.

[0084] At block 410, a bottom level of a stacked vertical transistor memory cell is provided. The bottom level can include a plurality of bottom vertical transistors having merged top source / drain portions. The plurality of bottom vertical transistors can include first and second non-floating transistors and first and second floating transistors. The floating transistors can have at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell.

[0085] At block 420, cross-coupled portions between the bottom level and a top level of the stacked vertical transistor memory cell are formed. The top level can include a plurality of top vertical transistors having merged bottom source / drain epitaxial regions ("epi"). The plurality of top vertical transistors can include first, second, third, and fourth top vertical transistors.

[0086] The plurality of bottom vertical transistors further include respective bottom source / drain epi, and the plurality of top vertical transistors further include respective top source / drain epi. The bottom source / drain epi and the top source / drain epi can be separated by a dielectric layer. The bottom level and the top level can be separated by an isolation layer.

[0087] The plurality of bottom vertical transistors can include n-type field effect transistors (nFETs), and the plurality of top vertical transistors include p-type field effect transistors (pFETs).

[0088] Forming the cross-coupling between the bottom level and the top level can include forming an epi connection from merged top source / drain epis between the first non-floating and floating transistors and between the second non-floating and floating transistors, forming an epi connection from merged bottom source / drain ep is between the first and third top vertical transistors and between the second and fourth top vertical transistors, and forming a gate-to-epi connection from metal between the first non-floating and second floating transistors and between the second non-floating transistor and the first floating transistor, and forming a gate-to-epi connection from metal between the first and second top vertical transistors and between the third and fourth top vertical transistors.

[0089] The bottom level and the top level can also include respective gate structures. Forming the cross-coupling can also include contacting the gate structure of the bottom level with the gate structure of the top level.

[0090] Further details regarding blocks 410 and 420 are described above with reference to Figures 1-17 Description.

[0091] Having described preferred embodiments of a semiconductor device and method of manufacturing the same (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes can be made in the particular embodiments of the disclosure disclosed which are within the scope of the disclosure as outlined by the appended claims. Having thus described aspects of the disclosure with the detail and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

[0092] In a preferred embodiment of the invention described herein, a semiconductor device is provided, comprising: a stacked vertical transistor memory cell, the stacked vertical transistor memory cell comprising: a bottom level comprising a plurality of bottom vertical transistors and gate structures, the plurality of vertical transistors comprising n-type field effect transistors (nFETs) with merged top source / drain epitaxial (epi) regions, the plurality of bottom vertical transistors comprising first and second non-floating transistors and first and second floating transistors, wherein the first and second floating transistors have at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell; a top level comprising a plurality of top vertical transistors and gate structures, the plurality of top vertical transistors comprising p-type field effect transistors (pFETs) with merged bottom source / drain epi, the plurality of top vertical transistors comprising a first top vertical transistor, a second top vertical transistor, a third top vertical transistor, and a fourth top vertical transistor; and a cross-coupling portion contacting the gate structures of the bottom level with the gate structures of the top level, the cross-coupling portion comprising: epi connections formed by the merged top source / drain epi between the first non-floating and floating transistors, and between the second non-floating and floating transistors; epi connections formed by the merged bottom source / drain epi between the first and third top vertical transistors, and between the second and fourth top vertical transistors; gate-to-epi connections formed by metal between the first non-floating and second floating transistors, and between the second non-floating and first floating transistors; and gate-to-epi connections formed by metal between the first and second top vertical transistors, and between the third and fourth top vertical transistors. The plurality of bottom vertical transistors can further comprise respective bottom source / drain epi, and the plurality of top vertical transistors can further comprise respective top source / drain epi. The device can further comprise a dielectric layer separating the bottom source / drain epi from the top source / drain epi, and an isolation layer separating the bottom level from the top level. The device can further comprise word lines, bit lines, power supply voltage, and ground contacts.

Claims

1. A semiconductor device comprising: a stacked vertical transistor memory cell comprising: a bottom tier comprising a plurality of bottom transistors, the plurality of bottom transistors comprising at least one non-floating transistor and at least one floating transistor, each of the plurality of bottom transistors having a merged top source / drain epi, the at least one floating transistor having at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell; a top tier comprising at least two top transistors, each of the top transistors having a merged bottom source / drain epi; and a cross-coupling comprising an epi connection and a gate-to-epi connection between the top tier and the bottom tier.

2. The device of claim 1, wherein: the plurality of bottom transistors comprises a plurality of bottom vertical transistors comprising a first non-floating transistor and a first floating transistor and a second non-floating transistor and a second floating transistor; and the at least two top transistors comprises a plurality of top vertical transistors comprising a first top vertical transistor, a second top vertical transistor, a third top vertical transistor, and a fourth top vertical transistor.

3. The device of claim 2, wherein, the cross-coupling comprises: an epi connection formed by the merged top source / drain epi between the first non-floating transistor and the first floating transistor and the merged top source / drain epi between the second non-floating transistor and the second floating transistor; an epi connection formed by the merged bottom source / drain epi between the first top vertical transistor and the third top vertical transistor and the merged bottom source / drain epi between the second top vertical transistor and the fourth top vertical transistor; a gate-to-epi connection formed by metal between the first non-floating transistor and the second non-floating transistor and metal between the second non-floating transistor and the first floating transistor; and a gate-to-epi connection formed by metal between the first top vertical transistor and the second top vertical transistor and metal between the third top vertical transistor and the fourth top vertical transistor.

4. The device of claim 2, wherein, the plurality of bottom vertical transistors comprise n-type field effect transistors (nFETs) and the plurality of top vertical transistors comprise p-type field effect transistors (pFETs).

5. The device of claim 2, wherein, the plurality of bottom vertical transistors further comprise respective bottom source / drain epis and the plurality of top vertical transistors further comprise respective top source / drain epis.

6. The device of claim 5, further comprising a dielectric layer separating the bottom source / drain epis from the top source / drain epis and an isolation layer separating the bottom tier from the top tier.

7. The device of claim 1, further comprising word lines, bit lines, power supply voltage, and ground contacts.

8. The device of claim 1, wherein, The cross-coupling also contacts the bottom-level gate structure with the top-level gate structure.

9. A method for fabricating a semiconductor device, comprising: forming a stacked vertical transistor memory cell, the stacked vertical transistor memory cell including a bottom level having a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor, each of the plurality of bottom transistors having a merged top source / drain epi, the at least one floating transistor having at least one terminal electrically disconnected from other transistors of the stacked vertical transistor memory cell, and a top level having at least two top transistors each having a merged bottom source / drain epi, wherein forming the stacked transistor memory cell includes: forming a cross-coupling including an epi connection and a gate-to-epi connection between the top level and the bottom level.

10. The method of claim 9, wherein: the plurality of bottom transistors includes a plurality of bottom vertical transistors including a first non-floating transistor and a first floating transistor and a second non-floating transistor and a second floating transistor; and the at least two top transistors includes a plurality of top vertical transistors including a first top vertical transistor, a second top vertical transistor, a third top vertical transistor, and a fourth top vertical transistor.

11. The method of claim 10, wherein, forming the cross-coupling further includes: forming an epi connection from the merged top source / drain epi between the first non-floating transistor and the first floating transistor and the merged top source / drain epi between the second non-floating transistor and the second floating transistor; forming an epi connection from the merged bottom source / drain epi between the first top vertical transistor and the third top vertical transistor and the merged bottom source / drain epi between the second top vertical transistor and the fourth top vertical transistor; forming a gate-to-epi connection from metal between the first non-floating transistor and the second floating transistor and metal between the second non-floating transistor and the first floating transistor; and forming a gate-to-epi connection from metal between the first top vertical transistor and the second top vertical transistor and metal between the third top vertical transistor and the fourth top vertical transistor.

12. The method of claim 10, wherein, the plurality of bottom vertical transistors includes n-type field effect transistors nFETs and the plurality of top vertical transistors includes p-type field effect transistors pFETs.

13. The method of claim 10, wherein, the plurality of bottom vertical transistors further includes respective bottom source / drain epis and the plurality of top vertical transistors further includes respective top source / drain epis.

14. The method of claim 13, wherein, The bottom source / drain epi and the top source / drain epi are separated by a dielectric layer, and wherein the bottom level and the top level are separated by an isolation layer.

15. The method of claim 9, wherein, The stacked vertical transistor device further includes word lines, bit lines, a power voltage, and a ground contact.

16. The method of claim 9, wherein, Forming the cross-coupling further includes contacting the gate structure of the bottom level and the gate structure of the top level.

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