Data Operations Based on Valid Memory Cell Count

Abstract

The present application relates to data operations based on a count of valid memory cells. A memory device includes a plurality of groups of memory blocks, each group includes a plurality of blocks, and each block includes a plurality of memory cells. A memory controller for the memory device performs operations including: for each group, maintaining a count of valid memory cells in the group; and maintaining a count of valid memory cells in each block of the memory device. The operations further include selecting a first group based on the count of valid memory cells, and the first group includes a target plurality of blocks. The operations further include: selecting a first target block from the target plurality of blocks; determining whether the first target block is to be erased; and erasing the first target block in response to determining that the first target block is to be erased.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to data operations based on valid memory cell counts, which may be part of a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory components that store data. The memory devices may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] In one aspect, the present application provides a system comprising: a memory device comprising multiple groups of memory blocks, each group comprising multiple blocks, and each block comprising multiple memory cells; and a memory controller configured to perform operations comprising the following: for each group of the memory device, maintaining a count of valid memory cells in the group; for each block of the memory device, maintaining a count of valid memory cells in the block; selecting a first group from multiple groups based on the count of valid memory cells in the first group, each valid memory cell storing valid data, the first group comprising a target multiple blocks; selecting a first target block from the target multiple blocks based on the count of valid memory cells in the first target block; determining whether the first target block will be erased based on the count of valid memory cells in the first target block; and erasing the first target block in response to determining that the first target block will be erased.

[0004] In another aspect, the present application provides a method, which includes: maintaining, by a memory controller of the memory system, a count of valid memory cells in each group and in each block of memory blocks of a memory device of the memory system, each valid memory cell storing valid data, the memory device including multiple groups of memory blocks, each group including multiple blocks, each block including multiple memory cells; selecting a first group from the multiple groups based on the count of valid memory cells in the first group, the first group including multiple target blocks; selecting a first target block from the multiple target blocks based on the count of valid memory cells in the first target block being equal to the total number of memory cells of the first target block; relocating all data in the first target block to a clean block of a second super block among multiple super blocks; and erasing the first target block.

[0005] In another aspect, the present application provides a non-transitory machine-readable storage medium comprising instructions, which, when executed by a processing device of a memory system, causes the processing device to: maintain a count of valid memory cells for each group and each block of memory blocks of a memory device of the memory system, each count of valid memory cells indicating the number of memory cells storing valid data; select a first group from a plurality of groups of memory blocks based on the count of valid memory cells in the first group, the first group comprising a target plurality of blocks; sort blocks in the target plurality of blocks based on the count of valid memory cells of each block in the target plurality of blocks; select a first target block from the target plurality of blocks based on the count of valid memory cells of the first target block; determine whether data of the first target block will be relocated based on the count of valid memory cells of the first target block; and in response to determining that data of the first target block will be relocated: identify one or more memory cells of the first target block storing valid data; relocate the valid data of the one or more memory cells to a clean block of a second group of the plurality of groups; and erase the first target block. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2A 1 to 2 illustrate example diagrams of how to select a memory block for a data operation based on a valid memory count according to some embodiments of the present disclosure.

[0009] Figure 3A B to B illustrate a flow chart of an example method for applying data operations based on effective memory counts of memory cells on a memory device according to some embodiments of the present disclosure.

[0010] Figures 4A to 4B A flow chart illustrating an example method for performing operations based on valid memory counts of memory cells on a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 The description provides an interaction diagram of interactions between components of a computing environment in the context of some embodiments, in which a method using the allocation techniques of data on a memory device as described herein is performed.

[0012] Figure 6is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Various aspects of the present disclosure are directed to data operations based on valid memory counts of memory cells on a memory device, which may be part of a memory subsystem, wherein the operations may enable the memory device to maintain clean memory cells for storing data within its physical memory locations (e.g., pages) of the memory device. The memory subsystem may be a storage device, a memory module, or a mixture of storage devices and memory modules. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (hereinafter also referred to as a "memory device"). The host system may provide data to be stored at the memory subsystem, and may request data to be retrieved from the memory subsystem.

[0014] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. Some memory devices, such as NAND memory devices, include an array of memory cells (e.g., flash cells) to store data. Each cell includes a transistor, and within each cell, the data is stored as a threshold voltage of the transistor based on the logical value of the cell (e.g., 0 or 1). The memory cells in these devices may be grouped into pages, which may refer to a logical unit of the memory device used to store data. For example, the memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. For some types of memory devices (e.g., NAND), pages are grouped to form blocks (also referred to herein as "memory blocks").

[0015] The host system may send an access request (e.g., a write command, a read command) to the memory subsystem to store data on a memory device at the memory subsystem, read data from a memory device on the memory subsystem, or read / write a configuration relative to a memory device on the memory subsystem. The data to be read or written as specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) for the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, name space) may be part of the metadata of the host data. The metadata may include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., for distinguishing the period of written data), valid bitmap (which LBAs or logical transfer units contain valid data), etc.

[0016] Data operations may be performed by the memory subsystem. Data operations may be operations initiated by the host. For example, the host system may initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem.

[0017] The memory subsystem may initiate media management operations, such as write operations, on host data stored on the memory device. For example, firmware of the memory subsystem may overwrite previously written host data from a location of the memory device to a new location as part of a garbage collection management operation. The overwritten data (e.g., as initiated by firmware) is hereinafter referred to as "garbage collected data".

[0018] Hereinafter, "user data" generally refers to host data and garbage collection data. Hereinafter, "system data" refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical memory address mapping tables (also referred to herein as L2P tables)), data from log records, high-speed scratch pad data, etc.

[0019] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may include one or more planes. For some types of non-volatile memory devices (e.g., NAND type devices), each plane includes a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block includes a set of pages. Each page includes a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is managed externally, for example, by an external controller. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same device package.

[0020] Conventional computer systems, such as conventional supercomputers, may use garbage collection operations in which invalid or failed data contents of non-volatile memory (e.g., NAND devices) are periodically erased to allow new data to be written to the non-volatile memory. However, conventional methods of garbage collection may involve time-consuming and energy-consuming data movement (e.g., between a host system and a memory subsystem). Conventional memory systems deal with the physical limitations of such memory systems by implementing algorithms for wear leveling. Wear leveling allows data to be written to various physical locations of a memory system to distribute wear across the memory system at a uniform rate. The garbage collection algorithm identifies memory and relocates memory from one location to another in conjunction with the wear leveling algorithm to extend the life of the memory system. In conventional non-volatile memory (e.g., NAND devices), data cannot be written to the same location twice without erasing the existing data. The memory device is divided into blocks, and the blocks are further divided into pages. Although data can be written directly to a page, the entire block must be erased before the page can be written again. In order to reclaim the space occupied by old data, invalid data or failed data, the entire block must be searched to relocate valid data before erasing the entire block. After erasing, the block is ready for new valid data to be written.

[0021] The memory subsystem may include flash translation layer (FTL) software that allows the operating system to read and write to the memory device. The FTL may provide conversion from virtual to physical memory addresses, which may call operations including wear leveling and garbage collection. Some memory devices (e.g., NAND flash) cannot write data to locations containing data. In practice, any data at the location is first erased before new data can be written to it. Erase operations typically take a long time because erase operations are performed one block at a time. Data is typically written to an empty location, and the location containing data is marked as invalid, rather than being erased before each data write.

[0022] When the physical location of the data is full or nearly full, a garbage collection operation is performed to relocate the valid data to a new (free) area and erase the original invalid data. A conventional garbage collection operation includes (a) selecting a block that is eligible for erasure, (b) copying the valid data to a separate location, and (c) erasing the selected block.

[0023] A workload is typically a collection of input / output characteristics that interface between a host and a storage device. Workload affects bandwidth and latency. Typically, a NAND device switches between single and mixed workload scenarios depending on the operations received from the host device. When in a single workload scenario, operations such as garbage collection can be run. However, during a mixed workload scenario, the host uses resources that cannot be allocated to resource-intensive operations such as garbage collection. In other words, in a typical mixed workload scenario, the host controller cannot execute read / write commands in conjunction with a garbage collection operation because it is too expensive in terms of resources.

[0024] Indeed, the inventors have contemplated, among other things, a method and corresponding system to account for mixed workload scenarios while still processing data operations, such as garbage collection operations, based on effective memory counts.

[0025] This multi-dimensional model accounts for physical location information such as LUNs. Additionally and / or alternatively, a robust single cursor garbage collection design has been contemplated to reduce latency, power consumption, and firmware overhead. The novel single cursor garbage collection design can identify specific segments of NAND blocks for immediate erasure to avoid power limiting / throttling.

[0026] Aspects of the present disclosure solve the above and other problems by enabling a memory subsystem to perform data operations based on an effective memory count. Specifically, various embodiments enable efficient wear leveling and garbage collection operations to be performed on a memory device to extend the useful life of the memory device and improve performance.

[0027] By using various embodiments, data operations based on the effective memory count can be performed on a memory device or memory subsystem. Additional operations include wear leveling and garbage collection. Therefore, some embodiments can speed up data erasure and save time and energy consumed by garbage collection operations on the memory device. Relative to transactional memory, a data operation mechanism based on the effective memory count can be used to enable a memory device or memory subsystem to pre-erase data blocks to increase garbage collection efficiency. In this way, the memory devices of various embodiments can avoid the need to use expensive, energy-consuming methods to handle and solve garbage collection operations.

[0028] Although various embodiments are described herein with respect to a memory subsystem controller, some embodiments implement the features described herein (e.g., operations for garbage collection, wear leveling) as part of a memory device (e.g., a controller, processor, or state machine of a memory die). For example, various embodiments implement garbage collection operations as part of a controller, processor, or state machine for each bank within a memory device.

[0029] Benefits include the ability to perform data operations across mixed workload scenarios, requiring only a single-threaded architecture, and the ability to proactively erase blocks with empty and / or invalid data.

[0030] Figure 1 An example computing environment 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, etc.

[0033] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110. The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices including a memory and a processing device.

[0034] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a low power double data rate (LPDDR), or any other suitable interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to multiple flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)), which may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory component may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages or memory blocks, which may refer to units of a memory component for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND), and 3D cross-point nonvolatile memory cell arrays are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] In general, the memory system controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical block addresses and physical block addresses. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local media controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] The memory subsystem controller 115 includes a data operation component 113 that can enable or facilitate the performance of data operations based on valid memory counts of memory cells on a memory device (e.g., memory devices 130, 140). For some embodiments, data operators based on valid memory counts enable the memory system to maintain a health level of clean memory cells to perform data operations such as write operations. The data operation component 113 can enable the memory subsystem 110 (via the memory subsystem controller 115) to perform operations including garbage collection operations. The memory subsystem can maintain a count of valid memory cells that indicates how many memory cells in a particular block of memory cells contain valid data. By utilizing the count of valid memory cells, the memory subsystem (via the memory subsystem controller 115) can perform data operations to free up memory cells for future write operations.

[0046] The data operation component 113 can determine which memory block will require the least amount of bandwidth and processing power to achieve the greatest amount of clean storage space based on the valid memory count. In addition, by utilizing the valid memory count, the memory subsystem can initiate a data erase operation without performing another operation to identify and relocate valid data, as performed in conventional systems. Additional details regarding the operation of the data operation component 113 are described below. Figure 2A and 2B An example of this situation is illustrated and described.

[0047] Figures 2A to 2B A flowchart illustrating an example method for applying operations based on valid memory counts of memory cells according to some embodiments of the present disclosure. Method 200 begins loading (operation 202) a list of memory block groups (also referred to herein as one or more "super blocks") identifying one or more super blocks of data within a memory device at a host system or alternatively at a memory controller. The memory controller sorts the list of super blocks based on the number of valid memory cell counts (operation 204). The valid memory cell count indicates the number of memory cells with valid data. This can be achieved by comparing the expected value of each memory cell with the actual value of each memory cell found by performing a P2L lookup to find the physical address mapped to the logical address and then using the logical address in the L2P table again to find the corresponding physical address. If the physical and logical addresses of each lookup match each other, the data is valid and the memory cell associated with the logical address is marked as containing valid data. However, when the physical and logical addresses do not match, the data is invalid and is also marked as such. The list can be organized in a hierarchical manner from lowest to highest or highest to lowest valid memory cell counts. Lists of valid and invalid data may be maintained at different granularities, including at the superblock level, the block level, and the memory cell level.

[0048] At operation 206, the processing device selects a Super Block from the list of Super Blocks. The selected Super Block includes one or more blocks. The selection of the Super Block may be based on the number of Active Memory Counts of the Super Block. In some embodiments, the Super Block with the lowest count of Active Memory Count is selected because it takes the least amount of resources to perform such operations and produces available data storage in the least amount of time.

[0049] Thereafter, at operation 208, the processing device selects a block from the Super Block. The selected block is temporarily marked as a "target block" during the entire operation. The selected "target block" may be the block with the smallest amount of valid memory count within the Super Block. As described above, the valid memory count is maintained at the Super Block, Block, and even at the memory cell level. Each Super Block may include one or more Blocks, and each Block may include one or more memory cells.

[0050] Method 200 Figure 2B 214, the processing device determines whether the count of valid memory cells of the selected "target block" is above zero. If not, meaning that the count of valid memory cells is equal to zero and the target block does not include any valid data, then at operation 216, the processing device erases the block. If yes, then the block includes one or more memory cells storing valid data, and method 200 proceeds to 218. Before the block can be erased, this data needs to be identified and relocated.

[0051] At operation 218, the processing device determines whether the count of valid memory cells is equal to the number of total memory cells. If so, then this means that the entire block is full of valid data. If not, then the block includes some valid and some invalid data. When the block includes some valid data and some invalid data, at operation 220, metadata is loaded to determine which memory cells of the target block include valid data. The controller may maintain a count of valid memory cells, but may not necessarily track which individual cells hold valid or invalid data. At operation 220, the target block undergoes a metadata search for valid data. As described above with respect to Figure 2A As described above, the logical address corresponding to the physical address is searched to determine whether the physical address is actually the physical address of valid data. If there is a match between the physical address and the logical address, the data in the physical address is valid and marked for relocation. If there is no match, relocation is not required and the physical address will be erased in a later operation.

[0052] Thereafter, the processing device relocates the data from the memory unit to a new location, as shown at operation 222. The new location may be in a separate block in a separate Super Block that is not currently undergoing a garbage collection operation.

[0053] The selected block is erased at operation 216 (see operation 222), and in some embodiments, method 200 ends at operation 224. However, if the selected Super Block includes more blocks with valid data, method 200 may be repeated as many times as necessary to erase each block of the Super Block to obtain a clean block.

[0054] Figure 3A and 3B An illustration of an example of performing data operations on a selected super block according to some embodiments of the present disclosure is shown. Figure 3A In the context of , a super block 302 is selected for data operations including garbage collection. Super block 302 may include multiple blocks, such as blocks 310, 320, 330, and 340. Each of blocks 310, 320, 330, and 340 may include one or more memory cells, such as 315-1, 315-2, 315-3, 315-4 to 315-n.

[0055] As shown, super block 302 has four different blocks 310, 320, 330, and 340. Each of the different blocks has five pages of memory cells. For blocks 310 and 340, only one of the five pages of memory cells includes memory cells with valid data (e.g., cells 315-n and 345-n). For blocks 320 and 330, two of the five pages of memory cells include memory cells with valid data. By identifying which blocks have the least number of memory cells with valid data, the controller can select the blocks that require the least amount of resources to implement to relocate and erase.

[0056] In addition, each block within the super block can be mapped for the controller to determine which memory cell within the block contains valid data. The memory controller can identify pages that span multiple blocks that contain valid data. For example, pages 315-4, 325-4, 335-4, and 345-4 are pages that span blocks 310, 320, 330, and 340.

[0057] The controller can recognize that there are two valid memory counts within a page. However, the controller may not necessarily know which page contains valid data. Figure 2B As described in operation 220 of , the controller will parse the block to find memory cells with valid data. The memory controller can be programmed to map the valid memory count per cell across pages and / or per block. The valid memory count of the super block is maintained at indicator 350, which indicates that for super block 302, there are six valid memory cells out of twenty.

[0058] The architecture of the operation can be implemented in a first scenario by looking at memory cells across multiple pages to determine which block to erase, for example with respect to Figure 2A The situation described. Figure 2B Describe the second scenario.

[0059] Figure 3B An illustration of an example superblock showing data operations based on an effective memory count according to some embodiments of the present disclosure. Figure 3A , super block 352 is selected for data operations including garbage collection. Super block 352 may include multiple blocks, such as blocks 360, 370, 380, and 390. Each of the blocks may include one or more memory cells, such as 365-1 to 365-n.

[0060] The memory controller determines that Super Block 352 has a valid memory count of six and maintains the count at indicator 398. Super Block 352 contains four different blocks, each with five memory cells. Super Block 352 therefore has a valid memory count of six out of twenty.

[0061] Likewise, for each block, the memory controller determines a block-specific valid memory count. Figure 3B In the example shown, block 360 has zero valid memory cells out of five. Although the memory controller determines a block-specific valid memory count for each block, if the block has a valid memory count of zero, the memory controller may queue block 360 for immediate erasure. The memory controller may then move to block 370 to determine the valid memory count. In this scenario, the memory controller determines that block 370 has two valid memory cells, block 380 has three valid memory cells, and 390 has one valid memory cell. Based on the valid memory counts, the memory controller may choose to perform a garbage collection operation on block 390, followed by block 370, followed by block 380, due to the lowest valid memory count.

[0062] like Figure 3A and 3B The two methods of identifying which memory cell to relocate and / or erase described in the can be implemented according to the methods described herein. In some embodiments, the two methods of identifying memory cells by page and block are implemented together. It should be understood and appreciated that Figure 3A and Figure 3B The disclosed contents can be used in series, separately or in combination of the two.

[0063] Figure 4AFlowchart of an example method 400 similar to method 200 for performing data operations based on an effective memory count according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1 The data operation component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] 4, method 400 illustrates an example of performing data operations based on valid memory counts according to some embodiments. At operation 405, a processing device maintains a count of valid memory cells per super block and a count of valid memory cells per block of a memory device.

[0065] At operation 410, the processing device selects a first Super Block based on a count of valid memory cells of the first Super Block. Each valid memory cell stores valid data, and the first Super Block includes a target plurality of blocks. After selecting the first Super Block, the processing device may sort blocks in the target plurality of blocks based on a count of valid memory cells in each block in the target plurality of blocks. Sorting the blocks may include sorting the blocks in increasing order of count of valid memory cells.

[0066] The processing device then selects a target block based on the count of valid memory cells in the first target block (see operation 415). The processing device may, for example, Figure 2A and 2B For example, the processing device may select the target block based on: (i) the lowest valid memory count, (ii) the valid memory count equals zero, or (iii) the valid memory count equals the number of memory cells within the block.

[0067] In FIG. 4B , the processing device at method 400 performs the following steps: Figure 4A Additional and / or alternative operations as shown in .

[0068] The method 400 then proceeds to operation 416, where the processing device determines whether the data of the target block is to be relocated. The valid memory count of the target block indicates whether there is dirty data, empty cells, or valid data. When the valid memory count is zero, there are no cells containing valid data. When the valid memory count is above zero, there are cells containing valid data. When the valid memory count is equal to the number of memory cells, all memory cells contain valid data, and the entire memory cell needs to relocate the data before the data stored in the memory cell can be erased.

[0069] At operation 417, the processing device identifies one or more memory cells storing valid data. Figure 2B As described in operation 220 of , the processing device finds which memory cells of the block include valid data.

[0070] At operation 418, the processing device relocates valid data of one or more memory cells to a clean block. In some embodiments, a clean block is an unoccupied block within a different Super Block that is not currently undergoing a data operation, such as garbage collection. In some embodiments, a clean block is a partially occupied block having one or more memory cells storing valid data, the partially occupied block being in a different Super Block that is not currently undergoing a data operation. In some embodiments, a clean block is a previously erased block within a current Super Block that is undergoing a data operation.

[0071] Return to Figure 4A , at operation 420, the processing device determines whether the target block will be erased. The processing device may check to see if the valid memory count is at zero to determine whether the target block will be erased. In some embodiments, the processing device may parse the block before erasing it to confirm that there are no memory cells containing valid data.

[0072] The method then proceeds to operation 425 where the processing device erases the target block. The target block is then cleared of any old or invalid data and is ready to be written again.

[0073] At operation 430, the processing device updates the count of valid memory cells based on erasing the target block. After erasing the target block, the count of valid memory cells of the Super Block is updated to reflect that the target block has a zero valid memory cell count. At operation 430, while updating the count of valid memory cells, the processing device may continue to perform data operations within the Super Block, start execution of data operations at a separate Super Block, or stop data operations related to garbage collection.

[0074] In an example, a memory device includes a plurality of super blocks. Each super block includes a plurality of blocks, and each block includes a plurality of memory cells. The memory device includes a memory controller configured to maintain a count of valid memory cells in a super block for each super block of the memory device. The memory controller also maintains a count of valid memory cells in each block of the memory device. The memory controller then selects a first super block based on the count of valid memory cells in a first super block. A first target block is selected from a super block based on the count of valid memory cells in a first target block. The memory controller determines whether to erase the first target block based on the count of valid memory cells. If the count of valid memory cells is zero, the memory controller erases the first target block. After erasing the first target block, the memory controller selects a second target block based on the count of valid memory cells in a second target block, and determines whether the second target block includes data to be relocated. In response to determining that the data of the second target block will be relocated, the memory controller identifies one or more memory cells storing valid data of the second target block and relocates the valid data to a clean block. The clean block may be a clean block in a second super block among a plurality of super blocks. After relocating the valid data to the clean block, the memory controller erases the second target block and updates the count of valid memory cells in the target multiple blocks. The memory controller may select a subsequent target block based on the count of valid memory cells in the subsequent target block, and determine whether to relocate the data of the subsequent target block based on the count of valid memory cells in the subsequent target block. In response to determining that the data of the subsequent target block will be relocated, the memory controller identifies one or more memory cells storing valid data of the subsequent target block, relocates the valid data to the clean block of the second super block, and erases the subsequent target block. The memory controller then updates the count of valid memory cells in the target multiple blocks based on erasing the subsequent target block. This process performed by the memory controller may continue until the valid memory count of the first super block is zero. This process may be suspended or terminated according to the processing needs of the memory controller.

[0075] In another example, a memory device includes a plurality of super blocks. Each super block includes a plurality of blocks, and each block includes a plurality of memory cells. The memory device includes a memory controller configured to maintain a count of valid memory cells in the super block for each super block of the memory device. The memory controller also maintains a count of valid memory cells in each block of the memory device. The memory controller then selects a first super block based on the count of valid memory cells in the first super block. A first target block is selected from the super block based on the count of valid memory cells in the first target block. The memory controller determines whether to erase the first target block based on the count of valid memory cells. If the count of valid memory cells is zero, the memory controller erases the first target block. After erasing the first target block, the memory controller selects a second target block based on the count of valid memory cells in the second target block being equal to the total number of memory cells of the second target block, and relocates all data of the second target block to a clean block of the second super block. The memory controller erases the second target block, and updates the count of valid memory cells in the target multiple blocks based on the erasure of the second target block. The memory controller may identify each subsequent target block of the target multiple blocks from the target multiple blocks that has a corresponding count of valid memory cells equal to the total number of memory cells of the target block, and for each subsequent target block, relocate all data in the subsequent target block to a second clean block of a second Super Block in the multiple Super Blocks, erase the subsequent target block, and update the count of valid memory cells in the target multiple blocks based on the erasure of the multiple subsequent target blocks. This process performed by the memory controller may continue until the valid memory count of the first Super Block is zero. This process may be paused or terminated according to the processing needs of the memory controller.

[0076] Figure 5 An interaction diagram is provided that illustrates interactions between components of a computing environment in the context of some embodiments, in which a method of allocating techniques for data on a memory device as described herein is performed. The operations of the method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is performed by a host system (e.g., 120), a memory subsystem controller (e.g., 115), a memory device (e.g., 130 or 140), or some combination thereof. Although the operations are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally and / or alternatively, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. In Figure 5In the context of the examples illustrated in , the host system may include host system 120 , the memory subsystem controller may include memory subsystem controller 115 , and the memory device may include memory device 140 .

[0077] like Figure 5 , at operation 502, the host system sends a memory command associated with a memory cell to the memory subsystem 110. At operation 504, the memory subsystem controller 115 receives a memory command associated with optimizing the memory cell. At operation 506, the memory device provides an indication of valid memory cells for each block of memory. In some embodiments, the flash translation layer may maintain a count of valid memory cells for each block of memory.

[0078] In response to the memory command received at operation 504, the memory subsystem controller 115 performs a garbage collection operation. At operation 508, the garbage collection operation includes: selecting a first Super Block based on the count of valid memory cells; selecting a target block based on the count of valid memory cells; and relocating data from the target block to another block in a separate Super Block. At operation 510, the memory device relocates data within the target block to another block in a separate Super Block. For example, Super Block #1 undergoes a garbage collection operation. Super Block #1 includes Target Block 1. Data stored within Target Block #1 undergoes a garbage collection operation, and according to some embodiments, the data within Target Block #1 is relocated to Block A within Super Block #2.

[0079] The memory controller determines whether the target block is ready to be erased (eg, whether all valid data has been relocated), and erases the target block based on the determination that the target block is ready to be erased (see operation 512).

[0080] Based on determining at operation 512 that the target block is to be erased, the target block is erased at operation 514. After erasing the target block, at operation 516 the memory controller provides a record of the super block having empty blocks to the host system, which receives the record at operation 518.

[0081] The host system may then decide to repeat steps 502 through 518 utilizing another selected Super Block (eg, a second Super Block) within the memory device based at least in part on the received record indicating a number of empty blocks.

[0082] Figure 6 An example machine illustrating a computer system 600 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to perform operations of the controller (e.g., execute an operating system to perform operations based on Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0083] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by the machine. Further, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform one or more of the methodologies discussed herein.

[0084] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0085] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0086] The data storage system 618 may include a machine-readable storage medium 628 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, in whole or in part, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0087] In one embodiment, instructions 626 include instructions for determining a memory usage based on an effective memory count component (e.g., Figure 1 The data operator component 109 of the present disclosure implements the functional instructions corresponding to the data operation. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for machine execution and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0088] Some portions of the previously detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are used by those skilled in the art of data processing to most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. The operations are operations that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient, primarily for general reasons, to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0089] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0090] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using various programming languages.

[0092] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0093] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader scope of embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a memory device comprising a plurality of groups of blocks, each group comprising a plurality of blocks, and each block comprising a plurality of memory cells, the plurality of groups being identified by a group list; as well as A memory controller configured to perform operations including: For each of the plurality of groups, maintaining a count of all valid memory cells in the group; For each block of the memory device, maintaining a count of all valid memory cells in the block; sorting the group list based on a count of all valid memory cells for each group in the group list; selecting, based on the sorted group list, a first group having a count of all valid memory cells, the count being a lowest count in the group list, each valid memory cell storing valid data, the first group comprising the target plurality of blocks; selecting the first target block from the target plurality of blocks based on a count of all valid memory cells in the first target block; determining whether the first target block is to be erased based on the count of all valid memory cells in the first target block; as well as The first target block is erased in response to determining that the first target block is to be erased.

2. The system of claim 1, wherein the selecting the first target block comprises selecting the first target block based on the count of all valid memory cells in the first target block being zero.

3. The system of claim 1, wherein the operations further comprise, after selecting the first group, sorting blocks in the target plurality of blocks based on a count of all valid memory cells in each block in the target plurality of blocks.

4. The system of claim 1 , wherein after erasing the first target block, the memory controller performs operations further comprising: The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the first target block.

5. The system of claim 4, further comprising: identifying, from the target plurality of blocks, each individual target block of the target plurality of blocks having a corresponding count of valid memory cells equal to zero; and For each individual target block, the individual target block is erased.

6. The system of claim 1, wherein the operations further comprise: selecting the second target block from the target plurality of blocks based on a count of all valid memory cells in the second target block; determining whether data of the second target block is to be relocated based on the count of all valid memory cells in the second target block; as well as In response to determining that the data of the second target block is to be relocated: identifying one or more memory cells of the second target block storing valid data; relocating the valid data of the one or more memory cells to a clean block of a second group of the plurality of groups; erasing the second target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the second target block.

7. The system of claim 6, further comprising: selecting the third target block from the target plurality of blocks based on a count of all valid memory cells in the third target block; determining whether data of the third target block is to be relocated based on the count of all valid memory cells in the third target block; as well as In response to determining that the data of the third target block is to be relocated: identifying one or more memory cells of the third target block storing valid data; relocating the valid data of the one or more memory cells to a clean block of a second group of the plurality of groups; erasing the third target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on erasing the third target block.

8. The system of claim 1, wherein the operations further comprise: After erasing the first target block: selecting the second target block from the target plurality of blocks based on a count of all valid memory cells in the second target block being equal to a total number of memory cells of the second target block; relocating all data of the second target block to a clean block of a second group of the plurality of groups; erasing the second target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the second target block.

9. The system of claim 8, further comprising: identifying, from the target plurality of blocks, each individual target block of the target plurality of blocks having a corresponding count of valid memory cells equal to the total count of memory cells in the individual target block; as well as For each individual target block: relocating all data in the individual target block to a second clean block in a second group of the plurality of groups; erasing the individual target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the individual target block.

10. The system of claim 1, wherein the operations are performed as part of a garbage collection process performed on the memory device.

11. A method comprising: maintaining, by a memory controller of a memory system, a count of all valid memory cells in each of a plurality of groups of blocks of a memory device and a count of all valid memory cells in each block of the memory device, the memory system comprising the memory device, each valid memory cell storing valid data, each group comprising a plurality of blocks, each block comprising a plurality of memory cells, the plurality of groups being identified by a group list; sorting the group list based on a count of all valid memory cells for each group in the group list; selecting, based on the sorted group list, a first group having a count of all valid memory cells that is a lowest count in the group list, the first group including the target plurality of blocks; selecting the first target block from the target plurality of blocks based on a count of all valid memory cells of the first target block being equal to a total number of memory cells of the first target block; relocating all data in the first target block to a clean block in a second group of the plurality of groups; as well as The first target block is erased.

12. The method according to claim 11, further comprising: The blocks in the target plurality of blocks are ordered based on a count of all valid memory cells of each block in the target plurality of blocks.

13. The method of claim 11, further comprising: identifying, from the target plurality of blocks, each individual target block of the target plurality of blocks having a corresponding count of valid memory cells equal to the total count of memory cells in the target block; as well as For each individual target block: relocating all data in the individual target block to a second clean block in a second group of the plurality of groups; erasing the individual target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the individual target block.

14. The method of claim 11, further comprising: selecting the second target block from the target plurality of blocks based on a count of all valid memory cells of the second target block; determining whether data of the second target block is to be relocated based on a count of all valid memory cells of the second target block; as well as In response to determining that the data of the second target block is to be relocated: identifying one or more memory cells of the second target block storing valid data; relocating the valid data of the one or more memory cells to a second clean block of a second group of the plurality of groups; erasing the second target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the second target block.

15. The method of claim 11, further comprising: selecting the second target block from the target plurality of blocks based on the counts of all valid memory cells of the second target block being equal to zero; erasing the second target block; and The count of all valid memory cells in the target plurality of blocks is updated based on the erasure of the second target block.

16. A non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory system, cause the processing device to: maintaining a count of all valid memory cells in each of a plurality of groups of blocks of a memory device and a count of all valid memory cells in each block of the memory device, the memory system comprising the memory device, each valid memory cell storing valid data, each group comprising a plurality of blocks, each block comprising a plurality of memory cells, the plurality of groups being identified by a group list; sorting the group list based on a count of all valid memory cells for each group in the group list; selecting, based on the sorted group list of blocks, a first group having a count of all valid memory cells that is a lowest count in the group list, the first group including the target plurality of blocks; sorting blocks in the target plurality of blocks based on a count of all valid memory cells of each block in the target plurality of blocks; selecting the first target block from the target plurality of blocks based on a count of all valid memory cells of the first target block; determining whether data of the first target block is to be relocated based on the count of all valid memory cells of the first target block; as well as In response to determining that data of the first target block is to be relocated: identifying one or more memory cells of the first target block storing valid data; relocating the valid data of the one or more memory cells to a clean block of a second group of the plurality of groups; as well as The first target block is erased.

17. The storage medium of claim 16, wherein the instructions further comprise instructions to: selecting the individual target block from the target plurality of blocks based on a count of all valid memory cells in the individual target block; determining whether data of the individual target block is to be relocated based on the count of all valid memory cells in the individual target block; as well as In response to determining that the data of the individual target block is to be relocated: identifying one or more memory cells of the second target block storing valid data; relocating the valid data of the one or more memory cells to a clean block of a second group of the plurality of groups; erasing the individual target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on erasing the individual target block.

18. The storage medium of claim 16, wherein the instructions further comprise instructions to: selecting the second target block from the target plurality of blocks based on the counts of all valid memory cells of the second target block being equal to zero; erasing the second target block; and The count of all valid memory cells in the target plurality of blocks is updated based on erasing the second target block.

19. The storage medium of claim 16, wherein the instructions further comprise instructions to: selecting the second target block from the target plurality of blocks based on a count of all valid memory cells of the second target block being equal to a total number of memory cells of the second target block; relocating all data in the second target block to a clean block of a second group of the plurality of groups; erasing the second target block; as well as The count of all valid memory cells in the target plurality of blocks is updated based on erasing the second target block.

20. The storage medium of claim 16, wherein the instructions execute as part of a garbage collection process performed on the memory system.

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