Valid data identification for garbage collection

Abstract

The present application relates to valid data identification for garbage collection. With respect to writing data to a block of memory cells, a memory system may identify a portion of a logical address space that contains a logical address of the data. The memory system may set a bit of a bitmap that may indicate that the block contains data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any number of portions, each portion corresponding to a different subset of a logical-to-physical L2P table, and the bitmap may contain any number of corresponding bits. In order to perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table for evaluation to determine whether different sets of data within the block are valid or invalid.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 129,373 filed by Palmer on December 21, 2020, entitled “VALID DATA IDENTIFICATION FOR GARBAGE COLLECTION,” which is assigned to the assignee of this application and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to efficient data identification for garbage collection. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, either of which can be stored by the memory cell. In order to access information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D cross-point), non-OR (NOR) and non-AND (NAND) memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) can lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of external power. Summary of the invention

[0006] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium storing code includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: determine to perform a garbage collection operation on a block of memory cells, wherein the block of memory cells stores data corresponding to a plurality of logical addresses within a logical address space; read a bitmap for the block of memory cells, wherein each bit of the bitmap corresponds to a respective portion of the logical address space and indicates whether the respective portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data; evaluate a subset of a logical-to-physical (L2P) table of the logical address space, the evaluation being performed based at least in part on bits of the bitmap indicating that at least one logical address within the plurality of logical addresses is within a portion of the subset of the logical address space corresponding to the L2P table; identify which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table; and perform a garbage collection operation on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: write a set of data to a subset of a memory cell block, the set of data corresponding to a logical address within a logical address space; identify a portion of the logical address space that includes the logical address based at least in part on writing the set of data to the subset of the memory cell block; and set a bit of a bitmap based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap set indicate that data corresponding to at least one logical address within the corresponding portion of the bits of the logical address space is stored within the memory cell block.

[0008] An apparatus is described. The apparatus includes: a memory array; a controller coupled to the memory array and configured to cause the apparatus to: determine to perform a garbage collection operation on a block of memory cells within the memory array, the block of memory cells storing data corresponding to a plurality of logical addresses within a logical address space; read a bitmap for the block of memory cells, wherein each bit of the bitmap corresponds to a respective portion of the logical address space and indicates whether the respective portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data; evaluate a subset of a logical-to-physical (L2P) table of the logical address space, the evaluation being performed based at least in part on bits of the bitmap indicating that at least one logical address within the plurality of logical addresses is within a portion of the subset of the logical address space corresponding to the L2P table; identify which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table; and perform a garbage collection operation on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

[0009] An apparatus is described. The apparatus includes: a memory array; a controller coupled to the memory array and configured to cause the apparatus to: write a set of data to a subset of memory cell blocks within the memory array, the set of data corresponding to logical addresses within a logical address space; identify a portion of the logical address space that includes the logical addresses based at least in part on writing the set of data to the subset of memory cell blocks; and set bits of a bitmap based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap set indicate that data corresponding to at least one logical address within the corresponding portion of the bits of the logical address space is stored within the memory cell blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting efficient data identification for garbage collection according to examples disclosed herein is illustrated.

[0011] Figure 2 An example of a block diagram supporting identification of valid data for garbage collection according to examples disclosed herein is illustrated.

[0012] Figure 3 An example of a process flow that supports identification of valid data for garbage collection according to examples disclosed herein is illustrated.

[0013] Figure 4 A block diagram of a memory system supporting efficient data identification for garbage collection according to examples disclosed herein is illustrated.

[0014] Figure 5 and 6 A flow chart illustrating one or more methods of supporting efficient data identification for garbage collection according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0015] A memory system may be configured to store data within memory cells, where different groups of memory cells may have different physical addresses within a physical address space of the memory system. Different sets of data may be associated with different logical addresses within a logical address space, which may alternatively be referred to as a system address space or a virtual address space, and may be referenced by a host device to identify different sets of data (e.g., a read or write command from a host device may indicate a corresponding set of data based on the logical address of the corresponding set of data). In some cases, a memory system may be organized into blocks of memory cells, and in some cases, a block of memory cells may be configured to store multiple sets of data, each set of data corresponding to a different logical block address (LBA) and stored in different groups of memory cells (e.g., different groups of memory cells within a block) having corresponding physical block addresses (PBAs).

[0016] The memory system may store and maintain a logical-to-physical (L2P) table indicating a mapping between a physical address space and a logical address space corresponding to a logical address. For example, the L2P table may indicate the physical address of a group of memory cells in which data associated with each logical address is stored. The L2P table may additionally be used by the memory system to determine whether data associated with a given physical address is valid. As used herein, an L2P table may refer to a single table or to multiple tables that collectively span corresponding logical address spaces, corresponding physical address spaces, or both.

[0017] In some cases, the memory system may perform one or more management (e.g., maintenance) operations to facilitate the performance of the memory system. For example, the memory system may determine to perform a garbage collection operation on a memory cell block. In conjunction with the garbage collection operation of the memory cell block, the memory system may evaluate the L2P table to identify which of the data groups stored by the memory cell block is valid. The memory system may then store the valid data in a different memory cell block and erase the data (e.g., valid data and invalid data) stored in the memory cell block, which may make the memory cell block available for storing, for example, new data.

[0018] In some cases, evaluating the entire L2P table to identify valid data stored by a memory cell block may be inefficient. For example, the L2P table may be relatively large, and evaluating the entire L2P table may take a correspondingly large amount of time. However, as described herein, a memory system may alternatively evaluate one or more subsets of the L2P table to identify valid data stored by a memory cell. For example, a memory system may store a bitmap for each memory cell block, wherein each bit of the bitmap corresponds to a corresponding subset of the L2P table, and indicates whether the memory cell block is storing any data associated with a logical address within a portion of the logical address space corresponding to the corresponding subset of the L2P table. Therefore, the bitmap of the memory cell block may indicate one or more subsets of the L2P table as being associated with the memory cell block. In this example, the memory system may not evaluate the entire L2P table to identify valid data stored by the memory cell block, but rather evaluate one or more subsets of the L2P table indicated by the bitmap. In some cases, this may improve the efficiency associated with garbage collection operations performed by the memory system (e.g., by reducing one or more associated delays). Additionally or alternatively, such techniques may allow overhead associated with garbage collection operations performed by the memory system to be tunable (e.g., adjustable, configurable) based on the sizes of various subsets of the L2P table configured (e.g., whether the L2P table is divided into relatively more small subsets, or relatively fewer large subsets), as well as other benefits that would be appreciated by one of ordinary skill in the art.

[0019] The features of the present disclosure are first described in reference Figures 1 to 3These and other features of the present disclosure are described in the context of the systems, block diagrams, and flow charts described herein. Figures 4 to 6 The described effective data identification for garbage collection is further illustrated and described in the related equipment diagram and flow chart.

[0020] Figure 1 An example of a system 100 that supports valid data identification for garbage collection according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0022] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0023] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, the coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or contained in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use, for example, the memory system 110 to write data to and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , and the host system 105 may be coupled to any number of memory systems 110 .

[0024] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0025] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 Although two memory devices 130-a and 130-b are shown in the example of FIG, the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130 - and other such operations - which may be broadly referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (such as error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuits with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store opcodes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for internal storage or computation, such as memory related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to the memory device 130) according to a cache policy.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 can operate in conjunction with the memory system controller 115, or can perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown, memory device 130a may include a local controller 135a, and memory device 130b may include a local controller 135b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 (e.g., a block of memory cells) may include a corresponding set of pages 175, and each page 175 may include a set of memory cells. In addition, each page 175 may be configured to store a corresponding set of data associated with one or more logical addresses (e.g., within a logical address space referenced by or otherwise associated with a host system).

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170 as long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to sharing of command decode, page address decode circuitry, or other circuitry between planes 165).

[0035] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which can alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but may be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that may be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that may be independently erased (e.g., erased simultaneously as part of a single erasing operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0037] In some cases, in order to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise designate the data retained in the old block 170 as invalid or obsolete, and may update the L2P table (e.g., the L2P mapping table) to associate the logical address (e.g., LBA) of the data with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be preferable to erasing and rewriting the entire old block 170, for example, due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0038] In some cases, an L2P table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated due to a newer or updated version of data stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address (such as a logical address referenced by the host system 105). Valid data may be the latest version of such data stored on the memory device 130. A page 175 that contains no data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations of the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm referred to as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in a block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0040] In some cases, evaluating the entire L2P table to identify valid data stored by a block of memory cells (e.g., during a garbage collection operation) may be inefficient. For example, the L2P table may be relatively large, and evaluating the entire L2P table may take a correspondingly large amount of time. However, as described herein, the memory system 110 may alternatively evaluate one or more subsets of the L2P table to identify valid data stored by the memory cells. For example, the memory system 110 may store a bitmap for each block 170 (e.g., within the block 170, within the local memory 120, at the local controller 135), wherein each bit of the bitmap corresponds to a corresponding subset of the L2P table and indicates whether the block 170 is storing any data associated with a logical address within a portion of the logical address space corresponding to the corresponding subset of the L2P table. Thus, the bitmap for the block 170 may indicate one or more subsets of the L2P table as being associated with the block 170. In this example, rather than evaluating the entire L2P table to identify valid data stored by block 170, memory system 110 may evaluate one or more subsets of the L2P table indicated by the bitmap. In some cases, this may improve efficiency associated with garbage collection operations performed by memory system 110 (e.g., by reducing one or more associated delays). Additionally or alternatively, such techniques may allow overhead associated with garbage collection operations performed by memory system 110 to be tunable (e.g., adjustable, configurable) based on the size of the various subsets of the L2P table configured (e.g., whether the L2P table is divided into relatively more small subsets, or relatively fewer large subsets), as well as other benefits that would be appreciated by one of ordinary skill in the art.

[0041] The system 100 may include any number of non-transitory computer-readable media that support valid data identification for garbage collection. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0042] Figure 2 An example of a block diagram 200 for supporting valid data identification for garbage collection according to an example disclosed herein is shown. The block diagram 200 may be implemented as shown in FIG. Figure 1 For example, a memory system, such as reference Figure 1 As described above, the memory unit block 270, the L2P table 210 and the bitmap 220 may be included. In addition, the memory unit block 270 may be as shown in FIG. Figure 1 2. Block diagram 200 may illustrate an example relationship between data 205 stored at a memory cell block 270, an L2P table 210, and a bitmap 220. In some cases, a memory system may include a bitmap 220 for each memory cell block 270 of the memory system. Additionally, the memory system may reference the same L2P table 210 for multiple (e.g., each) memory cell block 270 of the memory system.

[0043] The memory cell block 270 may store multiple sets of data 205. In some cases, the memory cell block 270 may include groups of memory cells (e.g., pages 175) each having a corresponding physical address (e.g., PBA) and configured to store corresponding data sets 205 corresponding to one or more logical addresses (e.g., LBA). For example, within the memory cell block 270, a first group of memory cells may store data 205-a corresponding to a first logical address, a second group of memory cells may store data 205-b corresponding to a second logical address, a third group of memory cells may store data 205-c corresponding to a third logical address, and a fourth group of memory cells may store data 205-d corresponding to a fourth logical address. Although the block diagram 200 illustrates the memory cell block 270 as storing data sets 205 associated with four logical addresses, the memory cell block 270 may be configured to store any number of data sets 205 associated with any number of logical addresses (e.g., 64 logical addresses, 6000 logical addresses).

[0044] The L2P table 210 may indicate a mapping between logical addresses (e.g., associated with a host system) and physical addresses (e.g., associated with a page of the memory cell block 270). That is, the L2P table 210 may indicate, for each logical address, a physical address of a memory cell at which data corresponding to the logical address is stored. For example, in some cases, the L2P table 210 may be an ordered list of physical addresses (e.g., PBAs), wherein each position within the L2P table 210 corresponds to a corresponding logical address (e.g., LBA), and thus a physical address listed in a particular position within the L2P table 210 indicates that data associated with the logical address corresponding to the position is stored at the memory cell having the listed physical address.

[0045] The L2P table 210 may be partitioned into any number of subsets 215 (e.g., one or more portions, one or more regions). Each subset 215 of the L2P table 210 may contain information associated with a corresponding portion (e.g., region) of the logical address space covered by the L2P table 210. For example, subset 215-a may contain information associated with a first set of logical addresses, subset 215-b may contain information associated with a second set of logical addresses, subset 215-c may contain information associated with a third set of logical addresses, and subset 215-d may contain information associated with a fourth set of logical addresses. In the example of block diagram 200, subset 215-a of the L2P table 210 may contain logical addresses associated with data 205-a, data 205-b, and data 205-c. Additionally, subset 215-c of the L2P table 210 may contain logical addresses associated with data 205-d. In some cases, the memory cell block 270 may not include any data 205 associated with one or more subsets 215 of the L2P table 210 (e.g., Figure 2 In the example, no data associated with subsets 215-b and 215-d is stored within memory cell block 270).

[0046] For each memory cell block 270, the memory system may indicate a corresponding bitmap 220. For each subset 215 of the L2P table 210, the bitmap 220 may indicate whether the memory cell block 270 contains any data 205 associated with the logical addresses covered by the subset 215. For example, the bitmap 220 may include a corresponding bit 225 associated with each subset 215 of the L2P table 210. For example, bit 225-a may be associated with subset 215-a, bit 225-b may be associated with subset 215-b, bit 225-c may be associated with subset 215-c, and bit 225-d may be associated with subset 215-d. The value of the bit 225 associated with the subset 215 may indicate whether the memory cell block 270 contains any data 205 with a logical address covered by the subset 215 (e.g., within the logical address range associated therewith). For example, bit 225-a of bitmap 220 may store a value (e.g., a logical value of "1") indicating that subset 215-a of L2P table 210 contains at least one logical address corresponding to data 205 stored in memory cell block. Conversely, for example, bit 225-b may store a different value (e.g., a logical value of "0") indicating that subset 215-b of L2P table 210 does not contain a logical address corresponding to any data 205 stored in memory cell block 270. In the example of block diagram 200, memory cell block 270 stores data 205 corresponding to logical addresses within subset 215-a and subset 215-c. Therefore, bitmap 220 may include bits 225-a and 225-c, respectively indicating that subsets 215-a and 215-c of L2P table 210 have logical addresses corresponding to data 205 stored in memory cell block 270. Additionally, bits 225 - b and 225 - d may indicate that subsets 215 - b and 215 - d , respectively, do not include a logical address corresponding to data 205 stored in block of memory cells 270 .

[0047] In some cases, the memory system may update the L2P table 210 and the bitmap 220 in conjunction with writing the data 205 to the memory cell block 270. For example, in conjunction with storing the data 205 in the memory cell block 270, the memory system may update the L2P table 210 to indicate that the data 205 corresponding to a certain logical address is stored in a memory cell having a certain physical address within the memory cell block 270. For example, in conjunction with writing the data 205-c corresponding to a certain logical address to the memory cell block 270, the memory system may update the L2P table 210 to indicate that the data 205-c corresponding to the certain logical address is stored within a third group of memory cells (e.g., the third page 175) within the memory cell block 270. Here, the logical address corresponding to the data 205-c may be within a range or other set of logical addresses associated with (e.g., mapped by, covered by) the subset 215-a of the L2P table 210. Thus, the memory system can update entries within a subset 215-a of the L2P table 210 based on writing data 205-c to a memory cell block 270, wherein the updated entry can map a logical address (e.g., LBA) of the data 205-c to a physical address (e.g., PBA) of a third group of memory cells (e.g., a third page 175) within the memory cell block 270.

[0048] Additionally or alternatively, the memory system may update the bitmap 220 in response to storing the data 205 in the memory cell block 270. For example, based on writing the data 205-c to the memory cell block 270, the memory system may set the bit 225-a (e.g., corresponding to the subset 215-a of the L2P table 210) to a value indicating that the memory cell block 270 is storing the data 205-c corresponding to at least one logical address covered by the subset 215-a of the L2P table 210.

[0049] In response to determining to perform a garbage collection operation at the memory cell block 270, the memory system may reference the bitmap 220 to identify one or more subsets 215 of the L2P table 210 for evaluation (e.g., to identify whether a given data set 205 stored by the memory cell block 270 is valid or invalid, as described in more detail elsewhere herein, including reference to the bitmap 220). Figure 3). The memory system may identify one or more subsets 215 to evaluate based on the value of bit 225 of bitmap 220. In the example of block diagram 200, the memory system may determine to evaluate subset 215-a and subset 215-c based on bitmap 220. That is, bits 225-a and 225-c may respectively indicate that subsets 215-a and 215-c each contain at least one logical address corresponding to data 205 stored by memory cell block 270. In addition, bits 225-b and 225-d may respectively indicate that subsets 215-b and 215-d do not contain any logical addresses corresponding to data 205 stored by memory cell block. Therefore, the memory system may evaluate subsets 215-a and 215-c of L2P table 210, and may avoid evaluating subsets 215-b and 215-d. Thus, the memory system may evaluate only a portion of L2P table 210 (eg, one or more subsets 215) when performing garbage collection on memory cell block 270, which may provide latency benefits, efficiency benefits, or both, among other possible benefits.

[0050] The size of the subset 215 may be configurable, either as part of the design of the memory system, or as a configurable parameter of the memory system, which may be configured after manufacturing (e.g., based on one or more fuse settings) or dynamically (e.g., during run time or as part of any initialization process, such as by a host system of the memory system). Thus, different memory systems may utilize different sizes for the subsets 215 of the L2P table 210, or the same memory system may utilize different sizes for the subsets 215 of the L2P table 210 at different times. Furthermore, in some cases, different subsets 215 may have different sizes simultaneously even within the same memory system. For example, for a first memory cell block 270, each subset 215 of the L2P table 210 may contain information associated with a first number of logical addresses. Additionally, for a second memory cell block 270, each subset 215 contains information associated with a second number of logical addresses (e.g., having a second size). As the size of the subset 215 for the L2P table 210 increases, the number of subsets 215 associated with the L2P table 210 decreases. Additionally, as the size of the subsets 215 for the L2P table 210 decreases, the number of subsets 215 increases.

[0051] Regardless of the size of the subsets 215 for the memory cell blocks 270, the memory system may use a bitmap 220 that includes corresponding bits 225 for each subset 215. Therefore, the size of each bitmap 220 may be based on the number of subsets 215 for the corresponding memory cell blocks 270 of the L2P table 210. In some cases, the memory system may utilize a smaller subset size for memory cell blocks 270 having SLC (or other memory cell blocks 270 associated with relatively higher speeds) and a larger subset size for memory cell blocks 270 having MLC, TLC, or QLC (or other memory cell blocks 270 associated with relatively lower speeds). The configurable size of each subset 215 can allow the overhead associated with garbage collection operations performed by the memory system to be adjustable (e.g., adjustable, configurable) based on the size of the various subsets 215 of the L2P table 210 (e.g., whether the L2P table 210 is divided into relatively more small subsets 215, or relatively fewer large subsets 215), as well as other benefits that will be appreciated by those of ordinary skill in the art.

[0052] In some cases, the size of the subset 215 may be fixed. That is, the size of the subset 215 of each L2P table 210 within the memory system may be predefined or preconfigured. In some other cases, the size of each subset 215 may be dynamic. For example, the host system may signal the memory system of the updated size of the subset 215 of the L2P table 210. Here, the memory system may invalidate the data 205 associated with the L2P table 210 to reconfigure the size of the subset 215 of the L2P table 210. In some instances, the memory system may perform a garbage collection operation on the memory cell block 270 associated with the L2P table 210 before reconfiguring the size of the subset 215 (and thus invalidating the data 205).

[0053] Figure 3 An example of a flowchart 300 for supporting valid data identification for garbage collection according to an example disclosed herein is illustrated. The flowchart 300 may be implemented as shown in FIG. Figure 1 and 2 For example, the operations described in flowchart 300 may be performed by Figure 1 and 2 300. The flowchart 300 may be implemented to store data at the memory system and to perform garbage collection operations at the memory system. In the following description of the flowchart 300, the operations may be performed in a different order or at a different time. Some operations may also be omitted from the flowchart 300, and other operations may be added to the flowchart 300.

[0054] At 305, data may be written (e.g., by a memory system) to a subset of the memory cell block. For example, the memory system may receive a write command indicating the data from the host system. The memory system may then write the data to the memory cell block in accordance with the write command. The data may correspond to a logical address (e.g., within a logical address space associated with the host system) and may be stored at a physical address (e.g., associated with a memory cell group (e.g., a memory cell page) within the memory cell block). The memory system may update an L2P table indicating a mapping between a logical address and a physical address.

[0055] At 310, a portion of the logical address space containing logical addresses (e.g., corresponding to data written to a subset of the memory cell block) may be identified by the memory system based on the memory cell groups within the memory cell block that write the data. That is, the logical address space may be partitioned into one or more portions, each of which contains one or more logical addresses. At 310, the memory system may identify which portions of the logical address space contain logical addresses corresponding to data written to the subset of the memory cell block.

[0056] At 315, a bit of the bitmap may be set by the memory system based on identifying the portion of the logical address space. That is, each bit of the bitmap may correspond to a respective portion of the logical address space (which in turn may correspond to a respective subset 215 as described herein), and the memory system may set the bit of the bitmap to a value indicating that the identified portion of the logical address space includes at least one logical address corresponding to data stored within the memory cell block. In some cases, the bit may have been set to a value indicating that the identified portion of the logical address space includes at least one logical address corresponding to data stored within the memory cell block. Here, the memory system may verify that the bit of the bitmap is set to the value, rather than setting the bit of the bitmap.

[0057] At 320, the bitmap may optionally be stored at the memory cell block. For example, in some cases, the bitmap associated with the memory cell block may be temporarily stored at a controller of the memory system (e.g., within the local memory 120) until the memory cell block is full. The memory system may determine that the memory cell block is full based on a threshold number of memory cells storing data (e.g., based on a threshold number of pages of a programmed block). Once the memory system determines that the memory cell block is full, the memory system may write the bitmap associated with the memory cell block to the block (e.g., to a page or other group of memory cells within the block). In another example, the memory system may write the bitmap associated with the memory cell block to a different portion of the memory system (e.g., to a different memory cell block).

[0058] At 325, it may be determined to perform (e.g., by the memory system) a garbage collection operation on the memory cell block. For example, the memory system may determine to perform garbage collection in response to a trigger (e.g., the number of memory cell blocks that are idle for a threshold duration and available for programming drops to a certain threshold number according to a certain cycle). In some other cases, the memory system may receive a command (e.g., from a host system) to perform a garbage collection operation on the memory cell block. When it is determined to perform garbage collection, the memory cell block may store multiple groups of data, each group corresponding to a respective logical address.

[0059] At 330, the bitmap may be read (e.g., by the memory system) to determine (e.g., identify) one or more subsets of the L2P table to evaluate in conjunction with the garbage collection operation. For example, the memory system may determine that the memory cell block contains data from one or more portions of the logical address space based on corresponding bits of the bitmap being set to one logical value (e.g., logical 1), and the memory system may determine that the memory cell block does not contain any data from one or more other portions of the logical address space based on corresponding bits of the bitmap being set to another logical value (e.g., logical 0).

[0060] At 335, each of the one or more subsets of the L2P table identified based on the read bitmap can be evaluated by the memory system. The one or more evaluated subsets of the L2P table can be those subsets indicated by the bitmap as corresponding to at least one set of data stored by the memory cell block. In some cases, the memory system can additionally avoid evaluating one or more other subsets of the L2P table. Here, the one or more other subsets of the L2P table can be those subsets indicated by the bitmap as not corresponding to any data stored by the memory cell block.

[0061] A logical address corresponding to valid data (e.g., from a set of logical addresses corresponding to data stored by a block of memory cells) may be identified by the memory system based on an evaluation of one or more subsets of the L2P table. For example, the L2P table (and its subsets) may associate a logical address with a corresponding physical address of a memory cell storing a valid instance of the data. Each time the data associated with a given logical address is updated (e.g., rewritten), the updated version of the data may be written to a new set of memory cells, and the L2P table may be updated to associate the logical address with the physical address of the new memory cell. A previous version of the data previously written to some other set of memory cells may become invalid (e.g., obsolete), and the L2P table may no longer associate the logical address with the physical address of the other set of memory cells. Thus, if the physical addresses of a set of memory cells within a block are listed in an evaluation subset of the L2P table, the data stored by the set of memory cells may be identified as valid. And if the physical addresses of a set of memory cells within a block are not listed in any evaluation subset of the L2P table, the data stored by the set of memory cells may be identified as invalid. This is of course merely one example, and one of ordinary skill in the art will appreciate other techniques for determining whether groups of memory cells within a block store valid or invalid data based on an evaluation of one or more subsets of the L2P table.

[0062] At 340, a garbage collection operation can be performed by the memory system based on identifying the logical addresses corresponding to valid data. To perform the garbage collection operation, the memory system can write (e.g., copy) the valid data (e.g., identified at 340) to memory cells within one or more other memory cell blocks. The memory system can avoid writing invalid data to any other memory cell blocks. The memory system can then erase the data from the memory cell blocks.

[0063] At 350, a bitmap associated with the memory cell block may be reset by the memory system based on performing a garbage collection operation. For example, the memory system may set each bit of the bitmap to a value indicating that any portion of the logical address space does not contain a logical address corresponding to data stored by the memory cell block.

[0064] Figure 4 A block diagram 400 of a memory system 420 supporting valid data identification for garbage collection according to examples disclosed herein is shown. The memory system 420 may be as described in reference Figures 1 to 34. The memory system 420 or its various components may be examples of devices for performing various aspects of valid data identification for garbage collection as described herein. For example, the memory system 420 may include a garbage collection initiator 425, a bitmap manager 430, an L2P table component 435, a valid data manager 440, a garbage collection manager 445, a data storage manager 450, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0065] The garbage collection initiator 425 may be configured as or otherwise support means for determining to perform a garbage collection operation on a block of memory cells, wherein the block of memory cells stores data corresponding to a plurality of logical addresses within a logical address space. The bitmap manager 430 may be configured as or otherwise support means for reading a bitmap of the block of memory cells, wherein each bit of the bitmap corresponds to a respective portion of the logical address space and indicates whether the respective portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data. The L2P table component 435 may be configured as or otherwise support means for evaluating a subset of an L2P table for the logical address space, the evaluation being performed based at least in part on bits of the bitmap indicating that at least one logical address within the plurality of logical addresses is within a portion of the logical address space corresponding to the subset of the L2P table. The valid data manager 440 may be configured as or otherwise support means for identifying which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table. Garbage collection manager 445 may be configured as or otherwise support means for performing garbage collection operations on a block of memory cells based at least in part on identifying which of a plurality of logical addresses correspond to valid data.

[0066] In some examples, the L2P table component 435 may be configured as or otherwise support means for avoiding evaluation of a second subset of the L2P table, wherein the avoidance is based at least in part on a second bit of the bitmap indicating that the plurality of logical addresses are each outside a second portion of the logical address space corresponding to the second subset of the L2P table.

[0067] In some examples, the L2P table component 435 may be configured to or otherwise support means for identifying that the plurality of logical addresses include one or more logical addresses within the additional portion of the logical address space based at least in part on the additional bits of the bitmap. In some examples, the L2P table component 435 may be configured to or otherwise support means for evaluating a second subset of the L2P table corresponding to the additional portion of the logical address space, wherein identifying which of the plurality of logical addresses correspond to valid data and performing a garbage collection operation on the block of memory cells is further based at least in part on evaluating the second subset of the L2P table.

[0068] In some examples, the additional portion of the logical address space corresponding to the second subset of the L2P table is discontinuous with the portion of the logical address space corresponding to the subset of the L2P table.

[0069] In some examples, bitmap manager 430 may be configured or otherwise support means for resetting each bit of the bitmap based at least in part on performing a garbage collection operation.

[0070] In some examples, the data storage manager 450 may be configured to or otherwise support means for writing a set of data to a memory cell block prior to determining to perform a garbage collection operation, the set of data corresponding to one of the plurality of logical addresses. In some examples, the L2P table component 435 may be configured to or otherwise support means for identifying the portion of the logical address space as including the one logical address based at least in part on writing the set of data to the memory cell block. In some examples, the bitmap manager 430 may be configured to or otherwise support means for setting a bit of a bitmap based at least in part on identifying the portion of the logical address space as including the one logical address, wherein the bit of the bitmap that is set indicates that at least one logical address within the plurality of logical addresses is within the portion of the logical address space, and wherein reading the bitmap includes a bit of the identification bitmap being set.

[0071] In some examples, to support performing garbage collection operations, the garbage collection manager 445 may be configured or otherwise support means for storing valid data corresponding to one or more of the plurality of logical addresses in one or more other memory cell blocks that are different from the memory cell block. In some examples, to support performing garbage collection operations, the garbage collection manager 445 may be configured or otherwise support means for erasing data corresponding to the plurality of logical addresses from the memory cell block based at least in part on storing the valid data to the one or more other memory cell blocks.

[0072] In some instances, the bitmap is stored within a controller of the memory system. In some cases, the bitmap is stored within a block of memory cells.

[0073] The data storage manager 450 may be configured or otherwise support means for writing a set of data to a subset of the memory cell block, the set of data corresponding to a logical address within the logical address space. In some examples, the L2P table component 435 may be configured or otherwise support means for identifying a portion of the logical address space that includes the logical address based at least in part on writing the set of data to the subset of the memory cell block. In some examples, the bitmap manager 430 may be configured or otherwise support means for setting bits of a bitmap based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap set indicate that data corresponding to at least one logical address within the corresponding portion of the bits of the logical address space is stored within the memory cell block.

[0074] In some examples, the data storage manager 450 may be configured or otherwise support means for writing a second set of data to a second subset of the memory cell block, the second set of data corresponding to a second logical address within the logical address space. In some examples, the L2P table component 435 may be configured or otherwise support means for identifying a second portion of the logical address space containing the second logical address based at least in part on writing the second set of data to the second subset of the memory cell block. In some examples, the bitmap manager 430 may be configured or otherwise support means for setting a second bit of the bitmap based at least in part on the identification, wherein the set second bit indicates that data corresponding to at least one logical address within the second portion of the logical address space is stored within the memory cell block.

[0075] In some examples, the second portion of the logical address space is discontinuous with the corresponding portion of the logical address space.

[0076] In some examples, the data storage manager 450 may be configured or otherwise support means for writing a third set of data to a third subset of the memory cell blocks, the third set of data corresponding to a third logical address within the logical address space. In some examples, the L2P table component 435 may be configured or otherwise support means for identifying that the third logical address is within the corresponding portion of the logical address space based at least in part on writing the third set of data to the third subset of the memory cell blocks. In some examples, the bitmap manager 430 may be configured or otherwise support means for ensuring that the bit is set based at least in part on identifying that the third logical address is within the corresponding portion of the logical address space.

[0077] In some examples, the data storage manager 450 may be configured or otherwise support means for determining that a threshold number of memory cells of the memory cell block are storing data based at least in part on writing the set of data to the memory cell block. In some examples, the bitmap manager 430 may be configured or otherwise support means for transmitting a bitmap from a controller of the memory system to a second subset of the memory cell block based at least in part on the determination.

[0078] In some examples, the garbage collection initiator 425 may be configured to or otherwise support means for determining to perform a garbage collection operation on a block of memory cells after setting a bit of a bitmap, wherein the block of memory cells stores data corresponding to a plurality of logical addresses within a logical address space. In some examples, the bitmap manager 430 may be configured to or otherwise support means for reading the bitmap to determine whether one or more logical addresses within a plurality of logical addresses are within a corresponding portion of the logical address space. In some examples, the L2P table component 435 may be configured to or otherwise support means for evaluating a subset of an L2P table of a logical address space, the subset of the L2P table corresponding to a corresponding portion of the logical address space, and the evaluation is based at least in part on a bit of the bitmap indicating that at least one logical address within the corresponding portion of the logical address space is stored within the block of memory cells. In some examples, the valid data manager 440 may be configured to or otherwise support means for identifying which of the plurality of logical addresses correspond to valid data based at least in part on the subset of the L2P table. In some examples, garbage collection manager 445 may be configured as or otherwise support means for performing garbage collection operations on a block of memory cells based at least in part on identifying which of a plurality of logical addresses correspond to valid data.

[0079] In some instances, to support setting bits of a bitmap, the bitmap manager 430 may be configured as or otherwise support a device for setting bits of a bitmap to a first value, wherein bits of the bitmap having the first value indicate that at least one logical address within a corresponding portion of a logical address space is stored within a memory cell block, and wherein bits of the bitmap having a second value indicate that no logical addresses within a corresponding portion of the logical address space are stored within the memory cell block.

[0080] Figure 5 A flow chart illustrating a method 500 for supporting valid data identification for garbage collection according to examples disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4The memory system described herein can be used to perform. In some examples, the memory system can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system can use dedicated hardware to perform various aspects of the described functions.

[0081] At 505, the method may include determining to perform a garbage collection operation on a memory cell block, wherein the memory cell block stores data corresponding to a plurality of logical addresses within a logical address space. The operations of 505 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 505 may be described with reference to Figure 4 The garbage collection initiator 425 described above is executed.

[0082] At 510, the method may include reading a bitmap of the block of memory cells, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space and indicates whether the corresponding portion of the logical address space includes one or more logical addresses corresponding to the data within the plurality of logical addresses. The operations of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 510 may be described with reference to Figure 4 The bitmap manager 430 described above performs the above.

[0083] At 515, the method may include evaluating a subset of the L2P table of the logical address space, the evaluation being performed based at least in part on a bit of the bitmap indicating that at least one logical address within the plurality of logical addresses is within a portion of the logical address space corresponding to the subset of the L2P table. The operations of 515 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 515 may be described with reference to Figure 4 The L2P table component 435 described above performs the above.

[0084] At 520, the method may include identifying which of the plurality of logical addresses correspond to valid data based at least in part on evaluating a subset of the L2P table. The operations of 520 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 520 may be described with reference to Figure 4 The described valid data manager 440 executes.

[0085] At 525, the method may include performing a garbage collection operation on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data. The operations of 525 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 525 may be described by reference to Figure 4 The described garbage collection manager 445 performs.

[0086] In some examples, an apparatus described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining to perform a garbage collection operation on a block of memory cells, wherein the block of memory cells stores data corresponding to a plurality of logical addresses within a logical address space; reading a bitmap for the block of memory cells, wherein each bit of the bitmap corresponds to a respective portion of the logical address space and indicates whether the respective portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data; evaluating a subset of an L2P table for the logical address space, the evaluation being performed based at least in part on bits of the bitmap indicating that at least one logical address within the plurality of logical addresses is within a portion of the logical address space corresponding to the subset of the L2P table; identifying which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table; and performing a garbage collection operation on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

[0087] Some examples of the method 500 and apparatus described herein may further include operations, features, circuits, logic, means, or instructions for avoiding evaluation of a second subset of the L2P table, wherein the avoiding is based at least in part on a second bit of the bitmap indicating that each of the plurality of logical addresses may be outside of a second portion of the logical address space corresponding to the second subset of the L2P table.

[0088] Some instances of the method 500 and apparatus described herein may further include operations, features, circuits, logic, devices, or instructions for: identifying that a plurality of logical addresses include one or more logical addresses within an additional portion of a logical address space based at least in part on additional bits of a bitmap; and evaluating a second subset of the L2P table corresponding to the additional portion of the logical address space, wherein identifying which of the plurality of logical addresses correspond to valid data and performing garbage collection operations on the block of memory cells may be further based at least in part on evaluating the second subset of the L2P table.

[0089] In some examples of the methods 500 and devices described herein, the additional portion of the logical address space corresponding to the second subset of the L2P table may be discontinuous with the portion of the logical address space corresponding to the subset of the L2P table.

[0090] Some examples of the method 500 and apparatus described herein may further include operations, features, circuits, logic, means, or instructions for resetting each bit of the bitmap based at least in part on performing a garbage collection operation.

[0091] Some instances of the method 500 and apparatus described herein may further include operations, features, circuits, logic, devices, or instructions for: writing a set of data to a memory cell block before determining to perform a garbage collection operation, the set of data corresponding to one of a plurality of logical addresses; identifying the portion of the logical address space as containing the one logical address based at least in part on writing the set of data to the memory cell block; and setting bits of a bitmap based at least in part on identifying the portion of the logical address space as containing the one logical address, wherein the bits of the bitmap that are set indicate that at least one logical address within a plurality of logical addresses may be within the portion of the logical address space, and wherein a read bitmap includes bits of the identification bitmap that are set.

[0092] In some instances of the method 500 and apparatus described herein, operations, features, circuits, logic, devices, or instructions for performing garbage collection operations may include operations, features, circuits, logic, devices, or instructions for storing valid data corresponding to one or more of a plurality of logical addresses in one or more other memory cell blocks that are different from the memory cell block and erasing data corresponding to the plurality of logical addresses from the memory cell block based at least in part on storing the valid data in the one or more other memory cell blocks.

[0093] In some examples of the method 500 and apparatus described herein, a bitmap may be stored within a controller of a memory system.

[0094] In some examples of the methods 500 and devices described herein, a bitmap may be stored within a block of memory cells.

[0095] Figure 6 A flow chart illustrating a method 600 for supporting valid data identification for garbage collection according to examples disclosed herein is shown. The operations of the method 600 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 4 The memory system described herein can be used to perform. In some examples, the memory system can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system can use dedicated hardware to perform various aspects of the described functions.

[0096] At 605, the method may include writing a set of data to a subset of the memory cell block, the set of data corresponding to a logical address within a logical address space. The operations of 605 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 605 may be described with reference to Figure 4 The data storage manager 450 described herein performs.

[0097] At 610, the method may include identifying a portion of a logical address space that includes a logical address based at least in part on writing the set of data to a subset of the memory cell block. The operations of 610 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 610 may be described with reference to Figure 4 The L2P table component 435 described above performs the above.

[0098] At 615, the method may include setting a bit of a bitmap based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bit of the bitmap set indicates that data corresponding to at least one logical address within the corresponding portion of the bit of the logical address space is stored within the memory cell block. The operations of 615 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 615 may be described with reference to Figure 4 The bitmap manager 430 described above performs the above.

[0099] In some examples, an apparatus described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: writing a set of data to a subset of a block of memory cells, the set of data corresponding to a logical address within a logical address space; identifying a portion of the logical address space containing the logical address based at least in part on writing the set of data to the subset of the block of memory cells; and setting bits of a bitmap based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap set indicate that data corresponding to at least one logical address within the corresponding portion of the bits of the logical address space is stored within the block of memory cells.

[0100] Some instances of the method 600 and apparatus described herein may further include operations, features, circuits, logic, devices, or instructions for: writing a second set of data to a second subset of the memory cell block, the second set of data corresponding to a second logical address within the logical address space; identifying a second portion of the logical address space containing the second logical address based at least in part on writing the second set of data to the second subset of the memory cell block; and setting a second bit of a bitmap based at least in part on the identification, wherein the set second bit indicates that data corresponding to at least one logical address within the second portion of the logical address space is stored within the memory cell block.

[0101] In some examples of the method 600 and apparatus described herein, the second portion of the logical address space may be discontinuous with the corresponding portion of the logical address space.

[0102] Some instances of the method 600 and apparatus described herein may further include operations, features, circuits, logic, devices, or instructions for: writing a third set of data to a third subset of the memory cell block, the third set of data corresponding to a third logical address within the logical address space; identifying that the third logical address may be within a corresponding portion of the logical address space based at least in part on writing the third set of data to the third subset of the memory cell block; and ensuring that a bit is set based at least in part on identifying that the third logical address may be within a corresponding portion of the logical address space.

[0103] Some examples of the method 600 and apparatus described herein may further include operations, features, circuits, logic, means, or instructions for determining that a threshold number of memory cells of the memory cell block can store data based at least in part on writing the set of data to the memory cell block; and transmitting a bitmap from a controller of the memory system to a second subset of the memory cell block based at least in part on the determination.

[0104] Some instances of the method 600 and apparatus described herein may further include operations, features, circuits, logic, devices, or instructions for: determining to perform a garbage collection operation on a memory cell block after setting bits of a bitmap, wherein the memory cell block stores data corresponding to multiple logical addresses within a logical address space; reading the bitmap to determine whether one or more logical addresses within the multiple logical addresses may be within a corresponding portion of the logical address space; evaluating a subset of an L2P table for the logical address space, the subset of the L2P table corresponding to a corresponding portion of the logical address space, and the evaluation is based at least in part on bits of the bitmap indicating that at least one logical address within the corresponding portion of the logical address space is stored within the memory cell block; identifying which of the multiple logical addresses correspond to valid data based at least in part on the subset of the L2P table; and performing a garbage collection operation on the memory cell block based at least in part on identifying which of the multiple logical addresses correspond to valid data.

[0105] In some examples of the methods 600 and devices described herein, operations, features, circuits, logic, devices, or instructions for setting bits of a bitmap may include operations, features, circuits, logic, devices, or instructions for setting bits of a bitmap to a first value, wherein the bits of the bitmap having the first value indicate that at least one logical address within the corresponding portion of the logical address space is stored within the memory cell block, and wherein the bits of the bitmap having the second value indicate that no logical addresses within the corresponding portion of the logical address space are stored within the memory cell block.

[0106] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0107] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0108] The terms “if, then,” “when,” “based on,” “based at least in part on,” and “in response to,” are interchangeable if used to describe a conditional action or process.

[0109] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some instances, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0110] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. If a component such as a controller couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0111] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. If a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0112] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0113] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "disconnected" or "deactivated".

[0114] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "better than other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0115] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0116] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. Features that implement the functions may also be physically located in various locations, including being distributed so that portions of the functions are implemented in different physical locations.

[0117] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0118] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), as included in the claims, indicates a list that includes endpoints, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0119] Computer-readable media include non-transitory computer storage media and communication media, which include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. In addition, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0120] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will appreciate various modifications to the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: determining to perform a garbage collection operation on a block of memory cells, wherein the block of memory cells stores data corresponding to a plurality of logical addresses within a logical address space; reading a bitmap of the block of memory cells, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space and indicates whether the corresponding portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data; evaluating a subset of a logical-to-physical L2P table of the logical address space, the evaluating being based at least in part on a bit of the bitmap indicating that at least one of the plurality of logical addresses is within a portion of the logical address space corresponding to the subset of the L2P table; identifying which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table; as well as The garbage collection operation is performed on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

2. The non-transitory computer-readable medium of claim 1 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Evaluation of a second subset of the L2P table is avoided, the avoiding being based at least in part on a second bit of the bitmap indicating that each of the plurality of logical addresses is outside a second portion of the logical address space corresponding to the second subset of the L2P table.

3. The non-transitory computer-readable medium of claim 1 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: identifying, based at least in part on additional bits of the bitmap, that the plurality of logical addresses includes one or more logical addresses within an additional portion of the logical address space; and A second subset of the L2P table corresponding to the additional portion of the logical address space is evaluated, wherein identifying which of the plurality of logical addresses correspond to valid data and performing the garbage collection operation on the block of memory cells is further based at least in part on evaluating the second subset of the L2P table.

4. The non-transitory computer-readable medium of claim 3, wherein the additional portion of the logical address space corresponding to the second subset of the L2P table is discontinuous with the portion of the logical address space corresponding to the subset of the L2P table.

5. The non-transitory computer-readable medium of claim 1 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Each bit of the bitmap is reset based at least in part on performing the garbage collection operation.

6. The non-transitory computer-readable medium of claim 1, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Before determining to perform the garbage collection operation, writing a set of data to the memory unit block, the set of data corresponding to one of the plurality of logical addresses; identifying the portion of the logical address space as including the one logical address based at least in part on writing the set of data to the block of memory cells; as well as The bit of the bitmap is set based at least in part on identifying the portion of the logical address space as including the one logical address, wherein the bit of the bitmap that is set indicates that at least one logical address within the plurality of logical addresses is within the portion of the logical address space, and wherein reading the bitmap includes identifying that the bit of the bitmap is set.

7. The non-transitory computer-readable medium of claim 1, wherein the instructions to perform the garbage collection operation, when executed by the processor of the electronic device, cause the electronic device to: storing the valid data corresponding to one or more of the plurality of logical addresses in one or more other memory cell blocks different from the memory cell block; and The data corresponding to the plurality of logical addresses is erased from the block of memory cells based at least in part on storing the valid data to the one or more other blocks of memory cells.

8. The non-transitory computer-readable medium of claim 1, wherein the bitmap is stored within a controller of a memory device including the block of memory cells.

9. The non-transitory computer-readable medium of claim 1, wherein the bitmap is stored within the block of memory cells.

10. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: writing a set of data to a subset of a block of memory cells of a memory system, the set of data corresponding to a logical address within a logical address space; identifying a portion of the logical address space comprising a plurality of logical addresses including the logical addresses of the set of data based at least in part on writing the set of data to the subset of the block of memory cells; and Bits of a bitmap are set based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap indicate that data stored within the block of memory cells corresponds to at least one logical address within the corresponding portion of the logical address space.

11. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: writing a second set of data to a second subset of the block of memory cells, the second set of data corresponding to a second logical address within the logical address space; identifying a second portion of the logical address space including the second logical address based at least in part on writing the second set of data to the second subset of the block of memory cells; as well as A second bit of the bitmap is set based at least in part on the identification, wherein the second bit being set indicates that data corresponding to at least one logical address within the second portion of the logical address space is stored within the block of memory cells.

12. The non-transitory computer-readable medium of claim 11, wherein the second portion of the logical address space is discontinuous with the corresponding portion of the logical address space.

13. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: writing a third set of data to a third subset of the block of memory cells, the third set of data corresponding to a third logical address within the logical address space; identifying that the third logical address is within the corresponding portion of the logical address space based at least in part on writing the third set of data to the third subset of the block of memory cells; and The bit is ensured to be set based at least in part on identifying that the third logical address is within the corresponding portion of the logical address space.

14. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determining that a threshold number of memory cells of the block of memory cells are storing data based at least in part on writing the set of data to the block of memory cells; and The bitmap is communicated from a controller of the memory system to a second subset of the blocks of memory cells based at least in part on the determination.

15. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: after setting the bit of the bitmap, determining to perform a garbage collection operation on the memory cell block, wherein the memory cell block stores data corresponding to a plurality of logical addresses within the logical address space; reading the bitmap to determine whether one or more logical addresses within the plurality of logical addresses are within the corresponding portion of the logical address space; evaluating a subset of a logical-to-physical L2P table for the logical address space, the subset of the L2P table corresponding to the corresponding portion of the logical address space, and the evaluating is performed based at least in part on the bit of the bitmap indicating that at least one logical address within the corresponding portion of the logical address space is stored within the block of memory cells; identifying which of the plurality of logical addresses correspond to valid data based at least in part on the subset of the L2P table; as well as The garbage collection operation is performed on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

16. The non-transitory computer-readable medium of claim 10, wherein the instructions to set the bits of the bitmap, when executed by the processor of the electronic device, cause the electronic device to: The bits of the bitmap are set to a first value, wherein the bits of the bitmap having the first value indicate that at least one logical address within the corresponding portion of the logical address space is stored within the memory unit block, and wherein the bits of the bitmap having a second value indicate that no logical addresses within the corresponding portion of the logical address space are stored within the memory unit block.

17. An apparatus comprising: Memory array; and a controller coupled to the memory array and configured to cause the apparatus to: determining to perform a garbage collection operation on a memory cell block within the memory array, the memory cell block storing data corresponding to a plurality of logical addresses within a logical address space; reading a bitmap of the block of memory cells, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space and indicates whether the corresponding portion of the logical address space includes one or more logical addresses within the plurality of logical addresses corresponding to the data; evaluating a subset of a logical-to-physical L2P table of the logical address space, the evaluating being based at least in part on a bit of the bitmap indicating that at least one of the plurality of logical addresses is within a portion of the logical address space corresponding to the subset of the L2P table; identifying which of the plurality of logical addresses correspond to valid data based at least in part on evaluating the subset of the L2P table; as well as The garbage collection operation is performed on the block of memory cells based at least in part on identifying which of the plurality of logical addresses correspond to valid data.

18. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: Evaluation of a second subset of the L2P table is avoided, the avoiding being based at least in part on a second bit of the bitmap indicating that each of the plurality of logical addresses is outside a second portion of the logical address space corresponding to the second subset of the L2P table.

19. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: identifying, based at least in part on additional bits of the bitmap, that the plurality of logical addresses includes one or more logical addresses within an additional portion of the logical address space; and A second subset of the L2P table corresponding to the additional portion of the logical address space is evaluated, wherein identifying which of the plurality of logical addresses correspond to valid data and performing the garbage collection operation on the block of memory cells is further based at least in part on evaluating the second subset of the L2P table.

20. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: Each bit of the bitmap is reset based at least in part on performing the garbage collection operation.

21. An apparatus comprising: Memory array; and a controller coupled to the memory array and configured to cause the apparatus to: writing a set of data to a subset of a block of memory cells within the memory array, the set of data corresponding to a logical address within a logical address space; identifying a portion of the logical address space comprising a plurality of logical addresses including the logical addresses of the set of data based at least in part on writing the set of data to the subset of the block of memory cells; and Bits of a bitmap are set based at least in part on the identification, wherein each bit of the bitmap corresponds to a corresponding portion of the logical address space, and wherein the bits of the bitmap indicate that data stored within the block of memory cells corresponds to at least one logical address within the corresponding portion of the logical address space.

22. The apparatus of claim 21, wherein the controller is further configured to cause the apparatus to: writing a second set of data to a second subset of the block of memory cells, the second set of data corresponding to a second logical address within the logical address space; identifying a second portion of the logical address space including the second logical address based at least in part on writing the second set of data to the second subset of the block of memory cells; as well as A second bit of the bitmap is set based at least in part on the identification, wherein the second bit being set indicates that data corresponding to at least one logical address within the second portion of the logical address space is stored within the block of memory cells.

23. The apparatus of claim 22, wherein the second portion of the logical address space is discontinuous with the corresponding portion of the logical address space.

24. The apparatus of claim 21, wherein the controller is further configured to cause the apparatus to: writing a third set of data to a third subset of the block of memory cells, the third set of data corresponding to a third logical address within the logical address space; identifying that the third logical address is within the corresponding portion of the logical address space based at least in part on writing the third set of data to the third subset of the block of memory cells; and The bit is ensured to be set based at least in part on identifying that the third logical address is within the corresponding portion of the logical address space.

25. The apparatus of claim 21, wherein the controller is further configured to cause the apparatus to: determining that a threshold number of memory cells of the block of memory cells are storing data based at least in part on writing the set of data to the block of memory cells; and The bitmap is transferred from a memory included in the controller to a second subset of the blocks of memory cells based at least in part on the determination.

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