central processing unit

Abstract

A central processing unit includes a core, a state memory, a plurality of bus nodes, a data generation unit, and a bus interface unit. The state memory stores a state. The bus interface unit couples the core and the state memory. The bus interface unit selectively couples the core to the plurality of bus nodes or the data generation unit according to the state.

Description

Technical Field

[0001] This case concerns a central processing unit. Background Technology

[0002] The debugging function of a Central Processing Unit (CPU) generally refers to software debugging. When the CPU executes a program, if the program produces unexpected results, the user can use a debugging device to control the CPU to enter debug mode. When the CPU is in debug mode, the user can read the registers and memory inside the CPU core to understand the CPU's current state, analyze and find out the cause of the unexpected behavior, and thereby correct the software-related problems.

[0003] Under normal operation, the CPU will respond to the request of the debugging device to enter the debugging mode. However, the CPU may fail to respond to the request of the debugging device for some reason and thus fail to enter the debugging mode. For example, when the CPU core is busy reading or writing to memory, it may not respond due to loss of data being transmitted by the memory or bus or other reasons, so that the CPU core cannot complete the instructions and thus the CPU cannot respond to the request to enter the debugging mode.

[0004] Traditionally, users can force the CPU core to abandon incomplete instructions by enabling specific register switches within the CPU core. This allows the CPU core to respond to requests to enter debug mode after the abandonment. However, this method cannot guarantee the rationality of the CPU's internal operation, thus increasing the difficulty of user analysis and judgment. Furthermore, forcing the CPU core to abandon incomplete instructions involves the overall circuit control of the CPU core. For example, to force the CPU core to abandon incomplete instructions, the CPU must consider an additional circuit control that is rarely executed under normal circumstances (such as circuit control for forcibly abandoning incomplete memory reads or writes). Moreover, enabling the CPU core to open its internal registers while it is busy reading or writing to memory increases the complexity of the CPU core circuitry. Increased complexity not only increases costs but also introduces unexpected problems due to supporting this method, further increasing the difficulty of debugging. Summary of the Invention

[0005] In view of this, in some embodiments, a central processing unit includes a core, a state memory, a plurality of bus nodes, a data generation unit, and a bus interface unit. The state memory stores a state, and the bus interface unit is coupled to the core and the state memory. Based on the state, the bus interface unit selectively couples the core to the plurality of bus nodes or the data generation unit.

[0006] In some embodiments, a central processing unit includes multiple cores, a state memory, multiple bus nodes, a data generation unit, and a bus interface unit. The state memory stores a state, and the bus interface unit is coupled to the cores and the state memory. Based on the state, the bus interface unit selectively couples the multiple cores to the multiple bus nodes or the data generation unit. Attached Figure Description

[0007] Figure 1 This is a block diagram of an embodiment of the central processing unit according to this case.

[0008] Figure 2 This is a block diagram of another embodiment of the central processing unit according to this case.

[0009] Figure 3 for Figure 1 or Figure 2 A block diagram of an embodiment of the bus interface unit.

[0010] Figure 4 for Figure 1 or Figure 2 A block diagram of another embodiment of the bus interface unit.

[0011] Figure 5 for Figure 1 or Figure 2 A block diagram of another embodiment of the bus interface unit.

[0012] Figure 6 This is a block diagram of another embodiment of the central processing unit according to this case. Detailed Implementation

[0013] Please refer to Figure 1 The central processing unit 10 includes a core 11, a state memory 12, a bus interface unit 13, a data generation unit 14, and multiple bus contacts 151-154. The core 11 and the state memory 12 are coupled to the bus interface unit 13. The multiple bus contacts 151-154 are located on one side of the central processing unit 10. The central processing unit 10 communicates with external components through the bus contacts 151-154. The number of bus contacts is unlimited and can be determined based on the length of information required for external communication. Figure 1The example uses four bus contacts 151-154. The state memory 12 can be a temporary register that stores a state. The bus interface unit 13 selectively couples the core 11 to the bus contacts 151-154 or to the data generation unit 14 based on the state. That is, when the state memory 12 is in a default state, the bus interface unit 13 is used to couple the core 11 to the bus contacts 151-154; when the state memory 12 is in another default state, the bus interface unit 13 is used to couple the core 11 to the data generation unit 14.

[0014] Based on this, during operation, an external device (e.g., debugging device 40) can directly or indirectly set the state of the state memory 12. The bus interface unit 13 can selectively couple the core 11 to bus contacts 151-154 or to the data generation unit 14 according to the state of the state memory 12. For example, the external device can set the state of the state memory 12 to a normal state or an intervening state. When the state memory 12 is in a normal state, the bus interface unit 13 couples the core 11 to bus contacts 151-154, and the core 11 can receive information from the external device (e.g., memory 20). When the core 11 continuously waits for information transmitted by memory 20, and the user cannot interrupt the waiting of the core 11, the user can directly or indirectly change the state of the state memory 12 from the normal state to the intervening state through the communication port 18. The bus interface unit 13 couples the core 11 to the data generation unit 14 according to the intervening state, so that the core 11 can receive information from the data generation unit 14 and stop waiting for information from memory 20 according to the received information.

[0015] In some embodiments, such as Figure 1As shown, a bus 30 is coupled between the central processing unit 10 and the memory 20. The bus 30 can serve as a communication channel between the central processing unit 10 and the memory 20. Therefore, the core 11 can perform read and write operations on the memory 20 through bus contacts 151-154 and via the bus 30. The aforementioned preset state can be a normal state, while another preset state can be an intervention state. When the state memory 12 is in a normal state, the bus interface unit 13 can couple the core 11 with the bus contacts 151-154. Therefore, the core 11 can communicate with the memory 20 outside the central processing unit 10 via the bus contacts 151-154 and the bus 30 under normal operating conditions. The core 11 can read or write to the memory 20 via the bus contacts 151-154 and the bus 30. When the central processing unit 10 is in an abnormal operating state, that is, when the core 11 does not receive information that should be transmitted from the memory 20, the state stored in the state memory 12 can be changed to an intervention state, so that the bus interface unit 13 interrupts the coupling between the core 11 and the memory 20. The bus interface unit 13 couples the core 11 to the data generation unit 14, and the core 11 communicates with the data generation unit 14 inside the central processing unit 10. This allows the core 11 to receive information from the data generation unit 14, and after the core 11 receives the information, it can stop waiting for information from the memory 20.

[0016] In some embodiments, the central processing unit 10 has a debugging mode, which a user can switch to in order to perform debugging functions on the central processing unit 10. For example... Figure 1 As shown, the central processing unit 10 also includes a debugging unit 17 and a communication port 18. The communication port 18 is also located on one side of the central processing unit 10. The central processing unit 10 can communicate with external components through the communication port 18. For example, the communication port 18 can be coupled to a debugging device 40 outside the central processing unit 10. The user can perform debugging on the central processing unit 10 according to the debugging signal S1 issued by the debugging device 40. In detail, the communication port 18 is coupled to the debugging unit 17, which includes a state memory 12. The debugging unit 17 is coupled to the cores 11 and 16 and the bus interface unit 13. The debugging unit 17 can observe the behavior of the core 11 and read the temporary register state of the core 11 according to the debugging signal received from the debugging device 40. The debugging unit 17 can also receive the signal S1 transmitted from the debugging device 40 through the communication port 18 and selectively set the state of the state memory 12 according to the signal S1, so that the state memory 12 is in a normal state or an intervention state.

[0017] When the state memory 12 is in a normal state, the core 11 will send the read instruction S2 to the bus interface unit 13 and wait to receive information from the memory 20. If the core 11 does not receive any information from the memory 20, and the user wishes to perform debugging on the central processing unit 10, the core 11 may be unable to respond to the request to enter debugging mode and successfully enter debugging mode because it cannot end the wait for information from the memory 20. At this time, the user can control the debugging device 40 to send signal S1. The central processing unit 10 receives signal S1 via communication port 18 and sends signal S1 to the debugging unit 17. The debugging device 40 can be a J-link probe, a U-link probe, or a D-stream probe, and is coupled to the communication port 18 via the Joint Test Action Group (JTAG). The debugging unit 17 sets the state of the state memory 12 to the intervention state according to the signal S1, so that the bus interface unit 13 couples the core 11 to the data generation unit 14. The data generation unit 14 can generate a corresponding dummy data S3 according to the read instruction S2 issued by the central processing unit 10 to the memory 20. The data generation unit 14 transmits the dummy data S3 to the bus interface unit 13, and the bus interface unit 13 then transmits the dummy data S3 to the core 11. Since the core 11 receives the dummy data S3 corresponding to the read instruction S2, the core 11 can stop waiting for the memory 20 to return information. The central processing unit 10 can thus successfully enter the debugging mode (that is, the content of the dummy data S3 is not limited, but only for the central processing unit 10 to recognize that the memory 20 has returned information).

[0018] In other embodiments, the state memory 12 is not limited to being located within the debugging unit 17. For example... Figure 2As shown, the state memory 12 may also be located within the serial communication bus unit 19 and coupled to the debugging unit 17 and the bus interface unit 13. The serial communication bus unit 19 may be, for example, but is not limited to, a Universal Asynchronous Receiver / Transmitter (UART) or an Inter-Integrated Circuit (I2C). The debugging device 40 may be a control panel application of a computer device, such as a command-line interface (CLI). The user can use the keyboard to input a command to stop the core 11 and wait for feedback information at the command-line interface. The debugging device 40 transmits a signal S1 for debugging according to the command. The signal S1 is transmitted to the debugging unit 17 via the communication port 18. The debugging unit 17 can selectively set the state of the state memory 12 according to the signal S1, so that the state memory 12 is in a normal state or an intervention state. When the debugging unit 17 sets the state of the state memory 12 to the intervention state according to the signal S1, the bus interface unit 13 couples the core 11 to the data generation unit 14. The data generation unit 14 generates the corresponding dummy data S3 according to the read instruction S2 and transmits it to the bus interface unit 13. The bus interface unit 13 then transmits the dummy data S3 to the core 11. The core 11 ends the waiting for the memory 20 to return information according to the dummy data S3 received from the corresponding read instruction S2. Therefore, the central processing unit 10 can respond to the requirement to enter the debugging mode and can successfully enter the debugging mode.

[0019] In some embodiments, if the core 11 can successfully enter the debugging mode after receiving the dummy data S3, the debugging device 40 can transmit another signal S11 to the debugging unit 17 via the communication port 18. The debugging unit 17 can restore the state of the state memory 12 to the normal state according to the other signal, and the central processing unit 10 then performs debugging operations in the debugging mode.

[0020] In some embodiments, the bus interface unit 13 can normally detect the state memory 12, that is, the bus interface unit 13 can actively read the state of the state memory 12 and make a judgment according to a fixed period or a dynamic period. When the bus interface unit 13 determines that the state memory 12 is in a normal state, the bus interface unit 13 couples the core 11 to the bus contacts 151-154; when the bus interface unit 13 determines that the state memory 12 is in an intervention state, the bus interface unit 13 couples the core 11 to the data generation unit 14.

[0021] In other embodiments, the bus interface unit 13 may also receive a trigger signal S10 when the state of the state memory 12 changes (from a normal state to an intervention state or from an intervention state to a normal state). The bus interface unit 13 then couples the core 11 to the bus contacts 151-154 or to the data generation unit 14 according to the trigger signal S10.

[0022] In some embodiments, for example, when the state memory 12 stores a normal state, the state memory 12 may correspond to a logic "1" value; when the state memory 12 stores an intervention state, the state memory 12 may correspond to a logic "0" value. That is, when the logic value corresponding to the state memory 12 is "1", the bus interface unit 13 couples the core 11 to the bus contacts 151-154; when the logic value corresponding to the state memory 12 is "0", the bus interface unit 13 couples the core 11 to the data generation unit 14.

[0023] In some embodiments, such as Figures 1 to 3 As shown, the bus interface unit 13 includes multiple temporary storage circuits, a multiplexer 133, and an arbitrator 134. The temporary storage circuits can be divided into two types: a command-side circuit 131 and a data-side circuit 132. The command-side circuit 131 and the data-side circuit 132 are respectively coupled between the core 11 and the arbitrator 134. The command-side circuit 131 is used to temporarily store and process commands for the core 11 to read from the memory 20, while the data-side circuit 132 is used to temporarily store and process data for the core 11 to read from and write to the memory 20.

[0024] The command-side circuit 131 is divided into three regions: command-side command area a1, command-side data area b1, and command-side response area c1. Command-side command area a1 is used to store command-side instructions from the core 11. Command-side data area b1 and command-side response area c1 are used to store dummy data from the data generation unit 14 or information transmitted from the memory 20 (via bus contacts 151-154) as command-side data and command-side response, respectively. The data-side circuit 132 is also divided into three regions: data-side command area a2, data-side data area b2, and data-side response area c2. Data-side command area a2 is used to store data-side instructions from the core 11. Data-side data area b2 and data-side response area c2 are used to store dummy data from the data generation unit 14 or information transmitted from the memory 20 as data-side data and data-side response, respectively.

[0025] Multiplexer 133 is coupled to state memory 12 and arbitrator 134. When state memory 12 is in a normal state, multiplexer 133 couples arbitrator 134 to bus contacts 151-154. At this time, arbitrator 134 can selectively couple multiplexer 133 to command-side circuit 131 or data-side circuit 132 according to the type of information transmitted by memory 20. When state memory 12 is in an intervention state, multiplexer 133 couples arbitrator 134 to data generation unit 14. At this time, arbitrator 134 can selectively couple multiplexer 133 to command-side circuit 131 or data-side circuit 132 according to dummy data S3 generated by data generation unit 14. Therefore, when the state memory 12 is in a normal state, the core 11 can be coupled to the bus contacts 151-154 via the command-side circuit 131 and / or the data-side circuit 132; when the state memory 12 is in an intervention state, the core 11 can be coupled to the data generation unit 14 via the command-side circuit 131 and / or the data-side circuit 132.

[0026] In some embodiments, the data generation unit 14 determines whether the command-side command area a1 and the data-side command area a2 store command-side instructions and data-side instructions, and generates dummy data corresponding to the command-side instructions and data-side instructions. When it is determined that the dummy data corresponds to a command-side instruction, the arbitrator 134 couples the multiplexer 133 to the command-side circuit 131; when it is determined that the dummy data corresponds to a data-side instruction, the arbitrator 134 couples the multiplexer 133 to the data-side circuit 132.

[0027] In some embodiments, for example, such as Figures 1 to 3As shown, when the core 11 wants to read information from the memory 20, the core 11 transmits a read instruction S2 to the bus interface unit 13. When the content of the read instruction S2 belongs to the aforementioned command, the bus interface unit 13 transmits the read instruction S2 to the command-side command area a1 of the command-side circuit 131 to store the read instruction S2 as a command-side instruction. The core 11 then waits for the memory 20 to return the information corresponding to the read instruction S2. When the core 11 does not receive the feedback information from the memory 20, the user may want to perform the debugging function on the central processing unit 10. However, at this time, the central processing unit 10 may not be able to enter the debugging mode because the core 11 cannot end the waiting for information. Therefore, the user can use the debugging device 40 to send the signal S1. The signal S1 is sent to the debugging unit 17 through the communication port 18. The debugging unit 17 sets the state of the state memory 12 from the normal state to the intervention state according to the signal S1. The multiplexer 133 in the bus interface unit 13 switches the arbitrator 134 from being coupled to the bus contacts 151-154 to being coupled to the data generation unit 14 according to the state of the state memory 12 being in the intervention state. When the data generation unit 14 determines that the command area a1 on the command side stores a read instruction S2 (which is a command side instruction), the data generation unit 14 generates dummy data S3 corresponding to the read instruction S2. The data generation unit 14 transmits the dummy data S3 to the arbitrator 134 via the multiplexer 133. The arbitrator 134 transmits the dummy data S3 to the command side circuit 131.

[0028] Since dummy data S3 corresponds to the command-side instruction stored in the command-side command area a1, and the command-side instruction is an instruction for reading memory 20 (read instruction S2), dummy data S3 may include at least command-side data S31 and command-side response S32. The command-side response S32 corresponds to command-side data S31, and the command-side response S32 is used to indicate whether command-side data S31 is valid or invalid information. Arbitrator 134 transfers command-side data S31 from dummy data S3 to command-side data area b1 for storage, and transfers command-side response S32 from dummy data S3 to command-side response area c1 for storage. Subsequently, bus interface unit 13 obtains dummy data S3 including command-side data S31 and command-side response S32 from command-side data area b1 and command-side response area c1, and transmits dummy data S3 to core 11. When the core 11 determines that it has received the dummy data S3 (including command-side data S31 and command-side response S32) corresponding to the read instruction S2, the core 11 can end the wait for the return information from the memory 20, so that the central processing unit 10 can respond to the request to enter the debugging mode and can successfully enter the debugging mode.

[0029] In other embodiments, for example, such as Figure 1 , Figure 2 and Figure 4As shown, when core 11 wants to read other information from memory 20, core 11 transmits a read instruction S4, whose content belongs to data, to bus interface unit 13. Bus interface unit 13 transmits the read instruction S4 to data-side command area a2 of data-side circuit 132 to store the read instruction S4 as a data-side instruction. When core 11 does not receive the corresponding read instruction S4 from memory 20 and cannot end the wait for the return information, if the user wants to perform the debugging function on central processing unit 10, the user can use the debugging device 40 to transmit signal S1 to the debugging unit 17 to set the state memory 12 to the intervention state. Multiplexer 133 couples arbitrator 134 to data generation unit 14 according to the intervention state. Data generation unit 14 determines that data-side command area a2 stores a read instruction S4 as a data-side instruction, and data generation unit 14 generates dummy data S5 corresponding to read instruction S4. Since the read instruction S4 is stored in the data-side command area a2, the arbitrator 134 couples the multiplexer 133 to the data-side circuit 132, so that the dummy data S5 generated by the data generation unit 14 is transmitted to the data-side circuit 132 via the multiplexer 133 and the arbitrator 134.

[0030] Since dummy data S5 corresponds to the read instruction S4 stored in the data-side command area a2, and the read instruction S4 is an instruction to read data from the memory 20, dummy data S5 may include data-side data S51 and data-side response S52. The data-side response S52 corresponds to data-side data S51, and the data-side response S52 is used to indicate whether data-side data S51 is valid or invalid. Arbitrator 134 transmits data-side data S51 to data-side data area b2 for storage, and transmits data-side response S52 to data-side response area c2 for storage. Bus interface unit 13 obtains dummy data S5, including data-side data S51 and data-side response S52, from data-side data area b2 and data-side response area c2, and transmits dummy data S5 to core 11. When the core 11 determines that it has received the dummy data S5 (including data-side data S51 and data-side response S52) corresponding to the read instruction S4, the core 11 can end the wait for the return information from the memory 20, so that the central processing unit 10 can respond to the request to enter the debugging mode and can successfully enter the debugging mode.

[0031] In other embodiments, for example, such as Figure 1 , Figure 2 and Figure 5As shown, taking the example of core 11 wanting to write another piece of information belonging to data to memory 20, core 11 transmits a write instruction S6 to bus interface unit 13. Bus interface unit 13 transmits the write instruction S6 to the data-side command area a2 of data-side circuit 132 to store the write instruction S6 as a data-side instruction. When core 11 continuously does not receive a write success message from memory 20 and cannot end the waiting for the message, if the user wants to perform a debugging function on central processing unit 10, the user can use debugging device 40 to transmit signal S1 to debugging unit 17 to set the state of state memory 12 to an intervention state. Multiplexer 133 couples arbitrator 134 to data generation unit 14 according to the intervention state. Data generation unit 14 determines that data-side command area a2 stores a write instruction S6 as a data-side instruction, and data generation unit 14 generates dummy data S7 corresponding to write instruction S6. Since the write instruction S6 is stored in the data-side command area a2, the arbitrator 134 couples the multiplexer 133 to the data-side circuit 132, so that the dummy data S7 generated by the data generation unit 14 is transmitted to the data-side circuit 132 via the multiplexer 133 and the arbitrator 134.

[0032] Since dummy data S7 corresponds to the write instruction S6 stored in the data-side command area a2, and the write instruction S6 is only an instruction to write data to memory 20, dummy data S7 may not include data-side data, only the data-side response. Dummy data S7 corresponds to the write instruction S6, and dummy data S7 is used to indicate whether the write to memory 20 was successful. Arbitrator 134 stores dummy data S7, which is the data-side response, in the data-side response area c2. Bus interface unit 13 retrieves dummy data S7 from the data-side response area c2 and transmits it to core 11. Since core 11 has received dummy data S7 corresponding to the write instruction S6, core 11 ends the wait for information from memory 20, and central processing unit 10 can thus successfully enter debugging mode.

[0033] In some embodiments, the length of the command-side data can be the same as the length of the command-side instruction; the length of the data-side data can be the same as the length of the data-side instruction. For example, the length of the command-side data and the length of the command-side instruction can both be 4 bits, or the length of the data-side data and the length of the data-side instruction can both be 4 bits. The lengths of the command-side response and the data-side response can be 1 bit. In some embodiments, the command-side data, data-side data, command-side response, and data-side response are all dummy data generated by the data generation unit 14, so the content of the command-side data, data-side data, command-side response, and data-side response can be any value.

[0034] In some embodiments, the central processing unit may include multiple cores, and the number is not limited to this document. Please refer to Figure 6 and in conjunction with reference Figures 1 to 5 The central processing unit 10' includes two cores 11 and 16. The operation of core 16 with the state memory 12, bus interface unit 13, memory 20, and data generation unit 14 is the same as described for core 11 in the above embodiments. Therefore, a simplified description is given below using an embodiment. When core 16 wants to read or write information stored in memory 20, core 16 transmits an instruction S8 to the command-side command area a1 of command-side circuit 131 via bus interface unit 13 to be stored as a command-side instruction (i.e., when the content of instruction S8 corresponds to a command), or transmits instruction S8 to the data-side command area a2 of data-side circuit 132 to be stored as a data-side instruction (i.e., when the content of instruction S8 corresponds to data). When core 16 continuously fails to receive the corresponding instruction S8 from memory 20 and cannot end the waiting for the information, if the user wishes to perform debugging on central processing unit 10, the user can use debugging device 40 to transmit signal S1 to debugging unit 17 (via communication port 18). Debugging unit 17 sets the state of state memory 12 from normal state to intervention state based on signal S1. Multiplexer 133 in bus interface unit 13 couples arbitrator 134 to data generation unit 14 according to the intervention state. Data generation unit 14 then generates corresponding dummy data S9 based on instruction S8 stored in command area a1 or data area a2. Depending on the storage location of instruction S8 (command side or data side), arbitrator 134 couples multiplexer 133 to command side circuit 131 or data side circuit 132. Data generation unit 14 transmits dummy data S9 to command side circuit 131 or data side circuit 132 via multiplexer 133 and arbitrator 134. Arbitrator 134, according to the corresponding instruction S8, stores the data or response included in dummy data S9 into the corresponding command-side data area b1, data-side data area b2, command-side response area c1, and data-side response area c2, respectively. Bus interface unit 13 retrieves dummy data S9 from data areas b1, b2, and response areas c1, c2 and transmits it to core 16. Core 16 determines that it has received dummy data S9 corresponding to instruction S8, and core 16 ends the wait for feedback information from memory 20, allowing central processing unit 10 to successfully enter debugging mode.

[0035] In some embodiments, to clearly identify which cores the read and write instructions transmitted by multiple cores originate from, each read and write instruction includes an identifier (Identification Code; ID) corresponding to its respective core. In the command-side command area a1 and the data-side command area a2, the command-side instructions and data-side instructions corresponding to the read and write instructions also include identifiers corresponding to their respective cores. That is, after read instructions S2, S4, and S6 are stored as command-side instructions or data-side instructions respectively, they all include the identifier corresponding to core 11; and instruction S8, after being stored as a data-side instruction or a data-side instruction, also includes the identifier corresponding to core 16. Furthermore, the dummy data S3, S5, and S7 corresponding to read instructions S2, S4, and S6 also include the identifier corresponding to core 11; and the dummy data S9 corresponding to instruction S8 also includes the identifier corresponding to core 16. More specifically, the command-side data S31 stored in the command-side data area b1, the command-side response S32 stored in the command-side response area c1, the data-side data S51 stored in the data-side data area b2, and the data-side response S52 stored in the data-side response area c2 all include the identifier corresponding to the core 11; the dummy data S7, after being stored as a command-side response, also includes the identifier corresponding to the core 11; and the data or response included in the dummy data S9 also includes the identifier corresponding to the core 16. Therefore, the bus interface unit 13 can correctly transmit the dummy data S3, S5, and S7 to the core 11 according to the identifier corresponding to the core 11, and correctly transmit the dummy data S9 to the core 16 according to the identifier corresponding to the core 16.

[0036] In some embodiments, the data generation unit 14 may be software, hardware, or firmware, and may also be a combination of logic circuits. When the data generation unit 14 is a logic circuit, it is always in a standby state. When the bus interface unit 13 couples the cores 11 and 16 to the data generation unit 14, the data generation unit 14 outputs the generated dummy data S3, S5, S7, and S9 to the cores 11 and 16 via the bus interface unit 13.

[0037] In summary, when the core sends read / write instructions to memory and continues to operate and wait because it has not received feedback from memory, if the user wants to interrupt the core's operation to allow the CPU to enter debug mode, the user can switch the state memory to the intervention state. This causes the multiplexer in the bus interface unit to switch the core, which was previously coupled to memory, to the data generation unit. The data generation unit then transmits the generated dummy data to the core via the bus interface unit. Since the dummy data corresponds to read / write instructions, the core stops waiting for feedback from memory, and the user can successfully operate the CPU to enter debug mode. Furthermore, in the bus interface, the temporary storage circuit is divided into command-side circuits and data-side circuits, and each of the command-side and data-side circuits is further divided into command area, data area, and response area. Therefore, the bus interface can handle the temporary storage and processing of dummy data more efficiently. Moreover, based on the core identifiers in the instructions, data, and responses, transmission errors can be avoided when dummy data is transmitted to the core. The core accurately receives the dummy data, and the CPU can successfully enter debug mode. Based on the above, not only can the problem of the central processing unit being unable to enter the debugging mode due to incomplete read and write operations be solved, but a simpler and more efficient way to put the central processing unit into the debugging mode can also be used, without causing additional burden on the central processing unit in terms of complexity and debugging.

[0038] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

[0039] [Symbol Explanation]

[0040] 10: Central Processing Unit

[0041] 10': Central Processing Unit

[0042] 11: Core

[0043] 12: State memory

[0044] 13: Bus Interface Unit

[0045] 131: Command-side circuit

[0046] 132: Data-side circuit

[0047] 133: Multiplexer

[0048] 134: Arbitrator

[0049] 14: Data Generation Unit

[0050] 151: Bus contact

[0051] 152: Bus contact

[0052] 153: Bus contact

[0053] 154: Bus contact

[0054] 16: Core

[0055] 17: Debugging Unit

[0056] 18: Communication Port

[0057] 19: Serial Communication Bus Unit

[0058] 20: Memory

[0059] 30: Bus

[0060] 40: Debugging device

[0061] a1: Command side command area

[0062] a2: Data side command area

[0063] b1: Command side data area

[0064] b2: Data side data area

[0065] c1: Command-side response area

[0066] c2: Data-side response area

[0067] S1: Signal

[0068] S2: Read command

[0069] S3: Dumb Data

[0070] S31: Command Side Data

[0071] S32: Command-side response

[0072] S4: Read command

[0073] S5: Dumb Data

[0074] S51: Data Side Data

[0075] S52: Data-side response

[0076] S6: Write command

[0077] S7: Dumb Data

[0078] S8: Instructions

[0079] S9: Dumb Data

[0080] S10: Trigger signal

[0081] S11: Signal

Claims

1. A central processing unit, comprising: core; State memory, used to store states; Multiple bus contacts; Data generation unit, which is used to generate dummy data; and A bus interface unit is coupled to the core and the state memory. The bus interface unit is used to selectively couple the core to the bus points or the data generation unit according to the state.

2. The central processing unit as claimed in claim 1, wherein, When the state is normal, the bus interface unit couples the core to the bus contacts; when the state is active, the bus interface unit couples the core to the data generation unit.

3. The central processing unit as described in claim 2, wherein, The bus interface unit includes: Command-side circuitry, including: The command-side command area is used to store command-side instructions from this core; The command-side data area is used to store command-side data; and The command-side response area is used to store command-side responses; and Data-side circuitry, including: The data-side command area is used to store data-side instructions from this core; Data-side data area, used to store data-side data; and The data-side response area is used to store data-side responses; Specifically, when the state is the intervention state and the dummy data corresponds to the command-side instruction, the bus interface unit stores the dummy data in the command-side data area and the command-side response area. When the state is the intervention state and the dummy data corresponds to the data-side instruction, the bus interface unit stores the dummy data in the data-side data area and the data-side response area.

4. The central processing unit as claimed in claim 3 further includes a debugging unit and a communication port, the debugging unit including the state memory, the debugging unit being coupled to the communication port, the core and the bus interface unit, the debugging unit selectively setting the state according to the signal of the communication port, so that the state is the normal state or the intervention state.

5. The central processing unit as described in claim 3 or 4, wherein, The bus interface unit includes a multiplexer that, in the normal state, couples the core to the bus contacts; and in the intervention state, couples the core to the data generation unit.

6. A central processing unit, comprising: Multiple cores; State memory, used to store states; Multiple bus contacts; Data generation unit, which is used to generate dummy data; and A bus interface unit is coupled to the cores and the state memory. The bus interface unit is used to selectively couple one of the cores to the bus nodes or the data generation unit according to the state.

7. The central processing unit as claimed in claim 6, wherein, When the state is normal, the bus interface unit couples the core to the bus contacts; when the state is active, the bus interface unit couples the core to the data generation unit.

8. The central processing unit as claimed in claim 7, wherein, The bus interface unit includes: Command-side circuitry, including: The command-side command area is used to store command-side instructions from these cores; The command-side data area is used to store command-side data; and The command-side response area is used to store command-side responses; and Data-side circuitry, including: The data-side command area is used to store data-side instructions from these cores; Data-side data area, used to store data-side data; and The data-side response area is used to store data-side responses; Specifically, when the state is the intervention state and the dummy data corresponds to the command-side instruction, the bus interface unit stores the dummy data in the command-side data area and the command-side response area. When the state is the intervention state and the dummy data corresponds to the data-side instruction, the bus interface unit stores the dummy data in the data-side data area and the data-side response area.

9. The central processing unit of claim 8, wherein the command-side instructions and the data-side instructions from the core include an identifier corresponding to the core, and the data generation unit generates dummy data including the identifier of the core based on the identifier of the core.

10. The central processing unit of claim 7 further includes a debugging unit and a communication port, the debugging unit including the state memory, the debugging unit being coupled to the communication port, the core and the bus interface unit, the debugging unit selectively setting the state according to the signal of the communication port so that the state is the normal state or the intervention state.

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