Package structure of RFID chip, RFID tag and product

Abstract

The application provides an RFID chip packaging structure, an RFID tag and a product to solve the packaging problem of the RFID chip. The RFID chip packaging structure comprises a chip die, an insulating layer and a metal layer. The insulating layer is located on the chip die, and the insulating layer has a through hole. The metal layer is located on the insulating layer and the chip die, and the metal layer is connected with the chip die through the through hole. The shape of the metal layer is a polygon. The area of the overlapping area between the metal layer of the chip and the antenna pin can be increased and kept stable. The insulating layer can make the gap size between the chip and the antenna pin have good consistency, and the consistency of the parasitic capacitance is good, so that the processed RFID tag has better reliability and radio frequency performance consistency.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to an RFID chip packaging structure, an RFID tag, and an RFID product. Background Technology

[0002] Radio Frequency Identification (RFID) technology, also known as electronic tags or wireless radio frequency identification, is a communication technology that can identify specific targets and read and write related data through radio signals without requiring mechanical or optical contact between the identification system and the specific target.

[0003] As a crucial component of RFID systems, RFID tags significantly impact the overall performance of the RFID system. RFID tags consist of a chip and an antenna, typically connected via a flip-chip process. The packaging structure of the RFID tag chip is a critical factor affecting the consistency of the RFID tag's radio frequency performance.

[0004] Currently, RFID tag chips are typically packaged using metal bumps on the surface of the chip die. This method can lead to poor parasitic capacitance consistency when using the Flip-Chip process for subsequent manufacturing. Summary of the Invention

[0005] This application provides an RFID chip packaging structure to solve the packaging problem of RFID chips.

[0006] Accordingly, this application also provides an RFID tag and an RFID product to ensure the realization and application of the above-mentioned RFID chip packaging structure.

[0007] To address the aforementioned issues, this application discloses an RFID chip packaging structure, comprising: a chip die, an insulating layer, and a metal layer; the insulating layer is located on the chip die and has through-holes; the metal layer is located on the insulating layer and the chip die, and is connected to the chip die through the through-holes, wherein the metal layer has a polygonal shape.

[0008] Optionally, the metal layer comprises at least one layer.

[0009] Optionally, the metal layer includes a first metal layer, a second metal layer, and a third metal layer;

[0010] The first metal layer is connected to the chip die through the via, the second metal layer is located on the first metal layer, and the third metal layer is located on the second metal layer.

[0011] Optionally, the first metal layer is a copper layer, the second metal layer is a nickel layer, and the third metal layer is a gold layer.

[0012] Optionally, the die has a pair of ports; the vias of the insulating layer are located on the ports of the die, and the metal layer is connected to the ports of the die through the vias.

[0013] Optionally, the paired ports are arranged diagonally on the chip die; each pair of ports is independent of each other and has a phase difference of 90°.

[0014] Optionally, the metal layer consists of four symmetrical polygonal metal regions; each metal region is connected to the port of the chip die through a via in the insulating layer.

[0015] Optionally, the angle between the tangential edge point of the polygon and the center point of the chip die is 5 degrees to 30 degrees.

[0016] Optionally, the thickness of the metal layer is 8 micrometers to 12 micrometers.

[0017] This application also discloses an RFID tag, which includes an antenna and an RFID chip. The RFID chip includes a die, an insulating layer, and a metal layer. The insulating layer is located on the die and has through holes. The metal layer is located on the insulating layer and the die, and is connected to the port of the die through the through holes. The RFID chip is placed on the pins of the antenna, and the pins of the antenna are connected to the port of the die through the metal layer.

[0018] Optionally, the chip die has two pairs of diagonally arranged ports; each pair of ports is independent of each other and has a phase difference of 90°.

[0019] Optionally, the metal layer consists of four symmetrical polygonal metal regions; each metal region is connected to the port of the chip die through a via in the insulating layer.

[0020] This application also discloses an RFID product, characterized in that the RFID product includes: an RFID tag;

[0021] The RFID tag includes: an antenna and an RFID chip;

[0022] The RFID chip includes: a bare chip die, an insulating layer, and a metal layer;

[0023] The insulating layer is located on the die, and the insulating layer has through-holes;

[0024] The metal layer is located on the insulating layer and the die, and the metal layer is connected to the port of the die through the via;

[0025] The RFID chip is placed on the pins of the antenna, and the pins of the antenna are connected to the ports of the chip die through the metal layer.

[0026] Compared with the prior art, the embodiments of this application have the following advantages:

[0027] In this embodiment, the RFID chip includes a die, an insulating layer, and a metal layer. The insulating layer is located on the die and has through-holes. The metal layer is located on the insulating layer and the die, and is connected to the die through the through-holes. The metal layer is polygonal in shape, which increases and stabilizes the area of ​​the overlapping region between the chip's metal layer and the antenna pins. Furthermore, the insulating layer ensures better consistency in the gap size between the chip and the antenna pins, as well as better consistency in parasitic capacitance, thereby giving the processed RFID tag better reliability and consistent radio frequency performance. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of an example of the packaging structure of an RFID chip according to an embodiment of this application;

[0029] Figure 2A This is a schematic diagram illustrating another example of the packaging structure of an RFID chip according to an embodiment of this application.

[0030] Figure 2B This is a schematic diagram of the shape of the metal layer in the RFID chip according to an embodiment of this application;

[0031] Figure 3 This is a cross-sectional view of another example of the packaging structure of an RFID chip according to an embodiment of this application;

[0032] Figure 4 This is a partial schematic diagram of an example RFID tag according to an embodiment of this application;

[0033] Figure 5 This is a schematic diagram showing the positions of an RFID chip and antenna pins in an RFID tag according to an embodiment of this application;

[0034] Figure 6 This is a schematic diagram showing the location of another RFID chip and antenna pins in an RFID tag according to an embodiment of this application.

[0035] Reference numerals in the attached figures: 1. Chip die; 2. Insulating layer; 3. Metal layer; 31. First metal layer; 32. Second metal layer; 33. Third metal layer; 4. Antenna pin. Detailed Implementation

[0036] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The embodiments of this application can be applied to the radio frequency field, involving the packaging structure of RFID chips and RFID tags, which can reduce the manufacturing cost of RFID tags and improve radio frequency performance.

[0038] Reference Figure 1 The diagram shows a cross-sectional view of an example of the packaging structure of an RFID chip according to an embodiment of this application.

[0039] Reference Figure 2A The diagram shows a schematic representation of an example of the packaging structure of an RFID chip according to an embodiment of this application.

[0040] The RFID chip's packaging structure consists of a chip die 1, an insulating layer 2, and a metal layer 3.

[0041] The insulating layer 2 is located on the die 1, and the metal layer 3 is located on the insulating layer 2. The insulating layer has through-holes, and the metal layer 3 is connected to the die 1 through the through-holes. The through-holes are located at the ports of the die 1, so that the metal layer 3 is connected to the ports of the die 1 through the through-holes.

[0042] The insulating layer may be a polyimide film with a thickness ranging from 8 micrometers to 12 micrometers (um), such as an insulating layer with a thickness of 10um.

[0043] The metal layer can be understood as a conductive layer, through which the chip die 1 can be connected to the antenna point. This metal layer can be made of various conductive metals, such as copper, nickel, gold, and conductive alloys.

[0044] An RFID chip includes a die, an insulating layer, and a metal layer. The insulating layer is located on the die and has through-holes. The metal layer is located on the insulating layer and the die, and is connected to the die through the through-holes. The metal layer is polygonal in shape, which can be irregular. This increases and stabilizes the overlap area between the metal layer and the antenna pins. Furthermore, the insulating layer ensures good consistency in the gap size and parasitic capacitance between the chip and the antenna pins, resulting in better reliability and consistent radio frequency performance of the manufactured RFID tag. In other examples, the polygon can also be regular, such as a polygon with a symmetrical structure. The polygon used for the metal layer needs to maintain consistent overlap area even if there is an angular shift during chip bonding; that is, the overlap area remains consistent before and after the shift.

[0045] The metal layer comprises at least one layer. In some examples, the metal layer may be composed of a single metal (or alloy), while in other examples, the metal layer may be composed of multiple metals forming a multilayer structure, depending on the requirements.

[0046] like Figure 3 In the example shown, the metal layer consists of three metal layers, which can be referred to as the first metal layer 31, the second metal layer 32, and the third metal layer 33, respectively.

[0047] The first metal layer 31 is a conductive layer and can be made of metals such as copper. For example, if the first metal layer is a copper layer, the cost can be reduced. The second metal layer 32 can be used as the bottom layer of the third metal layer 33 to increase wear resistance. For example, if it is made of nickel, the second metal layer can be a nickel layer. The third metal layer 33 is the outermost metal layer and can be made of gold. For example, if the third metal layer is a gold layer, the conductivity and corrosion resistance can be improved.

[0048] The above is an example of a multi-layered metal structure. In actual processing, other structures can be used for the metal layers, or the metals in each layer can be made of other materials, depending on the requirements. For example, the metal layer can be composed of a single material, such as a copper layer or a gold layer. Alternatively, the metal layer can be a two-layer structure, with a copper layer as the bottom layer and a gold layer as the top layer.

[0049] The thickness of the metal layer ranges from 8µm to 12µm. For example, as described above... Figure 3 In the three-layer structure, the copper layer 31 has a thickness of 10 μm, the nickel layer 32 has a thickness of 1 μm, and the gold layer 33 has a thickness of 0.5 μm. Of course, the thickness of each metal layer can also be adjusted within the thickness range, and this application embodiment does not limit this.

[0050] In this embodiment, the ports of the chip die 1 are arranged in pairs, the through-holes of the insulating layer 2 are located on the ports of the chip die 1, and the metal layer 3 is connected to the ports of the chip die 1 through the through-holes. The metal layer 3 can be an irregular polygonal shape, and the metal layer can be divided into multiple metal regions based on the number of ports of the RFID chip, with each port corresponding to an irregular polygonal metal region.

[0051] In one optional embodiment of this application, the paired ports are diagonally arranged on the die, each pair of ports being independent of each other and having a 90° phase difference. Figure 2A In the example, the RFID chip includes two pairs of diagonally intersecting ports. Correspondingly, the metal layer 3 consists of four symmetrical polygonal metal regions; each metal region is connected to a port on the chip die through a through-hole in the insulating layer. Figure 2A This is merely an example of an irregular polygon corresponding to a metal region; other regular or irregular polygons can be used in actual processing, and this application does not impose any limitations on this. The polygon used in the metal layer needs to maintain consistent overlap area even if there is angular displacement during chip bonding. Therefore, the shape of this polygon can be narrower in the tangential direction and longer in the radial direction to maintain area. For example... Figure 2B As shown, the tangential edge point of the polygon and the center point of the chip die can have a certain angle α, which can be 5 degrees to 30 degrees.

[0052] In this embodiment, the RFID chip can be an ultra-high frequency (UHF) RFID chip with two pairs of diagonally intersecting ports. Each pair of ports is independent and has a 90° phase difference. Each pair of diagonal ports can operate independently by connecting an antenna. When both ports operate simultaneously via their respective antennas, it is called a dual-port operating mode. In this embodiment, the metal layer 3 consists of four symmetrical irregular polygonal metal regions. These four irregular polygonal metal regions are connected to four ports RF1+, RF1-, RF2+, and RF2- (not shown in the figure) on the chip die through four through-holes on the insulating layer 2.

[0053] After encapsulating the RFID chip using the above packaging structure, an RFID tag can be constructed based on the RFID chip. (Refer to...) Figure 4 A partial schematic diagram of an example RFID tag is shown.

[0054] RFID tags are manufactured using a flip-chip process, where the chip and antenna are flip-chip. A flip-chip is a pinless structure that typically contains circuitry.

[0055] The RFID tag includes an antenna and an RFID chip, wherein the RFID chip adopts the above-described packaging structure. The RFID chip includes a die 1, an insulating layer 2, and a metal layer 3; the insulating layer 2 is located on the die 1 and has through-holes; the metal layer 3 is located on the insulating layer 2 and the die 1, and is connected to a port of the die 1 through the through-holes in the insulating layer 2; the RFID chip is placed on a pin 4 of the antenna, and the pin 4 of the antenna is connected to a port of the die 1 through the metal layer 3. The metal layer 3 has an irregular polygonal shape.

[0056] Specifically, anisotropic conductive adhesive is used to make the chip's pad (i.e., metal layer) and the antenna's pin area conductive, and the anisotropic conductive adhesive is cured by thermopressing. During this process, parasitic capacitance is formed between the chip and the antenna pins. The magnitude of this parasitic capacitance is affected by the pad size of the overlapping area between the chip and antenna, the antenna pin size, and the gap size between the chip and antenna pins. This parasitic capacitance causes changes in the chip's input impedance, especially the imaginary part of the impedance, thus affecting the impedance matching between the chip and the antenna. Poor consistency in parasitic capacitance leads to poor radio frequency performance consistency of the RFID tag. Compared to existing packaging structures using metal bumps, this embodiment uses a packaging structure with an irregular polygonal metal area forming the metal layer. This results in a larger pad area. Furthermore, due to the presence of an insulating layer, the gap size between the chip and antenna pins is more consistent during the flip-chip process. The aforementioned packaging structure also ensures more uniform stress on the chip during the flip-chip thermopressing process and better consistency in parasitic capacitance, resulting in better reliability and consistent radio frequency performance of the processed RFID tag.

[0057] The die has a pair of ports; the vias of the insulating layer are located on the ports of the die, and the metal layer is connected to the ports of the die through the vias.

[0058] The paired ports are diagonally arranged on the die; each pair of ports is independent and has a 90° phase difference. The metal layer consists of four symmetrical, irregular polygonal metal regions; each metal region is connected to a port on the die through a via in the insulating layer.

[0059] During flip-chip processing, the RFID chip may experience angle changes when placed on antenna pin 4. The pad in the chip packaging structure described in this embodiment has an irregular polygonal structure, which largely ensures that the area of ​​the overlapping region between the chip pad and the antenna pin remains consistent when the chip angle is incorrect. This results in stable parasitic capacitance and better consistent RF performance for the RFID tag. Figure 5 , Figure 6 In the two examples shown, when the angle of the RFID chip deviates, the metal layer can still be connected to the antenna pin, and the overlapping area of ​​the connection maintains a certain area at various angles, thereby obtaining stable parasitic capacitance and enabling the RFID tag to obtain better radio frequency performance consistency.

[0060] Taking the packaging method with four irregular polygonal metal areas as an example, it has a larger pad area compared to the common gold ball packaging method. At the same time, due to the presence of insulating layer 3, the gap size between the chip and the antenna pins is more consistent during the flip-chip process. In addition, compared to the small gold ball, the packaging structure shown in this embodiment makes the chip more uniformly stressed during the flip-chip hot pressing process, and the parasitic capacitance is more consistent, thus making the processed RFID tag have better reliability and radio frequency performance consistency.

[0061] Based on the above embodiments, this application also provides an RFID product, such as RFID tag-based access control products, logistics products, electronic certificates, anti-counterfeiting label products, etc. For example, logistics tags set on various logistics objects in a logistics warehouse.

[0062] The RFID product includes: an RFID tag; the RFID tag includes: an antenna and an RFID chip; the RFID chip includes: a die, an insulating layer, and a metal layer; the insulating layer is located on the die and has through holes; the metal layer is located on the insulating layer and the die, and the metal layer is connected to the port of the die through the through holes; the RFID chip is placed on the pins of the antenna, and the pins of the antenna are connected to the port of the die through the metal layer.

[0063] It should be noted that those skilled in the art should understand that the embodiments described in the specification are all preferred embodiments, and the structures involved are not necessarily required for the embodiments of this application.

[0064] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0065] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0066] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0067] The above provides a detailed description of an RFID chip packaging structure, an RFID tag, and an RFID product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A packaging structure for an RFID chip, characterized in that, include: Chip die, insulating layer, and metal layer; The insulating layer is located on the die, and the insulating layer has through-holes; The metal layer is located on the insulating layer and the die, and is connected to the die through the via. The metal layer is polygonal in shape so that if an angular shift occurs during the die coating process, the overlapping area of ​​the metal layer before and after the shift is consistent. The die has paired ports, and the vias of the insulating layer are located on the ports of the die. The metal layer is connected to the ports of the die through the vias. The paired ports are diagonally arranged on the die, each pair of ports is independent of each other and has a phase difference of 90°. Each pair of diagonal ports works independently by connecting an antenna. The metal layer consists of four symmetrical polygonal metal regions, and each metal region is connected to the ports of the die through the vias of the insulating layer.

2. The packaging structure of the RFID chip according to claim 1, characterized in that, The metal layer comprises at least one layer.

3. The RFID chip packaging structure according to claim 2, characterized in that, The metal layer includes a first metal layer, a second metal layer, and a third metal layer; The first metal layer is connected to the chip die through the via, the second metal layer is located on the first metal layer, and the third metal layer is located on the second metal layer.

4. The packaging structure of the RFID chip according to claim 3, characterized in that, The first metal layer is a copper layer, the second metal layer is a nickel layer, and the third metal layer is a gold layer.

5. The packaging structure of the RFID chip according to claim 1, characterized in that, The angle between the tangential edge point of the polygon and the center point of the chip die is 5 degrees to 30 degrees.

6. The packaging structure of the RFID chip according to claim 1, characterized in that, The thickness of the metal layer is 8 micrometers to 12 micrometers.

7. An RFID tag, characterized in that, The RFID tag includes: an antenna and an RFID chip; The RFID chip includes: a bare chip die, an insulating layer, and a metal layer; The insulating layer is located on the die, and the insulating layer has through-holes; The metal layer is located on the insulating layer and the die. The metal layer is connected to the port of the die through the via. The shape of the metal layer is polygonal so that if an angular shift occurs during the die lamination process, the overlapping area of ​​the metal layer before and after the shift is consistent. The die has paired ports. The via of the insulating layer is located on the port of the die. The metal layer is connected to the port of the die through the via. The paired ports are diagonally arranged on the die. Each pair of ports is independent of each other and has a phase difference of 90°. Each pair of diagonal ports works independently by connecting an antenna. The metal layer consists of 4 symmetrical polygonal metal regions. Each metal region is connected to the port of the die through the via of the insulating layer. The RFID chip is placed on the pins of the antenna, and the pins of the antenna are connected to the ports of the chip die through the metal layer.

8. An RFID product, characterized in that, The RFID products include: RFID tags; The RFID tag includes: an antenna and an RFID chip; The RFID chip includes: a bare chip die, an insulating layer, and a metal layer; The insulating layer is located on the die, and the insulating layer has through-holes; The metal layer is located on the insulating layer and the die. The metal layer is connected to the port of the die through the via. The shape of the metal layer is polygonal so that if an angular shift occurs during the die lamination process, the overlapping area of ​​the metal layer before and after the shift is consistent. The die has paired ports. The via of the insulating layer is located on the port of the die. The metal layer is connected to the port of the die through the via. The paired ports are diagonally arranged on the die. Each pair of ports is independent of each other and has a phase difference of 90°. Each pair of diagonal ports works independently by connecting an antenna. The metal layer consists of 4 symmetrical polygonal metal regions. Each metal region is connected to the port of the die through the via of the insulating layer. The RFID chip is placed on the pins of the antenna, and the pins of the antenna are connected to the ports of the chip die through the metal layer.

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