Systems and methods for automated determination of parasitic capacitance correction parameters of LED pixels

Abstract

Systems and methods for automatically determining parasitic capacitance (PC) correction parameters for a Light Emitting Diode (LED) pixel. When a test trigger signal is received by a PC detector, the PC detector starts a test process to measure the PC correction parameters of the LED pixel coupled to the PC detector. The PC detector determines the PC correction parameter for the corresponding LED pixel based on the detected PC characteristics and stores the PC correction parameter of the LED pixel with respect to a location of the LED pixel in the LED array to facilitate centralized PC correction on the LED pixel based on the PC correction parameter retrieved based on the pixel location.

Description

Attorney Docket 148820.619524SYSTEMS AND METHODS FOR AUTOMATED DETERMINATION OF PARASITIC CAPACITANCE CORRECTION PARAMETERS OF LED PIXELSCROSS REFERENCE

[0001] The present application claims priority to U.S. Provisional Patent Application No. 63 / 724,019, filed November 22, 2024, the contents of which are incorporated herein in their entirety.

[0002] The present teaching relates to automated approach to detecting parasitic capacitances (PC) associated with LED pixels and accordingly determining PC correction parameters to enable centralized PC corrections by a LED controller connecting and controlling a plurality of drivers that drive the lights of the LED pixels in a LED array. The centralized PC corrections are disclosed in a related Patent Cooperation Treaty (PCT) patent application with international application number PCT / US2024 / 028068, entitled “Systems and Methods for Integrated Controller / drivers module on One PCB for LED Display,” filed on June 5, 2024, which claims priority of multiple U.S. provisional patent applications, including U.S. provisional patent application no. 63 / 500,054, filed on May 4, 2023, a U.S. provisional patent application no. 63 / 471,112, filed on June 5, 2023, and a number of U.S. provisional patent applications filed same day on November 22, 2023, i.e., U.S. provisional patent application no. 63 / 602,068, U.S. provisional patent application no. 63 / 602,078, U.S. provisional patent application no. 63 / 602,083, U.S. provisional patent application no.63 / 602,086, U.S. provisional patent application no. 63 / 602,096, U.S. provisional patent application no. 63 / 602,097, U.S. provisional patent application no. 63 / 602,106, U.S. provisional patent application no. 63 / 602,121, U.S. provisional patent application no. 63 / 602,127, U.S. provisional patent application no. 63 / 602,136, U.S. provisional patent application no. 63 / 602,142, U.S. provisional patent application no. 63 / 602,146, and U.S. provisional patent application no. 63 / 602,155. The content of the related patent application PCT / US2024 / 028068 and all of the provisional applications associated with PCT / US2024 / 028068 is incorporated herein by reference in its entirety.Attorney Docket 148820.619524BACKGROUND1. Technical Field

[0003] The present disclosure relates to LED (Light Emitting Diode). More specifically, the present teaching relates to compensating parasitic capacitance in charging times for LEDs.2. Introduction

[0004] A light-emitting diode (LED) illuminates when the voltage across it exceeds a forward voltage drop, denoted by VF. Due to parasitic capacitance (PC) generally present in LEDs, there is a parasitic charging time before the voltage reaches VF and thus, there is delay in fully turning on an LED. It is known that the duration an LED is lit depends on a grayscale value of an associated pictorial data. Due to the inherent parasitic capacitance in each LED, the duration during which an LED is lit deviates from the expected duration determined based on the pixel data. In general, the actual light-on time for the LED is shorter than the duration for which the current is applied. Since both VF and PC vary with LEDs, resulting in different individual parasitic charging times so that the light-on times across different LEDs differ even if for the same grayscale value. Thus, variations in parasitic charging times across LEDs lead to distortion in visual effect, degrading image quality. This problem may be especially significant in low-grade regions in an image.

[0005] Effort has been made to address this issue. Some achieve so by adjusting the current-on time for each LED in such a way to compensate for parasitic charging time differences, ensuring expected light-on durations determined based on grayscale values. However, implementing such compensation requires additional circuitry in each driver chip and the compensation required for each driver chip is realized by individually measuring, calculating, and determining the adjustment needed. This significantly drive up the cost and the production complexity and the overall cost. This is especially so when there are thousands of driver chips in an LED.

[0006] Therefore, a more efficient and cost-effective solution for compensating parasitic charging time variations across LED displays is needed.Attorney Docket 148820.619524SUMMARY

[0007] The teachings disclosed herein relate to methods, systems, and programming for compensating parasitic charging times for LEDs:

[0008] In one example, a method, implemented on a machine is disclosed for determining parasitic capacitance (PC) correction parameters for an LED array including a plurality of LED pixels. When a test trigger signal is received by a parasitic capacitance (PC) detector, the PC detector starts a test process to measure the PC correction parameters of a LED pixel coupled to the PC detector. The PC detector determines the PC correction parameter for the corresponding LED pixel based on the detected PC characteristics and stores the PC correction parameter of the LED pixel with respect to a location of the LED pixel in the LED array to facilitate centralized PC correction on the LED pixel based on the PC correction parameter retrieved based on the pixel location.

[0009] In a different example, a system is disclosed for determining parasitic capacitance (PC) correction parameters for an LED array including a plurality of LED pixels and the use of such determined PC correction parameters for performing centralized PC correction with respect to each LED pixel in the LED array. The system includes one or more PC detectors each coupled to a corresponding LED pixel of the plurality of LED pixels. Each of the one or more PC detectors is configured to automatically determine a PC correction parameter for a corresponding LED pixel. Each PC detector includes a test controller and a test module working together to generate the PC correction parameter of the LED pixel based on the detected PC characteristics. The system further includes a PC correction storage unit that stores the PC correction parameter of the LED pixel with respect to a location of the LED pixel in the LED array. An LED controller is configured to perform centralized PC correction on each of the plurality of LED pixels in the LED array based on the PC correction parameter associated therewith retrieved from the PC correction parameter storage unit according to the location of the LED pixel in the LED array.

[0010] Additional benefits and novel features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The advantages of the present teachings may be realized and attained by practice or use of various aspects of the methodologies, instrumentalities and combinations set forth in the detailed examples discussed below.Attorney Docket 148820.619524BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The methods, systems and / or programming described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein:

[0012] FIG. 1 A (prior art) illustrates an exemplary output voltage of a LED showing a parasitic charging time;

[0013] FIG. IB (prior art) illustrates an example scheme of PC correction where a PC correction circuit is incorporated in each of multiple drivers;

[0014] FIG. 2 illustrates an exemplary partial internal construct of an integrated module with an LED controller providing centralized parasitic capacitance correction to multiple drivers, according to an embodiment of the present teaching;

[0015] FIG. 3 illustrates an exemplary internal construct of a centralized parasitic capacitance corrector in an LED controller for applying parasitic capacitance correction to multiple drivers, according to an embodiment of the present teaching;

[0016] FIG. 4 illustrates a flowchart of an exemplary process of a centralized parasitic capacitance corrector in an LED controller for applying parasitic capacitance correction to multiple drivers, according to an embodiment of the present teaching;

[0017] FIG. 5 illustrates an exemplary scheme for automated determination of PC correction parameters associated with multiple LED lights, according to an embodiment of the present teaching;

[0018] FIG. 6 depicts an exemplary internal construct of a PC detector for detecting the PC associated with each driver, according to an embodiment of the present teaching;

[0019] FIG. 7 depicts an exemplary internal construct of a test module, according to an embodiment of the present teaching;

[0020] FIG. 8 shows an exemplary circuit implementation for measuring some parameters for calculating PC correction parameters, according to an embodiment of the present teaching;

[0021] FIG. 9A illustrates a flowchart of an exemplary process for calculating PC correction parameters, according to an embodiment of the present teaching; andAttorney Docket 148820.619524

[0022] FIG. 9B illustrates a exemplary flowchart of a different exemplary process for calculating PC correction parameters, according to a different embodiment of the present teaching.DETAILED DESCRIPTION

[0023] Various embodiments of the disclosure are described in detail below. While specific implementations are described, this is done for illustration purposes only. Other components and configurations may be used without parting from the spirit and scope of the disclosure.

[0024] The present teaching relates to an additional improvement relating to the centralized parasitic capacitance correction disclosed in the PCT patent applicationPCT / US2024 / 028068. The additional improvement is directed to an automated approach to detecting individual parasitic capacitances associated with each of an array of LED lights and accordingly determining the corresponding PC correction parameters to centralized parasitic capacitance corrections via an LED controller controlling multiple drivers for driving the array of LED lights to carry out the centralized parasitic capacitance corrections.

[0025] A LED is known to have inherent parasitic capacitance. It is also known that parasitic capacitances affect the display quality. This is illustrated in FIG. 1 A with an example actual profile of an output voltage VOUT 110 of a LED in relation to an expected pulse duration 112 determined based on a desired grayscale value of a pixel associated with the LED light. The output voltage VOUT 110 is generated by a driver associated with the LED pixel when a constant current source of the driver begins sourcing the constant current into the LED pixel. As used herein, VOUT 110 denotes a voltage at an output node of the driver that is connected to the corresponding LED pixel. In some embodiments, the output voltage VOUT 110 may be provided as an input signal by a downstream module, as will be discussed with reference to the following figures. Ideally, to display a grayscale of a pixel, a pulse duration 112 is obtained, in which the output voltage VOUT 110 is expected to be higher than a minimum voltage, i.e., a forward voltage VF 114 of the LED, needed to turn on the LED. However, the actual profile of VOUT 110, as shown in FIG. 1A, deviates from the expected profile. Specifically, the actual profile of VOUT 110 exhibits a finite rising edge (that introduces a delay) and a falling edge due to the inherent PC associated with the LED. The notable is the parasitic charging time 118 associated with the rising edge. This effectively cuts short the LED lit time as the voltage during the parasitic charging time 118 is below VF 114 and thus does not turn on the LED. This discrepancy is responsible for aAttorney Docket 148820.619524 distortion on the grayscale value displayed, leading to inaccurate image content presentation.

[0026] FIG. IB (prior art) illustrates an example PC correction scheme in which each driver performs its own parasitic capacitance correction for their respective driving circuits. As shown, there are multiple drivers, driver 1 182- 1 , driver 2 182-2, . . . , driver N 182-N, each of which includes a corresponding driving circuit, i.e., driving circuit 1 172-1, driving circuit 2 172-2, . . ., driving circuit N 172-N, for driving a connected LED light, respectively. As each LED light has an inherent PC, the driver controlling the LED light needs to compensate for the PC. In this example PC correction scheme, each driver has its own PC corrector, i.e., PC corrector 1 152-1, PC corrector 2 152-2, ..., PC corrector N 152- N, each of which is individually designed based on the PC characteristics of the LED that it controls. Each PC corrector in a driver determines a PC correction parameter (i.e., PC correction parameter 1 162-1 for driving circuit 1 172-1, a PC correction parameter 2 162-2 for driving circuit 2 172-2, . . ., a PC correction parameter N 162-N for driving circuit N 172-N). This illustrated example PC correction scheme is costly because each driver is required to have its own PC correction circuitry therein. As a LED display panel often has thousands of LED lights, it is expensive to employ such a PC correction mechanism.

[0027] The PCT application PCT / US2024 / 028068 discloses a LED display system with modules, each of which is constructed to integrate a LED controller with drivers in its control. With such an integrated architecture, various functions traditionally performed by each driver using corresponding circuitries included therein can be centralized in the controller, yielding various improvements in terms of both performance and cost saving. This includes the function of parasitic capacitance correction. That is, with the LED display architecture as disclosed in the PCT application PCT / US2024 / 028068, the PC correction is consolidated and performed in a centralized manner by the LED controller instead of by individual drivers. An exemplary integrated module I-module 200 is illustrated in FIG. 2, which includes a LED controller 210 and a driver array 220 having therein a plurality of drivers (driver 1 220-1, driver 2 220-2, . . . , driver N 220-N) controlled by the LED controller 210. The I-module 200 comprises various circuitries for, e.g., communicating with other integrated modules and for controlling the display of image content allocated to LED lights driven by the drivers in the driver array 220.

[0028] Relevantly, the LED controller 210 comprises various circuitries for, e.g., communicating with serially connected I-modules, intercepting / storing image data allocated to LED lights driven by the drivers in the driver array 220, and generating signals forAttorney Docket 148820.619524 appropriately controlling each of the associated drivers in the driver array 220 to correctly display the pixel data. In this illustrated embodiment, the LED controller 210 includes a receiver / transmitter 230, a memory SRAM 240, a centralized parasitic capacitance corrector 250, a signal generator 260, and a screen refresher 270. The receiver / transmitter 230 is provided to receive data via 2-way communication connection with a serially connected I- module and, if the data is not designated to the I-module 200, transmit the data to the other serially connected I-module. If the received data is designated to the I-module 200 for display, the received data is stored in the SRAM 240 for further processing / display.

[0029] With respect to the data stored in SRAM 240, the LED controller 210 may further processes the data such as image enhancement and PC correction before generating control signals for the connected drivers in the driver array 220. Such control signals include RGB signal 280 used for generating the LED lights to display desired grayscale values in different color channels s well as GCLK signal 290 for clocking the LED lights. Different types of processing the LED controller 210 may apply to the data stored in SRAM 240 are disclosed in detail in the PCT application PCT / US2024 / 028068. Relevant to the present teaching, the parasitic capacitance corrector 250 in the LED controller 210 performs centralized parasitic capacitance corrections on the stored image data allocated to the drivers in the driver array 220 to compensate for the inherent PC characteristics associated with the respective LED lights driven by these drivers. The PC corrections are performed for each individual ones of the LED lights based on PC correction parameters 255 previously obtained by, testing these LED lights. In some embodiments, for each of the LED lights controlled by the I-module 200 via the driver array 220, a previous testing is conducted to detect the PC characteristics associated with the LED light and accordingly determine the PC correction parameter(s) to compensate. Such determined PC correction parameters for the LED lights controlled by the I-module 200 may then be stored in the PC correction parameters 255 to enable centralized PC corrections in operation.

[0030] The centralized PC corrections produce PC corrected image data, which is then provided to the signal generator 260 to create signals needed by the screen refresher 270 to generate corresponding control signals, i.e., RGB signal 280 and GCLK signal 290, for controlling the drivers in 220 to drive their respective LED lights to light in ways without the negative PC effects. In this way, each driver in driver array 220 takes an input that is already PC corrected. As such, there is no need to include a parasitic capacitance corrector in any of the drivers. This not only reduces the cost of the drivers but also increases the performance efficiency via the centralized operation in the LED controller 210.Attorney Docket 148820.619524

[0031] As shown in FIG. 2, to facilitate the centralized PC correction, PC correction parameters are stored in 255 so that the parasitic capacitance corrector 250 may retrieve and apply such stored PC correction parameters associated with each corresponding LED light to carry out the correction for the LED light. In some embodiments, the PC correction parameters may be stored in the storage 255 for the PC correction parameters based on pixel locations of each relevant LED light in a LED display panel. In such a way, the PC correction parameters associated with a LED light may be retrieved based on the pixel location of the LED light. In some embodiments, each I-module may store the PC correction parameters associated with the LED lights that it controls according to image blocks and then PC correction parameters within each block may be stored in a predetermined order. For instance, each block may correspond to a 128x128 sub image and within the block, the pre-determined order may be a raster scan starting from the top left pixel and ending at the lower right pixel in the block. With such a specified organization, the PC correction parameters for each LED light corresponding to a pixel may be located and retrieved for centralized parasitic capacitance correction.

[0032] FIG. 3 illustrates an exemplary internal construct of the parasitic capacitance corrector 250 in I-module 200 that carries out centralized parasitic capacitance corrections with respect to LED lights controlled by I-module 200, according to an embodiment of the present teaching. As depicted in FIG. 3, the parasitic capacitance corrector 250 takes image data for some pixels as input and generates PC corrected image data based on the input image data as well as the PC correction parameters associated with the pixels. In this illustrated embodiment, the parasitic capacitance corrector 250 includes a LED light block determiner 310, a PC correction parameter retriever 320, and a PC corrected data generator 330. The LED light block determiner 310 is provided to determine the block location of the input image data according to a mapping table 300. With the mapped block location of the input image data, the PC correction parameter retriever 320 retrieves, from the PC correction parameters 255, the PC correction parameters associated with the input image data. The PC correction parameters so retrieved corresponding to the input image data are then provided to the PC corrected data generator 330 so that PC corrections may be carried out on respective pixel data in the input image data using corresponding correction parameters to generate the PC corrected image data as output.

[0033] FIG. 4 is a flowchart of an exemplary process of the parasitic capacitance corrector 250 for applying centralized parasitic capacitance corrections, according to an embodiment of the present teaching. As discussed herein, when the LED light block determiner 310Attorney Docket 148820.619524 receives, at 400, image data from the SRAM 240, it determines, at 410, the corresponding locations of the pixels included in the input image data based on the address information in the input image data and the mapping table 300. Based on the corresponding locations so determined, the PC correction parameter retriever 320 retrieves, at 420 from the stored PC correction parameters 255, the PC correction parameters corresponding to each of the pixels in the image data. The PC corrected data generator 330 then applies the retrieved PC correction parameters respectively to corresponding pixels in the image data to perform, at 430, PC corrections and generate, at 440, the PC corrected image data.

[0034] As discussed herein, to enable centralized PC correction, PC correction parameters 255 are obtained and stored. Traditionally, the PC characteristics for each LED light are obtained through manual testing, which is laborious and inefficient. The present teaching is related to an automated scheme to obtain PC characteristics associated with individual LED pixels in a LED display. FIG. 5 illustrates an exemplary scheme for automatically detecting PC correction parameters associated with each of M x N LED pixels, according to an embodiment of the present teaching. As each LED pixel is driven by a driver chip, this exemplary scheme includes M x N PC detectors 510 (i.e., PC detector 11 510-11, . . ., PC detector IN 510- IN, PC detector 21 510-21, . . . , PC detector 2N 510-2N, PC detector 31 510-31, ..., PC detector 3N 510-3N, ..., PC detector Ml 510-M1, ..., PC detector MN 510- MN), each of which is provided to detect the PC characteristics of the LED lights at a corresponding pixel location in the M x N network. As shown in FIG. 5, each of the M x N PC detectors 510 each of the M x N PC detectors operates to receive a voltage VOUT (512) from the corresponding drivers 220 as input (as discussed with reference to FIG. 1 A), analyze the received signal to detect the PC characteristics of the LED pixel, and output the correction parameters for the LED pixel determined based on the detected PC characteristics. As discussed herein, the parasitic charging time for each LED pixel is part of the PC characteristics of the LED pixel. Once the parasitic time is detected, a rising time T may be determined as a correction parameter to compensate the inherent parasitic charging time of the LED pixel. In this illustrated embodiments, each PC detector outputs a rise timing signal T (516) and a forwarding voltage VF (514) to represent the PC correction parameters for the underlying LED pixel.

[0035] In operation, each PC detector processes the received VOUT (512) and outputs PC correction parameters, such as the forwarding voltage VF (514) and a timing signal T (516). Details relating to the processing of the VOUT (512) to derive the PC correction parameters are provided with reference to FIGS. 6 - 9B. Such PC correction parameters from eachAttorney Docket 148820.619524 individual PC detector with respect to corresponding individual drivers are then consolidated and stored in PC correction parameters 255 (e.g., indexed via pixel locations) as centralized PC correction parameters. As discussed herein, such stored PC correction parameters in PC correction parameters 255 may be retrieved in operation by the LED controller 210 in each I-module 200 to perform centralized PC corrections for those drivers in the same I-module 200.

[0036] In the embodiment as illustrated in FIG. 5, each of the M x N PC detectors 510 is provided to detect the PC characteristics of the corresponding LED pixel in the M x N matrix. In this configuration, the test trigger signal 600 can be provided to the M x N PC detectors to trigger each to carry out the test process to obtain PC correction parameters for their respective LED pixels. The test trigger signal 600 may be sent to all synchronously so that the M x N PC detectors may operate in a parallel manner. The test trigger signal 600 may also correspond to a series of triggering signals, each of which is associated with an address of an LED pixel. In this way, the M x N PC detectors may operate in a serial manner and each of them may be activated when the address included with the triggering signal matches the two dimensional location of the LED pixel.

[0037] Other configurations of the PC detectors with respect to the M x N LED lights may also be possible. For example, a single PC detector may be provided to determine the PC characteristics associated with all M x N individual LED pixels, e.g., in a sequential manner. To facilitate this mode of operation, the sole PC detector may, upon being triggered by the test trigger signal 600, operate to determine the PC characteristics and the corresponding PC correction parameters of each of the M x N LED pixels in a sequential manner using, e.g., a raster scan order, test trigger signal 600 may correspond to a series of triggering signals, each of which

[0038] Alternatively, another mode of operation may also be implemented to determine the PC correction parameters for the M x N LED pixels. For instance, the M x N matrix of LED pixels may be divided into m x n sub-matrices, where m < M and n < N, so that each sub-matrix includes (M / m) x (N / n) LED pixels. A PC detector may be provided with respect to each of the sub-matrices to obtain PC characteristics associated with the LED pixels in the sub-matrix. To facilitate the operation in this mode of operation, each of the m x n PC detectors may be activated upon receiving the test trigger signal 600. In some embodiments, the test trigger signal 600 may be transmitted to the m x n PC detectors simultaneously so that the m x n PC detectors may be activated in parallel. Once activated, each of the m x n PC detectors may operate to determine the PC characteristics andAttorney Docket 148820.619524 accordingly the PC correction parameters of the LED pixels included in its corresponding sub-matrix in a sequential manner. Yet in a different configuration, the m x n PC detectors may also be activated in a sequential manner. In some embodiments, this may be achieved via the test trigger signal 600 by having, e.g., a series of m x n triggering signals, each of which is directed to one of the PC detectors allocated to operate with respect to an appropriate sub-matrix. In a different implementation, m x n PC detectors may also be connected in a serial manner in a, e.g., raster scan order, so that when a PC detector completes its operation to determine the PC correction parameters in its corresponding submatrix, it may send a triggering signal to the next connected PC detector to start to process with respect to the next sub-matrix. In this way, the test trigger signal 600 may be provided to activate the first PC detector, e.g., the PC detector designated to process the sub-matrix located at the upper left comer of the M x N matrix.

[0039] Such determined PC correction parameters for the LED pixels may then be stored in the PC correction parameters 255, as illustrated in FIG. 2. As discussed herein, to allow correct retrieval of applicable PC correction parameters to facilitate centralized PC corrections, the PC correction parameters obtained according to the present teaching may be stored in 255 based on pixel locations of the corresponding LED pixels in the LED array. With such a specified organization, the PC correction parameters for each LED pixel may be located and retrieved for centralized parasitic capacitance correction.

[0040] FIG. 6 illustrates an exemplary internal construct of a PC detector, e.g., 510-11, according to an embodiment of the present teaching. In this illustrated embodiment, the PC detector 510-11 comprises a test controller 610 and a test module 630. A primary function of the PC detector 510-1 is to test the PC characteristics of a LED pixel and this primary function is performed by the test module 630. The test controller 610 is provided to control the testing process in response to an external test trigger signal 600 and accordingly issues a command 620 to activate the test module to carry out the primary testing function at the command time. In some embodiments, the external test trigger signal 600 may be provided by the LED controller 210 that controls the plurality of drivers 220-1, 220-2 . . . 220-N, as illustrated in FIG. 2. In addition to activating the test module 630 in response to the test trigger signal 600, the commend 620 from the test controller 610 may also include other operational parameters used to control the test module 630. This may include a specification on the specific test process to be carried out by the test module 630 and types of PC correction parameters (e.g., VF 514-11 and T 516-11) to be generated by the test module 630. As such, the test controller 610 may be programmable so that it may switchAttorney Docket 148820.619524 among multiple test processes that are suitable with respect to different types of driver chips and / or different uses in varying application cases.

[0041] When activated via command 620, the test module 630 may process the input signal VOUT 512-11 to derive the specified PC correction parameters (e.g., VF 514-11 and T 516- 11) based on the specification provided in the command 620. Other PC detectors in the M x N matrix (i.e., PC detector 12 510-12, ...., PC detector MN 510-MN) may also be similarly constructed. In some embodiments, the test trigger signal 600 may be sent to all PC detectors so that the testing operation across all LED pixels may be carried out in a synchronous manner. In some embodiments, the PC detectors may operate in a sequence and in this mode of operation, different test trigger signals may be sent to different PC detectors in a sequence with different timings. In some embodiments, the PC detection operation for the M x N LED pixels may be performed in a mixed mode, e.g., each row / column may be triggered at the same time and different rows / columns may be activated sequentially.

[0042] FIG. 7 illustrates an exemplary internal construct of the test module 630, according to an embodiment of the present teaching. In this illustrated embodiment, the test module 630 is provided to generate a timing signal T 516-11 and a forward voltage VF 514-11 as PC correction parameters. The illustrated test module 630 includes an analog-to-digital converter (ADC) 700, a comparator (CMP) 710, a counter 720, and buffers 730 including a VF buffer 730-1 for VF values and a T buffer 730-2 for T values. Both the ADC 700 and the comparator 710 receive an input signal VOUT 512-11. Upon receiving the command 620, the test module 630 carries out a test process to measure the timing signal T 516-11 and the forward voltage VF 514-11 in accordance with the command 620.

[0043] In operation, the test module 630 may be configured to operate in multiple test modes to characterize the parasitic charging behavior associated with the LED pixel. Two exemplary test modes are presented herein, including a first test process and a second test process. In operation, the mode of operation elected to carry out the testing may be specified via the command 620, provided to the test module 630 as an input. It should be appreciated that the first and the second test processes are provided merely as examples and not intended as limitations. Different, additional, or alternative test processes may be employed without departing from the principles of the present teaching.

[0044] With respect to the exemplary first and second processes, when the test module 630 is initiated, a constant current source of the driver begins sourcing the current I into the LED pixel, thereby causing the input signal VOUT 512-11 to ramp from an initial near-zeroAttorney Docket 148820.619524 voltage (e.g., a first voltage) in the presence of a parasitic capacitance C. In some embodiments, the first voltage can be approximated to be a zero voltage. In this way, the time T required for the input signal VOUT 512-11 to ramp to a voltage Vx satisfies the following formulated condition:T = (C / I) x Vx (1)

[0045] In some implementations, the difference between the first and the second test processes may be related to the voltage level Vx used by the comparator 710 as a comparison threshold, and therefore in the portion of the input signal VOUT 512-11 ramp that is measured by the counter 720, as detailed below. In some embodiments, the voltage level Vx may be specified in the command 620.

[0046] If the command 620 specifies to test the CP correction parameters in the first test mode, the test module 630 may proceed to measure a partial charging time Ti in response to the command 620 and computes a PC correction parameter from the partial charging time Ti. Specifically, the comparator 710 is provided with a reference voltage VREFthat is below the LED forward voltage so that the LED does not illuminate during the first process. That is, VREF does not exceed common forward voltages of the red LED (e.g. ,1.8V - 2.2V), green LED (e.g., 2.0V - 3.5V) or blue LED (e.g., 3.0V - 3.6V). In some embodiments, the value of VREFmay be provided with other operational parameters included in the command 620. Upon receiving the input signal VOUT 512-11, the reference voltage VREF, and the command 620, the comparator 710 compares the input signal VOUT (e.g., 512-11) against the reference voltage VREF as the input signal VOUT 512-11 ramps upward from the initial near-zero voltage to generate a comparison result (e.g., a two-state logic signal indicating whether the input signal VOUT 512-11 is below or above VREF). The comparison result is sent to the counter 720 when the comparison result changes from a first state indicating VOUT 512-11 < VREF to a second state indicating VOUT 512-11 > VREF.

[0047] The counter 720 is provided to count the passage of time for the comparison result to change from the first state to the second state, according to, e.g., the counting cycles of a clock signal, such as a GCLK signal. The counting continues while the comparison result is still in the first state and stops when the comparison result changes to the second state. In this manner, the counter 720 produces a count value corresponding to a number of clock cycles. This count value may be converted into a time value Ti based on a known period of the clock signal. The time value Ti represents the time required for the input signal VOUTAttorney Docket 148820.619524512-11 to rise from its initial level (e.g., OV) to VREF, and is subsequently stored in the T buffer 730-2. After the counter 720 stops counting, the input signal VOUT 512-11 continues to rise to a stable voltage corresponding to the forward voltage VF (514-11), which is measured by the ADC 700 and is stored in the VF buffer 730-1. To obtain the full charging time that corresponds to the PC correction parameter, the partial charging time Ti is scaled by the ratio between the input signal VOUT 512-11 and the reference voltage VREF:PC correction parameter = Ti x VF / VREF (2)

[0048] If the command 620 specifies to test the CP correction parameters in the second test mode, the test module 630 may proceed to measure a full charging time T2 in response to the instruction from the command 620. In this mode of operation, the test module 630 directly measures the PC correction parameter. Initially, upon receiving the command 620, the input signal VOUT 512-11 rises from 0V to a stable voltage corresponding to the forward voltage VF (514-11), which is measured by the ADC 700 and is then stored in the Vrbuffer 730-1. Then, the comparator 710 sets the reference voltage to be the forward voltage VF (514-11) in response to the VF (514-11) transmitted from the VF buffer 730-1. In other embodiments, the forward voltage VF 514-11 may be retrieved from a stored value in the VF buffer 730-1 previously obtained during a separate measurement phase. In a similar manner as described in the first test process, the counter 720 measures a time value T2 that corresponds to the time required for the input signal VOUT 512-11 to ramp from the initial near-zero voltage to the forward voltage VF (514-11). As such,PC correction parameter = T2 (3)

[0049] Therefore, the time measured in either the first or the second mode of operation (i.e., Ti or T2) may be used to determine the PC correction parameter associated with each LED pixel. In some embodiments, the test module 630 may be configured to seek more reliable test result by iteratively carrying outing the first and / or the second test processes so that an averaged value of the PC correction parameters may be obtained. For example, the test module 630 may be instructed by the command 620 to compute an average value of the PC correction parameters respectively obtained from the first test process and that from the second test process. As another example, the command 620 may specify a sequence of reference voltages VREF, each below the VF (514-11), for use in successive executions of theAttomey Docket 148820.619524 first test process. Such a sequence results in the generation of a corresponding series of (Ti, VREF) pairs. In some embodiments, the PC correction parameters may be then determined by extrapolating a full-charging time from the series of the measured (Ti, VREF) pairs, thereby improving the accuracy of the PC correction parameter measurements.

[0050] It should be appreciated that, although the foregoing description of the first and the second test processes is provided with respect to a single LED pixel, the test controller 610 and its associated test module 630 may be instantiated across an array of LED pixels, e.g., in an M x N matrix. When triggered by a corresponding test trigger signal 600, each PC detector (510) may autonomously process its respective input signal VOUT (512) to generate individual PC correction parameters for its associated LED pixel. Such automated, per-pixel detection of parasitic-charging characteristics enables the LED controller 210, which connects to and coordinates a plurality of drivers 220, to perform centralized parasitic capacitance corrections across the entire LED array.

[0051] FIG. 8 shows an exemplary circuit implementation inside the test module 630 for measuring a forward voltage VF for calculating PC correction parameters, according to an embodiment of the present teaching. In particular, the exemplary circuity implementation includes a voltage bias VDD, an ADC 700, a LED diode 800 and a constant current source 810, working together to measure the forward voltage VF 514-11 to be used to determine the PC correction parameters, as described with respect to the test module 630 of FIG. 7. Specifically, FIG. 8 illustrates one exemplary circuit implementation that enables the forward voltage VF 514-11 to be measured inside the test module 630. In some embodiments, the ADC 700 is coupled to a node where an input signal VOUT 512-11 is received, e.g., a node between the constant current source 810 and the LED diode 800. In operation, when a test process is initiated according to, e.g., the command 620, the constant current source 810 provides a substantially constant current to the LED diode 800, thereby causing the input signal VOUT 512-11 to ramp from an initial near-zero voltage in the presence of a parasitic capacitance C to a stable voltage corresponding to the forward voltage VF 514-11 of the LED diode 800. The ADC 700 then samples the voltage at the input signal VOUT 512-11 and converts the sampled analog voltage into a digital value indicative of the forward voltage VF 514-11. In this way, FIG. 8 illustrates one exemplary analog front-end configuration for obtaining the forward voltage information needed to determine the PC correction parameter.

[0052] In some embodiments, the constant current source 810 and the ADC 700 may be implemented inside the same driver for the LED pixel, such that the input signal VOUT 512-Attorney Docket 148820.61952411 is measured directly on-chip. In some other embodiments, a single constant current source 810 and a single ADC 700 may be shared across a plurality of drivers through, e.g., a multiplexing circuitry, allowing each LED pixel’s input signal VOUT 512-11 to be measured in sequence. In yet another embodiment, the ADC 700 may capture the input signal VOUT 512-11 under different sampling rates or biasing conditions to accommodate various accuracy or power constraints. For instance, these sampling rates or biasing conditions may be provided by the command 620.

[0053] FIG. 9A illustrates a flowchart of an exemplary process for calculating PC correction parameters, according to an embodiment of the present teaching. As illustrated, the exemplary process may correspond to the first test process carried out by the test module 630, as discussed with respect to FIG. 7. Specifically, at step 905, a reference voltage VREF is set to a value below a common forward voltage VF 514-11 of the LED pixel, such that the LED does not illuminate during the test process. At step 915, a constant current source, such as the constant current source 810 is enabled at time zero to supply a substantially constant current to the LED pixel, thereby causing an input signal VOUT 512- 11 to begin ramping upwards from an initial near-zero voltage level. In some embodiments, as the input signal VOUT 512-11 ramps, a comparator 710 monitors the input signal VOUT 512-11 with respect to the reference voltage VREF and produces a comparison result indicating whether the input signal VOUT 512-11 remains below the reference voltage VREF. In some embodiments, the comparison result may be a two-state logic signal indicating whether the input signal VOUT 512-11 is below (a first state) or above VREF (a second state). At step 925, a counter 720 that is operatively coupled to the comparator 710 records a count value corresponding to the number of clock cycles elapsed from the beginning of the ramp until the instant that the input signal VOUT 512-11 reaches the reference voltage VREF. This recorded count value is then converted to a time Ti that represents a partial charging time associated with the LED pixel. In some embodiments, after the partial charging time Ti is obtained, an ADC, such as the ADC 700 measures the forward voltage VF 514-11 of the LED pixel as the input signal VOUT 512-11 continue to rise toward a stable voltage corresponding to the forward voltage VF 514-11. At step 935, a PC correction parameter is calculated based on the measured partial charging time Ti. In some embodiments, the PC correction parameter is further based on the measured forward voltage VF 514-11, according to equations 1 and 2. In this manner, FIG. 9A provides an exemplary process for determining a PC correction parameter using a partial charging measurement obtained when the input signal VOUT 512-11 reaches a selected reference voltage VREF.Attorney Docket 148820.619524

[0054] FIG. 9B illustrates an exemplary flowchart of a different exemplary process for calculating PC correction parameters, according to a different embodiment of the present teaching. As illustrates, the different exemplary process may correspond to the second test process carried out by the test module 630, as discussed with respect to FIG. 7. Specifically, at step 907, a forward voltage VF 514-11 of the LED pixel is determined. In some embodiments, the forward voltage VF 514-11 may be obtained by enabling a substantially constant current through the LED pixel until an input signal VOUT 512-11 reaches a stable level, and sampling the resulting voltage at the input signal VOUT 512-11 via an ADC, such as the ADC 700, to produce a digital value indicative of the forward voltage VF 514-11. In some other embodiments, the forward voltage VF 514-11 may be retrieved from a stored value in the VF buffer 730-1 previously obtained during a separate measurement process. At step 917, a comparator 710 sets a reference voltage VREF to be equal to the determined forward voltage VF 514-11. At step 927, a constant current source, such as the constant current source 810, is enabled at time zero to supply a substantially constant current to the LED pixel, thereby causing the input signal VOUT 512-11 to begin ramping upwards from an initial near-zero voltage level toward the forward voltage VF 514-11. In some embodiments, as the input signal VOUT 512-11 ramps, the comparator 710 monitors the input signal VOUT 512-11 against the forward voltage VF 514-11 and produces a comparison result indicating whether the input signal VOUT 512-11 remains below or has reached the reference voltage VREF, i.e., the forward voltage VF 514-11. In some embodiments, the comparison result may be a two-state logic signal indicating whether the input signal VOUT 512-11 is below (a first state) or above VREF (a second state). At step 937, a counter 720 that is operatively coupled to the comparator 710 records a count value corresponding to the number of clock cycles elapsed from the beginning of the ramp until the instant that the input signal VOUT 512-11 reaches the reference voltage VREF. This recorded count value is then converted to a time T2 that represents a full charging time required for the input signal VOUT 512-11 to arise from its initial level to the forward voltage VF 514-11. At step 947, a PC correction parameter is calculated based on the measured time T2. In some embodiments, the PC correction parameter may be set to be equal to T2 so as to directly represent the full charging time associated with the LED pixel. In this manner, FIG. 9B provides a different exemplary process for determining a PC correction parameter compared to the process of FIG. 9 A. As discussed herein, the test module 630 may be configured to carry out a test process that incorporates one or more executions of the test processes illustrated in FIG. 9A and / or one or more executions of the test processes in FIG. 9B. In some embodiments, the testAttorney Docket 148820.619524 controller 610 may be programmable so that it may provide the test module 630 with a specific test process via a command 620, among multiple test processes that are suitable with respect to different types of driver chips and / or different uses in varying application cases.

[0055] In this manner, both FIG. 9A and FIG. 9B illustrate exemplary flowcharts that measures the PC correction parameters. As discussed herein, similar operations may be performed across an array of LED pixels, such that each PC detector (510) autonomously generate a PC correction parameter for its associated pixel. This automated, per-pixel operation enables an LED controller connecting and controlling multiple drivers to perform centralized parasitic-capacitance corrections throughout the LED array.

[0056] Accordingly, the improved LED control system according to the present teaching provides new architectures, internal modules, implementations and operational processes that enable automated, per-pixel characterization of parasitic capacitances across an array of LED lights to enable centralized compensation of such parasitic capacitances by a LED controller on behalf of a plurality of drivers. In one aspect, this automated characterization is performed via a plurality of PC detectors (e.g., PC detector 510-11), each comprising a test controller and a test module that cooperatively process an input signal VOUT from a corresponding LED pixel in response to a test trigger signal and one or more commands specifying test parameters. By detecting an individual parasitic charging behavior for each LED pixel and consolidating the computation and application of parasitic capacitance correction parameters at the LED controller, the present teaching significantly reduces the computation complexity at each driver, simplifies circuit design, and enhances the brightness uniformity across the entire LED array. In additional aspects, the test controller in each PC detector may be programmable to select among multiple test processes and to control which PC correction parameters are generated by the test module, thereby allowing the same overall architecture to be adapted to different types of driver chips and different application scenarios. In further aspects, test trigger signals may be applied to the PC detectors in a synchronous, sequential or mixed mode manners. With these improvements, the system and method disclosed in the present teaching provide a more uniform grayscale output, an increased display accuracy, and a higher robustness against LED-to-LED variations.

[0057] Those skilled in the art will recognize that the present teachings are amenable to a variety of modifications and / or enhancements. For example, although the implementation of various components described above may be embodied in a hardware device, it may also beAttorney Docket 148820.619524 implemented as a software only solution, e.g., an installation on an existing server. In addition, the techniques as disclosed herein may be implemented as a firmware, firmware / software combination, firmware / hardware combination, or a hardware / firmware / software combination.

[0058] While the foregoing has described what are considered to constitute the present teachings and / or other examples, it is understood that various modifications may be made thereto and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

Claims

Attorney Docket 148820.619524WE CLAIM:

1. A method for determining a parasitic capacitance (PC) correction parameter for a LED pixel in a LED array having a plurality of LED pixels, comprising: receiving a test trigger signal to start a test process; generating, in response to the test trigger signal, a command specifying one or more test parameters including a reference voltage; supplying, in response to the command, a current to the LED pixel to cause an input signal to the LED pixel to ramp upward from a first voltage; comparing the input signal against the reference voltage; detecting a timing value representing an amount of time required for the input signal to reach the reference voltage from the first voltage; measuring a second voltage representing a forward voltage of the LED pixel; determining a PC correction parameter for the LED pixel based on the timing value, the first voltage and the second voltage; and storing the PC correction parameter for the LED pixel with respect to a location of the LED pixel in the LED array to facilitate centralized PC correction on the LED pixel based on the PC correction parameter retrieved based on the location.

2. The method of claim 1, wherein the reference voltage is set below the second voltage of the LED pixel.

3. The method of claim 1, wherein the reference voltage is set to be equal to the second voltage of the LED pixel.

4. The method of claim 1, wherein recording the timing value comprises counting a number of cycles of a clock signal while the input signal is below the reference voltage.

5. The method of claim 1, wherein measuring the second voltage comprises sampling the input signal after the input signal reaches a stable voltage level.

6. The method of claim 1, wherein the command specifies one or more test parameters including a test process type.Attorney Docket 148820.6195247. The method of claim 1, further comprising receiving the test trigger signal synchronously by one or more PC detectors such that the test process for the plurality of LED pixels are carried out in a parallel manner.

8. The method of claim 1, further comprising receiving the test trigger signal in a sequence by one or more PC detectors such that the test process for the plurality of LED pixels are carried out in a sequential manner.

9. The method of claim 2, wherein generating the PC parameter comprises computing a scaled timing value based on a ratio between the second voltage and the reference voltage.

10. The method of claim 1, wherein the test process is carried out for all of the plurality of LED pixels of the LED array to produce a plurality of PC parameters for each LED pixel of the LED array.

11. A system for determining parasitic capacitance (PC) correction parameters for an LED array including a plurality of LED pixels, the system comprising: one or more PC detectors each coupled to a corresponding LED pixel of the plurality of LED pixels, wherein each of the one or more PC detectors is configured to automatically determine a PC correction parameter for a corresponding LED pixel, wherein each of the one or more PC detectors includes: a test controller configured to receive a test trigger signal and to generate a command specifying one or more test parameters in response to the test trigger signal, and a test module configured to, upon activated by the command, process an input signal associated with the LED pixel to generate a PC correction parameter for the LED pixel based on the input signal and the one or more test parameters; a PC correction parameter storage unit operatively coupled to the one or more PC detectors and configured to store the PC correction parameter for each of the plurality of LED pixels with respect to a location of the LED pixel in the LED array; and a LED controller configured to perform centralized PC correction on each of the plurality of LED pixels in the LED array based on the PC correction parameter associated therewith retrieved from the PC correction parameter storage unit according to the location of the LED pixel in the LED array.Attorney Docket 148820.61952412. The system of claim 11, wherein the test controller is programmable to select among the one or more test parameters based on a plurality of test processes.

13. The system of claim 11, wherein the test module is configured to control a constant current source to supply a current to the LED pixel corresponding to the PC detector to cause the input signal to ramp upward from a first voltage during the test process.

14. The system of claim 13, wherein the command specifies a reference voltage and wherein the test module is configured to compare the input signal against the reference voltage.

15. The system of claim 14, wherein the test module comprises a counter configured to record a timing value representing an amount of time required for the input signal to reach the reference voltage from the first voltage.

16. The system of claim 15, wherein the test module comprises an analog-to-digital converter configured to measure a second voltage representing a forward voltage of the LED pixel corresponding to the PC detector.

17. The system of claim 16, wherein the reference voltage specified in the command is set below the second voltage associated with the LED pixel corresponding to the PC detector.

18. The system of claim 16, wherein the reference voltage specified in the command is set to be equal to the second voltage associated with the LED pixel corresponding to the PC detector.

19. The system of claim 11, wherein the one or more PC detectors receive the test trigger signal synchronously such that the test process for the plurality of LED pixels are carried out in a parallel manner.

20. The system of claim 11, wherein the one or more PC detectors receive the test trigger signal in a sequence such that the test process for the plurality of LED pixels are carried out in a sequential manner.

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