A semiconductor structure and a method of fabricating the same
By forming a collector layer and a germanium-silicon epitaxial layer in the HBT device, the emitter structure and collector region are fabricated, solving the problems of large device area and deterioration of parasitic parameters caused by the collector lead-out method, and realizing the improvement of high-frequency performance and simplification of process of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-17
AI Technical Summary
Traditional heterojunction bipolar transistor (HBT) devices have a large device area, deteriorated parasitic parameters, limited collector conductivity, and limited high-frequency performance because the collector is located on the emitter side.
The process involves sequentially forming a collector layer and a germanium-silicon epitaxial layer on one side of the substrate layer to form an emitter structure, a collector region, and a base region. The width of the collector region is less than or equal to the width of the emitter structure. By using patterning, parasitic capacitance and resistance are reduced, and the process flow is simplified.
It significantly reduces collector-base parasitic capacitance and base resistance, improves the high-frequency performance and integration of the device, simplifies the process flow, and increases the process yield.
Smart Images
Figure CN122421418A_ABST