Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate, the substrate comprising an active region; an isolation layer, formed in the substrate of the active region; a gate layer, formed on the substrate of the active region, the gate layer comprising a main gate and an extension gate, the main gate being disconnected with the extension gate, and the projections of the main gate and the extension gate on the substrate being connected through the isolation layer. The application can eliminate the influence of the parasitic capacitance on the performance of the semiconductor device while keeping the original function of the gate layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Common device structures for achieving body contacts include BTS (Body Tied to Source) structures, T-gate structures, and H-gate structures. Figure 1 Taking the device with a T-gate structure shown as an example, from Figure 1 As can be seen, a T-type gate layer 11 is formed on the substrate. A source region 12 and a drain region 13 are formed on either side of the "|" portion of the T-type gate layer 11, respectively. A body contact region 14 is formed on the side of the substrate away from the source region 12 and drain region 13 at the "-" portion of the T-type gate layer 11. Among these, in the formation... Figure 1 In the process of forming the device with the T-gate structure shown, the junction AA' of the ion implantation region A1 when forming the source region 12 and the drain region 13 and the ion implantation region A2 when forming the body contact region 14 must be located on the "-" part of the T-gate layer 11. Otherwise, it may affect the formation range of the source region 12, the drain region 13 and the body contact region 14, and thus affect the device performance.

[0003] However, due to the influence of the critical dimensions of the fabrication process of the gate layer 11, source region 12, drain region 13 and body contact region 14, as well as the fluctuation of the alignment accuracy of the mask used, the gate length L1 of the "-" portion of the gate layer 11 in the direction from the source region 12 to the body contact region 14 cannot be too small (e.g., not less than 0.3 micrometers). However, if the gate length L1 of the "-" portion of the gate layer 11 in the direction from the source region 12 to the body contact region 14 is too large, it will lead to an increase in parasitic capacitance, thereby reducing the performance of the device.

[0004] Therefore, how to eliminate the impact of parasitic capacitance on device performance while maintaining the original function of the gate layer is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which enables the elimination of the influence of parasitic capacitance on the performance of the semiconductor device while maintaining the original function of the gate layer.

[0006] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0007] Substrate, the substrate including an active region;

[0008] An isolation layer is formed in the substrate of the active region;

[0009] A gate layer is formed on the substrate of the active region. The gate layer includes a main gate and an extended gate. The main gate is disconnected from the extended gate. The projections of the main gate and the extended gate on the substrate are connected through the isolation layer.

[0010] Optionally, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form a T-shape, with the main gate located at the "|" position of the T-shape and the extended gate located at the "―" position of the T-shape; or, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form an H-shape, with the main gate located at the "―" position of the H-shape and the extended gate located at the "|" position of the H-shape.

[0011] Optionally, the projections of the main gate and the extended gate onto the substrate extend onto the isolation layer.

[0012] Optionally, the semiconductor device further includes:

[0013] A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure being used to define the active region; the isolation layer and the shallow trench isolation structure are formed of the same material using the same process.

[0014] Optionally, the semiconductor device further includes:

[0015] The source region and drain region are formed in the active regions on both sides of the main gate, or in the active regions on both sides of the main gate and the isolation layer, respectively;

[0016] The body contact region is formed in the active region on the side of the extended gate and the isolation layer away from the main gate.

[0017] Optionally, the semiconductor device further includes:

[0018] Conductive plugs are formed on the main gate, the source region, the drain region, and the body contact region.

[0019] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0020] A substrate is provided, the substrate including an active region;

[0021] An isolation layer is formed in the substrate of the active region;

[0022] A gate layer is formed on the substrate of the active region. The gate layer includes a main gate and an extended gate. The main gate is disconnected from the extended gate. The projections of the main gate and the extended gate on the substrate are connected through the isolation layer.

[0023] Optionally, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form a T-shape, with the main gate located at the "|" position of the T-shape and the extended gate located at the "―" position of the T-shape; or, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form an H-shape, with the main gate located at the "―" position of the H-shape and the extended gate located at the "|" position of the H-shape.

[0024] Optionally, the projections of the main gate and the extended gate onto the substrate extend onto the isolation layer.

[0025] Optionally, before forming the gate layer on the substrate of the active region, the method of manufacturing the semiconductor device further includes:

[0026] Simultaneously, a shallow trench isolation structure and the isolation layer are formed in the substrate, the shallow trench isolation structure being used to define the active region.

[0027] Optionally, the method for manufacturing the semiconductor device further includes:

[0028] Source and drain regions are formed in the active regions on both sides of the main gate, or source and drain regions are formed in the active regions on both sides of the main gate and the isolation layer; and a body contact region is formed in the active regions on the side of the extended gate and the isolation layer away from the main gate.

[0029] Optionally, the method for manufacturing the semiconductor device further includes:

[0030] Conductive plugs are formed on the main gate, the source region, the drain region, and the body contact region.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] 1. The semiconductor device of the present invention comprises: a substrate, the substrate including an active region; an isolation layer formed in the substrate of the active region; and a gate layer formed on the substrate of the active region, the gate layer including a main gate and an extended gate, the main gate being disconnected from the extended gate, and the projections of the main gate and the extended gate on the substrate being connected through the isolation layer. This enables the original function of the gate layer to be maintained while eliminating the influence of parasitic capacitance on the performance of the semiconductor device. Furthermore, since the isolation layer is formed in the substrate, no precise control is required, and the process is simple.

[0033] 2. The semiconductor device manufacturing method of the present invention involves forming an isolation layer in the substrate of the active region; forming a gate layer on the substrate of the active region, wherein the gate layer includes a main gate and an extended gate, the main gate is disconnected from the extended gate, and the projections of the main gate and the extended gate on the substrate are connected through the isolation layer. This allows the original function of the gate layer to be maintained while eliminating the influence of parasitic capacitance on the performance of the semiconductor device. Furthermore, since the isolation layer is formed in the substrate, no precise control is required, and the process is simple. Attached Figure Description

[0034] Figure 1 This is a top view schematic diagram of an existing device with a T-shaped gate structure;

[0035] Figure 2a This is a schematic diagram of the semiconductor device according to Embodiment 1 of the present invention;

[0036] Figure 2b yes Figure 2a The diagram shows a cross-sectional view of the semiconductor device along the BB' direction;

[0037] Figure 3 This is a schematic diagram of the semiconductor device according to Embodiment 2 of the present invention;

[0038] Figure 4 This is a schematic diagram of the semiconductor device according to Embodiment 3 of the present invention;

[0039] Figure 5 This is a schematic diagram of the semiconductor device according to Embodiment 4 of the present invention;

[0040] Figure 6 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0041] Among them, the appendix Figures 1-6 The annotations in the attached figures are explained as follows:

[0042] 11-Gate layer; 12-Source region; 13-Drain region; 14-Body contact region; 20-Substrate; 201-Gate dielectric layer; 211-Main gate; 212-Extended gate; 212a-First part; 212b-Second part; 22-Source region; 23-Drain region; 24-Body contact region; 25-Sidewall; 26-Isolation layer; 27-Conductive plug; 28-Shallow trench isolation structure. Detailed Implementation

[0043] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0044] An embodiment of the present invention provides a semiconductor device, the semiconductor device comprising: a substrate including an active region; an isolation layer formed in the substrate of the active region; and a gate layer formed on the substrate of the active region, the gate layer including a main gate and an extended gate, the main gate being disconnected from the extended gate, and the projections of the main gate and the extended gate on the substrate being connected through the isolation layer.

[0045] See below. Figures 2a to 5 The semiconductor device provided in this embodiment is described in detail, wherein, Figure 2a , Figure 3 , Figure 4 and Figure 5 This is a top view of a semiconductor device.

[0046] The substrate 20 can be a single-layer structure or a multilayer structure composed of the same or different materials. The material of the substrate 20 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, or it can include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator. This application does not limit this.

[0047] The substrate 20 includes an active region.

[0048] The semiconductor device further includes a shallow trench isolation structure 28 formed in the substrate 20, the shallow trench isolation structure 28 being used to define the active region.

[0049] The isolation layer 26 is formed in the substrate 20 of the active region.

[0050] Preferably, the isolation layer 26 and the shallow trench isolation structure 28 are formed from the same material using the same process. That is, when the shallow trench isolation structure 28 is formed in the substrate 20, the isolation layer 26 is also formed in the substrate 20 surrounding the shallow trench isolation structure 28, thereby simplifying the process and reducing costs. In other embodiments, the isolation layer 26 and the shallow trench isolation structure 28 may also be formed using different processes.

[0051] The isolation layer 26 and the shallow trench isolation structure 28 can be made of at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, etc.

[0052] Preferably, the top surfaces of the shallow trench isolation structure 28 and the isolation layer 26 are not lower than the top surface of the substrate 20. In other embodiments, the top surfaces of the shallow trench isolation structure 28 and the isolation layer 26 may be slightly lower than the top surface of the substrate 20.

[0053] The gate layer is formed on the substrate 20 of the active region. The gate layer includes a main gate 211 and an extended gate 212. The main gate 211 and the extended gate 212 are disconnected, that is, there is a gap between the main gate 211 and the extended gate 212, and electrical connection cannot be achieved.

[0054] A gate dielectric layer 201 is formed between the gate layer and the substrate 20, and the gate layer, the gate dielectric layer 201 and the substrate 20 constitute the structure of a capacitor.

[0055] The gate dielectric layer 201 can be made of silicon oxide (relative permittivity of 4.1) or other dielectric materials. Using a low permittivity material for the gate dielectric layer 201 can reduce capacitance.

[0056] Sidewalls 25 are also formed on the sidewalls of the main grid 211 and the extension grid 212.

[0057] The projections of the main gate 211 and the extended gate 212 onto the substrate 20 are connected by the isolation layer 26.

[0058] In one embodiment, the projections of the main gate 211 and the extended gate 212 onto the substrate 20 can contact the isolation layer 26, meaning the boundaries of the projections of the main gate 211 and the extended gate 212 onto the substrate 20 contact the boundary of the isolation layer 26. In another embodiment, the projections of the main gate 211 and the extended gate 212 onto the substrate 20 can extend onto the isolation layer 26. This eliminates the need for precise alignment of the boundary of the isolation layer 26 when forming the main gate 211 and the extended gate 212, resulting in better process control.

[0059] Since the projections of the main gate 211 and the extended gate 212 onto the substrate 20 are connected through the isolation layer 26, when ion implantation is subsequently performed into the active region to form the source region 22, the drain region 23, and the body contact region 24, the main gate 211, the extended gate 212, and the isolation layer 26 are connected together to act as a barrier, preventing the source region 22 from connecting with the drain region 23 and causing a short circuit, or preventing the source region 22 and the drain region 23 from connecting with the body contact region 24 and causing a short circuit.

[0060] The semiconductor device further includes:

[0061] Source region 22 and drain region 23 are respectively formed in the active regions on both sides of the main gate 211, or respectively formed in the active regions on both sides of the main gate 211 and the isolation layer 26; the region below the main gate 211 located between the source region 22 and the drain region 23 is the channel region;

[0062] The body contact area 24 is formed in the active region of the extended gate 212 and the isolation layer 26 on the side away from the main gate 211.

[0063] The body contact region 24 is used to bring out the substrate 20 (i.e., the body region) located below the channel region. The shallow trench isolation structure 28 surrounds the source region 22, the drain region 23, and the body contact region 24.

[0064] In one embodiment, the source region 22 and the drain region 23 may extend into the substrate 20 below the sidewall 25, and the body contact region 24 may extend into the substrate 20 below the sidewall 25.

[0065] The source region 22 and the drain region 23 have the same doping type, and the body contact region 24 has a different or the same doping type as the source region 22. If the body contact region 24 and the source region 22 have different doping types, the formed semiconductor device is an enhancement-mode field-effect transistor; if the body contact region 24 and the source region 22 have the same doping type, the formed semiconductor device is a depletion-mode field-effect transistor.

[0066] When the doping type of the body contact region 24 is different from that of the source region 22, if the doping type of the source region 22 and the drain region 23 is N-type, then the doping type of the body contact region 24 is P-type; if the doping type of the source region 22 and the drain region 23 is P-type, then the doping type of the body contact region 24 is N-type. When the doping type of the body contact region 24 is the same as that of the source region 22, then the doping type of the source region 22, the drain region 23, and the body contact region 24 are all either N-type or P-type. N-type ions can include phosphorus, arsenic, etc., and P-type ions can include boron, gallium, etc.

[0067] like Figure 2a , Figure 3 and Figure 4 As shown, the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 onto the substrate 20 to form a T-shape, with the main gate 211 located at the "|" portion of the T-shape and the extended gate 212 located at the "―" portion of the T-shape; or, as... Figure 5 As shown, the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 on the substrate 20 to form an H-shape. The main gate 211 is located at the "―" part of the H-shape, and the extended gate 212 is located at the "|" part of the H-shape.

[0068] The main gate 211 is disconnected from the extended gate 212. The projections of the main gate 211 and the extended gate 212 on the substrate 20 can be connected by the isolation layer 26. The specific structure of the isolation layer 26 connecting the projections of the main gate 211 and the extended gate 212 on the substrate 20 is not limited to this. For example, the shape and size of the isolation layer 26, the main gate 211, and the extended gate 212 can be adjusted according to the actual process.

[0069] In one embodiment, such as Figure 2a , Figure 3 and Figure 5 As shown, the extended gate 212 may include a disconnected first portion 212a and a second portion 212b, the projections of the first portion 212a and the second portion 212b onto the substrate 20 being connected through the isolation layer 26. The projection of the main gate 211 onto the substrate 20 may extend from the active region on one side of the isolation layer 26 at least onto the isolation layer 26. Wherein, as... Figure 2a and Figure 5 As shown, the projection of the main gate 211 onto the substrate 20 can extend from the active region on one side of the isolation layer 26 only to the isolation layer 26. The source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211 and the isolation layer 26. The body contact region 24 is formed in the active region on the side of the extended gate 212 and the isolation layer 26 away from the main gate 211; or, as Figure 3 As shown, the projection of the main gate 211 onto the substrate 20 can extend from the active region on one side of the isolation layer 26 through the isolation layer 26 to the active region on the other side of the isolation layer 26. The source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211. The body contact region 24 is formed in the active region on the side of the extended gate 212 and the isolation layer 26 away from the source region 22 and the drain region 23, making the process more controllable.

[0070] It should be noted that the relationship between the gate length L2 of the extended gate 212 in the direction from the source region 22 to the body contact region 24 and the length of the isolation layer 26 in the direction from the source region 22 to the body contact region 24 is not limited.

[0071] Alternatively, in another embodiment, such as Figure 4 As shown, the extended gate 212 is an integral unit, the source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211 and the isolation layer 26, and the body contact region 24 is formed in the active region on the side of the extended gate 212 away from the main gate 211.

[0072] In one embodiment, both ends of the extended gate 212 extend from the active region to the shallow trench isolation structure 28. When the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 on the substrate 20 to form a T-shape, in one embodiment, the end of the main gate 211 away from the body contact region 24 may extend from the active region to the shallow trench isolation structure 28.

[0073] The semiconductor device further includes an interlayer dielectric layer (not shown) that covers the main gate 211 and the extended gate 212. The interlayer dielectric layer and the sidewall 25 fill the gap between the main gate 211 and the extended gate 212, meaning that the main gate 211 and the extended gate 212 are insulated from each other by the interlayer dielectric layer and the sidewall 25.

[0074] The materials of the interlayer dielectric layer and the sidewall 25 include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] The semiconductor device further includes a conductive plug 27 formed on the main gate 211, the source region 22, the drain region 23, and the body contact region 24. The conductive plug 27 is not formed on the extended gate 212, so that voltage can be applied to the main gate 211, the source region 22, the drain region 23, and the body contact region 24 through the conductive plug 27, but voltage cannot be applied to the extended gate 212.

[0076] When the isolation layer 26 connects the projection of the main gate 211 and the extended gate 212 on the substrate 20 to form a T-shape, preferably, the conductive plug 27 is formed on the main gate 211 on the shallow trench isolation structure 28, so as to ensure the reliability and performance stability of the semiconductor device.

[0077] To prevent the formation range of the source region 22, the drain region 23, and the body contact region 24 from being affected, the design of the ion implantation range for forming the source region 22, the drain region 23, and the body contact region 24 needs to consider the influence of fluctuations in the critical dimensions of the fabrication process of the extended gate 212, the body contact region 24, the source region 22, and the drain region 23, as well as the alignment accuracy of the mask used. Therefore, the ion implantation range for forming the source region 22, the drain region 23, and the body contact region 24 needs to extend from the substrate 20 to the extended gate 212 (e.g., Figure 2a , Figures 3-5 At the junction BB' of ion implantation regions B1 and B2, the length of the extended gate 212 required in the direction from the source region 22 to the bulk contact region 24 is (e.g., at the junction BB' of ion implantation regions B1 and B2). Figure 2a , Figures 3-5 The extended gate 212 in the semiconductor device has a gate length L2 in the direction from the source region 22 to the body contact region 24 that is sufficiently long (e.g., not less than 0.3 micrometers); however, if the length of the extended gate 212 is too long, it will result in an excessively large parasitic capacitance between the extended gate 212, the gate dielectric layer 201 and the substrate 20, thereby reducing the performance of the semiconductor device.

[0078] Therefore, in the semiconductor device of the present invention, the gate layer is designed such that the main gate 211 and the extended gate 212 are disconnected, that is, the main gate 211 and the extended gate 212 are insulated from each other, so that a voltage can be applied to the main gate 211 without applying a voltage to the extended gate 212; and, since the projections of the main gate 211 and the extended gate 212 on the substrate 20 are connected through the isolation layer 26, it is possible to prevent the source region 22 and the drain region 23 from connecting and causing a short circuit, or to prevent the source region 22 and the drain region 23 from connecting and causing a short circuit with the body contact region 24, respectively, when the source region 22, the drain region 23 and the body contact region 24 are formed by ion implantation. An isolation layer 26 is formed in the substrate 20. The size of the isolation layer 26 does not need to be controlled within a small range. When etching the gate material layer to form the main gate 211 and the extended gate 212, since the main gate 211 and the extended gate 212 are already isolated by the isolation layer 26, the gap between the main gate 211 and the extended gate 212 does not need to be precisely controlled, simplifying the process. This ensures that the formation range of the source region 22, the drain region 23, and the body contact region 24 is not affected. While meeting the device performance requirements, the parasitic capacitance formed by the extended gate 212, the gate dielectric layer 201, and the substrate 20 can be completely eliminated. This allows the parasitic capacitance to be eliminated while maintaining the original function of the gate layer, thereby improving the performance of the semiconductor device, especially for devices sensitive to gate capacitance (e.g., low-noise amplifiers).

[0079] In summary, the semiconductor device provided by this invention includes: a substrate, the substrate including an active region; an isolation layer formed in the substrate of the active region; and a gate layer formed on the substrate of the active region, the gate layer including a main gate and an extended gate, the main gate being disconnected from the extended gate, and the projections of the main gate and the extended gate on the substrate being connected through the isolation layer. The semiconductor device of this invention can maintain the original function of the gate layer while eliminating the influence of parasitic capacitance on the performance of the semiconductor device. Furthermore, since the isolation layer is formed in the substrate, precise control is not required, simplifying the process.

[0080] One embodiment of the present invention provides a method for manufacturing a semiconductor device, see reference. Figure 6 , Figure 6This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method comprising:

[0081] Step S1: Provide a substrate, the substrate including an active region;

[0082] Step S2: Form an isolation layer in the substrate of the active region;

[0083] Step S3: Form a gate layer on the substrate of the active region. The gate layer includes a main gate and an extended gate. The main gate is disconnected from the extended gate. The projections of the main gate and the extended gate on the substrate are connected through the isolation layer.

[0084] See below. Figure 2a , Figure 3 , Figure 4 and Figure 5 The method for manufacturing the semiconductor device provided in this embodiment will be described in more detail, wherein, Figure 2a , Figure 3 , Figure 4 and Figure 5 This is a top view of a semiconductor device.

[0085] According to step S1, a substrate 20 is provided, the substrate 20 including an active region.

[0086] The substrate 20 can be a single-layer structure or a multilayer structure composed of the same or different materials. The material of the substrate 20 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, or it can include layered substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator. This application does not limit this.

[0087] Before subsequently forming a gate layer on the substrate 20 of the active region, the method of manufacturing the semiconductor device further includes forming a shallow trench isolation structure 28 in the substrate 20, the shallow trench isolation structure 28 being used to define the active region.

[0088] According to step S2, an isolation layer 26 is formed in the substrate 20 of the active region.

[0089] Preferably, the isolation layer 26 and the shallow trench isolation structure 28 are formed from the same material using the same process. That is, when the shallow trench isolation structure 28 is formed in the substrate 20, the isolation layer 26 is also formed in the substrate 20 surrounding the shallow trench isolation structure 28, thereby simplifying the process and reducing costs. In other embodiments, the isolation layer 26 and the shallow trench isolation structure 28 may also be formed using different processes.

[0090] The isolation layer 26 and the shallow trench isolation structure 28 can be made of at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, etc.

[0091] Preferably, the top surfaces of the shallow trench isolation structure 28 and the isolation layer 26 are not lower than the top surface of the substrate 20. In other embodiments, the top surfaces of the shallow trench isolation structure 28 and the isolation layer 26 may be slightly lower than the top surface of the substrate 20.

[0092] According to step S3, a gate layer is formed on the substrate 20 of the active region. The gate layer includes a main gate 211 and an extended gate 212. The main gate 211 is disconnected from the extended gate 212. The projections of the main gate 211 and the extended gate 212 on the substrate 20 are connected through the isolation layer 26.

[0093] There is a gap between the main gate 211 and the extended gate 212, so an electrical connection cannot be achieved.

[0094] A gate material layer can be deposited first to cover the substrate 20, the shallow trench isolation structure 28 and the isolation layer 26, and then an etching process can be performed on the gate material layer to form the gate layer with the required pattern. That is, the gate material layer needs to be etched to break it to form the main gate 211 and the extended gate 212.

[0095] Before forming the gate layer on the substrate 20, a gate dielectric layer 201 can be formed on the active region of the substrate 20. The gate dielectric layer 201 is formed between the gate layer and the substrate 20. The gate layer, the gate dielectric layer 201 and the substrate 20 constitute the structure of a capacitor.

[0096] The gate dielectric layer 201 can be made of silicon oxide (relative permittivity of 4.1) or other dielectric materials. Using a low permittivity material for the gate dielectric layer 201 can reduce capacitance.

[0097] The projections of the main gate 211 and the extended gate 212 onto the substrate 20 can contact the isolation layer 26, that is, the projection boundaries of the main gate 211 and the extended gate 212 onto the substrate 20 contact the boundary of the isolation layer 26; in another embodiment, the projections of the main gate 211 and the extended gate 212 onto the substrate 20 can extend onto the isolation layer 26, so that when forming the main gate 211 and the extended gate 212, it is not necessary to precisely align the boundary of the isolation layer 26, and the process is better controlled.

[0098] Since the projections of the main gate 211 and the extended gate 212 onto the substrate 20 are connected through the isolation layer 26, when ion implantation is subsequently performed into the active region to form the source region 22, the drain region 23, and the body contact region 24, the main gate 211, the extended gate 212, and the isolation layer 26 are connected together to act as a barrier, preventing the source region 22 from connecting with the drain region 23 and causing a short circuit, or preventing the source region 22 and the drain region 23 from connecting with the body contact region 24 and causing a short circuit.

[0099] The method of manufacturing the semiconductor device further includes forming sidewalls 25 on the sidewalls of the main gate 211 and the extended gate 212.

[0100] After forming the sidewall 25, the method for manufacturing the semiconductor device further includes:

[0101] Source region 22 and drain region 23 are formed in the active regions on both sides of the main gate 211, or source region 22 and drain region 23 are formed in the active regions on both sides of the main gate 211 and the isolation layer 26; and a body contact region 24 is formed in the active regions of the extended gate 212 and the isolation layer 26 on the side away from the main gate 211.

[0102] The region located below the main gate 211 between the source region 22 and the drain region 23 is the channel region; the body contact region 24 is used to bring out the substrate 20 (i.e., the body region) located below the channel region. The shallow trench isolation structure 28 surrounds the source region 22, the drain region 23 and the body contact region 24.

[0103] In one embodiment, the source region 22 and the drain region 23 may extend into the substrate 20 below the sidewall 25, and the body contact region 24 may extend into the substrate 20 below the sidewall 25.

[0104] The source region 22 and the drain region 23 have the same doping type, and the body contact region 24 has a different or the same doping type as the source region 22. If the body contact region 24 and the source region 22 have different doping types, the formed semiconductor device is an enhancement-mode field-effect transistor; if the body contact region 24 and the source region 22 have the same doping type, the formed semiconductor device is a depletion-mode field-effect transistor.

[0105] When the doping type of the body contact region 24 is different from that of the source region 22, if the doping type of the source region 22 and the drain region 23 is N-type, then the doping type of the body contact region 24 is P-type; if the doping type of the source region 22 and the drain region 23 is P-type, then the doping type of the body contact region 24 is N-type. When the doping type of the body contact region 24 is the same as that of the source region 22, then the doping type of the source region 22, the drain region 23, and the body contact region 24 are all either N-type or P-type. N-type ions can include phosphorus, arsenic, etc., and P-type ions can include boron, gallium, etc.

[0106] like Figure 2a , Figure 3 and Figure 4 As shown, the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 onto the substrate 20 to form a T-shape, with the main gate 211 located at the "|" portion of the T-shape and the extended gate 212 located at the "―" portion of the T-shape; or, as... Figure 5 As shown, the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 on the substrate 20 to form an H-shape. The main gate 211 is located at the "―" part of the H-shape, and the extended gate 212 is located at the "|" part of the H-shape.

[0107] The main gate 211 is disconnected from the extended gate 212. The projections of the main gate 211 and the extended gate 212 on the substrate 20 can be connected by the isolation layer 26. The specific structure of the isolation layer 26 connecting the projections of the main gate 211 and the extended gate 212 on the substrate 20 is not limited to this. For example, the shape and size of the isolation layer 26, the main gate 211, and the extended gate 212 can be adjusted according to the actual process.

[0108] In one embodiment, such as Figure 2a , Figure 3 and Figure 5 As shown, the extended gate 212 may include a disconnected first portion 212a and a second portion 212b, the projections of the first portion 212a and the second portion 212b onto the substrate 20 being connected through the isolation layer 26. The projection of the main gate 211 onto the substrate 20 may extend from the active region on one side of the isolation layer 26 at least onto the isolation layer 26. Wherein, as... Figure 2a and Figure 5As shown, the projection of the main gate 211 onto the substrate 20 can extend from the active region on one side of the isolation layer 26 only to the isolation layer 26. The source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211 and the isolation layer 26. The body contact region 24 is formed in the active region on the side of the extended gate 212 and the isolation layer 26 away from the main gate 211; or, as Figure 3 As shown, the projection of the main gate 211 onto the substrate 20 can extend from the active region on one side of the isolation layer 26 through the isolation layer 26 to the active region on the other side of the isolation layer 26. The source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211. The body contact region 24 is formed in the active region on the side of the extended gate 212 and the isolation layer 26 away from the source region 22 and the drain region 23, making the process more controllable.

[0109] It should be noted that the relationship between the gate length L2 of the extended gate 212 in the direction from the source region 22 to the body contact region 24 and the length of the isolation layer 26 in the direction from the source region 22 to the body contact region 24 is not limited.

[0110] Alternatively, in another embodiment, such as Figure 4 As shown, the extended gate 212 is an integral unit, the source region 22 and the drain region 23 are respectively formed in the active regions on both sides of the main gate 211 and the isolation layer 26, and the body contact region 24 is formed in the active region on the side of the extended gate 212 away from the main gate 211.

[0111] In one embodiment, both ends of the extended gate 212 extend from the active region to the shallow trench isolation structure 28. When the isolation layer 26 connects the projections of the main gate 211 and the extended gate 212 on the substrate 20 to form a T-shape, in one embodiment, the end of the main gate 211 away from the body contact region 24 may extend from the active region to the shallow trench isolation structure 28.

[0112] After forming the source region 22, the drain region 23, and the body contact region 24, the method of manufacturing the semiconductor device further includes: forming an interlayer dielectric layer (not shown) on the isolation layer 26, the interlayer dielectric layer covering the main gate 211 and the extended gate 212. The interlayer dielectric layer and the sidewall 25 fill the gap between the main gate 211 and the extended gate 212, i.e., the main gate 211 and the extended gate 212 are insulated from each other by the interlayer dielectric layer and the sidewall 25.

[0113] The materials of the interlayer dielectric layer and the sidewall 25 include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0114] The method of manufacturing the semiconductor device further includes: forming conductive plugs 27 on the main gate 211, the source region 22, the drain region 23 and the body contact region 24, wherein the conductive plugs 27 are not formed on the extended gate 212, so that voltage can be applied to the main gate 211, the source region 22, the drain region 23 and the body contact region 24 through the conductive plugs 27, but voltage cannot be applied to the extended gate 212.

[0115] When the isolation layer 26 connects the projection of the main gate 211 and the extended gate 212 on the substrate 20 to form a T-shape, preferably, the conductive plug 27 is formed on the main gate 211 on the shallow trench isolation structure 28, so as to ensure the reliability and performance stability of the semiconductor device.

[0116] To prevent the formation range of the source region 22, the drain region 23, and the body contact region 24 from being affected, the design of the ion implantation range for forming the source region 22, the drain region 23, and the body contact region 24 needs to consider the influence of fluctuations in the critical dimensions of the fabrication process of the extended gate 212, the body contact region 24, the source region 22, and the drain region 23, as well as the alignment accuracy of the mask used. Therefore, the ion implantation range for forming the source region 22, the drain region 23, and the body contact region 24 needs to extend from the substrate 20 to the extended gate 212 (e.g., Figure 2a , Figures 3-5 At the junction BB' of ion implantation regions B1 and B2, the length of the extended gate 212 required in the direction from the source region 22 to the bulk contact region 24 is (e.g., at the junction BB' of ion implantation regions B1 and B2). Figure 2a , Figures 3-5 The extended gate 212 in the semiconductor device has a gate length L2 in the direction from the source region 22 to the body contact region 24 that is sufficiently long (e.g., not less than 0.3 micrometers); however, if the length of the extended gate 212 is too long, it will result in an excessively large parasitic capacitance between the extended gate 212, the gate dielectric layer 201 and the substrate 20, thereby reducing the performance of the semiconductor device.

[0117] Therefore, in the semiconductor device manufacturing method of the present invention, the gate layer is designed such that the main gate 211 and the extended gate 212 are disconnected, that is, the main gate 211 and the extended gate 212 are insulated from each other, so that a voltage can be applied to the main gate 211 without applying a voltage to the extended gate 212; and, since the projections of the main gate 211 and the extended gate 212 on the substrate 20 are connected through the isolation layer 26, when the source region 22, the drain region 23 and the body contact region 24 are formed by ion implantation, it is possible to prevent the source region 22 and the drain region 23 from connecting and causing a short circuit, or to prevent the source region 22 and the drain region 23 from connecting with the body contact region 24 respectively and causing a short circuit. An isolation layer 26 is formed in the substrate 20. The size of the isolation layer 26 does not need to be controlled within a small range. When etching the gate material layer to form the main gate 211 and the extended gate 212, since the main gate 211 and the extended gate 212 are already isolated by the isolation layer 26, the gap between the main gate 211 and the extended gate 212 does not need to be precisely controlled, simplifying the process. This ensures that the formation range of the source region 22, the drain region 23, and the body contact region 24 is not affected. While meeting the device performance requirements, the parasitic capacitance formed by the extended gate 212, the gate dielectric layer 201, and the substrate 20 can be completely eliminated. This allows the parasitic capacitance to be eliminated while maintaining the original function of the gate layer, thereby improving the performance of the semiconductor device, especially for devices sensitive to gate capacitance (e.g., low-noise amplifiers).

[0118] In summary, a method for manufacturing a semiconductor device includes: providing a substrate, the substrate including an active region; forming an isolation layer in the substrate of the active region; and forming a gate layer on the substrate of the active region, the gate layer including a main gate and an extended gate, the main gate being disconnected from the extended gate, and the projections of the main gate and the extended gate on the substrate being connected through the isolation layer. The method for manufacturing a semiconductor device of the present invention can eliminate the influence of parasitic capacitance on the performance of the semiconductor device while maintaining the original function of the gate layer, and since the isolation layer is formed in the substrate, no precise control is required, and the process is simple.

[0119] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate, the substrate including an active region; An isolation layer is embedded in the substrate of the active region; A gate layer is formed on the substrate of the active region. The gate layer includes a main gate and an extended gate. The main gate is disconnected from the extended gate. The projections of the main gate and the extended gate on the substrate are connected through the isolation layer. Sidewalls are formed on the sidewalls of the main grid and the extended grid; An interlayer dielectric layer is formed on the isolation layer, the interlayer dielectric layer covers the main gate and the extended gate, and the interlayer dielectric layer and the sidewall fill the gap between the main gate and the extended gate.

2. The semiconductor device as claimed in claim 1, characterized in that, The isolation layer connects the projections of the main gate and the extended gate on the substrate to form a T-shape, with the main gate located at the "|" position of the T-shape and the extended gate located at the "―" position of the T-shape; or, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form an H-shape, with the main gate located at the "―" position of the H-shape and the extended gate located at the "|" position of the H-shape.

3. The semiconductor device as described in claim 1, characterized in that, The projections of the main gate and the extended gate on the substrate extend onto the isolation layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure being used to define the active region; the isolation layer and the shallow trench isolation structure are formed of the same material using the same process.

5. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: The source region and drain region are formed in the active regions on both sides of the main gate, or in the active regions on both sides of the main gate and the isolation layer, respectively; The body contact region is formed in the active region on the side of the extended gate and the isolation layer away from the main gate.

6. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes: Conductive plugs are formed on the main gate, the source region, the drain region, and the body contact region.

7. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including an active region; An isolation layer is formed within the substrate of the active region; A gate layer is formed on the substrate of the active region. The gate layer includes a main gate and an extended gate. The main gate is disconnected from the extended gate. The projections of the main gate and the extended gate on the substrate are connected through the isolation layer. Sidewalls are formed on the sidewalls of the main grid and the extended grid; An interlayer dielectric layer is formed on the isolation layer, the interlayer dielectric layer covers the main gate and the extended gate, and the interlayer dielectric layer and the sidewall fill the gap between the main gate and the extended gate.

8. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The isolation layer connects the projections of the main gate and the extended gate on the substrate to form a T-shape, with the main gate located at the "|" position of the T-shape and the extended gate located at the "―" position of the T-shape; or, the isolation layer connects the projections of the main gate and the extended gate on the substrate to form an H-shape, with the main gate located at the "―" position of the H-shape and the extended gate located at the "|" position of the H-shape.

9. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The projections of the main gate and the extended gate on the substrate extend onto the isolation layer.

10. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, Before forming a gate layer on the substrate of the active region, the method for manufacturing the semiconductor device further includes: Simultaneously, a shallow trench isolation structure and the isolation layer are formed in the substrate, the shallow trench isolation structure being used to define the active region.

11. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The method for manufacturing the semiconductor device further includes: Source and drain regions are formed in the active regions on both sides of the main gate, or source and drain regions are formed in the active regions on both sides of the main gate and the isolation layer; and a body contact region is formed in the active regions on the side of the extended gate and the isolation layer away from the main gate.

12. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, The method for manufacturing the semiconductor device further includes: Conductive plugs are formed on the main gate, the source region, the drain region, and the body contact region.

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