Display device

Abstract

A display device is provided. The display device includes: pixels located on a substrate, each of the pixels including a light-emitting element and at least one transistor, the light-emitting element being electrically connected to the transistor through a first contact hole penetrating an insulating layer; and an initialization power line located on the substrate, the initialization power line being configured to supply initialization power to the pixels. The light-emitting element includes a first electrode electrically connected to the transistor through the first contact hole, a light-emitting layer provided on the first electrode, and a second electrode located on the light-emitting layer. The initialization power line includes a first conductive wire and a second conductive wire intersecting the first conductive wire. The initialization power line is electrically connected to a source electrode or a drain electrode of the transistor through a second contact hole penetrating the insulating layer.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201711471785.0, titled "Display Device", filed with the State Intellectual Property Office on December 29, 2017. Technical Field

[0002] An exemplary embodiment relates to a display device. Background Art

[0003] Generally, a display device includes a plurality of pixels. Each pixel includes a scan line configured to apply a scan signal, a data line configured to apply a data signal, and a power line configured to apply power. An organic light-emitting display device of such a display device may have a structure in which a plurality of power lines are coupled to each pixel.

[0004] In the power line, a current (IR) drop phenomenon due to resistance may occur. If the current drop phenomenon occurs, it may cause a brightness difference between pixels coupled to the same power line.

[0005] In addition, if the power line is open-circuited, power is not applied to pixels disposed outside the open-circuit point with respect to the direction of current flow. Therefore, dark spots may appear in the display device.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background of the inventive concept, and thus, it may include information that does not form the prior art known to those of ordinary skill in the art in the country. Summary of the Invention

[0007] An exemplary embodiment provides a display device having improved display quality.

[0008] Additional aspects will be set forth in the detailed description below, will be apparent in part from the present disclosure, or may be learned by practice of the inventive concept.

[0009] An exemplary embodiment may provide a display device including: pixels located on a substrate, each of the pixels including a light-emitting element and at least one transistor, the light-emitting element being electrically connected to the transistor through a first contact hole passing through an insulating layer; and an initialization power line located on the substrate, the initialization power line being configured to supply initialization power to the pixels. The light-emitting element includes a first electrode electrically connected to the transistor through the first contact hole, a light-emitting layer disposed on the first electrode, and a second electrode located on the light-emitting layer. The initialization power line includes a first conductive wire and a second conductive wire intersecting the first conductive wire. The initialization power line is electrically connected to a source electrode or a drain electrode of the transistor through a second contact hole passing through the insulating layer.

[0010] In an embodiment, the first conductive wire and the second conductive wire may surround at least a portion of the first electrode such that the first conductive wire and the second conductive wire may be spaced apart from the light-emitting element.

[0011] In an embodiment, the first conductive wire and the second conductive wire may intersect at an intersection region, and the second contact hole may be located at one side of the intersection region.

[0012] In an embodiment, the first conductive wire and the second conductive wire may form a plurality of closed loops having a rhombus shape.

[0013] In an embodiment, the plurality of closed loops may include a first closed loop and a second closed loop, the light-emitting element may include a first light-emitting element located in the first closed loop and a second light-emitting element located in the second closed loop, the first closed loop and the second closed loop may have the same size, and the first light-emitting element and the second light-emitting element may have different sizes.

[0014] In an embodiment, the first conductive wire and the second conductive wire may form a plurality of closed loops, the plurality of closed loops may include a first closed loop and a second closed loop, and the size of the first closed loop may be larger than the size of the second closed loop.

[0015] In an embodiment, two light-emitting elements may be disposed in the first closed loop, and one light-emitting element may be disposed in the second closed loop.

[0016] In an embodiment, the first conductive wire and the second conductive wire may form a plurality of closed loops, the light-emitting element may include a first light-emitting element and a second light-emitting element, the second light-emitting element has a size smaller than the size of the first light-emitting element, and the first light-emitting element and the second light-emitting element may be located in each of the plurality of closed loops.

[0017] In an embodiment, the plurality of closed loops may be arranged in a row direction and a column direction, each of the first light-emitting element and the second light-emitting element may be arranged along the row direction and the column direction, and the first light-emitting element and the second light-emitting element may be alternately arranged along a direction different from the row direction and the column direction.

[0018] In an embodiment, the first conductive wire and the second conductive wire may include a first region and a second region coupled to the first region, and the width of the first region may be greater than the width of the second region.

[0019] In an embodiment, the second contact hole may be located in the first region.

[0020] In an embodiment, the first conductive line and the second conductive line may form a plurality of closed loops, the light-emitting elements may include a first light-emitting element and a second light-emitting element, the second light-emitting element may have a size smaller than that of the first light-emitting element, and the first light-emitting element and the second light-emitting element may be located in each of the plurality of closed loops, wherein each of the plurality of closed loops may include a first region and a second region, the first region may surround the edge of the first light-emitting element, the second region may surround the edge of the second light-emitting element, and the second region may be smaller than the first region.

[0021] In an embodiment, the display device may further include: scan lines located on a substrate, the scan lines being electrically coupled to pixels; and data lines located on the substrate, the data lines being electrically coupled to pixels, wherein the first conductive line may extend in a direction inclined with respect to the scan lines and the data lines.

[0022] In an embodiment, the initialization power line may have a grid form.

[0023] In an embodiment, the first conductive line and the second conductive line may bypass the first electrode of the light-emitting element in each of the pixels.

[0024] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, are used to explain the principles of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification.

[0026] Figure 1 is a plan view showing a display device according to an exemplary embodiment.

[0027] Figure 2 is a block diagram showing a pixel and a driving unit according to an exemplary embodiment.

[0028] Figure 3 is a diagram showing Figure 2 an equivalent circuit diagram of an embodiment of the pixel shown in

[0029] Figure 4 is a diagram showing in detail Figure 3 a plan view of the pixel shown in

[0030] Figure 5 is a cross-sectional view taken along line I-I' of Figure 4

[0031] Figure 6 is a cross-sectional view taken along line II-II' of Figure 4 ​​

[0032] Figure 7 is a plan view showing Figures 2 to 6 the active pattern, source electrode, and drain electrode shown in

[0033] Figure 8 is a plan view showing Figures 2 to 6 the scan line, emission control line, and lower electrode of the storage capacitor shown in

[0034] Figure 9 is a plan view showing Figures 2 to 6 the upper electrode of the storage capacitor shown in

[0035] Figure 10 is a plan view showing Figures 2 to 6 the data line, connection line, auxiliary connection line, power line, and bridge pattern shown in

[0036] Figures 11 to 14 is a plan view showing Figures 2 to 6 the initialization power line and the organic light emitting diode shown in DETAILED DESCRIPTION

[0037] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. However, it is apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments.

[0038] In the drawings, for clarity and descriptive purposes, the dimensions and relative dimensions of layers, films, panels, regions, etc. may be exaggerated. Additionally, like reference numerals denote like elements.

[0039] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. For purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as by way of example XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Although terms such as first, second, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or section from another. Thus, a first element, component, region, layer, and / or section discussed below may be termed a second element, component, region, layer, and / or section without departing from the teachings of the present disclosure.

[0041] For descriptive purposes, spatial relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "beneath" or "below" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "beneath" can encompass both an orientation of above and below. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatial relative descriptors used herein are to be interpreted accordingly.

[0042] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless otherwise expressly stated in the context, the singular forms "a," "an," and "the" are also intended to include the plural forms. Additionally, when the terms "comprises" and variations thereof are used in this specification, it is stated that there are the stated features, integers, steps, operations, elements, components, and / or groups thereof, but it does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] Various exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of ideal exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the particular regions shown, but will include deviations in shapes due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or gradients in implantation concentration rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation will result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are in fact schematic, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to be limiting.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and not in an idealized or overly formal sense, unless expressly so defined herein.

[0045] Figure 1 is a plan view showing a display device according to an exemplary embodiment.

[0046] Referring to Figure 1 , a display device according to an exemplary embodiment may include: a substrate SUB; pixels PXL disposed on the substrate SUB; a driving unit disposed on the substrate SUB and configured to drive the pixels PXL; and a line unit (not shown) configured to couple the pixels PXL to the driving unit.

[0047] The substrate SUB may include a pixel region PXA and a peripheral region PPA. The pixel region PXA may be a region where pixels PXL for displaying an image are disposed. Each pixel PXL will be described later herein. The peripheral region PPA may be a region where no pixels PXL are disposed and no image is displayed. A part of the driving unit for driving the pixels PXL and the line unit (not shown) for coupling the pixels PXL to the driving unit may be disposed in the peripheral region PPA. The peripheral region PPA may correspond to a bezel to be formed in a final product of the display device. The width of the bezel may be determined based on the width of the peripheral region PPA.

[0048] The pixel region PXA can have various shapes. For example, the pixel region PXA can be set in various forms such as a closed polygon, a circle, an ellipse, or a shape including sides formed by curves, as well as a semi - circle, a semi - ellipse, or a shape including sides formed by straight lines and curves. In the case where the pixel region PXA includes a plurality of regions, each region can be set in various forms such as a closed polygon, a circle, an ellipse, or a shape including sides formed by curves, as well as a semi - circle, a semi - ellipse, or a shape including sides formed by straight lines and curves. The surface areas of the plurality of regions can be the same as or different from each other.

[0049] In the present exemplary embodiment, an example in which the pixel region PXA is set with a single region having a rectangular shape including linear sides will be described.

[0050] The peripheral region PPA can be provided on at least one side of the pixel region PXA. In an exemplary embodiment, the peripheral region PPA can surround the outer periphery of the pixel region PXA. In an exemplary embodiment, the peripheral region PPA can include a horizontal portion extending in the lateral direction of the display device and a vertical portion extending in the longitudinal direction of the display device. The vertical portions of the peripheral region PPA can include a pair of vertical portions separated from each other in the lateral direction of the pixel region PXA.

[0051] Pixels PXL can be provided in the pixel region PXA on the substrate SUB. Each pixel PXL refers to the smallest unit for displaying an image, and a plurality of pixels can be provided. Each pixel PXL can include an organic light - emitting device that emits white light and / or colored light. Each pixel PXL can emit light of any one of red, green, and blue colors, and it is not limited thereto. For example, each pixel PXL can emit light of any one of cyan, magenta, yellow, and white colors.

[0052] The pixels PXL can be arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2. However, the arrangement of the pixels PXL is not limited to a specific arrangement. In other words, the pixels PXL can be arranged in different forms. For example, some of the pixels PXL can be arranged such that the first direction DR1 is the row direction, but the remaining pixels PXL can be arranged such that a direction other than the first direction DR1 (e.g., a direction inclined to the first direction DR1) is the row direction. Alternatively, the pixels PXL can be arranged such that a direction inclined to both the first direction DR1 and the second direction DR2 is the column direction, and a direction intersecting the column direction is the row direction. Here, the column direction can be inclined to the first direction DR1 and the second direction DR2.

[0053] The driving unit can supply signals to each pixel PXL through the line unit, thereby controlling the operation of the pixel PXL. In Figure 1 for explanatory purposes, the line unit is omitted. The line unit will be described subsequently herein.

[0054] The driving unit may include: a scan driver SDV configured to supply a scan signal to each pixel PXL through a scan line; an emission driver EDV configured to supply an emission control signal to the pixel PXL through an emission control line; a data driver DDV configured to supply a data signal to the pixel PXL through a data line; and a timing controller (not shown). The timing controller can control the scan driver SDV, the emission driver EDV, and the data driver DDV.

[0055] The scan driver SDV may be disposed in a vertical portion of the peripheral area PPA. In an embodiment, a pair of vertical portions of the peripheral area PPA may be disposed at positions separated from each other in a lateral direction with respect to the pixel area PXA, and the scan driver SDV may be disposed in at least one of the vertical portions of the peripheral area PPA. The scan driver SDV may extend a predetermined length in a longitudinal direction of the peripheral area PPA.

[0056] In an exemplary embodiment, the scan driver SDV may be directly mounted on the substrate SUB. In the case where the scan driver SDV is directly mounted on the substrate SUB, the scan driver SDV may be formed together with the pixel PXL during the process of forming the pixel PXL. However, the position where the scan driver SDV is disposed or the method of disposing the scan driver SDV is not limited thereto. For example, the scan driver SDV may be disposed on a separate chip and then mounted on the substrate SUB in a chip-on-glass manner. Alternatively, the scan driver SDV may be mounted on a printed circuit board and then coupled to the substrate SUB through a connector.

[0057] The emission driver EDV may also be disposed in a vertical portion of the peripheral area PPA in a manner similar to that of the scan driver SDV. The emission driver EDV may be disposed in at least one of the vertical portions of the peripheral area PPA. The emission driver EDV may extend a predetermined length in a longitudinal direction of the peripheral area PPA.

[0058] In an exemplary embodiment, the emission driver EDV may be directly mounted on the substrate SUB. In the case where the emission driver EDV is directly mounted on the substrate SUB, the emission driver EDV may be formed together with the pixel PXL during the process of forming the pixel PXL. However, the position where the emission driver EDV is provided or the method of providing the emission driver EDV is not limited thereto. For example, the emission driver EDV may be provided on a separate chip and then mounted on the substrate SUB in a chip - on - glass manner. Alternatively, the emission driver EDV may be mounted on a printed circuit board and then coupled to the substrate SUB through a connector.

[0059] In an exemplary embodiment, an example has been shown in which the scan driver SDV and the emission driver EDV are provided adjacent to each other and are formed only on one side of the vertical portion of the peripheral area PPA. However, the present disclosure is not limited thereto. The arrangements of the scan driver SDV and the emission driver EDV can be changed in various ways. For example, the scan driver SDV may be provided in one vertical portion of the peripheral area PPA, and the emission driver EDV may be provided in another vertical portion of the peripheral area PPA. Alternatively, the scan driver SDV may be provided in two vertical portions of the peripheral area PPA, and the emission driver EDV may be provided only in one vertical portion of the peripheral area PPA.

[0060] The data driver DDV may be provided in the peripheral area PPA. The data driver DDV may be provided in the horizontal portion of the peripheral area PPA. The data driver DDV may extend a predetermined length in the lateral direction of the peripheral area PPA.

[0061] In an exemplary embodiment, the positions of the scan driver SDV, the emission driver EDV, and / or the data driver DDV may be changed relative to each other as needed.

[0062] The timing controller (not shown) may be coupled to the scan driver SDV, the emission driver EDV, and the data driver DDV through lines in various ways. The position where the timing controller is provided is not limited to a specific position. For example, the timing controller may be mounted on a printed circuit board and may be coupled to the scan driver SDV, the emission driver EDV, and the data driver DDV through a flexible printed circuit board. The printed circuit board on which the timing controller is mounted may be provided at various positions (e.g., on one side of the substrate SUB or on the back surface of the substrate SUB).

[0063] Figure 2 is a block diagram showing a pixel and a driving unit according to an exemplary embodiment.

[0064] Referring to Figure 2 , a display device according to an exemplary embodiment may include a pixel PXL, a driving unit, and a line unit.

[0065] In an embodiment, a plurality of pixels PXL may be provided. The driving unit may include a scan driver SDV, an emission driver EDV, a data driver DDV, and a timing controller TC. Figure 2 The positions of the scan driver SDV, the emission driver EDV, the data driver DDV, and the timing controller TC shown are for illustrative purposes only, and they may be provided at other positions in an actual display device.

[0066] The line unit may supply signals from the driving unit to each pixel PXL, and may include a scan line, a data line, an emission control line, a power line PL, and an initialization power line. The scan line may include a plurality of scan lines S1 to Sn. The emission control line may include a plurality of emission control lines E1 to En. The data line may include a plurality of data lines D1 to Dm. The data lines D1 to Dm and the power line PL may be coupled to the pixel PXL.

[0067] The pixel PXL may be provided in a pixel region PXA. The pixel PXL may be coupled to the scan lines S1 to Sn, the emission control lines E1 to En, the data lines D1 to Dm, and the power line PL. When a scan signal is supplied from the scan lines S1 to Sn, the pixel PXL may be supplied with a data signal from the data lines D1 to Dm.

[0068] The pixel PXL may be supplied with a first driving power supply ELVDD, a second driving power supply ELVSS, and an initialization power supply Vint. The first driving power supply ELVDD may be applied through the power line PL.

[0069] Each of the pixels PXL may include a driving transistor and an organic light emitting diode (not shown). In response to the data signal, the driving transistor may control the amount of current flowing from the first driving power supply ELVDD through the organic light emitting diode to the second driving power supply ELVSS. Before supplying the data signal to each pixel PXL, the gate electrode of the driving transistor may be initialized by the voltage of the initialization power supply Vint. Accordingly, the voltage of the initialization power supply Vint may be set lower than the voltage of the data signal.

[0070] The scan driver SDV may supply a scan signal to the scan lines S1 to Sn in response to a first gate control signal GCS1 supplied from the timing controller TC. For example, the scan driver SDV may sequentially supply the scan signal to the scan lines S1 to Sn. When the scan signal is sequentially supplied to the scan lines S1 to Sn, the pixels PXL may be sequentially selected on a horizontal line basis.

[0071] The emission driver EDV can supply an emission control signal to emission control lines E1 to En in response to a second gate control signal GCS2 supplied from the timing controller TC. For example, the emission driver EDV can sequentially provide the emission control signal to the emission control lines E1 to En.

[0072] The width of the emission control signal can be set to be larger than the width of the scan signal. For example, the emission control signal can be supplied to the i-th (where i is a natural number) emission control line Ei such that the period of the emission control signal at least partially overlaps with the periods of the scan signal supplied to the (i - 1)-th scan line Si-1 and the scan signal supplied to the i-th scan line Si.

[0073] In addition, the emission control signal can be set to a gate cutoff voltage (e.g., a high voltage) so that the transistors included in the pixel PXL can be cut off. The scan signal can be set to a gate conduction voltage (e.g., a low voltage) so that the transistors included in the pixel PXL can be turned on.

[0074] The data driver DDV can supply data signals to data lines D1 to Dm in response to a data control signal DCS. The data signals supplied to the data lines D1 to Dm can be supplied to the pixels PXL selected by the scan signal.

[0075] The timing controller TC can supply the gate control signals GCS1 and GCS2 to the scan driver SDV and the emission driver EDV. The gate control signals GCS1 and GCS2 are generated based on timing signals supplied from an external device. The timing controller TC can supply the data control signal DCS to the data driver DDV.

[0076] Each of the gate control signals GCS1 and GCS2 can include a start pulse and a clock signal. The start pulse can control the timing of the first scan signal or the first emission control signal. The clock signal can be used to shift the start pulse.

[0077] The data control signal DCS can include a source start pulse and a clock signal. The source start pulse can control the time when data sampling starts. The clock signal can be used to control the sampling operation.

[0078] Figure 3 shows an Figure 2 equivalent circuit diagram of an embodiment of the pixel shown in. In Figure 3 for the sake of description, a pixel PXL coupled to the j-th (where j is a natural number) data line Dj and the i-th scan line Si is shown.

[0079] Referring to Figure 2 and Figure 3, a pixel PXL according to an exemplary embodiment may include an organic light-emitting diode (OLED), a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0080] The OLED may include an anode coupled to the first transistor T1 via the sixth transistor T6 and a cathode coupled to a second driving power supply ELVSS. The OLED may emit light having a predetermined luminance corresponding to the current supplied from the first transistor T1.

[0081] The voltage of the first driving power supply ELVDD may be set to be higher than the voltage of the second driving power supply ELVSS such that current may flow to the OLED.

[0082] The seventh transistor T7 may be coupled between an initialization power supply Vint and the anode of the OLED. The gate electrode of the seventh transistor T7 may be coupled to the (i + 1)-th scan line Si+1. When a scan signal is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 may be turned on such that the voltage of the initialization power supply Vint may be supplied to the anode of the OLED. The voltage of the initialization power supply Vint may be set to be lower than the voltage of the data signal.

[0083] The sixth transistor T6 may be coupled between the first transistor T1 and the anode of the OLED. The gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. When an emission control signal is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and may be turned on otherwise.

[0084] The fifth transistor T5 may be coupled between the first driving power supply ELVDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be coupled to the i-th emission control line Ei. When an emission control signal is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and may be turned on otherwise.

[0085] A first electrode of the first transistor (T1; driving transistor) may be coupled to the first driving power supply ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 may be coupled to the anode of the OLED via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control the current flowing from the first driving power supply ELVDD via the OLED to the second driving power supply ELVSS in response to the voltage of the first node N1. In other words, the first driving power supply ELVDD may be electrically coupled to the anode of the OLED through the first transistor T1.

[0086] The third transistor T3 may be coupled between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the third transistor T3 may be turned on, such that the second electrode of the first transistor T1 may be electrically coupled to the first node N1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0087] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to the (i - 1)-th scan line Si-1. When a scan signal is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 may be turned on, such that the voltage of the initialization power supply Vint may be supplied to the first node N1.

[0088] The second transistor T2 may be coupled between the j-th data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the second transistor T2 may be turned on, such that the first electrode of the first transistor T1 may be electrically coupled to the j-th data line Dj.

[0089] The storage capacitor Cst may be coupled between the first driving power supply ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0090] In an exemplary embodiment, the directions in which the scan lines and the emission control lines extend may be changed. For example, unlike the foregoing exemplary embodiment in which the scan lines and the emission control lines extend in a first direction DR1 that is a lateral direction, the scan lines and the emission control lines may extend in a second direction DR2 that is a longitudinal direction.

[0091] Figure 4 is a plan view showing in detail Figure 3 the pixel shown in Figure 5 is a cross-sectional view taken along Figure 4 line I - I' of Figure 6 is a cross-sectional view taken along Figure 4 line II - II' of

[0092] In Figures 4 to 6 three scan lines Si-1, Si, and Si+1, an emission control line Ei, a power line PL, and a data line Dj coupled to a single pixel PXL are shown based on the pixel PXL disposed at the i-th row and the j-th column in the pixel region PXA. In Figures 4 to 6In this context, for the sake of description, the scan line of the (i - 1)-th row refers to "the (i - 1)-th scan line Si-1", the scan line of the i-th row refers to "the i-th scan line Si", the scan line of the (i + 1)-th row refers to "the (i + 1)-th scan line Si+1", the emission control line of the i-th row refers to "the emission control line Ei", the data line of the j-th column refers to "the data line Dj", and the j-th power line refers to "the power line PL".

[0093] Referring to Figures 2 to 6 , the display device may include a substrate SUB, a line unit, and a pixel PXL.

[0094] The substrate SUB may include a transparent insulating material to allow light transmission. The substrate SUB may be a rigid substrate. For example, the substrate SUB may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0095] The substrate SUB may be a flexible substrate. Here, the substrate SUB may be a film substrate or a plastic substrate including a polymer organic material. For example, the substrate SUB may include at least one of the following compounds: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetyl cellulose, and cellulose acetate propionate. However, the material constituting the substrate SUB may be changed, and the material constituting the substrate SUB may include, for example, fiber-reinforced plastic (FRP).

[0096] The line unit may be disposed on each of the pixels PXL and may include scan lines Si-1, Si, and Si+1, data lines Dj, emission control line Ei, power line PL, and initialization power line IPL.

[0097] The scan lines Si-1, Si, and Si+1 may extend in a first direction DR1. The scan lines Si-1, Si, and Si+1 may include the (i - 1)-th scan line Si-1, the i-th scan line Si, and the (i + 1)-th scan line Si+1 arranged in sequence in a second direction DR2. The scan lines Si-1, Si, and Si+1 may receive scan signals. For example, the (i - 1)-th scan line Si-1 may receive the (i - 1)-th scan signal. The i-th scan line Si may receive the i-th scan signal. The (i + 1)-th scan line Si+1 may receive the (i + 1)-th scan signal.

[0098] The emission control line Ei may extend in the first direction DR1. The emission control line Ei may be disposed between the i-th scan line Si and the (i + 1)-th scan line Si+1 and at a position separated from the i-th scan line Si and the (i + 1)-th scan line Si+1. The emission control line Ei may receive an emission control signal.

[0099] The data line Dj can extend in the second direction DR2. The data line Dj can receive a data signal.

[0100] The power line PL can extend in the second direction DR2. The power line PL can be disposed at a position separated from the data line Dj. A first driving power supply (refer to Figure 2 and Figure 3 ELVDD) can be applied to the power line PL.

[0101] The initialization power supply Vint can be applied to the initialization power line IPL. The initialization power line IPL can bypass the OLED. In other words, the initialization power line IPL can not be stacked with the OLED.

[0102] Each of the pixels PXL can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and an OLED.

[0103] The first transistor T1 can include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, a first drain electrode DE1, and a connection line CNL.

[0104] The first gate electrode GE1 can be coupled to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. The connection line CNL can couple the first gate electrode GE1, the third drain electrode DE3, and the fourth drain electrode DE4 to each other. A first end of the connection line CNL can be coupled to the first gate electrode GE1 through a first contact hole CH1. A second end of the connection line CNL can be coupled to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2.

[0105] In an exemplary embodiment, each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 can be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the first source electrode SE1 and the first drain electrode DE1 can be formed of a semiconductor layer doped with impurities. The first active pattern ACT1 can be formed of an undoped semiconductor layer.

[0106] The first active pattern ACT1 can have a strip shape extending in a predetermined direction and can be bent several times in the longitudinal direction. The first active pattern ACT1 can be stacked with the first gate electrode GE1 in a plan view. Since the first active pattern ACT1 can be relatively long, the channel region of the first transistor T1 can also be relatively long. Therefore, the driving range of the gate voltage to be applied to the first transistor T1 can be increased. Therefore, the gray scale of the light emitted from the OLED can be precisely controlled.

[0107] The first source electrode SE1 may be coupled to a first end of the first active pattern ACT1. The first source electrode SE1 may be coupled to a second drain electrode DE2 of the second transistor T2 and a fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be coupled to a second end of the first active pattern ACT1. The first drain electrode DE1 may be coupled to a third source electrode SE3 of the third transistor T3 and a sixth source electrode SE6 of the sixth transistor T6.

[0108] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0109] The second gate electrode GE2 may be coupled to the i-th scan line Si. The second gate electrode GE2 may be provided as a part of the i-th scan line Si, or may be formed to have a shape protruding from the i-th scan line Si. In an exemplary embodiment, each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities. The second active pattern ACT2 may be formed of an undoped semiconductor layer. The second active pattern ACT2 may correspond to a part of the second transistor T2 that overlaps with the second gate electrode GE2. A first end of the second source electrode SE2 may be coupled to the second active pattern ACT2. A second end of the second source electrode SE2 may be coupled to the data line Dj through a sixth contact hole CH6. A first end of the second drain electrode DE2 may be coupled to the second active pattern ACT2. A second end of the second drain electrode DE2 may be coupled to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0110] The third transistor T3 may have a dual-gate structure to prevent current leakage. In other words, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b. The 3a-th transistor T3a may include a 3a-th gate electrode GE3a, a 3a-th active pattern ACT3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor T3b may include a 3b-th gate electrode GE3b, a 3b-th active pattern ACT3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. Hereinafter, the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b will be referred to as the "third gate electrode GE3". The 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b will be referred to as the "third active pattern ACT3". The 3a-th source electrode SE3a and the 3b-th source electrode SE3b will be referred to as the "third source electrode SE3". The 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b will be referred to as the "third drain electrode DE3".

[0111] The third gate electrode GE3 may be coupled to the i-th scan line Si. The third gate electrode GE3 may be provided as a part of the i-th scan line Si or may be formed in a shape protruding from the i-th scan line Si. For example, the 3a-th gate electrode GE3a may have a shape protruding from the i-th scan line Si. The 3b-th gate electrode GE3b may be provided as a part of the i-th scan line Si.

[0112] Each of the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor layer doped with impurities. The third active pattern ACT3 may be formed of an undoped semiconductor layer. The third active pattern ACT3 may correspond to a part of the third transistor T3 that overlaps with the third gate electrode GE3. The first end of the third source electrode SE3 may be coupled to the third active pattern ACT3. The second end of the third source electrode SE3 may be coupled to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. The first end of the third drain electrode DE3 may be coupled to the third active pattern ACT3. The second end of the third drain electrode DE3 may be coupled to the fourth drain electrode DE4 of the fourth transistor T4. The third drain electrode DE3 may be coupled to the first gate electrode GE1 of the first transistor T1 by a connection line CNL through a second contact hole CH2 and a first contact hole CH1.

[0113] The fourth transistor T4 may have a double-gate structure to prevent current leakage. The fourth transistor T4 may include a 4a-th transistor and a 4b-th transistor. The 4a-th transistor may include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor may include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. Hereinafter, the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b will be referred to as "the fourth gate electrode GE4". The 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b will be referred to as "the fourth active pattern ACT4". The 4a-th source electrode SE4a and the 4b-th source electrode SE4b will be referred to as "the fourth source electrode SE4". The 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b will be referred to as "the fourth drain electrode DE4".

[0114] The fourth gate electrode GE4 can be coupled to the (i - 1)-th scan line Si-1. The fourth gate electrode GE4 can be set as a part of the (i - 1)-th scan line Si-1 or formed to have a shape protruding from the (i - 1)-th scan line Si-1. For example, the 4a-th gate electrode GE4a can be set as a part of the (i - 1)-th scan line Si-1. The 4b-th gate electrode GE4b can be formed to have a shape protruding from the (i - 1)-th scan line Si-1.

[0115] Each of the fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed of a semiconductor layer doped with impurities. The fourth active pattern ACT4 can be formed of an undoped semiconductor layer. The fourth active pattern ACT4 can correspond to a part of the fourth transistor T4 that overlaps with the fourth gate electrode GE4.

[0116] The first end of the fourth source electrode SE4 can be coupled to the fourth active pattern ACT4. The second end of the fourth source electrode SE4 can be coupled to the seventh drain electrode DE7 of the seventh transistor T7 of the pixel PXL disposed on the (i - 1)-th row and the initialization power line IPL. The first end of the fourth drain electrode DE4 can be coupled to the fourth active pattern ACT4. The second end of the fourth drain electrode DE4 can be coupled to the third drain electrode DE3 of the third transistor T3. The fourth drain electrode DE4 can be coupled to the first gate electrode GE1 of the first transistor T1 by a connection line CNL through the second contact hole CH2 and the first contact hole CH1.

[0117] The fifth transistor T5 can include a fifth gate electrode GE5, a fifth active pattern ACT5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0118] The fifth gate electrode GE5 can be coupled to the emission control line Ei. The fifth gate electrode GE5 can be set as a part of the emission control line Ei, or can be formed in a shape protruding from the emission control line Ei. Each of the fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed of a semiconductor layer doped with impurities. The fifth active pattern ACT5 can be formed of an undoped semiconductor layer. The fifth active pattern ACT5 can correspond to a part of the fifth transistor T5 that overlaps with the fifth gate electrode GE5. The first end of the fifth source electrode SE5 can be coupled to the fifth active pattern ACT5. The second end of the fifth source electrode SE5 can be coupled to the power line PL through the fifth contact hole CH5. The first end of the fifth drain electrode DE5 can be coupled to the fifth active pattern ACT5. The second end of the fifth drain electrode DE5 can be coupled to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0119] The sixth transistor T6 can include a sixth gate electrode GE6, a sixth active pattern ACT6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0120] The sixth gate electrode GE6 can be coupled to the emission control line Ei. The sixth gate electrode GE6 can be set as a part of the emission control line Ei, or can be formed in a shape protruding from the emission control line Ei. Each of the sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 can be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed of a semiconductor layer doped with impurities. The sixth active pattern ACT6 can be formed of an undoped semiconductor layer. The sixth active pattern ACT6 can correspond to a part of the sixth transistor T6 that overlaps with the sixth gate electrode GE6. The first end of the sixth source electrode SE6 can be coupled to the sixth active pattern ACT6. The second end of the sixth source electrode SE6 can be coupled to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. The first end of the sixth drain electrode DE6 can be coupled to the sixth active pattern ACT6. The second end of the sixth drain electrode DE6 can be coupled to the seventh source electrode SE7 of the seventh transistor T7.

[0121] The seventh transistor T7 can include a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0122] The seventh gate electrode GE7 may be coupled to the (i + 1)-th scan line Si+1. The seventh gate electrode GE7 may be set as a part of the (i + 1)-th scan line Si+1 or formed to have a shape protruding from the (i + 1)-th scan line Si+1. Each of the seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor layer doped with impurities. The seventh active pattern ACT7 may be formed of an undoped semiconductor layer. The seventh active pattern ACT7 may correspond to a part of the seventh transistor T7 that overlaps with the seventh gate electrode GE7. The first end of the seventh source electrode SE7 may be coupled to the seventh active pattern ACT7. The second end of the seventh source electrode SE7 may be coupled to the sixth drain electrode DE6 of the sixth transistor T6. The first end of the seventh drain electrode DE7 may be coupled to the seventh active pattern ACT7. The second end of the seventh drain electrode DE7 may be coupled to the initialization power line IPL. An auxiliary connection line AUX may be disposed between the second end of the seventh drain electrode DE7 and the initialization power line IPL. The first end of the auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 through a ninth contact hole CH9. The second end of the auxiliary connection line AUX may be coupled to the initialization power line IPL through an eighth contact hole CH8. In other words, the initialization power line IPL may be electrically coupled to the seventh drain electrode DE7 through the eighth contact hole CH8 and the ninth contact hole CH9. Additionally, the second end of the seventh drain electrode DE7 may be coupled to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL disposed on the (i + 1)-th row. Accordingly, both the seventh drain electrode DE7 of the pixel PXL disposed on the (i + 1)-th row and the fourth source electrode SE4 of the fourth transistor T4 may be coupled to the initialization power line IPL by the auxiliary connection line AUX through the eighth contact hole CH8 and the ninth contact hole CH9.

[0123] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be formed of the first gate electrode GE1 of the first transistor T1.

[0124] The upper electrode UE may overlap with the first gate electrode GE1 and may cover the lower electrode LE in a plan view. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area between the upper electrode UE and the lower electrode LE. The upper electrode UE may extend in a first direction DR1. In an exemplary embodiment, a voltage having the same level as the level of the first driving power supply ELVDD may be applied to the upper electrode UE. The upper electrode UE may include an opening OPN in a region having a first contact hole CH1, and the first gate electrode GE1 contacts the connection line CNL through the first contact hole CH1.

[0125] The OLED may include a first electrode AD, a second electrode CD, and a light-emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0126] The first electrode AD may be a pixel electrode disposed in a light-emitting region corresponding to each pixel PXL. The first electrode AD may be coupled to a seventh source electrode SE7 of a seventh transistor T7 and a sixth drain electrode DE6 of a sixth transistor T6 through a seventh contact hole CH7 and a tenth contact hole CH10. A bridging pattern BRP may be disposed between the seventh contact hole CH7 and the tenth contact hole CH10. The first electrode AD may be coupled to the bridging pattern BRP through the tenth contact hole CH10. The bridging pattern BRP may be coupled to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7.

[0127] The first electrode AD may be electrically coupled to a power line PL and thus be applied with a first driving power supply (refer to Figure 2 and Figure 3 ELVDD). The second electrode CD may be coupled to a second driving power supply (refer to Figure 2 and Figure 3 ELVSS).

[0128] In Figure 4 , although the first electrode AD has been shown as covering most of the pixel PXL, the present disclosure is not limited thereto. For example, the first electrode AD may not be stacked with some transistors.

[0129] Hereinafter, the structure of a display device according to an exemplary embodiment will be described in a stacking order with reference to Figures 4 to 6 .

[0130] A semiconductor pattern may be disposed on a substrate SUB. The semiconductor pattern may include first to seventh active patterns ACT1 to ACT7, first to seventh source electrodes SE1 to SE7, and first to seventh drain electrodes DE1 to DE7. The first to seventh active patterns ACT1 to ACT7, the first to seventh source electrodes SE1 to SE7, and the first to seventh drain electrodes DE1 to DE7 may include a semiconductor material.

[0131] A buffer layer (not shown) may be disposed between the substrate SUB and the semiconductor pattern.

[0132] A gate insulating layer GI may be disposed on the substrate SUB on which the active pattern has been formed.

[0133] The (i - 1)-th scan line Si-1, the i-th scan line Si, the (i + 1)-th scan line Si+1, the emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may be the lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be integrally formed with the i-th scan line Si. The fourth gate electrode GE4 may be integrally formed with the (i - 1)-th scan line Si-1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be integrally formed with the emission control line Ei. The seventh gate electrode GE7 may be integrally formed with the (i + 1)-th scan line Si+1.

[0134] The first interlayer insulating layer IL1 may be disposed on the substrate SUB on which the (i - 1)-th scan line Si-1 and the like have been formed.

[0135] The upper electrode UE of the storage capacitor Cst may be disposed on the first interlayer insulating layer IL1. The upper electrode UE may cover the lower electrode LE. The upper electrode UE and the lower electrode LE may form the storage capacitor Cst together, and the first interlayer insulating layer IL1 is disposed between the upper electrode UE and the lower electrode LE.

[0136] The second interlayer insulating layer IL2 may be disposed on the substrate SUB on which the upper electrode UE has been formed.

[0137] The data line Dj, the connection line CNL, the auxiliary connection line AUX, the bridging pattern BRP, and the power line PL may be disposed on the second interlayer insulating layer IL2.

[0138] The data line Dj may be coupled to the second source electrode SE2 through a sixth contact hole CH6 passing through the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the gate insulating layer GI.

[0139] The first end of the connection line CNL may be coupled to the first gate electrode GE1 through a first contact hole CH1 passing through the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The second end of the connection line CNL may be coupled to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0140] The auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 through a ninth contact hole CH9 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0141] The bridging pattern BRP can be a pattern that is configured as a medium for binding the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD to each other between the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD. The bridging pattern BRP can be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 that penetrates through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2. Accordingly, the bridging pattern BRP can be electrically coupled to the first drain electrode DE1 through the sixth transistor T6.

[0142] The power line PL can be coupled to the upper electrode UE of the storage capacitor Cst through a third contact hole CH3 and a fourth contact hole CH4 that penetrate through the second interlayer insulating layer IL2. The power line PL can be coupled to the fifth source electrode SE5 through a fifth contact hole CH5 that penetrates through the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the gate insulating layer GI.

[0143] The protective layer PSV can be disposed on a substrate SUB on which data lines Dj and the like have been formed.

[0144] The OLED and the initialization power line IPL can be disposed on the protective layer PSV. The OLED can include a first electrode AD, a second electrode CD, and a light emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0145] The initialization power line IPL and the first electrode AD can be disposed on the protective layer PSV.

[0146] The initialization power line IPL can be disposed on the protective layer PSV and at a position separated from the first electrode AD. The initialization power line IPL can include a material that is the same as the material of the first electrode AD. For example, the initialization power line IPL can at least include a transparent conductive oxide. In an exemplary embodiment, although an example in which the initialization power line IPL includes a transparent conductive oxide is shown, the present disclosure is not limited thereto. For example, the initialization power line IPL can include a reflective layer and a transparent conductive layer disposed above or below the reflective layer. The initialization power line IPL can be coupled to the auxiliary connection line AUX through an eighth contact hole CH8 that penetrates through the protective layer PSV. Accordingly, the initialization power line IPL can be coupled to the seventh drain electrode DE7 through the auxiliary connection line AUX.

[0147] The first electrode AD can be coupled to the bridging pattern BRP through a tenth contact hole CH10 that penetrates through the protective layer PSV. Since the bridging pattern BRP can be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD can ultimately be electrically coupled to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0148] The pixel defining layer PDL for defining the light emitting region corresponding to each pixel PXL can be disposed on a substrate SUB on which a first electrode AD or the like has been formed. The pixel defining layer PDL can expose the upper surface of the first electrode AD and can protrude from the substrate SUB along the periphery of the pixel PXL.

[0149] The light emitting layer EML can be disposed in the light emitting region surrounded by the pixel defining layer PDL. The second electrode CD can be disposed on the light emitting layer EML. The encapsulation layer SLM covering the second electrode CD can be disposed on the second electrode CD.

[0150] Either the first electrode AD or the second electrode CD can be an anode, and the other can be a cathode. For example, the first electrode AD can be an anode and the second electrode CD can be a cathode.

[0151] In addition, at least one of the first electrode AD and the second electrode CD can be a transmissive electrode. For example, in the case where the OLED is a bottom emission type OLED, the first electrode AD can be a transmissive electrode and the second electrode CD can be a reflective electrode. In the case where the OLED is a top emission type OLED, the first electrode AD can be a reflective electrode and the second electrode CD can be a transmissive electrode. In the case where the OLED is a double-sided emission type OLED, both the first electrode AD and the second electrode CD can be transmissive electrodes. In this embodiment, an example where the OLED is a top emission type OLED and the first electrode AD is an anode is shown.

[0152] The first electrode AD can include a reflective layer (not shown) that emits light and a transparent conductive layer (not shown) disposed above or below the reflective layer. At least one of the transparent conductive layer and the reflective layer can be combined with the seventh source electrode SE7.

[0153] The reflective layer can include a material capable of reflecting light. For example, the reflective layer can include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and their alloys.

[0154] The transparent conductive layer can include a transparent conductive oxide. For example, the transparent conductive layer can include at least one transparent conductive oxide of ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum zinc oxide), GZO (gallium-doped zinc oxide), ZTO (zinc tin oxide), GTO (gallium tin oxide), and FTO (fluorine-doped tin oxide).

[0155] The pixel defining layer PDL may include an organic insulating material. For example, the pixel defining layer PDL may include at least one of polystyrene, PMMA (polymethyl methacrylate), PAN (polyacrylonitrile), PA (polyamide), PI (polyimide), PAE (polyarylether), heterocyclic polymers, parylene, epoxy resins, BCB (benzocyclobutene), siloxane resins, and silane resins.

[0156] The light emitting layer EML may be disposed on the exposed surface of the first electrode AD. The light emitting layer EML may have a multi-layer thin film structure including at least a light generating layer (LGL). For example, the light emitting layer EML may include: a hole injection layer (HIL) for injecting holes; a hole transport layer (HTL) having excellent hole transport performance and suppressing the movement of electrons that have not combined with holes in the light generating layer, thus increasing the recombination chance between holes and electrons; a light generating layer for emitting light through the recombination of injected electrons and holes; a hole blocking layer (HBL) for suppressing the movement of holes that have not combined with electrons in the light generating layer; an electron transport layer (ETL) disposed to smoothly transport electrons to the light generating layer; and an electron injection layer (EIL) for injecting electrons. The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer of the light emitting layer EML may be common layers commonly disposed in adjacent pixels PXL.

[0157] The color of the light generated from the light generating layer may be one of red, green, blue, and white, but is not limited in this embodiment. For example, the color of the light generated from the light generating layer may be one of magenta, cyan, and yellow.

[0158] The second electrode CD may be a semi-transmissive reflective layer. For example, the second electrode CD may be a thin metal layer having a thickness that allows the light emitted from the light emitting layer EML to pass through. The second electrode CD may allow some of the light generated from the light emitting layer EML to pass through it, and may reflect the remaining light generated from the light emitting layer EML.

[0159] The second electrode CD may include a material having a work function lower than that of the transparent conductive layer. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and their alloys.

[0160] Some of the light emitted from the light emitting layer EML may not pass through the second electrode CD, and the light reflected by the second electrode CD may be reflected again by the reflective layer. That is, the light emitted from the light emitting layer EML may resonate between the reflective layer and the second electrode CD. The light extraction efficiency of the OLED can be improved by the resonance of light.

[0161] The distance between the reflective layer and the second electrode CD can be changed according to the color of the light emitted from the light-emitting layer EML. That is, according to the color of the light emitted from the light-emitting layer EML, the distance between the reflective layer and the second electrode CD can be adjusted to correspond to the resonance distance.

[0162] The encapsulation layer SLM can prevent oxygen or water from penetrating into the OLED. The encapsulation layer SLM can include a plurality of inorganic layers (not shown) and a plurality of organic layers (not shown). For example, the encapsulation layer SLM can include a plurality of unit encapsulation layers each including an inorganic layer and an organic layer provided on the inorganic layer. The inorganic layer can be provided in the uppermost portion of the encapsulation layer SLM. The inorganic layer can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0163] Figure 7 It shows Figures 2 to 6 a plan view of the active pattern, source electrode, and drain electrode shown in Figure 8 It shows Figures 2 to 6 a plan view of the scan line, emission control line, and lower electrode of the storage capacitor shown in Figure 9 It shows Figures 2 to 6 a plan view of the upper electrode of the storage capacitor shown in Figure 10 It shows Figures 2 to 6 a plan view of the data line, connection line, auxiliary connection line, power line, and bridging pattern shown in Figures 11 to 14 It shows Figures 2 to 6 a plan view of the initialization power line and the OLED shown in Figures 7 to 14 For the sake of description,

[0164] Referring to Figures 2 to 14 , a semiconductor pattern can be provided on the substrate SUB. The semiconductor pattern can include a first active pattern ACT1 to a seventh active pattern ACT7, a first source electrode SE1 to a seventh source electrode SE7, and a first drain electrode DE1 to a seventh drain electrode DE7. The first active pattern ACT1 to the seventh active pattern ACT7, the first source electrode SE1 to the seventh source electrode SE7, and the first drain electrode DE1 to the seventh drain electrode DE7 can be provided on the same layer and can be formed by the same process. The first active pattern ACT1 to the seventh active pattern ACT7, the first source electrode SE1 to the seventh source electrode SE7, and the first drain electrode DE1 to the seventh drain electrode DE7 can include a semiconductor material.

[0165] The first end of the first active pattern ACT1 can be coupled to the first source electrode SE1, and the second end of the first active pattern ACT1 can be coupled to the first drain electrode DE1. The first end of the second active pattern ACT2 can be coupled to the second source electrode SE2, and the second end of the second active pattern ACT2 can be coupled to the second drain electrode DE2. The first end of the third active pattern ACT3 can be coupled to the third source electrode SE3, and the second end of the third active pattern ACT3 can be coupled to the third drain electrode DE3. The first end of the fourth active pattern ACT4 can be coupled to the fourth source electrode SE4, and the second end of the fourth active pattern ACT4 can be coupled to the fourth drain electrode DE4. The first end of the fifth active pattern ACT5 can be coupled to the fifth source electrode SE5, and the second end of the fifth active pattern ACT5 can be coupled to the fifth drain electrode DE5. The first end of the sixth active pattern ACT6 can be coupled to the sixth source electrode SE6, and the second end of the sixth active pattern ACT6 can be coupled to the sixth drain electrode DE6. The first end of the seventh active pattern ACT7 can be coupled to the seventh source electrode SE7, and the second end of the seventh active pattern ACT7 can be coupled to the seventh drain electrode DE7.

[0166] The scan lines Si-1, Si, Si+1, and Si+2, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst can be disposed on the gate insulating layer GI disposed on the semiconductor pattern. The scan lines Si-1, Si, Si+1, and Si+2, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst can be disposed on the same layer and can be formed by the same process.

[0167] The scan lines Si-1, Si, Si+1, and Si+2 can include the (i-1)-th scan line Si-1, the i-th scan line Si, the (i+1)-th scan line Si+1, and the (i+2)-th scan line Si+2.

[0168] In the i-th pixel row, the first gate electrode GE1 can be disposed on the lower electrode LE. The fourth gate electrode GE4 can be disposed on the (i-1)-th scan line Si-1. The second gate electrode GE2 and the third gate electrode GE3 can be disposed on the i-th scan line Si. The seventh gate electrode GE7 can be disposed on the (i+1)-th scan line Si+1. The fifth gate electrode GE5 and the sixth gate electrode GE6 can be disposed on the emission control line Ei.

[0169] In the (i+1)-th pixel row, the first gate electrode GE1 can be disposed on the lower electrode LE. The fourth gate electrode GE4 can be disposed on the i-th scan line Si. The second gate electrode GE2 and the third gate electrode GE3 can be disposed on the (i+1)-th scan line Si+1. The seventh gate electrode GE7 can be disposed on the (i+2)-th scan line Si+2. The fifth gate electrode GE5 and the sixth gate electrode GE6 can be disposed on the emission control line Ei+1.

[0170] The upper electrode UE of the storage capacitor Cst may be disposed on the first interlayer insulating layer IL1, and the first interlayer insulating layer IL1 is disposed on the scan lines Si-1, Si, Si+1 and Si+2, the emission control lines Ei and Ei+1, and the lower electrode LE.

[0171] The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the bridging pattern BRP may be disposed on the second interlayer insulating layer IL2 disposed on the upper electrode UE. The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the bridging pattern BRP may be disposed on the same layer and may be formed by the same process.

[0172] The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4 may be coupled to the second source electrode SE2 through the sixth contact hole CH6 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0173] The power line PL may extend parallel to the data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4 or the scan lines Si-1, Si and Si+1 (e.g., the data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4). The power line PL may be coupled to the upper electrode UE through the third contact hole CH3 and the fourth contact hole CH4 passing through the second interlayer insulating layer IL2. The power line PL may be coupled to the fifth source electrode SE5 through the fifth contact hole CH5 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0174] The connection line CNL may be coupled to the first gate electrode GE1 through the first contact hole CH1 passing through the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The connection line CNL may be coupled to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2.

[0175] The auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 through the ninth contact hole CH9 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0176] The bridging pattern BRP may be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

[0177] The protective layer PSV can be disposed on the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the bridge pattern BRP. The OLED and the initialization power line IPL can be disposed on the protective layer PSV. Each of the OLEDs can include a first electrode AD disposed on the protective layer PSV, a light-emitting layer EML disposed on the first electrode AD, and a second electrode CD disposed on the light-emitting layer EML.

[0178] The initialization power line IPL can be disposed on the protective layer PSV and at a position separated from the first electrode AD. The initialization power line IPL can be coupled to the auxiliary connection line AUX through an eighth contact hole CH8 passing through the protective layer PSV. Accordingly, the initialization power line IPL can be coupled to the seventh drain electrode DE7 through the auxiliary connection line AUX.

[0179] The initialization power supply Vint can be applied to the initialization power line IPL. The initialization power line IPL can include a plurality of first conductive lines CP1 and a plurality of second conductive lines CP2 intersecting and electrically coupled to the first conductive lines CP1. Accordingly, different from the case where the initialization power line IPL includes only the first conductive lines CP1 or the second conductive lines CP2, the initialization power line IPL can prevent a voltage drop of the initialization power supply Vint. In addition, even if the lines of the first conductive lines CP1 and the second conductive lines CP2 are short-circuited or open-circuited at any one point, the initialization power line IPL can apply the initialization power supply Vint to adjacent pixels PXL. Accordingly, the display device can prevent deterioration of display quality.

[0180] The initialization power line IPL can be not superposed with the first electrode AD. For example, the initialization power line IPL can bypass the first electrode AD of the OLED. The first conductive lines CP1 and the second conductive lines CP2 can be disposed at positions separated from the first electrode AD. For example, the first conductive lines CP1 and the second conductive lines CP2 can be disposed in a region between the first electrodes AD of adjacent OLEDs. In addition, the first conductive lines CP1 and the second conductive lines CP2 can extend in a direction inclined at least with respect to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 or the scan lines Si-1, Si, and Si+1 (for example, both the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1).

[0181] Initializing the power line IPL may further include a contact area CHR that extends from each point where the first conductive line CP1 and the second conductive line CP2 intersect toward the adjacent first electrode AD, and may be coupled to the auxiliary connection line AUX through the eighth contact hole CH8. The width of the contact area CHR may be greater than the width of each of the first conductive line CP1 and the second conductive line CP2.

[0182] The first conductive line CP1 and the second conductive line CP2 may bypass the first electrode AD in various shapes.

[0183] For example, the first conductive line CP1 and the second conductive line CP2 may form Figure 11 the shape shown in, where each of the first conductive line CP1 and the second conductive line CP2 extends in one direction, and the first conductive line CP1 and the second conductive line CP2 may intersect each other. A single OLED may be disposed in each of the regions formed by intersecting the first conductive line CP1 and the second conductive line CP2.

[0184] Alternatively, the first conductive line CP1 and the second conductive line CP2 may form Figure 12 the shape shown in, where each of the first conductive line CP1 and the second conductive line CP2 extends in one direction, and the first conductive line CP1 and the second conductive line CP2 intersect each other. Additionally, at least a portion of the first conductive line CP1 or the second conductive line CP2 (e.g., a portion of the first conductive line CP1) may be removed. In this case, multiple OLEDs may be disposed in each of the regions formed by intersecting the first conductive line CP1 and the second conductive line CP2. For example, two OLEDs may be disposed in each of the regions formed by intersecting the first conductive line CP1 and the second conductive line CP2.

[0185] As an option, the first conductive line CP1 and the second conductive line CP2 may form Figure 13 the shape shown in, where the first conductive line CP1 and the second conductive line CP2 intersect each other. In this case, at least a portion of the first conductive line CP1 or the second conductive line CP2 (e.g., a portion of the first conductive line CP1) may be removed. Multiple OLEDs may be disposed in each of the regions formed by intersecting the first conductive line CP1 and the second conductive line CP2. At least a portion of the first conductive line CP1 or the second conductive line CP2 may be bent, and the bent portions may be formed repeatedly. Thus, the first conductive line CP1 and the second conductive line CP2 may form a shape that bypasses the first electrode AD while being adjacent to the first electrode AD.

[0186] As another alternative, the first conductive line CP1 and the second conductive line CP2 may form Figure 14The shape shown in the figure, where the first conductive wire CP1 and the second conductive wire CP2 intersect each other. In this case, at least a part of the first conductive wire CP1 or the second conductive wire CP2 (for example, a part of the first conductive wire CP1) can be removed. A plurality of OLEDs can be provided in each of the regions formed by intersecting the first conductive wire CP1 and the second conductive wire CP2. At least a part of the first conductive wire CP1 or the second conductive wire CP2 can be bent, and the bent portions can be formed repeatedly.

[0187] The first conductive wire CP1 and the second conductive wire CP2 can include a first region R1 and a second region R2 coupled to the first region R1. The width of the first region R1 can be greater than the width of the second region R2. In the first conductive wire CP1 and the second conductive wire CP2, the first region R1 can be parallel to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 or the scan lines Si-1, Si, Si+1, and Si+2 (for example, the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4).

[0188] In the present embodiment, although the first region R1 of the first conductive wire CP1 and the second conductive wire CP2 has been shown as being parallel to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 or the scan lines Si-1, Si, Si+1, and Si+2, the present disclosure is not limited thereto. For example, the first region R1 of the first conductive wire CP1 and the second conductive wire CP2 can be inclined with respect to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 or the scan lines Si-1, Si, Si+1, and Si+2.

[0189] When the first electrode AD does not overlap with the third transistor T3 or the fourth transistor T4, leakage current may be caused by the third transistor T3 or the fourth transistor T4 due to external light. When the first electrode AD does not overlap with the third transistor T3 or the fourth transistor T4, the second region R2 can overlap with the third transistor T3 or the fourth transistor T4. The second region R2 can block external light that can be incident on the third transistor T3 or the fourth transistor T4. Therefore, the second region R2 can prevent leakage current of the third transistor T3 or the fourth transistor T4 due to external light.

[0190] The first region R1 can apply a signal or power to the pixel PXL, and the first regions R1 can be arranged adjacent to each other. The first regions R1 can overlap with signal lines or power lines that are parallel to each other. For example, the first region R1 can overlap with both one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and a power line PL arranged adjacent to the data line. Here, the first region R1 can be used as a shielding electrode for preventing parasitic capacitance formed between adjacent signal lines or power lines.

[0191] As described above, in the display device according to the exemplary embodiment, the initialization power line has a grid structure, so that a voltage drop of the initialization power supply can be prevented. Accordingly, the display quality of the display device can be improved. In addition, even if a part of the initialization power line of the display device is short-circuited or open-circuited, the initialization power can be applied to the pixels set adjacent to the short-circuited or open-circuited point. Accordingly, deterioration of the display quality of the display device can be prevented.

[0192] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but to the broader scope of the appended claims and various apparent modifications and equivalent arrangements.

Claims

1. A display device, the display device comprising: Pixels, located on a substrate, each pixel of the pixels includes a light-emitting element located on a protective layer and at least one transistor located under the protective layer, the protective layer has a first contact hole and a second contact hole, and both the first contact hole and the second contact hole penetrate the protective layer; An initialization power line, configured to supply initialization power to the pixels and electrically connected to the source electrode or the drain electrode of the transistor; A scan line, located on the substrate, the scan line is electrically coupled to the pixels; And A data line, located on the substrate, the data line is electrically coupled to the pixels, wherein the light-emitting element includes a first electrode electrically connected to the transistor, a light-emitting layer disposed on the first electrode, and a second electrode located on the light-emitting layer, the first electrode is disposed on the protective layer and in the first contact hole, wherein the initialization power line is disposed on the protective layer and in the second contact hole, and includes a first conductive wire and a second conductive wire that intersect and are connected to form a grid structure, wherein the first conductive wire and the second conductive wire bypass the first electrode of the light-emitting element and do not overlap with the first electrode in a plan view, and wherein the first conductive wire extends in a direction inclined to the scan line and the data line.

2. The display device according to claim 1, wherein, the first conductive wire and the second conductive wire surround at least a part of the first electrode, such that the first conductive wire and the second conductive wire are spaced apart from the light-emitting element.

3. The display device according to claim 2, wherein, the first conductive wire and the second conductive wire intersect at an intersection region, and wherein the second contact hole is located at one side of the intersection region.

4. The display device according to claim 2, the first conductive wire and the second conductive wire form a plurality of closed loops having a diamond shape.

5. The display device according to claim 4, wherein, the plurality of closed loops include a first closed loop and a second closed loop, wherein the light-emitting element includes a first light-emitting element located in the first closed loop and a second light-emitting element located in the second closed loop, wherein the first closed loop and the second closed loop have the same size, wherein the first light-emitting element and the second light-emitting element have different sizes.

6. The display device according to claim 2, wherein, the first conductive wire and the second conductive wire form a plurality of closed loops, wherein the plurality of closed loops include a first closed loop and a second closed loop, wherein the size of the first closed loop is larger than the size of the second closed loop.

7. The display device according to claim 6, wherein, two of the light-emitting elements are disposed in the first closed loop, and wherein one of the light-emitting elements is disposed in the second closed loop.

8. The display device according to claim 2, wherein, the first conductive wire and the second conductive wire form a plurality of closed loops, Wherein, the light-emitting element includes a first light-emitting element and a second light-emitting element, the second light-emitting element having a size smaller than that of the first light-emitting element, and wherein, the first light-emitting element and the second light-emitting element are located in each of the plurality of closed loops.

9. The display device according to claim 8, wherein, the plurality of closed loops are arranged in a row direction and a column direction, wherein each of the first light-emitting element and the second light-emitting element is arranged along the row direction and the column direction, and wherein the first light-emitting element and the second light-emitting element are alternately arranged along a direction different from the row direction and the column direction.

10. A display device, the display device comprising: Pixels, located on a substrate, each pixel of the pixels including a light-emitting element located on a protective layer and at least one transistor located under the protective layer, the protective layer having a first contact hole and a second contact hole, both the first contact hole and the second contact hole passing through the protective layer; and An initialization power line, configured to supply initialization power to the pixels and electrically connected to the source electrode or the drain electrode of the transistor, wherein, the light-emitting element includes a first electrode electrically connected to the transistor, a light-emitting layer provided on the first electrode, and a second electrode located on the light-emitting layer, the first electrode being provided on the protective layer and in the first contact hole, wherein, the initialization power line is provided on the protective layer and in the second contact hole, and includes a first conductive wire and a second conductive wire that intersect and are connected to form a grid structure, wherein, the first conductive wire and the second conductive wire bypass the first electrode of the light-emitting element and do not overlap with the first electrode in a plan view, and wherein, the first conductive wire and the second conductive wire include a first region and a second region combined with the first region, and the width of the first region is greater than the width of the second region.

11. The display device according to claim 10, wherein, the second contact hole is located in the first region.

12. The display device according to claim 10, wherein, the first conductive wire and the second conductive wire form a plurality of closed loops, wherein, the light-emitting element includes a first light-emitting element and a second light-emitting element, the second light-emitting element having a size smaller than that of the first light-emitting element, and wherein, the first light-emitting element and the second light-emitting element are located in each of the plurality of closed loops, wherein, each of the plurality of closed loops includes a first region and a second region, the first region surrounding the edge of the first light-emitting element, the second region surrounding the edge of the second light-emitting element, and wherein, the second region is smaller than the first region.

13. The display device according to claim 10, wherein, the first conductive wire and the second conductive wire surround at least a part of the first electrode such that the first conductive wire and the second conductive wire are spaced apart from the light-emitting element.

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