Storage devices

Abstract

The present application relates to a memory device. A memory device includes a wordline driver. The wordline driver is coupled to an array of bit cells via wordlines. The wordline driver includes a first driver circuit, a second driver circuit, and a modulation circuit. The first and second driver circuits are configured to select a wordline. The modulation circuit is coupled to the first and second driver circuits via the selected wordline and is configured to modulate at least one signal transmitted via the selected wordline. The first and second driver circuits are further configured to charge the selected wordline to generate a first voltage signal and a second voltage signal at two locations on the selected wordline. The first and second voltage signals are substantially identical. A method is also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices. Background Art

[0002] Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). In some embodiments, an SRAM device includes an SRAM array, and the SRAM array includes memory cells. A memory cell typically includes a transistor coupled to a bit line and a word line. The bit line and word line are used to read data from and write data to the memory cell. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a memory device is provided, comprising: a word line driver coupled to an array of bit cells arranged in rows and columns through a plurality of word lines, the word line driver comprising: a first drive circuit and a second drive circuit, the first drive circuit and the second drive circuit being configured to select one word line from the plurality of word lines; and a modulation circuit coupled to the first drive circuit and the second drive circuit through the selected word line, and configured to modulate at least one signal transmitted through the selected word line, wherein the first drive circuit and the second drive circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions on the selected word line, and the first voltage signal is substantially the same as the second voltage signal.

[0004] According to a second aspect of the present disclosure, a memory device is provided, comprising: a plurality of bit cells arranged in rows and columns; and a word line driver coupled between a power supply voltage terminal and a reference voltage terminal and coupled to the plurality of bit cells through a plurality of word lines, wherein the word line driver is configured to select one word line among the plurality of word lines in a first row, and the word line driver comprises: at least one driver circuit configured to generate a first voltage signal on the selected word line at a first node, the first node being coupled to some of the plurality of bit cells in the first row, and the at least one driver circuit configured to generate a second voltage signal on the selected word line at a second node, the second node being coupled to other some of the plurality of bit cells in the first row; and a first modulation circuit and a second modulation circuit coupled between the reference voltage terminal and at least one of the first node or the second node, and configured to modulate the first voltage signal and the second voltage signal on the selected word line.

[0005] According to a third aspect of the present disclosure, a method is provided, comprising: selecting a word line from a plurality of word lines coupled to an array of bit cells; generating a first voltage signal at a first node and a second voltage signal at a second node through a first drive circuit and a second drive circuit, wherein the first drive circuit is coupled to the selected word line at the first node and the second drive circuit is coupled to the selected word line at the second node; and modulating the first voltage signal and the second voltage signal through a modulation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure.

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1 The word line driver shown corresponds to the equivalent circuit of the word line driver.

[0009] Figure 3 According to some embodiments of the present disclosure, Figure 2 The word line driver shown corresponds to a flow chart of a word line driver method.

[0010] Figure 4 According to some embodiments of the present disclosure Figure 2 The word line driver shown corresponds to the layout diagram of the word line driver.

[0011] Figure 5 According to some embodiments of the present disclosure Figure 1 The word line driver shown corresponds to the equivalent circuit of the word line driver.

[0012] Figure 6 According to some embodiments of the present disclosure Figure 5 The word line driver shown corresponds to the layout diagram of the word line driver.

[0013] Figure 7 According to some embodiments of the present disclosure Figure 1 The word line driver shown corresponds to the equivalent circuit of the word line driver.

[0014] Figure 8 According to some embodiments of the present disclosure Figure 7 The word line driver shown corresponds to the layout diagram of the word line driver.

[0015] Figure 9 is a block diagram of a system for designing an IC layout design according to some embodiments of the present disclosure.

[0016] Figure 10 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, by itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0018] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and in no way limits the scope and meaning of the present disclosure or any exemplified term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0019] Although the terms "first," "second," etc., may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0020] Herein, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0021] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used throughout this description to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] As used herein, "approximately," "about," "approximately," or "substantially" shall generally refer to any approximation of a given value or range, wherein the approximation varies according to the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The numerical quantities given herein are approximate, meaning that the term "approximately," "about," "approximately," or "substantially" can be inferred if not explicitly stated, or that other approximate values ​​are intended.

[0023] Figure 1 FIG2 shows a schematic diagram of a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 is implemented by a static random access memory (SRAM). Figure 1 As shown in FIG. 1 , the memory device 100 includes a memory cell array 110, a memory cell array 120, and a word line driver WLD. The word line driver WLD is arranged and coupled between the memory cell array 110 and the memory cell array 120.

[0024] Word line driver WLD is coupled between a power supply voltage terminal VDD and a reference voltage terminal, which in some embodiments of the present disclosure is referred to as ground. Word line driver WLD is also coupled to a control circuit (not shown) and is configured to provide a voltage signal or a current signal on word lines WL_L and WL_R in response to a control signal generated by the control circuit. Word line driver WLD is coupled to memory cell array 110 via word line WL_L and to memory cell array 120 via word line WL_R to read from or write to corresponding memory cells in memory cell arrays 110 and / or 120.

[0025] In some embodiments, the signal provided on word line WL_L or WL_R has a voltage value substantially equal to the voltage difference between the power supply voltage terminal VDD and a reference voltage terminal (hereinafter referred to as, for example, ground). In various embodiments, each voltage signal provided on word line WL_L and on word line WL_R has a voltage value lower than the voltage difference between the power supply voltage terminal VDD and ground. In other words, the voltage of word line WL_L or WL_R provided by word line driver WLD is lower than the voltage provided by a power supply (not shown) (i.e., the difference between VDD and ground). In another explanation, word line driver WLD is configured to implement a suppressed voltage on word lines WL_L and WL_R to drive memory cells using the suppressed voltage. In some embodiments of the present disclosure, word lines WL_L and WL_R having the suppressed voltage are indicated as suppressed word lines.

[0026] Each of the memory cell arrays 110 and 120 includes memory cells MC arranged in rows and columns. Figure 1 Only one memory cell MC in the memory cell array 120 is marked. In some embodiments, the memory cell array 110 and the memory cell array 120 are symmetrical with respect to the word line driver WLD. In some embodiments, the number and arrangement of the memory cells MC included in the memory cell array 110 are the same as the number and arrangement of the memory cells MC included in the memory cell array 120. For example, referring to Figure 1 , the memory cells MC in each of the memory cell arrays 110 and 120 are arranged in n+1 rows and m+1 columns. In some other embodiments, the memory cell array 110 and the memory cell array 120 are asymmetric with respect to the word line driver WLD. The number of columns included in the memory cell array 110 is different from the number of columns included in the memory cell array 120.

[0027] The memory cells MC in the memory cell array 110 are coupled to word lines WL_L0, WL_L1, ..., and WL_Ln and bit lines BL_L0, BL_L1, ..., and BL_Lm. For simplicity, each of the word lines WL_L0, WL_L1, ..., and WL_Ln is referred to as WL_L below for description, because in some embodiments, the word lines WL_L0, WL_L1, ..., and WL_Ln operate in a similar manner. Similarly, each of the bit lines BL_L0, BL_L1, ..., and BL_Lm is referred to as BL_L below for description. Similar to the memory cells MC in the memory cell array 110, the memory cells MC in the memory cell array 120 are coupled to word lines WL_R0, WL_R1, ..., and WL_Rn and bit lines BL_R0, BL_R1, ..., and BL_Rm. For simplicity, each of the word lines WL_R0, WL_R1, ..., and WL_Rn is referred to as WL_R below for description, because in some embodiments, the word lines WL_R0, WL_R1, ..., and WL_Rn operate in a similar manner. Similarly, each of the bit lines BL_R0, BL_R1, ..., and BL_Rm is referred to as BL_R below for description.

[0028] The above numbers of word lines WL_L or WL_R and bit lines BL_L or BL_R are given for illustration purposes, and various numbers of word lines WL_L or WL_R and bit lines BL_L or BL_R are within the intended scope of the present disclosure.

[0029] Each memory cell MC in the memory cell array 110 is coupled to one of the word lines WL_L and one of the bit lines BL_L in the corresponding row and the corresponding column. In addition, in the corresponding row, each memory cell MC in the memory cell array 120 is coupled to one of the word lines WL_R and one of the bit lines BL_R in the same row. For example, in Figure 1 In the top row shown, memory cells MC in memory cell array 110 are coupled to word line WL_L0, and memory cells MC in memory cell array 120 are coupled to word line WL_R0. Word lines WL_L0 and WL_R0 are coupled to each other via word line driver WLD and activated by word line driver WLD. In other words, word line driver WLD is configured to drive the memory cells in the corresponding row by selecting and charging word lines WL_L and WL_R in that row (i.e., word lines WL_L0 and WL_R0 in this example).

[0030] In some embodiments, each memory cell MC in the memory cell array 110 or 120 is implemented by an SRAM bit cell in a six-transistor (6T) configuration. Each memory cell MC includes a pair of cross-coupled inverters and a pair of access transistors. The pair of cross-coupled inverters is implemented by two transistors of one type (e.g., p-type metal oxide semiconductor transistors (PMOS transistors)) and two transistors of the other type (e.g., n-type metal oxide semiconductor transistors (NMOS transistors)). The pair of access transistors is implemented by two transistors (e.g., two NMOS transistors). The pair of access transistors is selectively coupled to the bit line BL_L or BL_R and is driven by the word line WL_L or WL_R. The configuration of the above-mentioned memory cell MC is given for illustrative purposes. Various configurations of the memory cell MC are within the intended scope of the present disclosure.

[0031] The configuration of the memory device 100 described above is given for illustrative purposes. Various configurations of the memory device 100 are within the contemplated scope of the present disclosure.

[0032] refer to Figure 2 . Figure 2 According to some embodiments of the present disclosure Figure 1 The equivalent circuit 200 of the word line driver WLD shown corresponds to the word line driver WLD. The equivalent circuit 200 of the word line driver WLD is shown using resistors and transistors to illustrate effective circuit connections. The word line driver WLD includes a header circuit 210, a driver circuit 220 (including driver circuits 221a, 221b, and 222), and a modulation circuit 230. In some embodiments, the transistors shown in circuits 210, 221a, 221b, 222, or 230 are their equivalent circuits. In some embodiments, Figure 2 The illustrated resistance elements R0 , R1 , R2 , R3 , and R4 are parasitic resistances in the equivalent circuit 200 .

[0033] for Figure 2 As described above, the word line driver WLD is coupled between the power supply voltage terminal VDD and the reference voltage terminal (hereinafter referred to as, for example, ground). The word line driver WLD is configured to output signals on the word line WL at two corresponding output terminals WL_L and WL_R in response to control signals (including, for example, the decoder signal MWLB). In some embodiments, Figure 2 The word lines WL shown correspond to Figure 1 One of the word lines WL_L0, WL_L1, ..., and WL_Ln and one of the word lines WL_R0, WL_R1, ..., and WL_Rn are shown as being arranged in the same row as the word line WL_L. Figure 1In the illustrated memory device 100, output terminals WL_L and WL_R are indicated as terminals for selectively charging the word line WL. The signal on the word line WL output from the word line driver WLD at the output terminal WL_L is coupled to some memory cells (e.g., Figure 1 The signal on the word line WL output from the word line driver WLD at the output terminal WL_R is coupled to other memory cells (eg, MC) in the same row through the word line WL. Figure 1 Memory cells MC in the memory cell array 120 shown).

[0034] The header circuit 210 is coupled to the power supply voltage terminal VDD via a resistor element R0 and is coupled to driver circuits 221a and 211b via resistor elements R1 and R2, respectively. Driver circuit 221a is coupled in series to driver circuit 221b and in parallel to driver circuit 222. Driver circuit 221a is also coupled to output terminal WL_L (i.e., node n3) and is further coupled to modulation circuit 230 at node n5 on word line WL via resistor element R3. Driver circuit 221b is coupled to output terminal WL_R (i.e., node n4) and is further coupled to modulation circuit 230 at node n5 via resistor element R4. Driver circuit 222 is coupled between output terminal WL_L (i.e., node n3) and ground. Modulation circuit 230 is coupled between node n5 and ground.

[0035] refer to Figure 2 In equivalent circuit 200, header circuit 210 includes transistors MH1, ..., and MH2, which are PMOS transistors in some embodiments. The gate terminals of each of transistors MH1, ..., and MH2 are coupled together and coupled to a control circuit (not shown) for receiving a control signal MP0 outputted from the control circuit. The source terminals of transistors MH1, ..., and MH2 are coupled to each other and to a power supply voltage terminal VDD via a resistor element R0. The drain terminals of transistors MH1, ..., and MH2 are coupled to each other and to a driver circuit 221a via a node n1 and to a driver circuit 221b via a node n2. In other words, the drain terminal of transistor MH1 is coupled to driver circuit 221a via node n1, and the drain terminal of transistor MH2 is coupled to driver circuit 221b via a node n2.

[0036] Driver circuit 221a includes transistor M1-1, which in some embodiments is a PMOS transistor. Driver circuit 221b includes transistor M1-2, which in some embodiments is a PMOS transistor. Driver circuit 222 includes transistor M2, which in some embodiments is an NMOS transistor. The gate terminals of transistor M1-1, transistor M1-2, and transistor M2 are coupled together and further coupled to a word line decoder (not shown) for receiving decoder signal MWLB output from the word line decoder. The source terminal of transistor M1-1 is coupled to node n1 via resistor element R1 for receiving one of the voltage / current signals output from header circuit 210. The drain terminal of transistor M1-1 is coupled to node n3 (also indicated as output terminal WL_L) and further coupled to the source terminal of transistor M2. Furthermore, the drain terminal of transistor M1-1 is coupled to modulation circuit 230 via resistor element R3. The source terminal of transistor M1-2 is coupled to node n2 via resistor element R2 for receiving one of the voltage / current signals output from header circuit 210. The drain terminal of transistor M1-2 is coupled to node n4, also denoted as output terminal WL_L. Furthermore, the drain terminal of transistor M1-2 is coupled to modulation circuit 230 via resistor element R4. The source terminal of transistor M2 is coupled to node n3. The drain terminal of transistor M2 is coupled to ground. In some embodiments, transistor M2 and at least one of transistor M1-1 or transistor M1-2 are configured to function as inverters.

[0037] Modulation circuit 230 includes a transistor M3, which in some embodiments is a PMOS transistor. The gate terminal of transistor M3 is coupled to a control circuit (not shown) for receiving a control signal RAEN outputted by the control circuit. The source terminal of transistor M3 is coupled to node n5 on word line WL, and the drain terminal of transistor M3 is coupled to ground.

[0038] Resistor element R0 is coupled between power supply voltage terminal VDD and transistor MH1. Resistor element R1 is coupled between node n1 and transistor M1-1. Resistor element R2 is coupled between node n2 and transistor M1-2. Resistor element R3 is coupled between node n3 and node n5. Resistor element R4 is coupled between node n3 and node n5. Resistor element R3 and resistor element R4 are coupled in series on a word line.

[0039] In some embodiments, at least one of the resistance elements R0-R4 is referred to as an internal resistance included in the word line driver WLD, which includes, for example, transistors MH1, MH2, M1-1, M1-2, M2, and M3, or conductive lines coupled therebetween. In some other embodiments, at least one of the resistance elements R0-R4 is referred to as a parasitic resistance of the wiring included in the word line driver WLD. In some embodiments, the parasitic resistance is also hereinafter referred to as an internal resistance. In other words, at least one of the resistance elements R0-R4 is referred to as an equivalent resistance. For example, referring to Figure 2 In some embodiments, the resistance element R3 is an equivalent resistance of a portion of the word line WL including the output terminal WL_L, and the resistance element R4 is an equivalent resistance of another portion of the word line WL including the output terminal WL_R. In various embodiments, at least one of the resistance elements R0-R4 is referred to as a physical resistor included in the word line driver WLD and has the following characteristics: Figure 2 The corresponding electrical connections or configurations are shown.

[0040] Continue to refer Figure 2 In some embodiments, the resistance element R0 is the equivalent internal resistance of the header circuit 210. The resistance element R0 includes at least one of the internal resistances of transistors MH1 and MH2, or a conductive line coupled between (including), for example, transistors MH1 and MH2, or between transistor MH1 and the power supply voltage node VDD. In some other embodiments, the resistance element R0 is the internal resistance of the conductive line coupled between transistor MH1 and the power supply voltage node VDD. In addition, the resistance element R1 is the equivalent internal resistance of the driver circuit 221a. The resistance element R1 includes the internal resistance of transistor M1-1, and a conductive line coupled between (including), for example, transistor M1-1 and node n1. Similarly, the resistance element R2 is the equivalent internal resistance of the driver circuit 221b. The resistance element R2 includes the internal resistance of transistor M1-2, and a conductive line coupled between (including), for example, transistor M1-2 and node n2. In some embodiments, the resistive element R1 is an internal resistance of a conductive line coupled between the transistor MH1 and the node n1 , and the resistive element R2 is an internal resistance of a conductive line coupled between the transistor M1 - 2 and the node n2 .

[0041] In addition, at least one of the resistance elements R3 or R4 is the equivalent internal resistance of the modulation circuit 230. At least one of the resistance elements R3 or R4 includes the internal resistance of the transistor M3. The resistance element R3 includes the equivalent internal resistance of the conductive line coupled between (including), for example, the transistor M3 and the node n3. In other words, the internal resistance of the conductive line coupled between the drive circuit 221a and the modulation circuit 230 is included in the resistance element R3. Similarly, the resistance element R4 includes the equivalent internal resistance of the conductive line coupled between (including), for example, the transistor M3 and the node n4. In other words, the internal resistance of the conductive line coupled between the drive circuit 221b and the modulation circuit 230 is included in the resistance element R4. In various embodiments, the resistance element R3 is the internal resistance of the conductive line coupled between the transistor M3 and the node n3, and the resistance element R4 is the internal resistance of the conductive line coupled between the transistor M3 and the node n4.

[0042] The above-described embodiment of equivalent circuit 200 is provided for illustrative purposes. Various embodiments of equivalent circuit 200 are within the contemplated scope of the present disclosure. For example, in some embodiments, equivalent circuit 200 further includes control circuitry for generating control signals MP0 and RAEN. In various embodiments, equivalent circuit 200 further includes a wordline decoder for generating decoder signal MWLB. In alternative embodiments, transistors MH1, MH2, M1-1, M1-2, and M2 are configured to function as switches.

[0043] refer to Figure 3 . Figure 3 According to some embodiments of the present disclosure, Figure 2 The word line driver WLD shown corresponds to a flow chart of a word line driver method 300 . Figure 3 Reference to method 300 in Figure 2 The following description of the word line driver WLD in includes exemplary operations. However, Figure 3 The operations in the embodiment of the present invention are not necessarily performed in the order shown. In other words, operations may be appropriately added, replaced, changed in order, and / or eliminated according to the spirit and scope of various embodiments of the present disclosure.

[0044] In operation S310, in response to a decoder signal, a driving circuit is driven to select a word line. Figure 2As shown, in response to decoder signal MWLB, driver circuits 221a, 221b, and 222 are driven to select word line WL. Specifically, in response to decoder signal MWLB, transistor M1-1 of driver circuit 221a and transistor M1-2 of driver circuit 221b are turned on. At the same time, since transistor M2 is an NMOS transistor different from transistors M1-1 and M1-2, it is turned off in response to decoder signal MWLB. Through the above operation, word line WL coupled to transistors M1-1 and M1-2 that are turned on is indicated as the selected word line WL.

[0045] In some embodiments, driver circuits 221a and 221b are referred to as two separate pull-up circuits. In other words, transistors M1-1 and M1-2 function as pull-up transistors, configured to charge word line WL to a high voltage relative to ground. In some embodiments, driver circuit 222 is referred to as a pull-down circuit. In other words, transistor M2 functions as a pull-down transistor, configured to couple word line WL to ground.

[0046] In operation S320, in response to the control signal, the header circuit is driven to provide the operating signal to the driving circuit. In other words, at least one transistor (functioning as a switch) included in the header circuit is driven by the control signal to couple the operating signal from the power supply to the driving circuit. For illustration, as shown in FIG. Figure 2 As shown, in response to a control signal MP0, the header circuit 210 is driven to provide signals (e.g., current signals Is1 and Is2, or voltage signals (not shown)) to the driver circuits 221a and 221b. Specifically, in response to the decoder signal MP0, the transistors MH1 and MH2 of the header circuit 210 are turned on, and signals are coupled from the power supply voltage terminal VDD to nodes n1 and n2, respectively, through the transistors MH1 and MH2 of the header circuit 210. Since the node n1 is further coupled to the transistor M1-1 of the driver circuit 221a, and the node n2 is further coupled to the transistor M1-2 of the driver circuit 221b, the signals are further coupled to the driver circuits 221a and 221b, respectively.

[0047] In some embodiments, referring back to Figure 2, current signal Is1 is transmitted from node n1 through resistor element R1 to transistor M1-1, and current signal Is2 is transmitted from node n2 through resistor element R2 to transistor M1-2. In some other embodiments, transistors MH1, MH2, M1-1, M1-2, and M2 included in word line driver WLD are ideal transistors used as switches, and their internal resistances (also called equivalent resistances) are indicated as corresponding resistor elements R0-R4. In various embodiments, resistor element R1 is the internal resistance of transistor M1-1, and resistor element R2 is the internal resistance of transistor M1-2. In addition, transistor M1-1 is identical to transistor M1-2. Therefore, resistor element R1 is substantially identical to resistor element R2. Therefore, current signal Is1 is substantially equal to current signal Is2. In other words, the voltage signal (not shown) input to transistor M1-1 is substantially equal to the voltage signal (not shown) input to transistor M1-2. In alternative embodiments, resistor element R1 includes the internal resistance of transistor M1-1 and the wiring between node n1 and transistor M1-1. The resistance element R2 includes the internal resistance of the transistor M1-2 and the wiring between the node n2 and the transistor M1-2. Since the resistance element R1 is the same as the resistance element R2, the current signal Is1 is substantially equal to the current signal Is2.

[0048] In operation S330, in response to the operation signal provided by the header circuit, the driver circuit is driven to charge the selected word line. In other words, the operation signal is coupled to the selected word line by the turned-on driver circuit, and the selected word line is charged by the driver circuit. Figure 2 As shown, by coupling the voltage signal output from the header circuit 210 to the selected word line WL, the driver circuits 221a and 221b are activated to charge the selected word line WL. Specifically, since the transistors M1-1 and M1-2 are turned on (functioning as two corresponding switches), the signals are coupled from nodes n1 and n2 to nodes n3 and n4, respectively. In addition, nodes n3 and n4 are indicated as output terminals WL_L and WL_R of the word line driver WLD, and are also referred to as input terminals of the selected word line WL. With the above operation, the selected word line WL is charged at two corresponding nodes n3 (i.e., node WL_L) and n4 (i.e., node WL_R) by the transistor M1-1 of the driver circuit 221a and the transistor M1-2 of the driver circuit 221b, respectively.

[0049] In some embodiments, as described above with reference to Figure 2 and Figure 3As discussed in operation S320 of the present invention, since current signal Is1 is substantially equal to current signal Is2 and no other passive components are coupled between transistor M1-1 and node n3 or between transistor M1-2 and node n4, current signals Is1 and Is2 provided to nodes n3 and n4 are identical. In other words, the two corresponding nodes n3 (i.e., node WL_L) and n4 (i.e., node WL_R) of the selected word line WL are charged by the same current signal Is1 or Is2.

[0050] In operation S340, in response to another control signal, the modulation circuit is driven to modulate the signal output to the selected word line. In other words, the signal at the selected word line is coupled to a lower voltage terminal (e.g., ground) by the activated modulation circuit, and the voltage or current of the selected word line is modified by the modulation circuit. For illustration, as shown in FIG. Figure 2 As shown, in response to control signal REAN, modulation circuit 230 is driven to modulate the signal output to the selected word line WL. Specifically, in response to control signal REAN, transistor M3 of modulation circuit 230 is turned on, and current signal Is1 is transmitted from node n3 to node n5 through resistor R3, and current signal Is2 is transmitted from node n4 to node n5 through resistor R4. Current signals Is1 and Is2 are then coupled together as current signal Is. Signal Is at the selected word line WL is transmitted from node n5 to ground through transistor M3 of modulation circuit 230. Through the above operation, the voltage or current of the selected word line WL (the final output signal on the selected word line WL) is lower than the voltage or current of the power supply (e.g., power supply voltage VDD). Thus, word line suppression is achieved, and the suppression voltage at the selected word line WL is provided to the memory cells, driving them with a lower voltage or current.

[0051] In some embodiments, as described above with reference to Figure 2 and Figure 3 As discussed in operations S320 and S330, current signal Is1 is substantially equal to current signal Is2. Furthermore, in some embodiments, resistance element R3 includes transistor M3 and the internal resistance of the wiring between node n3 and node n5. Resistance element R4 includes transistor M3 and the internal resistance of the wiring between node n4 and node n5. In some other embodiments, the wiring between driver circuit 221a and modulation circuit 230 is substantially the same as the wiring between driver circuit 221b and modulation circuit 230. Therefore, resistance element R3 is substantially the same as resistance element R4. Therefore, the voltage difference between nodes n3 and n5 is substantially equal to the voltage difference between nodes n4 and n5. Therefore, the signals output at nodes n3 and n4 on the selected word line WL are equal to each other.

[0052] In some methods, only two with e.g. Figure 2 The driver circuits 221a and 221b corresponding to the drive circuits are included in the word line driver and are configured to charge the selected word line at one of the two output terminals. However, the two output terminals correspond to the two internal resistors of the selected word line, so when the selected word line is charged, the voltage signals output through the two output terminals are different from each other, which causes an imbalance in the voltage level on the selected word line, resulting in IR drop problems and speed mismatch in read / write operations, etc.

[0053] Compared with the above method, in the embodiments of the present disclosure, for example, referring to Figure 2 and Figure 3 , the driver circuit, represented as a pull-up circuit, is divided into two driver circuits 221a and 221b, and driver circuits 221a and 221b are coupled to two separate output terminals WL_L and WL_R. Because the total resistance of a portion of word line driver WLD, including, for example, resistor element R1, transistor M1-1, and resistor element R3, is substantially equal to the total resistance of another portion of word line driver WLD, including, for example, resistor element R2, transistor M1-2, and resistor element R4, the voltage difference therebetween is substantially the same. In other words, there is no voltage difference between the respective output terminals WL_L and WL_R. Therefore, the selected word line WL has a balanced voltage level, which improves read / write operation speed and IR drop issues, and can avoid speed mismatches in read / write operations, etc.

[0054] refer to Figure 4 . Figure 4 According to some embodiments of the present disclosure Figure 2 The word line driver WLD shown corresponds to a word line driver layout diagram 400 .

[0055] for Figure 4 , the layout structure of transistor M1-1 is arranged adjacent to the layout structure of transistor M2. In addition, the layout structure of transistor M1-1 is arranged between the layout structure of transistor M2 and the layout structure of transistor M3. The layout structure of transistor M3 is arranged between the layout structure of transistor M1-1 and the layout structure of transistor M1-2. In other words, in the layout diagram, the layout structure of modulation circuit 230 is arranged between the layout structure of drive circuit 221a and the layout structure of drive circuit 221b. In addition, the layout structure of transistor MH is separated from at least one of the layout structures of transistors M2, M1-1, M3 or M1-2. In some embodiments, Figure 4 The illustrated layout structure of the transistors MH corresponds to an equivalent circuit of the transistors MH1 , . . . , and MH2 included in the header circuit 210 .

[0056] In some embodiments, at least one of the layout structures of transistors M2, M1-1, M3, M1-2, or MH has an area different from that of other transistors in layout diagram 400. The area of ​​the layout structure is referred to as the area used to form transistors (including, for example, transistors M2, M1-1, M3, M1-2, and MH) in layout diagram 400. The area of ​​the layout structure / design is associated with the driving capability of the corresponding transistor. For example, Figure 4 As shown, the layout structures of transistors M2, M1-1, M3, M1-2, and MH have the same width as each other, and at least one of the layout structures of transistors M2, M1-1, M3, M1-2, or MH has a length different from that of the other transistors. Figure 4 In the transistor layout shown, transistor M2 has a length of L2; transistor M1-1 has a length of L1; transistor M3 has a length of L3; transistor M1-2 has a length of L1; and transistor MH has a length of LH. Therefore, at least one of transistors M2, M1-1, M3, M1-2, or MH has a different drive capability than the other transistors. In some embodiments, the area of ​​the layout design is positively correlated with the drive capability. For example, as the area of ​​the layout design increases, the drive capability of the corresponding transistor increases.

[0057] In some embodiments, length L1 is substantially equal to length L2, and the area of ​​transistor M1-1 or M1-2 is substantially the same as that of transistor M2. In some other embodiments, length L1 is greater than length L3, and the area of ​​transistor M1-1 or M1-2 is greater than that of transistor M3. In various embodiments, length L1 is greater than length LH, and the area of ​​transistor M1-1 or M1-2 is greater than that of transistor MH.

[0058] In some embodiments, the layout structures of the transistor M1 - 1 and the transistor M1 - 2 have the same area in the layout diagram 400 , so as to form two identical transistors M1 - 1 and M1 - 2 .

[0059] Continue to refer Figure 4, the layout structures of transistors M2, M1-1, M3, M1-2, and MH are separated from each other by at least one distance. In some embodiments, the distance between the layout structures is associated with the wiring length in the word line driver WLD. In some other embodiments, the wiring length in the word line driver WLD is also associated with the driving capability of the corresponding transistors M2, M1-1, M3, M1-2, and MH. Distance D1 extends from the middle of the layout structure of transistor M2 (i.e., half of the length L2 of transistor M2) to the middle of the layout structure of transistor M1-1 (i.e., half of the length L1 of transistor M1-1). Distance D2 extends from the middle of the layout structure of transistor M1-1 (i.e., half of the length L1 of transistor M1-1) to the middle of the layout structure of transistor M3 (i.e., half of the length L3 of transistor M3). In addition, the distance from the middle of the layout structure of transistor M3 (i.e., half of the length L3 of transistor M3) to the middle of the layout structure of transistor M1-2 (i.e., half of the length L1 of transistor M1-2) is also represented as distance D2. In other words, the layout structure of the transistor M3 is arranged in the middle of the layout structures of the two separate transistors M1 - 1 and M1 - 2 .

[0060] In some embodiments, Figure 4 The distance D1 or D2 shown is indicated as the wiring length of a conductive track (not shown) arranged in multiple metal layers (e.g., M0-M3 layers). The conductive track in layout diagram 400 corresponds to a conductive line coupled between corresponding transistors. Since the conductive track is made of metal, the length of the conductive track is positively correlated with the resistance of the conductive track. In some embodiments, reference Figure 4 , the length of the conductive track coupled between transistor M1-1 and transistor M3 is substantially equal to distance D2. Similarly, the length of the conductive track coupled between transistor M1-2 and transistor M3 is also substantially equal to distance D2. Therefore, the conductive track between transistors M1-1 and M3 is substantially the same as the conductive track between transistors M1-2 and M3. Therefore, the internal resistance of the conductive line coupled between transistors M1-1 and M3 (i.e., resistive element R3) is equal to the internal resistance of the conductive line coupled between transistors M1-2 and M3 (i.e., resistive element R4).

[0061] In some embodiments, transistor M3, the conductive track coupled between transistor M3 and transistor M1-1, and the conductive track coupled between transistor M3 and transistor M1-2 are symmetrical about the center of transistor M3 in layout diagram 400. In some other embodiments, transistor M1-2 and the conductive track coupled between transistor M1-2 and transistor M3 are formed in layout diagram 400 by mirroring transistor M1-1 and the conductive track coupled between transistor M1-1 and transistor M3 relative to the center of transistor M3. In other words, transistors M1-1 and M1-2 are mirror images of each other relative to transistor M3. In other words, transistor M3 is placed in the center of transistors M1-1 and M1-2.

[0062] For illustrative purposes, Figure 4 The configuration and arrangement of the layout diagram 400 shown in FIG. Figure 2 Various configurations and arrangements of the word line driver WLD in are within the contemplated scope of the present disclosure. For example, in some embodiments, in the layout diagram, transistor MH is arranged adjacent to transistor M2.

[0063] refer to Figure 5 . Figure 5 According to some embodiments of the present disclosure Figure 1 The word line driver WLD shown corresponds to an equivalent circuit 500 of the word line driver WLD. The word line driver WLD includes a header circuit 510, a driver circuit 520 (including driver circuits 521a, 521b, and 522), and a modulation circuit 530.

[0064] In some embodiments, Figure 5 The word line driver WLD shown is Figure 2 The header circuit 510 and the driver circuits 521a, 521b and 522 correspond to the alternative embodiment of the word line driver WLD shown in FIG. Figure 2 The header circuit 210 and the driver circuits 221a, 221b and 222 are shown. Figure 5 The configuration and / or relationship between the head circuit 510, the driving circuits 521a, 521b and 522, and the modulation circuit 530 in the embodiment of the present invention are similar to those described above. Figure 2 Therefore, they are not described in further detail here. Figure 2 An embodiment of the word line driver WLD, Figure 5 The same elements in the drawings are designated with the same reference numerals for ease of understanding.

[0065] and Figure 2Compared to the embodiment shown, the word line driver WLD further includes resistor elements R5 and R6 on the word line WL. All the resistor elements R3, R4, R5 and R6 are on the word line WL and are coupled between the two separate output terminals WL_L and WL_R of the word line WL. In some other embodiments, referring to Figure 5 Resistor element R3 is the internal resistance of word line WL coupled between nodes n3 and n5. Resistor element R5 is the internal resistance of word line WL coupled between nodes n5 and n6. Resistor element R6 is the internal resistance of word line WL coupled between nodes n6 and n7. Resistor element R4 is the internal resistance of word line WL coupled between nodes n7 and n4.

[0066] In addition, the modulation circuit 530 also includes transistors M4-1 and M4-2, which are PMOS transistors in some embodiments. Transistors M4-1, M3, and M4-2 are coupled in parallel and are coupled to the selected word line WL at nodes n5, n6, and n7, respectively. The gate terminal of each of transistors M4-1 and M4-2 is coupled to a control circuit (not shown) for receiving a control signal RASEL[1] having a logic value indicating "1" output from the control circuit. The source terminal of transistor M4-1 is coupled to node n5, and the drain terminal of transistor M4-1 is coupled to ground. The source terminal of transistor M4-2 is coupled to node n7, and the drain terminal of transistor M4-2 is coupled to ground. The gate terminal of transistor M3 is coupled to the control circuit for receiving the same control signal RASEL[0] having a logic value indicating "0" output from the control circuit. The source terminal of transistor M3 is coupled to node n6, and the drain terminal of transistor M3 is coupled to ground.

[0067] In some embodiments, a logic value indicated as "1" is referred to as a logic high, and a logic value indicated as "0" is referred to as a logic low. In various embodiments, control signal RASEL[1] is configured to turn on transistors M4-1 and M4-2 and turn off transistor M3. Similarly, control signal RASEL[0] is configured to turn off transistors M4-1 and M4-2 and turn on transistor M3.

[0068] In some embodiments, for operation Figure 5 The method of the word line driver WLD shown is similar to that described above. Figure 3 Example of .

[0069] for Figure 3 The description of operation S310 shown is similar to that of reference Figure 2 Operation S310, referring to Figure 5, the transistors M1-1 and the transistor M1-2 of the corresponding driving circuits 521a and 521b are turned on in response to the decoder signal MWLB, and the word line WL coupled to the turned-on transistors M1-1 and M1-2 is represented as a selected word line WL.

[0070] for Figure 3 The description of operation S320 shown is similar to that of reference Figure 2 Operation S320, referring to Figure 5 , transistors MH1 and MH2 of header circuit 510 are turned on in response to decoder signal MP0. A signal (e.g., current signal Is1) is coupled from power supply voltage terminal VDD to node n1 through transistor MH1, and further coupled to transistor M1-1 of driver circuit 521a through resistor R1. Simultaneously, a signal (e.g., current signal Is2) is coupled from power supply voltage terminal VDD to node n2 through transistor MH2, and further coupled to transistor M1-2 of driver circuit 521b through resistor R2.

[0071] for Figure 3 The description of operation S330 shown is similar to that of reference Figure 2 Operation S330, referring to Figure 5 , signal Is1 is transmitted through transistor M1-1 to node n3, which is represented as one of the output terminals of word line driver WLD. Furthermore, signal Is2 is transmitted through transistor M1-2 to node n4, which is represented as another of the output terminals of word line driver WLD. Subsequently, the selected word line WL is charged at two corresponding nodes n3 (i.e., node WL_L) and n4 (i.e., node WL_R) via transistor M1-1 of driver circuit 521a and transistor M1-2 of driver circuit 521b.

[0072] for Figure 3 For a description of operation S340, refer to Figure 5 , in response to the control signal RASEL[1], transistor M3 is turned off and transistors M4-1 and M4-2 are turned on. Current signal Is1 is transmitted from node n3 to node n5 through resistor element R3. At the same time, current signal Is2 is transmitted from node n4 to node n7 through resistor element R4. Subsequently, current signal Is1 is transmitted from node n5 to ground through transistor M4-1. At the same time, current signal Is2 is transmitted from node n7 to ground through transistor M4-2. Through the above operation, the selected word line WL is provided with a lower voltage (indicated as a first voltage and not shown) at the two corresponding output terminals WL_L and WL_R. Therefore, the suppressed word line WL is provided to the memory cells so as to drive these memory cells with a lower voltage or current.

[0073] In addition, reference Figure 5 In some embodiments, in response to control signal RASEL[0], transistor M3 is turned on and transistors M4-1 and M4-2 are turned off. Current signal Is1 is transmitted from node n3 to node n5 through resistor R3 and is further coupled to node n6 through resistor R5. Simultaneously, current signal Is2 is transmitted from node n4 to node n7 through resistor R4 and is further coupled to node n6 through resistor R6. Subsequently, current signals Is1 and Is2 are transmitted together from node n5 as current signal Is at node n6, and current signal Is is transmitted to ground through transistor M3. Thus, similar to the embodiment driven by control signal RASEL[1] as described above, the two corresponding output terminals WL_L and WL_R of the selected word line WL are modulated to have lower voltage or current values. Consequently, the suppressed word line WL is provided with a second voltage at its two corresponding output terminals WL_L and WL_R. This second voltage is different from the first voltage achieved by the embodiment driven by control signal RASEL[1].

[0074] In some embodiments, the control signal RASEL having a logic value of 0 or 1 is in the memory device (corresponding to, for example, Figure 1 The modulation circuit 530 is determined by the developer during the back-end manufacturing of the memory device. In some other embodiments, the modulation circuit 530 is configured to modulate the signal output from the word line driver WLD using one of various voltage or current values. Since the transistor M3 may have a different driving capability than each of the transistors M4-1 and M4-2, the second voltage on the selected word line driven by the control signal RASEL[0] is different from the first voltage on the selected word line driven by the control signal RASEL[1]. In various embodiments, the operation of selecting / determining the control signal RASEL[0] or RASEL[1] to drive the modulation circuit 530 is referred to as additional margin adjustment (EMA) of the memory device.

[0075] refer to Figure 6 . Figure 6 According to some embodiments of the present disclosure Figure 5 The word line driver WLD shown corresponds to a word line driver layout diagram 600 .

[0076] for Figure 6As shown in the figure, the layout structure of transistor M2 is arranged adjacent to the layout structure of transistor M1-1. The layout structure of transistor M1-1 is arranged between the layout structure of transistor M2 and transistor M4-1. The layout structure of transistor M4-1 is arranged between the layout structure of transistor M1-1 and transistor M3. The layout structure of transistor M3 is arranged between the layout structure of transistor M4-1 and transistor M4-2. The layout structure of transistor M4-2 is arranged between the layout structure of transistor M3 and transistor M1-2. The layout structure of transistor M1-2 is arranged between the layout structure of transistor M4-2 and transistor MH. In other words, in the layout diagram, the modulation circuit (including transistors M3, M4-1 and M4-2) is arranged between two separate drive circuits including transistors M1-1 and M1-2.

[0077] In some embodiments, transistors M2, M1-1, M4-1, M3, M4-2, M1-2, and MH have different driving capabilities to achieve the above reference Figure 3 and Figure 5 For example, refer to Figure 6 , the layout structure of transistor M2 has a length L2; the layout structure of transistor M1-1 or M1-2 has a length L1; the layout structure of transistor M4-1 or M4-2 has a length L4; the layout structure of transistor M3 has a length L3; and the layout structure of transistor MH has a length LH. In some embodiments, length L1 is greater than each of lengths LH, L3, and L4.

[0078] In some embodiments, at least two of the transistors M2, M1-1, M4-1, M3, M4-2, M1-2, and MH have the same driving capability to operate identically. Figure 6 , the layout structure of transistors M1-1 and M1-2 has the same length L1, and the layout structure of transistors M4-1 and M4-2 has the same length L4. Therefore, transistor M1-1 is the same as transistor M1-2, and transistor M4-1 is the same as transistor M4-2. Therefore, the internal resistance of transistor M1-1 (i.e., resistance element R1) is equal to the internal resistance of transistor M1-2 (i.e., resistance element R2). In addition, the internal resistance of transistor M4-1 (i.e., resistance element R3) is equal to the internal resistance of transistor M4-2 (i.e., resistance element R4). In alternative embodiments, length L2 is the same as length L1, or length L4 is the same as length L3.

[0079] In some embodiments, the layout structures of transistors M2, M1-1, M4-1, M3, M4-2, M1-2, and MH are separated from each other by different distances to form corresponding conductive tracks of different wiring lengths in several metal layers. Figure 6In the transistor layout shown, the middle of transistor M2 (i.e., half of transistor M2's length L2) is separated from the middle of transistor M1-1 (i.e., half of transistor M1-1's length L1) by a distance D1. The middle of transistor M1-1 (i.e., half of transistor M1-1's length L1) is separated from the middle of transistor M3 (i.e., half of transistor M3's length L3) by a distance D2, which is different from distance D1.

[0080] In some embodiments, Figure 4 In at least one of the transistor layout structures shown, transistors M2, M1-1, M4-1, M3, M4-2, M1-2, or MH are separated from each other by the same distance to form corresponding conductive tracks with the same wiring length. Figure 6 In the transistor layout shown, the middle of transistor M1-2 (i.e., half the length L1 of transistor M1-2) is separated from the middle of transistor M3 (i.e., half the length L3 of transistor M3) by a distance D2. Therefore, the length of the conductive track coupled between transistors M1-1 and M3 is the same as the length of the conductive track coupled between transistors M1-2 and M3, and is substantially equal to distance D2. Consequently, the internal resistance of the conductive line coupled between transistors M1-1 and M3 (including resistors R3 and R5) is equal to the internal resistance of the conductive line coupled between transistors M1-2 and M3 (including resistors R4 and R6).

[0081] In addition, reference Figure 6 ,for Figure 6 In the transistor layout structure shown, the middle of transistor M1-1 (i.e., half of the length L1 of transistor M1-1) is separated from the middle of transistor M4-1 (i.e., half of the length L4 of transistor M4-1) by a distance D3. In addition, the middle of transistor M1-2 (i.e., half of the length L1 of transistor M1-2) is separated from the middle of transistor M4-2 (i.e., half of the length L4 of transistor M4-2) by a distance D3. Therefore, based on the reference Figure 5 For the same reasons discussed above regarding distance D2, the internal resistance of the conductive line coupled between transistors M1-1 and M4-1 (ie, resistive element R3) is equal to the internal resistance of the conductive line coupled between transistors M1-2 and M4-2 (ie, resistive element R4).

[0082] refer to Figure 7 . Figure 7 According to some embodiments of the present disclosure Figure 1The word line driver WLD shown corresponds to an equivalent circuit 700 of the word line driver WLD. The word line driver WLD includes a header circuit 710, a driver circuit 720 (including driver circuits 721 and 722), a modulation circuit 730 (including modulation circuits 731 and 732), and resistor elements R0, R1, R2, and R3. Figure 7 The configuration and / or relationship between the head circuit 710, the drive circuits 721 and 722 in the embodiment are similar to those described above. Figure 2 or Figure 5 Therefore, they are not described in further detail here. Figure 2 or Figure 5 An embodiment of the word line driver WLD, Figure 7 The same elements in the drawings are marked with the same reference numerals for ease of understanding.

[0083] The header circuit 710 is coupled to the power supply voltage terminal VDD via a resistor element R0 and to the driver circuit 721 via a resistor element R1. The driver circuit 721 is coupled in parallel to the driver circuit 722 and is coupled to modulation circuits 731 and 732 via resistor elements R2 and R3, respectively. The driver circuit 722 is coupled between the output terminal WL_L (i.e., node n5) and ground. The modulation circuit 731 is coupled between the node n3 on the word line WL and ground. The modulation circuit 732 is coupled between the output terminal WL_R (i.e., node n4) on the word line WL and ground.

[0084] and Figure 2 Compared to the illustrated embodiment, the equivalent circuit 700 includes transistors MH1 , . . . , and MH2 coupled in parallel, and each of their drain terminals is further coupled to the driving circuit 721 via the node n1 .

[0085] Driver circuit 721 includes transistor M1, which in some embodiments is a PMOS transistor, and driver circuit 722 includes transistor M2, which in some embodiments is an NMOS transistor. The gate terminals of transistor M1 and transistor M2 are coupled together and further coupled to a wordline decoder (not shown), configured to be driven by the wordline decoder in response to a decoder signal MWLB. The source terminal of transistor M1 is coupled to node n1 via resistor R1 for receiving a signal output from header circuit 710. The drain terminal of transistor M1 is coupled to node n2 on wordline WL and further coupled to node n3 on wordline via resistor R2. Node n3 is also coupled to modulation circuit 731. Furthermore, the drain terminal of transistor M1 is coupled to node n2 and further coupled to node n4 (i.e., output terminal WL_R) via resistor R3. Node n4 is also coupled to modulation circuit 732. The source terminal of transistor M2 is coupled to node 5 (i.e., output terminal WL_L). In some embodiments, transistors M2 and M1 are configured to function as inverters.

[0086] In addition, the modulation circuit 731 includes a transistor M3-1, which in some embodiments is a PMOS transistor, and the modulation circuit 732 includes a transistor M3-2, which in some embodiments is a PMOS transistor. The gate terminal of the transistor M3-1 is coupled to a control circuit (not shown) for receiving a control signal RAEN outputted from the control circuit. The source terminal of the transistor M3-1 is coupled to a node n3 on the word line WL, and the drain terminal of the transistor M3-1 is coupled to ground. The gate terminal of the transistor M3-2 is also coupled to the control circuit (not shown) and is configured to be driven in response to the control signal RAEN. The source terminal of the transistor M3-2 is coupled to a node n4 (i.e., the output terminal WL_R), and the drain terminal of the transistor M3-2 is coupled to ground.

[0087] Furthermore, resistive element R1 is coupled between node n1 and transistor M1. Resistive element R2 is coupled between node n2 (also coupled to transistor M1) and node n3 (also coupled to transistor M3-1). Resistive element R3 is coupled between node n2 (also coupled to transistor M1) and node n4 (also coupled to transistor M3-2).

[0088] In some embodiments, for operation Figure 7 The method of the word line driver WLD shown is similar to that described above. Figure 3 Example of .

[0089] for Figure 3 The description of operation S310 shown is similar to that of reference Figure 2 Operation S310, referring to Figure 7, the transistor M1 of the driving circuit 721 is turned on in response to the decoder signal MWLB, and the word line WL coupled to the turned-on transistor M1 is indicated as the selected word line WL.

[0090] for Figure 3 The description of operation S320 shown is similar to that of reference Figure 2 Operation S320, referring to Figure 7 , transistors MH1 and MH2 of the header circuit 710 are turned on in response to the decoder signal MP0. A signal (e.g., current signal Is) is coupled from the power supply voltage terminal VDD to the node n1 through the transistors of the header circuit 710, and further coupled to the transistor M1 of the driver circuit 721 through the resistor element R1.

[0091] for Figure 3 The description of operation S330 shown is similar to that of reference Figure 2 Operation S330, referring to Figure 7 , the signal Is is transmitted to the node n2 on the selected word line WL through the transistor M1. Subsequently, the selected word line WL is charged at the node n2, which is further coupled to two separate nodes n5 (i.e., node WL_L) and n4 (i.e., node WL_R) to serve as output terminals of the word line driver WLD.

[0092] Since the node n2 is also represented as a shunt node on the word line WL, the signal coupled from the transistor M1 in operation S330 is divided into two partial signals Is1 and Is2. Figure 3 For a description of operation S340, refer to Figure 7 , transistor M3-1 of modulation circuit 731 and transistor M3-2 of modulation circuit 732 are turned on in response to control signal RAEN. Current signal Is1 is transmitted from node n2 to node n3 through resistor element R2 and is further coupled to ground through transistor M3-1. Simultaneously, current signal Is2 is transmitted from node n2 to node n4 through resistor element R3 and is further coupled to ground through transistor M3-2. As a result, the two corresponding output terminals WL_L and WL_R of the selected word line WL are modulated to have lower voltage or current values, providing an inhibited word line.

[0093] refer to Figure 8 . Figure 8 According to some embodiments of the present disclosure Figure 7 The word line driver WLD shown corresponds to a word line driver layout diagram 800 .

[0094] for Figure 8As shown in the diagram, the layout structure of transistor M2 is arranged adjacent to the layout structure of transistor M3-1. The layout structure of transistor M3-1 is arranged between the layout structure of transistor M2 and the layout structure of transistor M1. The layout structure of transistor M1 is arranged between the layout structure of transistor M3-1 and the layout structure of transistor M3-2. In other words, in the layout diagram, the driving circuit M1 is arranged between the two separate modulation circuits including transistors M3-1 and M3-2. The layout structure of transistor M3-2 is arranged between the layout structure of transistor M1 and the layout structure of transistor MH.

[0095] In some embodiments, transistors M2, M3-1, M1, M3-2, and MH have different driving capabilities to achieve the above reference Figure 3 and Figure 7 For example, refer to Figure 8 , the length of the transistor M2 is L2; ​​the length of the transistor M3-1 or M3-2 is L3; the length of the transistor M3 is L3; and the length of the transistor MH is LH.

[0096] In some embodiments, at least two of transistors M2, M3-1, M1, M3-2, and MH have the same driving capability to operate identically. Figure 8 In the transistor layout shown, transistors M3-1 and M3-2 have the same length, L3. Therefore, transistor M3-1 is identical to transistor M3-2. Therefore, the internal resistance of transistor M3-1 (i.e., resistive element R2) is equal to the internal resistance of transistor M3-2 (i.e., resistive element R3). In an alternative embodiment, length L2 is the same as length L1, and transistors M2, M3-1, and M3-2 are identical to one another.

[0097] In some embodiments, the layout structures of transistors M2, M3-1, M1, M3-2, and MH are separated from each other by different distances to form corresponding conductive tracks with different wiring lengths in several metal layers. Figure 8 In the transistor layout shown, the middle of transistor M2 (i.e., half of the length L2 of transistor M2) is separated from the middle of transistor M3-1 (i.e., half of the length L3 of transistor M3-1) by a distance D1. The middle of transistor M3-1 (i.e., half of the length L3 of transistor M3-1) is separated from the middle of transistor M1 (i.e., half of the length L1 of transistor M1) by a distance D2, which is different from distance D1.

[0098] In some embodiments, at least one of the layout structures of transistors M2, M3-1, M1, M3-2, and MH is separated from each other by the same distance to form corresponding conductive tracks with the same wiring length. Figure 8In the transistor layout shown, the middle of transistor M1 (i.e., half the length L1 of transistor M1) is separated from the middle of transistor M3-2 (i.e., half the length L3 of transistor M3-2) by a distance D2. Therefore, the length of the conductive track coupled between transistors M1 and M3-1 is the same as the length of the conductive track coupled between transistors M1 and M3-2, and is substantially equal to distance D2. Consequently, the internal resistance R2 of the conductive line coupled between transistors M1 and M3-1 is equal to the internal resistance R3 of the conductive line coupled between transistors M1 and M3-2.

[0099] Now refer to Figure 9 . Figure 9 is a block diagram of an electronic design automation (EDA) system 900 for designing an integrated circuit layout according to some embodiments of the present disclosure. The EDA system 900 is configured to implement Figure 3 disclosed in and combined with Figure 2-8 One or more operations of method 300 are further explained. In some embodiments, EDA system 900 includes an APR system.

[0100] In some embodiments, EDA system 900 is a general-purpose computing device that includes a hardware processor 920 and a non-transitory computer-readable storage medium 960. Storage medium 960 is encoded with (i.e., stores) computer program code (instructions) 961, i.e., a set of executable instructions. Execution of instructions 961 by hardware processor 920 (at least in part) represents an EDA tool that implements, for example, part or all of method 300.

[0101] The processor 920 is electrically coupled to a computer-readable storage medium 960 via a bus 950. The processor 920 is also electrically coupled to an I / O interface 910 and a manufacturing tool 970 via the bus 950. A network interface 930 is also electrically connected to the processor 920 via the bus 950. The network interface 930 is connected to a network 940 so that the processor 920 and the computer-readable storage medium 960 can be connected to external components via the network 940. The processor 920 is configured to execute computer program code 961 encoded in the computer-readable storage medium 960 so that the EDA system 900 can be used to perform part or all of the processes and / or methods described. In one or more embodiments, the processor 920 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0102] In one or more embodiments, the computer-readable storage medium 960 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 960 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 960 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0103] In one or more embodiments, the storage medium 960 stores computer program code 961 configured to enable the EDA system 900 (where such execution is (at least in part) on behalf of an EDA tool) to perform part or all of the described processes and / or methods. In one or more embodiments, the storage medium 960 also stores information that facilitates the execution of part or all of the described processes and / or methods. In one or more embodiments, the storage medium 960 stores a library 962 of standard cells, including such standard cells as disclosed herein, for example, as described above with respect to Figure 1 The memory cell array 110 or 120 in question includes memory cells MC.

[0104] EDA system 900 includes an I / O interface 910. I / O interface 910 is coupled to external circuitry. In one or more embodiments, I / O interface 910 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or cursor direction keys for communicating information and commands to processor 920.

[0105] EDA system 900 also includes a network interface 930 coupled to processor 920. Network interface 930 allows EDA system 900 to communicate with a network 940 to which one or more other computer systems are connected. Network interface 930 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 900.

[0106] The EDA system 900 also includes a fabrication tool 970 coupled to the processor 920. The fabrication tool 970 is configured to fabricate an integrated circuit based on the design file processed by the processor 920 and / or the IC layout design as described above, including, for example Figure 1 The memory device 100 is shown.

[0107] The EDA system 900 is configured to receive information through an I / O interface 910. The information received through the I / O interface 910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 920. The information is transmitted to the processor 920 via a bus 950. The EDA system 900 is configured to receive information related to a UI through the I / O interface 910. This information is stored in a computer-readable medium 960 as a user interface (UI) 963.

[0108] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 900. In some embodiments, the system is implemented using a software application such as that available from CADENCE DESIGN SYSTEMS, Inc. A tool such as , or another suitable layout generation tool, is used to generate a layout diagram including standard cells.

[0109] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., hard disk), a semiconductor memory (e.g., ROM, RAM), a memory card, and the like.

[0110] Figure 10 1 is a block diagram of an IC manufacturing system 1000 and an associated IC manufacturing process according to some embodiments of the present disclosure. In some embodiments, based on a layout diagram, the IC manufacturing system 1000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0111] exist Figure 10In the present invention, IC manufacturing system 1000 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 1040, such as design room 1010, mask room 1020, and IC manufacturer / fabricator ("fab") 1030. The entities in IC manufacturing system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1010, mask room 1020, and IC manufacturer / fabricator 1030 are owned by a single larger company. In some embodiments, two or more of design room 1010, mask room 1020, and IC manufacturer / fabricator 1030 coexist in a common facility and use common resources.

[0112] The design office (or design team) 1010 generates an IC design layout 1011. The IC design layout 1011 includes a plurality of IC components 1040 (e.g., Figure 1 The memory device 100 shown includes the above reference Figure 2 、 Figure 5 and / or Figure 7 Various geometric patterns (e.g., Figure 4 、 Figure 6 and / or Figure 8 10). The IC layout design depicted). The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers of the various components that make up the IC device 1040 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1011 includes various IC features (e.g., fins, gate electrodes, source and drain, conductive segments or vias for interconnecting layers, and openings for pads) formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers disposed on the semiconductor substrate. The design studio 1010 implements an appropriate design process to form the IC design layout diagram 1011. The design process includes one or more of logical design, physical design, or layout and routing. The IC design layout diagram 1011 is presented in one or more data files having geometric pattern information. For example, the IC design layout diagram 1011 can be expressed in a GDSII file format or a DFII file format.

[0113] The mask chamber 1020 includes mask data preparation 1021 and mask fabrication 1022. The mask chamber 1020 uses the IC design layout drawing 1011 to fabricate one or more masks 1023, which are used to fabricate various layers of the IC device 1040 based on the IC design layout drawing 1011. The mask chamber 1020 performs mask data preparation 1021, wherein the IC design layout drawing 1011 is converted into a representative data file ("RDF"). The mask data preparation 1021 provides the RDF to the mask fabrication 1022. The mask fabrication 1022 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1023 or a semiconductor wafer 1033. The mask data preparation 1021 processes the IC design layout drawing 1011 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / fabricator 1030. In Figure 10 , mask data preparation 1021 and mask fabrication 1022 are shown as separate elements. In some embodiments, mask data preparation 1021 and mask fabrication 1022 may be collectively referred to as mask data preparation.

[0114] In some embodiments, mask data preparation 1021 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1011. In some embodiments, data preparation 1021 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0115] In some embodiments, data preparation 1021 includes a mask rule checker (MRC) that checks an IC design layout 1011, which has been processed in OPC, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1011 to compensate for the constraints during mask fabrication 1022, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0116] In some embodiments, data preparation 1021 includes a lithography process check (LPC), which simulates a process that will be performed by the IC manufacturer / fabricator 1030 to manufacture the IC device 1040. The LPC simulates the process based on the IC design layout drawing 1011 to create a simulated manufactured device, for example, the IC device 1040. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after the simulated manufactured device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout drawing 1011.

[0117] It should be understood that the above description of data preparation 1021 has been simplified for clarity. In some embodiments, data preparation 1021 includes additional features such as logic operations (LOPs) to modify IC design layout 1011 according to manufacturing rules. Furthermore, the processes applied to IC design layout 1011 during data preparation 1021 can be performed in a variety of different orders.

[0118] After data preparation 1021 and during mask fabrication 1022, a mask 1023 or a set of masks 1023 are fabricated based on the modified IC design layout 1011. In some embodiments, mask fabrication 1022 includes performing one or more photolithographic exposures based on the IC design layout 1011. In some embodiments, an electron beam (e-beam) or a plurality of electron beams are used to form a pattern on a mask (photomask or reticle) 1023 based on the modified IC design layout 1011. The mask 1023 can be formed using various techniques. In some embodiments, the mask 1023 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) that has been applied to the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1023 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1023 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1023, the various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1022 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in semiconductor wafer 1033, in an etching process to form various etched regions in semiconductor wafer 1033, and / or in other suitable processes.

[0119] IC manufacturer / fabricator 1030 includes wafer fabrication 1032. IC manufacturer / fabricator 1030 is an IC manufacturing enterprise that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer / fabricator 1030 is a semiconductor foundry. For example, there may be one fabrication facility for front-end fabrication (front-end of line (FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end of line (BEOL) fabrication) for interconnecting and packaging IC products, and a third fabrication facility may provide other services for the foundry.

[0120] IC manufacturer / fabricator 1030 uses (one or more) masks 1023 manufactured by mask chamber 1020 to manufacture IC device 1040. Therefore, IC manufacturer / fabricator 1030 uses IC design layout 1011 at least indirectly to manufacture IC device 1040. In some embodiments, semiconductor wafer 1033 is manufactured by IC manufacturer / fabricator 1030 using (one or more) masks 1023 to form IC device 1040. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1011. Semiconductor wafer 1033 includes a silicon substrate, or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1033 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0121] In addition, in some embodiments of the present disclosure, at least one of the transistors is implemented by at least one metal oxide semiconductor (MOS) transistor, at least one bipolar junction transistor (BJT), etc., or a combination thereof. Various circuits or devices implementing the transistors in the aforementioned embodiments are within the intended scope of the present disclosure.

[0122] In some embodiments, a memory device is disclosed. The memory device includes a wordline driver. The wordline driver is coupled to an array of bit cells arranged in rows and columns via a plurality of wordlines. The wordline driver includes a first driver circuit, a second driver circuit, and a modulation circuit. The first driver circuit and the second driver circuit are configured to select one wordline from the plurality of wordlines. The modulation circuit is coupled to the first driver circuit and the second driver circuit via the selected wordline and is configured to modulate at least one signal transmitted via the selected wordline. The first driver circuit and the second driver circuit are further configured to charge the selected wordline to generate a first voltage signal and a second voltage signal at two locations on the selected wordline. The first voltage signal and the second voltage signal are substantially identical.

[0123] In some embodiments, the modulation circuit is coupled to the first driver circuit and the second driver circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

[0124] In some embodiments, the word line driver further includes a header circuit coupled to the first driver circuit and the second driver circuit and configured to provide substantially the same operating voltage signal to the first driver circuit and the second driver circuit.

[0125] In some embodiments, the modulation circuit includes at least one switch. The at least one switch is coupled to the first drive circuit and the second drive circuit. The at least one switch is configured to couple the first voltage signal and the second voltage signal to a reference voltage terminal. The first drive circuit is identical to the second drive circuit.

[0126] In some embodiments, the modulation circuit includes two first switches and a second switch. The two first switches are configured to couple a selected word line to a reference voltage terminal in response to a control signal having a first logic value. The second switch is coupled between the first switches and in parallel with the first switches. The second switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal having a second logic value.

[0127] In some embodiments, in a layout diagram, the second switch is arranged between the first switches, and the first switch is arranged between the first driver circuit and the second driver circuit. In the layout diagram, an area of ​​one of the first switches is substantially the same as an area of ​​the other of the first switches and is smaller than an area of ​​at least one of the first driver circuit or the second driver circuit.

[0128] Also disclosed is a memory device including a plurality of bit cells and a word line driver. The plurality of bit cells are arranged in rows and columns. The word line driver is coupled between a power supply voltage terminal and a reference voltage terminal and is coupled to the plurality of bit cells via a plurality of word lines. The word line driver is configured to select a word line from a plurality of word lines in a first row. The word line driver includes at least one driver circuit, a first modulation circuit, and a second modulation circuit. The at least one driver circuit is configured to generate a first voltage signal on the selected word line at a first node, the first node being coupled to some of the plurality of bit cells in the first row. The at least one driver circuit is further configured to generate a second voltage signal on the selected word line at a second node, the second node being coupled to other of the plurality of bit cells in the first row. The first modulation circuit and the second modulation circuit are coupled between the reference voltage terminal and at least one of the first node or the second node. The first modulation circuit and the second modulation circuit are configured to modulate the first and second voltage signals on the selected word line.

[0129] In some embodiments, the at least one driving circuit is coupled to the first modulation circuit and the second modulation circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

[0130] In some embodiments, the first modulation circuit includes a first switch coupled between a first node and a reference voltage terminal. The second modulation circuit includes a second switch coupled between a second node and the reference voltage terminal. Each of the first switch and the second switch is configured to couple the selected word line to the reference voltage terminal in response to the control signal when the at least one driver circuit is activated in response to the decoder signal.

[0131] In some embodiments, in the layout diagram, the at least one driving circuit is arranged between the first modulation circuit and the second modulation circuit. In the layout diagram, the distance between the first modulation circuit and the at least one driving circuit is substantially equal to the distance between the second modulation circuit and the at least one driving circuit.

[0132] In some embodiments, the first modulation circuit includes a first switch. The second modulation circuit includes a second switch and a third switch. The first switch, the second switch, and the third switch are coupled in parallel between the selected word line and the reference voltage terminal. The second switch is identical to the third switch.

[0133] In some embodiments, the first switch is coupled to the second switch and the third switch respectively through two first portions of the selected word line, the two first portions corresponding to substantially the same equivalent resistance. The second switch and the third switch are coupled to the first node and the second node respectively through two second portions of the selected word line, the two second portions corresponding to substantially the same equivalent resistance.

[0134] In some embodiments, when the at least one driver circuit is activated in response to the decoder signal, the first switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal having a first logic value, or each of the second switch and the third switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal having a second logic value.

[0135] In some embodiments, the at least one driver circuit includes a first driver circuit and a second driver circuit. The first driver circuit is coupled to a first node and configured to generate a first voltage signal on a selected word line at the first node in response to a decoder signal. The second driver circuit is coupled to a second node and configured to generate a second voltage signal on the selected word line at the second node in response to the decoder signal. The first voltage signal and the second voltage signal are substantially the same.

[0136] In some embodiments, the wordline driver further includes a header circuit. The header circuit is coupled between a power supply voltage terminal and the at least one driver circuit. The header circuit includes at least one first switch and at least one second switch. The at least one first switch is coupled to the first driver circuit via a first equivalent resistor. The at least one second switch is coupled in parallel with the at least one first switch and coupled to the second driver circuit via a second equivalent resistor, the second equivalent resistor being substantially the same as the first equivalent resistor.

[0137] Also disclosed is a method comprising the following operations: selecting a word line from a plurality of word lines coupled to an array of bit cells; generating a first voltage signal at a first node and a second voltage signal at a second node by a first driver circuit and a second driver circuit; modulating the first and second voltage signals by a modulation circuit; coupling the first driver circuit to the selected word line at a first node, and coupling the second driver circuit to the selected word line at a second node.

[0138] In some embodiments, generating the first voltage signal and the second voltage signal includes the following operations: a power supply voltage signal at a power supply voltage terminal where the first drive circuit and the second drive circuit are coupled in parallel is coupled to a first node and a second node via a first equivalent resistor and a second equivalent resistor, respectively. The first equivalent resistor and the second equivalent resistor are substantially the same.

[0139] In some embodiments, the operation of modulating the first voltage signal and the second voltage signal includes the following operations: the first voltage signal at the first node is coupled to a reference voltage terminal via a first equivalent resistor. The second voltage signal at the second node is coupled to the reference voltage terminal via a second equivalent resistor. The first equivalent resistor and the second equivalent resistor are substantially the same.

[0140] In some embodiments, the operation of modulating the first voltage signal and the second voltage signal includes the following operations: in response to a control signal having a first logic value, the first voltage signal at the first node and the second voltage signal at the second node are coupled to a reference voltage terminal through a first equivalent resistor and a second equivalent resistor, respectively, via two first switches of the modulation circuit, wherein the second equivalent resistor is substantially the same as the first equivalent resistor. In response to a control signal having a second logic value, the first voltage signal at the first node and the second voltage signal at the second node are coupled to the reference voltage terminal through a third equivalent resistor and a fourth equivalent resistor, respectively, via the second switch of the modulation circuit, wherein the fourth equivalent resistor is substantially the same as the third equivalent resistor.

[0141] In some embodiments, the method further comprises the following operations. A layout diagram of a memory device including a first driver circuit, a second driver circuit, and a modulation circuit is generated. Based on the layout diagram, at least one of the following items is manufactured: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit. In the layout diagram, the modulation circuit is arranged between the first driver circuit and the second driver circuit, and the area of ​​the modulation circuit is smaller than the area of ​​at least one of the first driver circuit or the second driver circuit.

[0142] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0143] Example 1. A memory device comprising: a word line driver coupled to an array of bit cells arranged in rows and columns through a plurality of word lines, the word line driver comprising: a first driver circuit and a second driver circuit configured to select one word line from the plurality of word lines; and a modulation circuit coupled to the first driver circuit and the second driver circuit through the selected word line and configured to modulate at least one signal transmitted through the selected word line, wherein the first driver circuit and the second driver circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions on the selected word line, and the first voltage signal is substantially the same as the second voltage signal.

[0144] Example 2. The memory device of Example 1, wherein the modulation circuit is coupled to the first driver circuit and the second driver circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

[0145] Example 3. The memory device of Example 1, wherein the word line driver further comprises: a header circuit coupled to the first driver circuit and the second driver circuit and configured to provide substantially the same operating voltage signal to the first driver circuit and the second driver circuit.

[0146] Example 4. A memory device according to Example 1, wherein the modulation circuit includes: at least one switch, the at least one switch coupled to the first drive circuit and the second drive circuit, and configured to couple the first voltage signal and the second voltage signal to a reference voltage terminal, wherein the first drive circuit is the same as the second drive circuit.

[0147] Example 5. A memory device according to Example 1, wherein the modulation circuit includes: two first switches, which are configured to couple the selected word line to a reference voltage terminal in response to a control signal having a first logic value; and a second switch, which is coupled between the first switches and in parallel with the first switch and is configured to couple the selected word line to the reference voltage terminal in response to the control signal having a second logic value.

[0148] Example 6. A memory device according to Example 5, wherein, in a layout diagram, the second switch is arranged between the first switches, and the first switch is arranged between the first drive circuit and the second drive circuit, and an area of ​​one of the first switches is substantially the same as an area of ​​the other of the first switches and is smaller than an area of ​​at least one of the first drive circuit or the second drive circuit.

[0149] Example 7. A memory device comprising: a plurality of bit cells arranged in rows and columns; and a word line driver coupled between a power supply voltage terminal and a reference voltage terminal and coupled to the plurality of bit cells through a plurality of word lines, wherein the word line driver is configured to select one word line of the plurality of word lines in a first row, and the word line driver comprises: at least one driver circuit configured to generate a first voltage signal on the selected word line at a first node, the first node being coupled to some of the plurality of bit cells in the first row, and the at least one driver circuit configured to generate a second voltage signal on the selected word line at a second node, the second node being coupled to other some of the plurality of bit cells in the first row; and a first modulation circuit and a second modulation circuit coupled between the reference voltage terminal and at least one of the first node or the second node, and configured to modulate the first voltage signal and the second voltage signal on the selected word line.

[0150] Example 8. The memory device of Example 7, wherein the at least one driving circuit is coupled to the first modulation circuit and the second modulation circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

[0151] Example 9. A memory device according to Example 7, wherein the first modulation circuit includes a first switch, wherein the first switch is coupled between the first node and the reference voltage terminal, the second modulation circuit includes a second switch, wherein the second switch is coupled between the second node and the reference voltage terminal, and each of the first switch and the second switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal when the at least one driver circuit is activated in response to a decoder signal.

[0152] Example 10. A memory device according to Example 7, wherein, in the layout diagram, the at least one driving circuit is arranged between the first modulation circuit and the second modulation circuit, and the distance between the first modulation circuit and the at least one driving circuit is substantially equal to the distance between the second modulation circuit and the at least one driving circuit.

[0153] Example 11. A memory device according to Example 7, wherein the first modulation circuit includes a first switch, the second modulation circuit includes a second switch and a third switch, the first switch, the second switch, and the third switch are coupled in parallel with each other between the selected word line and the reference voltage terminal, and the second switch is identical to the third switch.

[0154] Example 12. A memory device according to Example 11, wherein the first switch is coupled to the second switch and the third switch respectively through two first portions of the selected word line, the two first portions corresponding to substantially the same equivalent resistance, and the second switch and the third switch are coupled to the first node and the second node respectively through two second portions of the selected word line, the two second portions corresponding to substantially the same equivalent resistance.

[0155] Example 13. A memory device according to Example 11, wherein, when the at least one driving circuit is activated in response to a decoder signal, the first switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal having a first logic value, or each of the second switch and the third switch is configured to couple the selected word line to the reference voltage terminal in response to the control signal having a second logic value.

[0156] Example 14. A memory device according to Example 7, wherein the at least one driver circuit includes a first driver circuit and a second driver circuit, the first driver circuit is coupled to the first node and is configured to generate the first voltage signal on the selected word line at the first node in response to a decoder signal, the second driver circuit is coupled to the second node and is configured to generate the second voltage signal on the selected word line at the second node in response to the decoder signal, and the first voltage signal is substantially the same as the second voltage signal.

[0157] Example 15. The memory device of Example 14, wherein the word line driver further comprises: a header circuit coupled between the power supply voltage terminal and the at least one driver circuit, wherein the header circuit comprises: at least one first switch coupled to the first driver circuit via a first equivalent resistance; and at least one second switch coupled in parallel with the at least one first switch and coupled to the second driver circuit via a second equivalent resistance, the second equivalent resistance being substantially the same as the first equivalent resistance.

[0158] Example 16. A method comprising: selecting a word line of a plurality of word lines coupled to an array of bit cells; generating a first voltage signal at a first node and a second voltage signal at a second node by a first driver circuit and a second driver circuit, wherein the first driver circuit is coupled to the selected word line at the first node and the second driver circuit is coupled to the selected word line at the second node; and modulating the first voltage signal and the second voltage signal by a modulation circuit.

[0159] Example 17. A method according to Example 16, wherein generating the first voltage signal and the second voltage signal includes: coupling the power supply voltage signal at the power supply voltage terminal where the first drive circuit and the second drive circuit are coupled in parallel to the first node and the second node through a first equivalent resistor and a second equivalent resistor, respectively, wherein the first equivalent resistor is substantially the same as the second equivalent resistor.

[0160] Example 18. A method according to Example 16, wherein modulating the first voltage signal and the second voltage signal includes: coupling the first voltage signal at the first node to a reference voltage terminal through a first equivalent resistor, and coupling the second voltage signal at the second node to the reference voltage terminal through a second equivalent resistor, wherein the first equivalent resistor is substantially the same as the second equivalent resistor.

[0161] Example 19. A method according to Example 16, wherein modulating the first voltage signal and the second voltage signal includes: in response to a control signal having a first logic value, coupling the first voltage signal at the first node and the second voltage signal at the second node to a reference voltage terminal through a first equivalent resistor and a second equivalent resistor, respectively, via two first switches of the modulation circuit, and the second equivalent resistor is substantially the same as the first equivalent resistor; or in response to the control signal having a second logic value, coupling the first voltage signal at the first node and the second voltage signal at the second node to the reference voltage terminal through a third equivalent resistor and a fourth equivalent resistor, respectively, via the second switch of the modulation circuit, and the fourth equivalent resistor is substantially the same as the third equivalent resistor.

[0162] Example 20. The method according to Example 16 further includes: generating a layout diagram of a memory device including the first driver circuit, the second driver circuit and the modulation circuit; and based on the layout diagram, manufacturing at least one of the following items: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit, wherein, in the layout diagram, the modulation circuit is arranged between the first driver circuit and the second driver circuit, and the area of ​​the modulation circuit is smaller than the area of ​​at least one of the first driver circuit or the second driver circuit.

Claims

1. A storage device comprising: A word line driver coupled to an array of bit cells arranged in rows and columns through a plurality of word lines, the word line driver comprising: a first driver circuit and a second driver circuit configured to select one word line among the plurality of word lines; and a modulation circuit coupled to the first driver circuit and the second driver circuit through the selected word line and configured to modulate at least one signal transmitted through the selected word line, The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two locations of the selected word line, and the first voltage signal is substantially the same as the second voltage signal. The first driving circuit includes a first switch, and The second drive circuit includes a second switch, and a control terminal of the first switch is coupled to a control terminal of the second switch.

2. The memory device according to claim 1, wherein The modulation circuit is coupled to the first driving circuit and the second driving circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

3. The memory device according to claim 1, wherein The word line driver further includes: A header circuit is coupled to the first driving circuit and the second driving circuit and is configured to provide substantially the same operating voltage signal to the first driving circuit and the second driving circuit.

4. The memory device according to claim 1, wherein The modulation circuit includes: at least one switch coupled to the first drive circuit and the second drive circuit and configured to couple the first voltage signal and the second voltage signal to a reference voltage terminal, The first driving circuit is the same as the second driving circuit.

5. The memory device according to claim 1, wherein The modulation circuit includes: two third switches configured to couple the selected word line to a reference voltage terminal in response to a control signal having a first logic value; and A fourth switch is coupled between and in parallel with the third switches and is configured to couple the selected word line to the reference voltage terminal in response to the control signal having a second logic value. The memory device according to claim 5 , wherein: In the layout diagram, The fourth switch is arranged between the third switches, and the third switch is arranged between the first drive circuit and the second drive circuit, and An area of ​​one of the third switches is substantially the same as an area of ​​another one of the third switches and is smaller than an area of ​​at least one of the first drive circuit or the second drive circuit.

7. A storage device comprising: a plurality of bit cells arranged in rows and columns; as well as a word line driver coupled between a power supply voltage terminal and a reference voltage terminal and coupled to the plurality of bit cells through a plurality of word lines, The word line driver is configured to select one word line among the plurality of word lines in the first row, and the word line driver comprises: at least one driver circuit configured to generate a first voltage signal on a selected word line at a first node coupled to a first portion of the plurality of bit cells in the first row, and to generate a second voltage signal on the selected word line at a second node coupled to a second portion of the plurality of bit cells in the first row; and a first modulation circuit and a second modulation circuit, the first modulation circuit and the second modulation circuit being coupled between the reference voltage terminal and at least one of the first node or the second node and configured to modulate the first voltage signal and the second voltage signal on the selected word line, wherein the first portion is different from the second portion, and The resistance between the at least one driving circuit and the first portion is substantially equal to the resistance between the at least one driving circuit and the second portion.

8. The memory device according to claim 7, wherein: The at least one driving circuit is coupled to the first modulation circuit and the second modulation circuit respectively through two portions of the selected word line, the two portions corresponding to substantially the same equivalent resistance.

9. The memory device according to claim 7, wherein: The first modulation circuit includes a first switch, wherein the first switch is coupled between the first node and the reference voltage terminal, The second modulation circuit includes a second switch, wherein the second switch is coupled between the second node and the reference voltage terminal, and Each of the first switch and the second switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal when the at least one driving circuit is activated in response to a decoder signal.

10. The memory device according to claim 7, wherein In the layout diagram, The at least one driving circuit is arranged between the first modulation circuit and the second modulation circuit, and A distance between the first modulation circuit and the at least one driving circuit is substantially equal to a distance between the second modulation circuit and the at least one driving circuit.

11. The memory device according to claim 7, wherein: The first modulation circuit includes a first switch, The second modulation circuit includes a second switch and a third switch, The first switch, the second switch, and the third switch are coupled in parallel with each other between the selected word line and the reference voltage terminal, and The second switch is identical to the third switch.

12. The memory device according to claim 11, wherein The first switch is coupled to the second switch and the third switch through two first portions of the selected word line, respectively, the two first portions corresponding to substantially the same equivalent resistance, and The second switch and the third switch are coupled to the first node and the second node, respectively, through two second portions of the selected word line, the two second portions corresponding to substantially the same equivalent resistance.

13. The memory device according to claim 11, wherein When the at least one driver circuit is activated in response to the decoder signal, The first switch is configured to couple the selected word line to the reference voltage terminal in response to a control signal having a first logic value, or Each of the second switch and the third switch is configured to couple the selected word line to the reference voltage terminal in response to the control signal having a second logic value.

14. The memory device according to claim 7, wherein: The at least one driving circuit includes a first driving circuit and a second driving circuit, The first driver circuit is coupled to the first node and configured to generate the first voltage signal on the selected word line at the first node in response to a decoder signal, The second driver circuit is coupled to the second node and is configured to generate the second voltage signal on the selected word line at the second node in response to the decoder signal, and The first voltage signal is substantially the same as the second voltage signal.

15. The memory device according to claim 14, wherein The word line driver further includes: a header circuit coupled between the power supply voltage terminal and the at least one driver circuit, wherein the header circuit comprises: at least one first switch, the at least one first switch being coupled to the first driving circuit via a first equivalent resistor; and At least one second switch is coupled in parallel with the at least one first switch and is coupled to the second drive circuit via a second equivalent resistor, wherein the second equivalent resistor is substantially the same as the first equivalent resistor.

16. A method for a memory device, comprising: selecting a word line of a plurality of word lines coupled to the array of bit cells; generating a first voltage signal at a first node and a second voltage signal at a second node by a first driver circuit and a second driver circuit, wherein the first driver circuit is coupled to a selected word line at the first node and the second driver circuit is coupled to the selected word line at the second node; modulating the first voltage signal and the second voltage signal by a modulation circuit; receiving a decoder signal via a control terminal of a first switch in the first driving circuit; and The decoder signal is received through a control terminal of a second switch in the first driving circuit.

17. The method according to claim 16, wherein Generating the first voltage signal and the second voltage signal includes: coupling a power supply voltage signal at a power supply voltage terminal where the first drive circuit and the second drive circuit are coupled in parallel to the first node and the second node through a first equivalent resistor and a second equivalent resistor, respectively; The first equivalent resistance is substantially the same as the second equivalent resistance.

18. The method according to claim 16, wherein Modulating the first voltage signal and the second voltage signal includes: coupling the first voltage signal at the first node to a reference voltage terminal through a first equivalent resistor, and coupling the second voltage signal at the second node to the reference voltage terminal through a second equivalent resistor, The first equivalent resistance is substantially the same as the second equivalent resistance.

19. The method according to claim 16, wherein Modulating the first voltage signal and the second voltage signal includes: In response to a control signal having a first logic value, coupling the first voltage signal at the first node and the second voltage signal at the second node to a reference voltage terminal through a first equivalent resistor and a second equivalent resistor, respectively, via two third switches of the modulation circuit, the second equivalent resistor being substantially the same as the first equivalent resistor; or In response to the control signal having a second logic value, the first voltage signal at the first node and the second voltage signal at the second node are coupled to the reference voltage terminal through a third equivalent resistor and a fourth equivalent resistor, respectively, via a fourth switch of the modulation circuit, and the fourth equivalent resistor is substantially the same as the third equivalent resistor.

20. The method of claim 16, further comprising: generating a layout diagram of a memory device including the first driving circuit, the second driving circuit, and the modulation circuit; and manufacturing at least one of the following based on the layout: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit, In the layout diagram, the modulation circuit is arranged between the first driving circuit and the second driving circuit, and the area of ​​the modulation circuit is smaller than the area of ​​at least one of the first driving circuit or the second driving circuit.

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