Single-staircase read of memory cells coarsely programmed via interleaved two-pass data programming technique

Abstract

The present application relates to single-staircase reading of memory cells coarsely programmed via an interleaved two-pass data programming technique. A memory system is used to store multiple data bits in a memory cell. A memory device coarsely programs the threshold voltage of the memory cell to a first level representing a combination of bit values ​​based on a mapping between bit value combinations and threshold levels. The threshold levels are divided into groups, each group containing a subset of the threshold levels and having an associated read voltage that separates the threshold levels in the subset. A group identifier is determined for the memory cell, the first group of the groups containing the first level. The memory device applies read voltages from different groups interleaved in increasing order in a sequence to read the memory cell when the applied read voltage is associated with the first group. The threshold voltage of the memory cell is finely programmed using the data bits read back from the memory cell.

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, techniques for programming voltage thresholds of memory cells in a memory system to store multiple bits of data per memory cell. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present application provides a method comprising: receiving a plurality of pages of data bits; programming a threshold voltage of each respective memory cell in a page of memory cells to a respective first level representing a combination of bit values ​​according to a first mapping between combinations of bit values ​​and threshold levels, each bit value being from one of the plurality of pages of data bits, each of the threshold levels being in one of a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having a set of associated read voltages separating the threshold levels in the subsets; calculating a group identification for the respective memory cells, the group identification identifying a first group among the plurality of groups, the first group containing the respective first level, the group identification having at least two bits; ramping a voltage applied to the page of memory cells to a sequence of read voltages in increasing order to retrieve the plurality of pages of data bits from the page of memory cells, wherein the read voltages for the plurality of groups are interleaved in the sequence; and determining whether the threshold voltage of the respective memory cell is lower than a read voltage in the sequence when the read voltage applied to the page of memory cells is associated with the first group.

[0004] In another aspect, the present application further provides a memory device comprising: an integrated circuit package enclosing the memory device; a plurality of memory cell pages formed on at least one integrated circuit die; and a latch; wherein in response to a command identifying a memory cell page within the plurality of memory cell pages, the memory device is configured to receive a plurality of data bit pages in the latch; in a first pass, programming a threshold voltage of each respective memory cell in the memory cell page to a respective first level representing a combination of bit values ​​according to a mapping between combinations of bit values ​​and threshold levels, each bit value being from one of the plurality of data bit pages, the threshold levels being divided into a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having a set of associated read voltages separating the threshold levels in the subset; calculating at least two page bits of a group identifier, the respective memory cells having a group identifier. an identification, wherein the group identification has one bit in each of the at least two pages, the group identification of the corresponding memory cell identifying a first group among the plurality of groups, the first group containing the corresponding first levels to which the corresponding memory cells were programmed in the first pass; increasing the voltage applied to the memory cell page to a sequence of read voltages in increasing order to read the memory cell page, wherein the read voltages of the plurality of groups are interleaved in the sequence; determining the plurality of pages of data bits read into the latch based on whether the threshold voltage of the corresponding memory cell is lower than the read voltage in the sequence when the read voltage applied to the memory cell page is associated with the first group; and in a second pass, programming the threshold voltages of the corresponding memory cells in the memory cell page to the corresponding first levels representing the combination of bit values ​​according to the mapping.

[0005] In yet another aspect, the present application further provides a memory subsystem comprising: a processing device; and at least one memory device, the memory device having a plurality of memory cell pages, including a first memory cell page and at least two second memory cell pages; wherein the processing device is configured to provide a plurality of data pages to the memory device and identify the first memory cell page to store the plurality of data pages; wherein in response to the plurality of data pages, the memory device is configured to: perform a first programming pass on the first memory cell page, wherein a threshold voltage of each corresponding memory cell in the first memory cell page is programmed to a corresponding first level representing a combination of bit values ​​according to a mapping between a combination of bit values ​​and threshold levels, each bit value being from one of the plurality of data pages, the threshold levels being divided into a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having a set of associated read voltages separating the threshold levels in the subset; and calculate at least two page bits of a group identifier, the corresponding memory cells a memory cell having a group identifier having one bit in each of the at least two pages, the group identifier being calculated to identify a first group among the plurality of groups, the first group containing the respective first levels to which the respective memory cells were programmed in the first programming pass; buffering the at least two page bits of the group identifier in the at least two second memory cell pages in a single-level cell (SLC) mode; increasing a voltage applied to the memory cell page to a sequence of read voltages in increasing order to read the first memory cell page, wherein the read voltages for the plurality of groups are interleaved in the sequence; determining the plurality of pages of data bits based on whether the threshold voltage of the respective memory cells is lower than a read voltage in the sequence in response to a determination that the read voltage applied to the memory cell page is associated with the first group; and in a second pass, programming the threshold voltages of the respective memory cells in the first memory cell page to the respective first levels representing the combination of bit values ​​according to the mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0007] Figure 1 An example computing system having a memory subsystem is described according to some embodiments of the present disclosure.

[0008] Figure 2 An integrated circuit memory device having a program manager configured to program the threshold voltages of memory cells to store data is described according to one embodiment.

[0009] Figure 3An example of programming memory cells to store multiple bits per memory cell is shown according to one embodiment.

[0010] Figure 4 A two-pass programming technique that stores multiple bits per memory cell is shown according to one embodiment.

[0011] Figure 5 Voltage distributions for two-pass programming of memory cells are described according to one embodiment.

[0012] Figure 6 Mapping to threshold levels and group identifications in a two-pass programming of memory cells to store data is shown according to one embodiment.

[0013] Figure 7

[0014] Techniques to coarsely program memory cells to store data at the QLC level and to read the coarsely programmed memory cells are shown according to one embodiment.

[0014] Figure 8

[0066] Another technique to read coarsely programmed memory cells is shown according to one embodiment.

[0015] Figure 9

[0014] A technique to determine the value of a bit stored in a memory cell coarsely programmed at a set of predefined threshold levels is shown according to one embodiment.

[0016] Figure 10

[0014] A method to read memory cells that are coarsely programmed in a set of predefined threshold levels is shown according to one embodiment.

[0017] Figure 11

[0066] A technique for reading two bits of a memory cell coarsely programmed in QLC mode is described according to one embodiment.

[0018] Figure 12 A method of two-pass programming of memory cells is shown according to some embodiments.

[0019] Figure 13 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0020] At least some aspects of the present disclosure are directed to techniques for improving storage of multiple bits per memory cell in a memory subsystem. Figure 1 Examples of storage devices and memory modules are described. Typically, a host system can utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0021] Integrated circuit memory cells (e.g., flash memory cells) can be programmed to store data by being in a state where they are at a predefined voltage. For example, if a memory cell is configured / programmed in a state that allows a large amount of current to pass through the memory cell at a predefined voltage, the memory cell is storing a bit 1; and otherwise, the memory cell is storing a bit 0. Furthermore, a memory cell can store multiple bits of data by being configured / programmed differently at multiple predefined voltages. For example, a memory cell can store multiple bits of data by having a combination of states at multiple predefined voltages; and different combinations of the states of the memory cell at the predefined voltages can be interpreted as representing different states of the data bits stored in the memory cell.

[0022] Although the threshold voltage of a memory cell can be adjusted / programmed by applying a voltage pulse to the memory cell, it is generally difficult to precisely adjust / program the threshold voltage of a memory cell to a predefined voltage. A typical programming operation may move the threshold voltage of a memory cell to a voltage region where the probability level of the threshold voltage variation is actually at different voltages within the threshold distribution region.

[0023] Thus, a programming operation can move the threshold voltage of a memory cell into a threshold distribution region where the probability density level of the memory cell's threshold voltage being at any voltage in the region is higher than a predefined threshold density. Programming operations that produce a wide threshold distribution region are coarse and, therefore, less accurate than programming operations that produce a narrow threshold distribution region. Coarse programming operations are typically faster than fine, accurate programming operations.

[0024] To store multiple bits per memory cell, the threshold voltage of the memory cell can be programmed into different regions so that each of the regions represents a different bit value combination.

[0025] To reduce the probability of errors when reading memory cells, it is desirable to reduce, minimize, and / or eliminate the overlap in threshold voltage regions caused by programming operations. Increasing the number of bits stored per memory cell leads to a need to reduce the width of the threshold distribution region, and therefore to increase the precision / accuracy of programming operations.

[0026] Improving the precision / accuracy of programming operations generally results in a longer time period for data programming operations. As the time used to program the threshold voltage of a memory cell increases, the speed at which data can be stored in the memory cell decreases.

[0027] By programming the threshold voltage of a memory cell to a narrow threshold distribution area, multiple programming passes can be used to accelerate the storage of data in the memory cell. An initial coarse programming pass can be used to quickly shift the threshold voltage of the memory cell with less precision. As a result, the threshold voltage of the memory cell is shifted to a relatively wide threshold distribution area. Subsequent fine programming passes can be used to fine-tune the threshold voltage of the memory cell and shift it to a relatively narrow area of ​​the threshold voltage distribution to reduce the probability of read errors. The combination of coarse and fine programming can be faster than programming the memory cell directly to a narrow threshold distribution area.

[0028] Multi-pass programming can result in increased complexity in the circuitry used to apply the multi-pass programming. For example, in some implementations, a buffer can be used to store input data for use in a subsequent programming pass. Optionally, some memory cells in the memory device can be used in single-level cell (SLC) mode to temporarily store / buffer input data, one bit per memory cell, for subsequent use in the next pass. From a user's perspective, such an arrangement can eliminate the need for a separate type of memory cell for buffering data, but can increase the write amplification of the memory device and / or reduce the available memory / storage capacity.

[0029] At least some aspects of the present disclosure address the above-mentioned and other deficiencies by coarsely programming multiple bits per memory cell and storing group indicators of the possible threshold levels of the coarsely programmed individual memory cells. Because the group indicator eliminates some threshold levels from being read from the memory cell, the memory device can accurately read back data from the memory cell even if its threshold voltage is coarsely programmed to a wide threshold distribution. Because the group indicator allows the memory device to read data stored in the memory cell in the form of its coarsely programmed threshold voltage, the coarsely programmed memory cell can be used as a buffer for data to be stored in the memory cell in a subsequent fine programming operation. Storing the group indicator consumes fewer resources than storing the entire data to be stored back in the memory cell during fine programming.

[0030] For example, a memory cell can be coarsely programmed to one of sixteen possible threshold levels to store four bits of data in a quad-level cell (QLC) mode. The sixteen possible threshold levels can be divided into four groups, where the group division is configured to increase the voltage gap between adjacent voltage levels in each group. For example, when sorted by voltage, the threshold levels of the four groups can be fully interleaved to increase the minimum spacing between the threshold levels in each individual group.

[0031] A two-bit group indicator can be stored in one or more memory cells to identify the threshold level group of the memory cell. Because the group indicator typically limits the possible threshold levels of a memory cell to one-quarter of the 16 possible levels for 4-bit data, a memory device can perform a read operation to obtain 4 bits of data stored in the coarsely programmed memory by distinguishing its coarsely programmed threshold level from four possible coarsely programmed threshold levels. This corresponds to reading a memory cell programmed to store 2 bits of data (or multi-level cell (MLC) mode). Reading data in MLC mode can be accurately performed using coarser threshold programming than reading data in QLC mode. The two-bit group indicator can be stored / buffered in two memory cells (e.g., one bit per cell) in single-level cell (SLC) mode. Since 4 bits of data can be read from the coarsely programmed memory cell with the help of the two-bit group indicator, the need to buffer 4 bits of data in four memory cells in SLC mode can be eliminated. Consequently, the described technique can reduce write amplification and / or increase the memory / storage capacity available to the end user.

[0032] In some embodiments, the group indicator can be calculated based on an exclusive-or or exclusive-or operation applied to four bits to be stored in the memory cell. For example, one bit of a two-bit group indicator can be calculated based on the exclusive-or (or exclusive-or) of two of the four bits to be stored in the memory cell; and the other bit of the group indicator can be calculated based on the exclusive-or (or exclusive-or) of the four bits to be stored in the memory cell.

[0033] When multiple bits from multiple memory cells are configured as codewords using linear error correction code (ECC) techniques (e.g., low-density parity check (LDPC)), the exclusive OR of the codewords can produce a codeword with bits from the group indicator of the memory cells. Therefore, the exclusive OR (or exclusive OR) of the codewords remains decodable, and ECC techniques can be used to recover from errors when reading the group indicator.

[0034] When the group indicator is calculated based on the exclusive OR (or exclusive OR) of the four bits to be stored in the memory cell, the coarsely programmed memory cell can be read to retrieve two of the four bits; and the remaining two bits can be calculated based on the exclusive OR (or exclusive OR) of the group indicator bit and the bits read from the coarsely programmed memory cell. Alternatively, the redundant information provided by the group indicator can be used to recover from errors in reading the memory cell.

[0035] Because the threshold levels of the four groups are staggered, the read voltages used to read the four groups are also staggered. During the reading of memory cells that have been coarsely programmed to the threshold levels of the QLC mode, the voltages applied to the memory cells are sequentially increased to the read voltages of the four groups according to the order in which the read voltages increase. Thus, in a single pass, the state of the memory cells is tested with monotonically increasing read voltages to determine the bit value of the data stored in the memory cells. This technique can reduce the overhead of ramping the voltage applied to the memory cells during reading and, therefore, increase the speed of two-pass programming of the memory cells.

[0036] After retrieving the data stored in the coarsely programmed memory cells with the help of the group indicators, fine programming operations can be applied to narrow the threshold distribution region so that the group indicators are no longer needed to accurately read the memory cells.

[0037] Such programming techniques may reduce the requirement to use separate memory cells to buffer data for fine programming passes, reduce write amplification, and / or increase memory / storage capacity available to a user.

[0038] Figure 1 An example computing system 100 is described according to some embodiments of the present disclosure that includes a memory subsystem 110. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or such combinations.

[0039] The memory subsystem 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0040] Computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0041] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0042] The host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0043] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Bus Attached (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, or any other interface. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via the PCIe interface, the host system 120 can further utilize a high-speed NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0044] The processing device 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls communications via a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 116 may send commands or requests to the memory subsystem 110 to obtain desired access to the memory devices 130, 140. The controller 116 may further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry may convert responses received from the memory subsystem 110 into information for the host system 120.

[0045] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading, writing, or erasing data at the memory devices 130 and 140, as well as other such operations. In some cases, the controller 116 is integrated into the same package as the processing device 118. In other cases, the controller 116 is separate from the package of the processing device 118. The controller 116 and / or the processing device 118 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 116 and / or the processing device 118 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0046] Memory devices 130 and 140 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0047] Some examples of non-volatile memory devices include negative-and (NAND) flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing them. For example, NAND-type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0048] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a quintuple-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0049] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0050] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations (e.g., in response to commands dispatched on a command bus by the controller 116). The controller 115 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0051] The controller 115 may include a processing device 117 (e.g., a processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0052] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a controller 115, but in alternative embodiments of the present disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., by an external host, or provided by a processor or controller separate from the memory subsystem).

[0053] Typically, the controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0054] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0055] In some embodiments, memory device 130 includes a local media controller 150 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller for media management (e.g., local media controller 150) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0056] Controller 115 and / or memory device 130 may include a program manager 113 configured to perform interleaved two-pass data programming with reduced write amplification. In some embodiments, controller 115 in memory subsystem 110 and / or controller 150 in memory device 130 may include at least a portion of program manager 113. In other embodiments, or in combination, controller 116 and / or processing device 118 in host system 120 may include at least a portion of program manager 113. For example, controller 115, controller 116, and / or processing device 118 may include logic circuitry that implements program manager 113. For example, controller 115 or processing device 118 (e.g., a processor) of host system 120 may be configured to execute instructions stored in memory to perform the operations of program manager 113 described herein. In some embodiments, program manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, programming manager 113 may be part of the firmware of memory subsystem 110, the operating system of host system 120, a device driver or application, or any combination thereof.

[0057] For example, the program manager 113 implemented in the controller 115 and / or the controller 150 may receive a predetermined number N of data groups (e.g., pages) for coarse programming into a group of memory cells in the memory device 130. The coarsely programmed group of memory cells is then finely programmed to store a predetermined number N of bits per memory cell. The program manager 113 generates a set of multi-bit indicators (e.g., n-bit indicators) for the memory cells by applying an XOR (or XOR) operation to the data groups. The program manager 113 initiates coarse programming to store the predetermined number N of data groups (e.g., pages) into the group of memory cells, where each memory cell in the group of memory cells is finely programmed to store a predetermined number N of bits per memory cell. NOne of the threshold levels stores one bit from each of the predetermined number N of data groups. Each memory cell in the group of memory cells has a corresponding indicator having a plurality of bits, each of which is generated based on an exclusive-or or exclusive-or operation on some or all of its bits stored via coarse programming. When an n-bit group indicator is used, the indicator is stored in 2 n When the indicator has a particular set of bit values, the set of possible threshold levels for the memory cell corresponds to the set of possible threshold levels for the memory cell after selecting each threshold level for the set. N Threshold level elimination 2 n -1 continuous threshold level. n Group selection 2 N The first 2 of the threshold levels n Therefore, 2 n The threshold levels of the groups are interleaved in 2 to represent the value of N bits. N 2 possible combinations N Since the group indicator eliminates the intermediate threshold levels, the memory device can distinguish between the two N-n The data coarsely programmed into the group of memory cells can be read using a coarsely programmed threshold distribution area. For example, with the help of a group indicator that identifies a particular group, a programming accuracy of storing Nn bits per memory cell can be sufficient to read a memory cell programmed to store N bits of data in a particular group. For example, a memory cell coarsely programmed in QLC mode but with MLC programming accuracy can be accurately read with a 2-bit group indicator; and the bits of the group indicator can be calculated based on the "exclusive OR" (or "exclusive OR") of two of the four bits and the "exclusive OR" (or "exclusive OR") of the four bits. The "exclusive OR" (or "exclusive OR") preserves the ECC decodability of the indicator group. Therefore, the reliability of reading the group indicator is improved.

[0058] The n-bit group indicator provides n bits of redundant information for the N data bits coarsely programmed in the memory cell. Thus, the memory device can be configured to read only Nn data bits from the memory cell and obtain the remaining n bits using the n-bit redundant information provided by the n-bit group indicator. Alternatively, the N-bit data and the n-bit group indicator can be used to form a codeword for error recovery using ECC techniques (e.g., LDPC).

[0059] 2 nThe read voltages for each group can be combined into a list of voltages in a monotonically increasing order for sensing and thus reading the roughly programmed groups of memory cells. The groups of memory cells are applied with voltages starting from the lowest in the list to the highest in the list. At each applied read voltage, the memory device senses whether a significant current can pass through the memory cell at the applied read voltage. The result of sensing the current can be used to update the relevant bit to be stored in the memory cells in the relevant group. By sensing each of the read voltages once in increasing order, all groups of memory cells can be read to obtain multiple data groups. Therefore, there is no need to ramp the voltage multiple times to read different groups individually. Combining reads reduces overhead and therefore improves the speed of two-pass programming operations.

[0060] Figure 2 According to one embodiment, an integrated circuit memory device is described having a program manager configured to program the threshold voltage of a memory cell to store data. For example, Figure 1 The memory device 130 in the memory subsystem 110 can use Figure 2 The integrated circuit memory device 130 is implemented.

[0061] The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes multiple groups of memory cells 131, ..., 133, which may be formed in one or more integrated circuit dies. A typical memory cell in group 131 (or group 133) may be programmed to store one or more bits of data.

[0062] Some of the memory cells in the integrated circuit memory device 130 may be configured to operate together for a specific type of operation. For example, memory cells on an integrated circuit die may be organized into planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page may have multiple strings of memory cells. For example, an integrated circuit die may be the smallest unit that can independently execute commands or report status; the same concurrent operation can be performed in parallel on multiple planes in an integrated circuit die; a block may be the smallest unit for performing an erase operation; and a page may be the smallest unit for performing a data programming operation (writing data into a memory cell). Each string has its memory cells connected to a common bit line; and the control gates of memory cells in the same position in a string in a block or page are connected to a common word line. Control signals can be applied to the word lines and bit lines to address individual memory cells.

[0063] The integrated circuit memory device 130 has a communication interface 147 to receive a command having an address 135 from the controller 115 of the memory subsystem 110, retrieve memory data 144 from the memory cell identified by the memory address 135, and provide at least the memory data 144 as part of a response to the command. Optionally, the memory device 130 can decode the memory data 144 (e.g., using error correction code (ECC) techniques) and provide the decoded data as part of the response to the command. The address decoder 141 of the integrated circuit memory device 130 converts the address 135 into a control signal to select a group of memory cells in the integrated circuit memory device 130; and the read / write circuit 143 of the integrated circuit memory device 130 performs an operation to determine the memory data 144 stored in the memory cell at the address 135.

[0064] Integrated circuit memory device 130 has a set of latches 145 to temporarily hold memory data 144 while read / write circuit 143 is programming the threshold voltages of a memory cell group (e.g., 131 or 133). For example, read / write circuit 143 can program the threshold voltages of memory cells in memory cell group 131 to store N bits per memory cell. A memory cell group (e.g., 131 or 133) has M memory cells. Latches 145 are configured to store N×M data bits in the form of N data groups. Each of the data groups has M data bits to be stored in the M memory cells in the memory cell group (e.g., 131 or 133).

[0065] When latch 145 has N data groups to be stored in a memory cell group (e.g., 131), program manager 113 is configured to determine and program the threshold voltage levels of the memory cells in the memory cell group (e.g., 131). The threshold voltage levels may be determined based on the values ​​of the bits in memory data 144 and a Gray code that maps bit value combinations to threshold levels, such that any two combinations of bit values ​​represented by two consecutive threshold levels differ by only one bit.

[0066] In one embodiment, the memory device 130 receives N data groups from the controller 115 of the memory subsystem 110 for coarse programming of the threshold voltages of the memory cells in the memory cell group (e.g., 131). The coarse programming operation moves the threshold voltage of the memory cell to a voltage region close to the threshold level for storing the N data groups. The coarse programming is configured to store the N data groups into the memory cell group, where each memory cell stores one bit from each of the N data groups. The coarse programming maps the N bit value to be stored in each memory cell to its coarsely programmed threshold level, which is a 2-bit threshold level for representing N bits of data. N2 possible combinations N Generate an indicator to identify the 2 containing the coarsely programmed threshold level of the memory cell. N The n-bit indicator reduces the subset to 2 N-n In one embodiment, the coarse programming of the memory cells 110 is performed by programming the memory cells 111 to store Nn bits. The coarse programming of the memory cells 111 to store Nn bits can be ... To perform fine programming, memory device 130 reads the group indicator, reads data from the coarsely programmed group of memory cells (e.g., 131), and applies a voltage pulse to narrow the threshold distribution region so that the finely programmed group of memory cells (e.g., 131) can be read without the aid of the group indicator. After fine programming, the group indicator can be discarded or deleted.

[0067] In some embodiments, the threshold levels for coarse programming and fine programming are determined using Gray code, as in Figure 6 Gray codes can map combinations of bit values ​​to threshold levels such that when the threshold level represented by the bit value combination changes to the next higher or lower threshold level, one and only one of the bit values ​​changes. In some implementations, the indicator set can be calculated by applying an exclusive OR (or exclusive OR) to N data sets.

[0068] Figure 3 An example of programming memory cells to store multiple bits per memory cell is shown according to one embodiment. For example, Figure 3 Examples can be found in Figure 1 and / or Figure 2 is implemented in the memory device 130.

[0069] exist Figure 3, memory cell group 131 has memory cells 137, ..., 139. A plurality of data groups 151, 157, ..., 159 provide data bits to be stored in memory cells 137, ..., 139. The number of bits provided in each data group (e.g., 157, 159, or 151) is equal to the number of memory cells 137 through 139 in memory cell group 131. Each memory cell (e.g., 139 or 137) stores a group of bits, one from each of data groups 151, 157, ..., and 159.

[0070] For example, data bits 161, 163, ..., 165 from data groups 151, 157, ..., 159 are stored in one memory cell 137, and the voltage threshold of memory cell 137 is programmed by read / write circuit 143 to a level representing the value of data bits 161, 163, ..., 165. Similarly, data bits 171, 173, ..., 175 from data groups 151, 157, ..., 159 are stored in another memory cell 139 and are represented by the level of the voltage threshold of memory cell 139.

[0071] Optionally, the data bits in the data group can be organized into codewords 153, ..., 155 according to error detection and data recovery techniques, such as error correction codes (ECC), such as low-density parity check (LDPC) codes.

[0072] For example, codeword 153 in data group 151 may include data bits 161 through 162. When one of the data bits in codeword 153 is erroneous, the error may be detected and corrected (eg, using low-density parity check (LDPC) techniques).

[0073] When data groups 151, 157, ..., 159 are stored in latches 181, 183, ..., 185, read / write circuit 143 programs the 149 thresholds of memory cells 137, ..., 139 so that the voltage thresholds of memory cells 137, ..., 139 represent the values ​​of corresponding data bits from data groups 151, 157, ..., 159.

[0074] Mapping combinations of values ​​of data bits (e.g., 161, 163, ..., 165) to be stored in a memory cell (e.g., 137) to levels of voltage thresholds of the memory cell (e.g., 137) based on a Gray code. For example, the read / write circuit 143 may include a Gray code table (e.g., as Figure 6 , 165) with a set of data bits (e.g., 161, 163, ..., 165) in a memory cell (e.g., 137) and the threshold levels of the memory cell (e.g., 137) representing the values ​​of the set of data bits (e.g., 161, 163, ..., 165).

[0075] To speed up the operation of programming the 149 threshold voltages of memory cells 137, ..., 139 to store data groups 151, 157, ..., 159, read / write circuit 143 can be configured to use a two-pass programming operation. In the first coarse programming, the threshold voltages of memory cell group 131 are moved to a relatively wide threshold distribution region adjacent to the fine threshold distribution region. The coarsely programmed threshold voltages are determined based on the threshold levels representing data groups 151, 157, ..., 159. A set of threshold level indicators are temporarily calculated and stored / buffered to assist in accurately reading data groups 151, 157, ..., 159 from the coarsely programmed memory cell group 131. After reading data groups 151, 157, ..., 159 back into latches 183, ..., 185, read / write circuitry 143 may perform fine programming to move the threshold voltages of memory cells 137, ..., 139 to a fine threshold distribution region representing the data bits in data groups 151, ..., 157, 159, as described below in conjunction with Figures 4 to 12 Further detailed discussion.

[0076] Figure 4 A two-pass programming technique for storing multiple bits per memory cell is presented according to one embodiment. For example, Figure 4 The technology can be Figure 1 The memory subsystem 110 Figure 2 is implemented in the memory device 130.

[0077] exist Figure 4 In FIG. 2 , a certain number (N) of data bits 163 to 165 are used to determine a coarse programming threshold level T 203 through a mapping 201 between bit value combinations and coarse programming threshold levels.

[0078] All possible coarse programmed threshold levels are classified into 2 n groups. For example, 2 N The coarsely programmed threshold levels are numbered in increasing order. Classification 205 is configured to sort the first 2 n The threshold levels are set to 2 n For 2 n For each of the groups, the classifier 205 is configured to remove the next consecutive 2 n -1 threshold level to select the next threshold level of the group. Therefore, 2 N The coarse programming threshold level is divided equally into 2 n groups, each with 2 N-n Each pair of adjacent threshold levels in a group is replaced by 2 threshold levels belonging to other groups. n-1 threshold level apart. The threshold levels in a group are staggered. Group identifier 207 provides an identification of the group containing the threshold levels 203 of the memory cells 137 after coarse programming. Since group identifier 207 limits the threshold levels 203 to 2 N-n The coarse programming can be performed with one of the Nn threshold levels, and thus with sufficient accuracy to read from a memory cell storing Nn bits per memory cell.

[0079] A first pass of threshold programming 219 is performed to move the threshold voltage 221 of memory cell 137 of memory cell group 131 to a relatively wider threshold distribution region. Read / write circuitry 143 may store 209 the group identification 207 of memory cell 137 in one or more other memory cells 191 (e.g., in a different memory cell group 133 in SLC mode).

[0080] To fine-tune memory cell 137 to store data bits 161, 163, ..., 165, read / write circuit 143 may read 211 the group identifier of memory cell 137 from memory cell 191 to assist in the operation of reading 213 memory 137 to retrieve data bits 161, 163, ..., 165. Group identifier 207 eliminates the 2 bits representing the values ​​of data bits 161, 163, ..., 165. n Thus, the group identifier allows the read / write circuit 143 to determine the value of the data bits 161, 163, ..., 165 based on the threshold voltage 221, which is coarsely programmed into a relatively wide threshold distribution region, such as in Figure 5 The read / write circuit 143 may read 213 data bits 161, 163, ..., 165 from the memory cell 137 into the latches 183, ..., 185, respectively.

[0081] During fine programming of memory cell 137, data bits 161, 163, ..., 165 in latches 181, 183, ..., 185 are again used to determine a fine programming threshold level 223 via a mapping 217 between bit value combinations and fine programming threshold levels. The mapping 217 to threshold level 223 for fine programming may be the same as the mapping 201 to threshold level 203 for coarse programming.

[0082] A second pass of threshold programming 229 is performed to move the threshold voltages 225 of the memory cells 137 of the memory cell group 131 to a relatively narrow threshold distribution region. This region is narrow enough to allow the read / write circuit 143 to determine the data bits 161, 163, ..., 165 based on sensing the threshold voltages 225 of the memory cells 137. Therefore, the group identifier 207 can be discarded after the second pass of threshold programming 229.

[0083] Figure 5 According to one embodiment, the voltage distribution of the two-pass programming of the memory cell is described. Figure 5 The distribution described in Figure 4 A two-pass programming technique is used to store data in QLC mode (four bits per memory cell).

[0084] exist Figure 5 In order to program the memory cell 137 to store data in the QLC mode, the threshold voltage of the memory cell is moved to the voltage V0, V2, ..., V 15 One of the 16 QLC threshold levels 0, 1, ..., 15 centered at .

[0085] After fine QLC threshold programming 229, the threshold distribution region narrows, as illustrated by the curve illustrated for fine QLC. For example, when memory cell 137 is finely programmed to QLC threshold level 0, the probability level of the threshold voltage of memory cell 137 is at a voltage close to V0, as illustrated by curve 241 centered around V0. The voltage range of curve 241 represents the threshold distribution region at QLC threshold level 0 after fine QLC programming.

[0086] Similarly, when memory cell 137 is finely programmed to QLC threshold level 1, the probability level of the threshold voltage of memory cell 137 being at a voltage close to V1 is illustrated by curve 243 centered on V1. The voltage range of curve 243 represents the threshold distribution region at QLC threshold level 1 after fine QLC programming.

[0087] At voltage region 249, curves 241 and 243 overlap, indicating that when the threshold voltage of memory cell 137 is found in region 249, there is ambiguity as to whether memory cell 137 is programmed at threshold level 0 to represent one set of bit values ​​or at threshold level 1 to represent another set of bit values. When the mapping between bit value combinations and threshold levels is based on a Gray code, the bit values ​​represented by threshold level 0 and threshold level 1 differ by one bit. Therefore, there is a low probability that this bit, determined based on the threshold voltage of memory cell 137, will be read incorrectly. Errors in such bits can typically be detected and corrected through ECC / LPDC decoding of the codeword (e.g., 153) in the data group (e.g., 151) containing the bit. Reducing the overlapping region can improve the accuracy of reading memory cell 137. However, reducing the width of distribution curves 241, 243 requires greater precision and, therefore, longer time to program the threshold voltage of memory cell 137.

[0088] exist Figure 5In order to program the threshold voltage of memory cell 137 to a fine QLC level having narrow distribution curves 241, 243, etc., the read / write circuit 143 of memory device 130 initially coarsely programs the memory cell to a corresponding coarse QLC level according to four data bits (e.g., 161, 163, ..., 165) to be stored in memory cell 137.

[0089] For example, when the four data bits of memory cell 137 are coarsely programmed to QLC threshold level 0, the probability level of the threshold voltage of memory cell 137 being at a voltage close to V0 is illustrated by curve 251 centered on V0. The voltage range of curve 251 represents the threshold distribution region at QLC threshold level 0 after coarse programming.

[0090] Similarly, when the three data bits of memory cell 137 are coarsely programmed to QLC threshold level 1, the probability level of the threshold voltage of memory cell 137 being at a voltage close to V1 is illustrated by curve 253 centered on V1. The voltage range of curve 253 represents the threshold distribution region at QLC threshold level 1 after coarse programming.

[0091] The coarse QLC curves (eg, 251 and 253) overlap significantly with each other, which can lead to many read errors.

[0092] To reduce coarse programming time and reduce read errors, a group identifier 207 is calculated and / or stored to identify a set of threshold levels that contains the threshold levels of the coarsely programmed memory cells 137 .

[0093] exist Figure 5 In

[15] , the sixteen threshold levels for coarse QLC programming are divided into four groups. The first four levels of coarse QLC programming, V0, V1, V2, and V3, are assigned to groups 0, 1, 2, and 3, respectively. For each group, the next selected threshold level can be identified by eliminating the next three consecutive threshold levels. Thus, each group has four threshold levels, corresponding to the threshold levels for MLC mode.

[0094] For example, the threshold level V0 of the coarse QLC programming is selected for Group 0 as its threshold level V0 for MLC reading. After eliminating the next three consecutive threshold levels V1, V2, and V3 of the coarse QLC programming, the threshold level V4 of the coarse QLC programming is selected for Group 0 as its threshold level V1 for the next MLC reading. Thus, the threshold levels V0, V4, V8, and V 12 Threshold levels V0, V1, V2, and V3 in group 0 are classified as MLC read. If memory cell 137 is coarsely programmed to threshold levels V0, V4, V8, and V 12If any of the above is true, then the memory cell 137 is classified in group 0 for reading its data. The threshold levels of the other groups 1, 2, or 3 for MLC reading are selected in a similar manner.

[0095] When group identification 207 indicates that memory cell 137 is coarsely programmed to the threshold level contained in group 0 for MLC reading, the possible threshold voltage distributions are represented by alternating curves 251, 255, etc. The distribution curves for groups 1, 2, and 3 for MLC reading are not possible. Therefore, the threshold voltage of memory cell 137 can be unambiguously mapped back to the threshold level and back to the bit value represented by the threshold level.

[0096] Similarly, when group identification 207 indicates that memory cell 137 is coarsely programmed to a threshold level in group 1 for MLC reading, possible threshold voltage distributions are represented by alternating curves 253, 257, etc. Distribution curves for other threshold levels (e.g., curve 251) are not possible. Therefore, the threshold voltage of memory cell 137 can be mapped back to a unique threshold level and back to the bit value represented by the corresponding threshold level.

[0097] The group identifier 207 allows the read / write circuit 143 to distinguish between the alternating distribution curves for the coarsely programmed memory cells (e.g., 251, 255, ... in group 0; or 253, 237, ... in group 1). A reduced number of distribution curves (e.g., 251, 255, ... in group 0; or 253, 237, ... in group 1) can be read in MLC mode. Thus, the distribution curves (251, 255, ...; 253, 257, ...) for coarse QLC programming can be as coarse as those programmed for MLC mode; and the coarsely programmed memory cell 137 can be read in MLC mode identified by the group identifier 207.

[0098] For example, based on group identification 207 identifying memory cell 137 that is coarsely programmed according to the levels in group 0, read / write circuit 143 can use group 0 MLC read mode to determine the coarsely programmed threshold level of memory cell 137 and thus the four data bits (e.g., 163, ..., 165) stored in memory cell 137 by coarse programming.

[0099] Similarly, based on group identification 207 identifying memory cell 137 as coarsely programmed according to the levels in group 1, read / write circuit 143 can use group 1 MLC read pattern to determine the coarsely programmed threshold level of memory cell 137 and thus the four data bits (e.g., 163, ..., 165) stored in memory cell 137 by coarse programming.

[0100] From another perspective, the threshold distribution curve for each group (e.g., 0, 1, 2, or 3) can be viewed as the result of programming corresponding data to corresponding threshold levels in a corresponding MLC mode. The MLC threshold levels for each group are configured to represent corresponding QLC threshold levels and, therefore, corresponding four-bit values. The voltage levels for the different groups 0, 1, 2, and 3 MLC programs are offset from one another so that their distribution curves do not overlap (or overlap is reduced / minimized to allow for correction of occasional errors through ECC operations). The set of voltage levels for the groups 0, 1, 2, and 3 MLC programs corresponds to the threshold levels for QLC programming. Based on the group identifier 207, the memory cell 137 will be read according to one of the groups 0, 1, 2, and 3 MLC modes.

[0101] After the threshold voltage of memory cell 137 is coarsely programmed to the coarse QLC level, the threshold voltage of memory cell 137 can be further finely programmed to corresponding fine QLC levels to represent the four data bits (e.g., 161, 163, . . . , 165) stored in memory cell 137. The threshold distribution region of the fine QLC level is reduced in width from the corresponding coarse QLC level, so that memory device 130 can determine the programmed threshold level from the threshold voltage of memory cell 137 without the help of group identifier 207.

[0102] Figure 6 According to one embodiment, mapping to threshold levels and group identifiers in two programming passes of memory cells to store data is shown. For example, Figure 6 The mapping can be Figure 5 Used together with the distribution curve described in.

[0103] Figure 6 An example of data programming in QLC mode is illustrated, where the threshold voltage of a memory cell (e.g., 137) is programmed to represent a four-bit value. A page of memory cells is programmed (written) together. Since each cell stores four bits, the page of memory cells can store data bits for four pages of data, where the number of data bits in a data page is equal to the number of memory cells in the memory cell page. For example, each data page is Figure 3 An example of a data group as described in; and the memory cell page is Figure 3 An example of a memory cell group described in .

[0104] Conventionally and / or for convenience, the four data pages of the QLC mode are named as lower page (LP), upper page (UP), extra page (XP), and top page (TP). A memory cell (e.g., 137) in the QLC mode stores one bit from each of the four pages. Since the values ​​of the four data bits stored in the memory cell (e.g., 137) have 16 different combinations, as shown in FIG. Figure 6As illustrated in the table shown in , the threshold voltage of a memory cell (eg, 137) is programmed to one of 16 QLC threshold levels to represent a corresponding combination of bit values.

[0105] Figure 6 The table shown in illustrates an example Gray code that maps between the values ​​of four data bits (e.g., 161, 163, ..., 165) stored in a QLC memory cell (e.g., 137) and the threshold level 203 of the memory cell (e.g., 137). For example, when a memory cell (e.g., 137) is determined to have a QLC threshold level of 0, the memory cell (e.g., 137) is considered to store 1 as a TP bit, 1 as an XP bit, 1 as an UP bit, and 1 as a LP bit. Similarly, to store 1, 1, 0, and 1 as the TP bit, XP bit, UP bit, and LP bit in a memory cell (e.g., 137), the threshold voltage is programmed to level 1. Increasing threshold levels represent increasing threshold voltages to be programmed for the memory cell (e.g., 137).

[0106] Gray code (e.g., as in Figure 6 ) has a characteristic / property in which one and only one bit value changes between two consecutive threshold levels. For example, when the QLC threshold level changes from 0 to 1, Figure 6 In the table, only the UP bit changes from 1 to 0. Similarly, when the QLC threshold level changes between 1 and 2 (or, 2 and 3, 3 and 4, 4 and 5, etc.), only the LP bit changes (or, respectively, the UP bit, TP bit, XP bit, etc.).

[0107] exist Figure 6 , QLC levels 0, 4, 8, 12 are arranged in Group 0, and Group 0 is identified by a two-bit ID having 0 and 0 as bits 0 and 1, respectively. QLC levels 0, 4, 8, 12 can be considered MLC levels 0, 1, 2, and 3 for Group 0. Memory cells 137 programmed to the QLC levels in Group 0 can be read in the MLC mode dedicated to Group 0.

[0108] QLC levels 1, 5, 9, 13 are arranged in Group 1, and Group 1 is identified by a two-bit ID having 1 and 0 as bits 0 and 1, respectively. QLC levels 1, 5, 9, 13 can be considered MLC levels 0, 1, 2, and 3 for Group 1. Memory cells 137 programmed to the QLC levels in Group 1 can be read in the MLC mode dedicated to Group 1.

[0109] QLC levels 2, 6, 10, 14 are arranged in Group 2, and Group 2 is identified by a two-bit ID with 1 and 1 as bits 0 and 1, respectively. QLC levels 2, 6, 10, 14 can be considered MLC levels 0, 1, 2, and 3 for Group 2. Memory cells 137 programmed to the QLC levels in Group 2 can be read in the MLC mode dedicated to Group 2.

[0110] QLC levels 3, 7, 11, 15 are arranged in Group 3, and Group 3 is identified by a two-bit ID having 0 and 1 as bits 0 and 1, respectively. QLC levels 3, 7, 11, 15 can be considered MLC levels 0, 1, 2, and 3 for Group 3. Memory cells 137 programmed to the QLC levels in Group 3 can be read in the MLC mode dedicated to Group 3.

[0111] exist Figure 6 In the example, bit 0 of the group ID is equal to the exclusive OR of the TP bit, XP bit, UP bit, and LP bit; and bit 1 of the group ID is equal to the exclusive OR of the TP bit and LP bit. Therefore, the set of TP bits, XP bits, UP bits, and LP bits, as well as bits 0 and 1 of the group ID, can be considered an LDPC codeword, which can be used to detect and correct errors in some of the bits in the codeword. Alternatively, an exclusive OR relationship on the bits can be used to calculate some of the TP bits, XP bits, UP bits, and LP bits from the group ID. For example, the TP bit can be calculated based on the exclusive OR of bit 1 of the group ID and the LP bit; and the XP bit can be calculated based on the exclusive OR of the UP bit and bits 1 and 0 of the group ID.

[0112] Figure 6 An example is described in which bits 0 and 1 of the group ID are calculated via exclusive OR. Alternatively, bits 0 and 1 of the group ID may be calculated via exclusive OR.

[0113] Typically, a group identifier (ID) can be calculated based on the exclusive OR (or exclusive OR) of the bits to be stored in the memory cell (e.g., the UP bit, the UP bit, and the LP bit). When such a group identifier is used, one or more bits (e.g., the TP and XP bits) of the bits stored in the memory cell can be calculated based on the exclusive OR (or exclusive OR) of the group identifier and other bits. Such an arrangement can simplify reading multiple bits from the memory cell.

[0114] Figure 5 and 6An example is illustrated in which each pair of adjacent, closest MLC levels in each group is separated by one MLC level from each group in the other groups. This arrangement maximizes the minimum distance between the closest pairs of MLC levels in each group. Generally, it is not necessary to interleave the MLC levels of different groups in this manner. When each pair of adjacent MLC levels in each group is sufficiently separated, the MLC levels of each group can be accurately read even if the threshold distribution for coarse QLC programming (e.g., as illustrated by curves 251, 253, 255, 257) is too wide to be read in QLC mode without the aid of group identifier 207.

[0115] Figure 7

[0014] Techniques to coarsely program memory cells to store data at the QLC level and to read the coarsely programmed memory cells are shown according to one embodiment.

[0116] Figure 7 The technology is to use Figure 4 Examples of technology. Figure 7 The technology can be used Figure 6 The mapping shown in Figure 5 This is implemented using the threshold distribution described in .

[0117] exist Figure 7 In the embodiment of the present invention, the four data bits to be stored in the memory cell 137 are received as the LP bit 261, the UP bit 263, the XP bit 265, and the TP bit 267. A logic circuit calculates an exclusive OR 273 of the four data bits to generate bit A 274 of the group identifier 207 of the memory cell 137; and another logic circuit calculates an exclusive OR 271 of the TP bit 267 and the LP bit 261 to generate bit B 272 of the group identifier 207 of the memory cell 137.

[0118] Figure 7 The illustration shows the use of exclusive OR 271 and exclusive OR 273 to calculate the group identifier 207. Alternatively, exclusive OR may be used.

[0119] When the LP bit 261 and the TP bit 267 are combined using an exclusive-OR 271 to form bit B 272 of the group identifier 207, the ECC / LPDC codeword containing the LP bit 261 and the TP bit 267 is effectively combined via the exclusive-OR to generate a valid ECC / LPDC codeword containing bit B 272. Therefore, ECC / LPDC techniques can be used to detect and / or correct errors in reading bit B 272 of the group identifier 207.

[0120] Similarly, when bit A 274 is calculated via XOR 273, a valid ECC / LPDC codeword containing bit A 274 is also generated based on the XOR of the codeword containing the LP bit, the UP bit, the XP bit, and the TP bit. Errors in bit A 274 of the read group identifier 207 can be detected and / or corrected using ECC / LPDC techniques.

[0121] In SLC mode, the group identifier 207 can be cached in two memory cells. Alternatively, the group identifier 207 can be buffered in a memory cell in MLC mode.

[0122] For example, the value of bit A 274 of a page of memory cells coarsely programmed in QLC mode can be stored / buffered in one page of memory cells in SLC mode; and the value of bit B 272 can be stored / buffered in another page of memory cells in SLC mode. After reading the SLC buffer page, ECC / LPDC techniques can be applied to the codewords in the SLC buffer page to detect and / or correct errors.

[0123] The combination of the values ​​of the LP bit, UP bit, XP bit, and TP bit is mapped to the QLC threshold level (e.g., using Figure 6 ). The read / write circuits 143 of the memory device 130 may apply a coarse programming pulse to move the threshold voltage 221 of the memory cell 137 to a coarse threshold distribution region.

[0124] For example, when the combination of values ​​of the LP bit, the UP bit, the XP bit, and the TP bit corresponds to a coarse QLC threshold level V0, the threshold voltage 221 of the memory cell 137 is moved into the region represented by the curve 251. The probability density of voltages where the threshold voltage 221 is within the region of the curve 251 is highest at voltage V0 and decreases away from voltage V0.

[0125] To read the memory cell 137, the group identifier 207 is used to determine a read voltage 275 to test the threshold level of the memory cell 137. For example, when the memory cell 137 is programmed to the threshold level V0 and is therefore in group 0, a read voltage between V0 and V1 of the group 0 MLC level can be used to determine that the threshold voltage 221 of the memory cell 137 is lower than the read voltage. For example, the read / write circuit 143 applies a read voltage to the memory cell 137 and determines whether a significant current passes through the memory cell. If a significant current passes through the memory cell, the threshold voltage 221 of the memory cell 137 is lower than the applied read voltage; and the memory cell is determined to be programmed at the threshold V0 of the group 0 MLC level; and the values ​​of the LP bit, UP bit, XP bit, and TP bit represented by the threshold levels can be determined according to Figure 6 Determined by the table described in .

[0126] If no substantial current flows through memory cell 137 when a read voltage between V0 and V1 of the group 0 MLC levels is applied, then memory cell 137 is not programmed at the threshold level V0 of the group 0 MLC levels. Therefore, further read threshold voltages between V1 and V2 and between V2 and V3 of the group 0 MLC levels may be applied to determine whether the threshold voltage of memory cell 137 is programmed at V1, V2, or V3 of the group 0 MLC levels.

[0127] When group identification 207 indicates that threshold voltage 221 is programmed according to group 1, 2, or 3, a corresponding read voltage 275 configured according to group 1, 2, or 3 MLC levels may be applied to determine the threshold level of memory cell 137 based on whether threshold voltage 221 is lower than read voltage 275.

[0128] Figure 7 An example is shown of combining two bits (TP bit 267 and LP bit 261) to generate bit 272 of group ID 207. Such a selection could be Figure 6 The Gray code (2-4-4-5) described in [ 15 ] produces the best results. In general, more or fewer bits can be used to generate the bits of group ID 207. For example, when using another Gray code (3-4-4-4), one bit of group ID 207 can be calculated based on the exclusive OR of the LP bit, the UP bit, and the XP bit, and another bit can be calculated based on the exclusive OR of the LP bit, the UP bit, and the TP bit. For example, when using a further Gray code (3-3-4-5), one bit of group ID 207 can be calculated based on the exclusive OR of the LP bit, the UP bit, and the XP bit, and another bit can be calculated based on the exclusive OR of the UP bit, the XP bit, and the TP bit. For example, when using yet another Gray code, one bit of group ID 207 can be equal to XP, and another bit can be calculated based on the exclusive OR of the LP bit, the UP bit, the XP bit, and the TP bit. Thus, the techniques are not limited to a particular number of bit combinations.

[0129] Figure 8

[0066] Another technique to read coarsely programmed memory cells is shown according to one embodiment.

[0130] Similar to Figure 7 technology, Figure 8 The technique uses XOR 271 and XOR 273 to calculate the group identifier 207. Alternatively, XOR can be used.

[0131] In addition to using group ID 207 to determine read voltage 275 to read 213 memory cell 137 in MLC mode, bits 272 and 274 of group ID 207 are used to calculate TP bit 267 and XP bit 265 using XOR 283 and XOR 281 .

[0132] Since the TP bit and the XP bit can be calculated using the LP bit 261 , the UP bit 263 and the group identifier 207 , the operation of reading 213 the memory cell 137 can be simplified by reading the 4-bit LP bit and the UP bit.

[0133] Figure 8 The following describes an example of calculating the TP bit and the XP bit using the group identifier 207. Alternatively, the LP bit and / or the UP bit can be calculated based on the TP bit and / or the XP bit. For example, the LP bit 261 can be calculated based on the exclusive OR of the TP bit and bit B 272 of the group identifier 207; and the UP bit 263 can be calculated based on the exclusive OR of the XP bit 265 and bits 272 and 274 of the group identifier 207.

[0134] Figure 9

[0014] A technique to determine the value of a bit stored in a memory cell coarsely programmed at a set of predefined threshold levels is shown according to one embodiment.

[0135] For example, you can use Figure 9 The technology to read the programmed Figure 5 Memory cell 137 having a threshold level in group 0, 1, 2, or 3 MLC levels as illustrated in FIG.

[0136] exist Figure 9 , curves 193, 195, 197, and 199 represent probability distributions of threshold voltage 221 of memory cell 137 after programming at threshold levels V0, V1, V2, and V3, respectively.

[0137] Read voltage V R0 、V R1 and V R2 The read / write circuit 143 of the memory device 130 can be configured between adjacent threshold distribution curves 193, 195, 197, and 199. R0 、V R1 or V R2 ) is applied to the memory cell 137 and senses whether a substantial current (e.g., above a threshold) passes through the memory cell 137. If a substantial current passes through the memory cell, the threshold voltage 221 of the memory cell 137 is lower than the applied read voltage (e.g., V R0 、V R1 or V R2 ).

[0138] In block 301, when the threshold voltage 221 of the memory cell 137 is found to be lower than the read voltage V R0 , the threshold voltage 221 of the memory cell 137 is seen to be programmed to the level V0, which means that the stored bit 291 in the memory cell 137 has the first value associated with the level V0 (e.g., Figure 9Otherwise, in block 303, when the threshold voltage 221 of the memory cell 137 is found to be lower than the read voltage V R1 , the threshold voltage 221 of the memory cell 137 is seen to be programmed to the level V1, which indicates that the stored bit 291 in the memory cell 137 has the second value associated with the level V1 (e.g., Figure 9 Otherwise, in block 305, when the threshold voltage 221 of the memory cell 137 is found to be lower than the read voltage V R2 , the threshold voltage 221 of the memory cell 137 is seen to be programmed to the level V2, which indicates that the stored bit 291 in the memory cell 137 has a third value associated with the level V2 (e.g., Figure 9 Otherwise, the threshold voltage 221 of the memory cell 137 is seen to be programmed to the level V3, which indicates that the stored bit 291 in the memory cell 137 has a fourth value associated with the level V3 (e.g., Figure 9 1) in the example described in .

[0139] When the mapping between the levels V0, V1, V2 and V3 and their corresponding values ​​is known, it is possible to skip the operation of current sensing at some of the read voltages.

[0140] exist Figure 9 In the example illustrated in FIG, levels V1 and V2 are both used to represent the same zero value. The threshold voltage 221 of a memory cell 137 programmed at successive V1 or V2 provides the same zero value for the stored bit 291. Therefore, it is not necessary to separately test whether a memory cell 137 is programmed at V1 or V2; and the reading of the voltage V R1 When reading the voltage V R0 The current sensing at block 301 indicates that the threshold voltage 221 of the memory cell 137 is above V R0 , it can be concluded 307 that the threshold level of the memory cell 137 is higher than V0. R2 The current sensing at block 305 indicates that the threshold voltage 221 of the memory cell 137 is below V R2 , conclusion 309 can be drawn: the threshold level of memory cell 137 is lower than V3. From conclusions 307 and 309, it can be determined that memory cell 137 is programmed at V1 or V2. Since threshold levels V1 and V2 both represent the same zero value, the value of stored bit 291 can be determined unambiguously.

[0141] Typically, it is sufficient to perform sensing at a pair of adjacent, closest threshold levels that separate the values. The value of the stored bit 291 can be initially assumed and set to have a value represented by the lowest level V0 (e.g., 1). The minimum read voltage (e.g., V0 and V1) that separates the levels (e.g., V0 and V1) that represent different values ​​(e.g., 1 and 0) can be used. R0 ) may be applied to the memory cell 137. When a read voltage (eg, V R0 ) when the current flowing through the memory cell 137 is sensed to be above the threshold, the assumed value of the stored bit 291 is correct; otherwise, the assumed value is inverted to the value immediately above the read voltage (e.g., V R0 ) represents the value (e.g., 0) of the next level (e.g., V1) above ). Such sensing operations can be repeated at increasingly higher read voltages separating levels representing different bit values ​​until the value of the stored bit 291 is determined.

[0142] Figure 9 An example of a mapping between the value of the stored bit 291 and threshold levels V0, V1, V2, and V3 is illustrated, which corresponds to a mapping between the value of the LP bit and the group 0 MLC level. Figure 9 The techniques of can be similarly applied to the mapping between the value of the UP bit (XP bit or TP bit) and the group 1 (2 or 3) MLC level.

[0143] Figure 10 According to one embodiment, a method for reading memory cells that are coarsely programmed in a set of predefined threshold levels is shown. For example, Figure 10 The method can be used by the read / write circuit 143 of the memory device 130 using the above combined Figure 9 The discussed techniques are implemented.

[0144] At block 321 , the memory device 130 sets the result of reading the stored bit 291 from the memory cell to a bit value (eg, 1) associated with a first threshold distribution region (eg, represented by the distribution curve 193 ).

[0145] At block 323, memory device 130 applies a read voltage (e.g., V) to memory cell 137 that is between two adjacent threshold distribution regions (e.g., represented by distribution curves 193 and 195) representing different bit values ​​(e.g., 1 and 0). R0 ).

[0146] At block 325, the memory device 130 determines whether the threshold voltage 221 of the memory cell 137 is below the read voltage (eg, V R0 For example, when reading a voltage (e.g., V R0) is compared with the threshold value. If the current is greater than the threshold value, then the threshold voltage 221 of the memory cell 137 is lower than the read voltage (e.g., V R0 and identifies the value of the stored bit 291. At block 331, the memory device 130 provides the result as the value of the stored bit 291.

[0147] If the threshold voltage 221 of the memory cell 137 is higher than the read voltage (eg, V R0 ), then at block 327, memory device 130 inverts the result to set the result to the bit value (e.g., 0) associated with the higher of the two regions (e.g., represented by distribution curve 195).

[0148] At block 329, the memory device 130 determines whether there is a next read voltage (eg, V R2 ), the next read voltage separates two adjacent threshold distribution regions (e.g., represented by distribution curves 197 and 199) representing different bit values ​​(e.g., 0 and 1). If there is a next read voltage, then the next read voltage (e.g., V R2 ) Repeat the operations in blocks 323 to 329.

[0149] Typically, a group of memory cells (e.g., 131) has different memory cells (e.g., 137, ..., 139) that are programmed to different levels in the MLC levels of groups 0, 1, 2, and 3. It is possible to sequentially read the memory cells in group 0 and the memory cells in group 1, etc. However, such an arrangement can result in the overhead of taking time to ramp the voltages to reach the read voltages for the respective groups 0, 1, 2, and 3.

[0150] To reduce overhead, the read voltages for groups 0, 1, 2, and 3 can be stacked, interleaved, and arranged in increasing order so that the memory device 130 can gradually increase the various read voltages applied to a group of memory cells (e.g., 137, ..., 139), from the lowest voltage to the highest read voltage. When a particular group of read voltages (e.g., group 0 MLC levels) is applied, the results for each memory cell belonging to that group can be updated based on the current sensed through the memory cell, as shown in FIG. Figure 11 As described in .

[0151] Figure 11

[0066] A technique for reading two bits of a memory cell coarsely programmed in QLC mode is described according to one embodiment.

[0152] Figure 11 The example uses Figure 6 The mapping of LP and UP bits shown in the QLC voltage level V0 to V 15The corresponding values ​​mapped to the LP and UP bits.

[0153] For the memory cells in group 0, the read voltage V R00 、V R10 and V R20 To determine the bit values ​​of the LP bit and the UP bit stored in the memory cell.

[0154] For the memory cells in group 1, the read voltage V R01 、V R11 and V R21 To determine the bit values ​​of the LP bit and the UP bit stored in the memory cell.

[0155] For the memory cells in group 2, the read voltage V R02 、V R12 and V R22 To determine the bit values ​​of the LP bit and the UP bit stored in the memory cell.

[0156] For the memory cells in group 3, the read voltage V R03 、V R13 and V R23 To determine the bit values ​​of the LP bit and the UP bit stored in the memory cell.

[0157] The read voltages for groups 0, 1, 2, and 3 may be in increasing order (e.g., V R00 ,、V R01 、V R02 、V R03 、V R10 、V R11 ,…,V R23 ) are stacked and staggered so that the memory devices 130 apply read voltages one after another as the read voltage increases to minimize the time overhead of setting the read voltage.

[0158] The values ​​of the LP bits of the memory cells in groups 0, 1, 2, and 3 are initially set to values ​​1, 1, 0, and 0 associated with the lowest threshold levels of groups 0, 1, 2, and 3 (eg, QLC levels VO, Vl, V2, and V3), respectively.

[0159] The values ​​of the UP bits of the memory cells in groups 0, 1, 2, and 3 are initially set to values ​​1, 0, 0, and 1 associated with the lowest threshold levels of groups 0, 1, 2, and 3 (e.g., QLC levels VO, Vl, V2, and V3), respectively.

[0160] When reading the voltage V R00 When applied to the memory cell group 131, the current through each memory cell of the group 0 is sensed. If the threshold voltage of the sensed memory cell is lower than the applied read voltage V R00, then the assumed bit value 1 programmed at V0 is confirmed; and no further updates to the LP bit value are performed. Optionally, a read operation at one or more higher read voltages (e.g., V R20 ) under further sensing; however, since the threshold voltage of the sensed memory cell will again be confirmed to be lower than the applied read voltage (eg, V R20 ), so no further update is performed on the assumed value. Otherwise, if the threshold voltage of the sensed memory cell is higher than the applied read voltage V R00 , then the assumed bit value of the sensed memory cell is inverted to 0, corresponding to the 0 value associated with the next level V4 and V8 of the group 0 memory cell; and until the read voltage V R20 The LP bit value of the group 0 memory cell will be updated or confirmed.

[0161] Since the value of the UP bit remains the same for V0 and V4, in response to reading the voltage V R00 The memory cells of group 0 are sensed and no operation is required / performed.

[0162] Subsequently, the memory device 130 increases the voltage applied to the memory cell group 131 to V R01 . Sense the current through each group 1 memory cell; and can be based on the read voltage V R01 The current sensing result under the current is used to confirm or invert the assumed LP bit for the sensed memory cell. Since the group 1 memory cells may have different values ​​for their UP bits for reading at voltages below the read voltage V R01 V1 is higher than the read voltage V R01 The V5 of the program can also be based on the read voltage V R01 The current sensing result under is used to confirm or invert the assumed UP bit for the sensed memory cell. R01 The current sensing results performed on the Group 1 memory cells can be used to confirm or invert both their LP and UP bits.

[0163] Subsequently, the memory device 130 increases the voltage applied to the memory cell group 131 to V R02 Since the LP bit value is for the voltage across V R02 The threshold voltage remains the same, so in response to the read voltage V R02 However, the value of the UP bit is lower than V R02 The threshold voltage changes to have a value higher than V R02 The threshold voltage can be based on the read voltage V R02 The current sensing result below is used to confirm or invert the assumed UP bit for the sensed memory cell.

[0164] Subsequently, the memory device 130 increases the voltage applied to the memory cell group 131 to V R03 Since the LP bit value is for the voltage across V R03 The threshold voltage remains the same, so in response to the read voltage V R02 The UP bit has a value lower than V R03 The threshold voltage changes to have a value higher than V R03 The threshold voltage can be based on the read voltage V R03 The current sensing result below is used to confirm or invert the assumed UP bit for the sensed memory cell.

[0165] In a similar manner, when the memory device 130 increases the voltage applied to the memory cell group 131 to V R10 , V of group 1 R11 , V of group 2 R12 and V in group 3 R13 , respectively, based on the V R12 and V of group 3 storage cells R13 The current sensing result under the condition of LP is used to confirm or reverse the assumed LP value; and the V R10 , V of group 1 storage unit R11 and V of the group 2 memory cells R12 The current sense result below is used to confirm or invert the assumed UP value.

[0166] Subsequently, when the memory device 130 increases the voltage applied to the memory cell group 131 to V R20 , V of group 1 R21 , V of group 2 R22 and V in group 3 R23 , respectively, based on the V R20 and V of group 1 storage cells R21 The current sensing result under the condition of LP is used to confirm or reverse the assumed LP value; and the V R21 , V of group 2 storage cells R22 and V of group 3 memory cells R23 The current sense result below is used to confirm or invert the assumed UP value.

[0167] Figure 11 An example of reading the LP bit and the UP bit is described. After determining the LP bit and the UP bit, the XP bit and the TP bit can be calculated from the LP bit and the UP bit and the group identifier 207, as shown in Figure 8 As described in .

[0168] In some cases, a request is received to retrieve one of the data groups 151, 157, ..., 159 corresponding to the value of the LP bit of the memory cells 137, ..., 139 in the memory cell group 131. In response to such a request, operations related to reading the UP bit may be skipped. For example, the operation of reading the UP bit at the voltage V may be skipped. R02 、V R03 、V R11 、V R22 and V R23 This is because the sensing result is used to determine the UP bit but not the LP bit.

[0169] Similarly, in response to a request for the value of the UP bit of memory cells 137 , . . . , 139 in memory cell group 131 , operations related to reading the LP bit but not related to reading the UP bit may be skipped.

[0170] In addition, the voltage V R00 、V R01 、V R02 、V R03 、V R10 ,…,V R22 and V R23 The result of sensing the current at the applied read voltage is similarly read (e.g., assumed, confirmed, inverted) TP and / or XP bits. For example, a request may be made to retrieve the TP values ​​of a page of memory cells that do not have LP values, UP values, or XP values. Thus, some of the read voltages (e.g., V R10 、V R11 ) current sensing under .

[0171] Figure 12 A method of two-pass programming of memory cells is shown according to some embodiments. Figure 12 The method may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software / firmware (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 12 The method is at least partly based on Figure 1 Controller 150 or Figure 2 The processing logic in the memory device 130 is executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0172] For example, Figure 12 The method may be implemented in the memory device 130 and / or the program manager 113 of the memory subsystem 110 .

[0173] At block 341, program manager 113 receives multiple pages of data bits. For example, controller 115 of memory subsystem 110 may send a write command where four pages of data are to be stored in a page of memory cells in memory device 130. Memory device 130 may place the four pages in latches 145 to facilitate programming of four data bits in each memory cell in the page of memory cells.

[0174] At block 343, the program manager 113 instructs the read / write circuit 143 to coarsely program the threshold voltage of each respective memory cell (e.g., 137) in the page of memory cells to a respective first level 203 representing a combination of bit values ​​for data bits 161, 163, ... 165, each data bit from one of the plurality of pages of data bits. The first level 203 represents the combination according to a first mapping 201 between combinations of bit values ​​and threshold levels. Each of the threshold levels is in one of a plurality of groups; and each of the plurality of groups contains a subset of the threshold levels and has a set of associated read voltages that separate the threshold levels in the subset.

[0175] For example, when four pages of data bits are received for storage in a page of memory cells, the data bits 161, 163, ..., 165 may be LP bit 261, UP bit 263, XP bit 265, and TP bit 267; and the first mapping 201 may be based on Figure 6 The table illustrated in is used to store data in corresponding memory cells 137 in quad level cell (QLC) mode.

[0176] For example, the threshold levels may be divided into groups such that between each pair of closest threshold levels in each respective one of a plurality of groups, there exists a threshold level that is in a group other than the respective one of the plurality of groups, as in Figure 5 and Figure 6 The threshold levels of the different groups are staggered; and the read voltages of the groups are staggered, as in Figure 12 As described in .

[0177] At block 345, the program manager 113 calculates the group identifier 207 for the corresponding memory cell 137 to identify a first group of the plurality of groups containing the corresponding first level. The group identifier may have at least two bits to separate the threshold levels into a larger number of groups and thereby reduce the number of threshold levels in the first group and reduce the accuracy requirements for coarse programming of the corresponding memory cell 137 while allowing reading of data stored in the coarsely programmed corresponding memory cell 137.

[0178] For example, a first bit 272 of the two bits of the group identifier 207 may be calculated based on applying a logical operation to two of the data bits (e.g., the LP bit 261, the UP bit 263, the XP bit 265, and the TP bit 267) (e.g., the LP bit 261 and the TP bit 267). A second bit 274 of the two bits of the group identifier 207 may be calculated based on applying a logical operation to the data bits (e.g., the LP bit 261, the UP bit 263, the XP bit 265, and the TP bit 267), as shown in FIG. Figure 6 、 Figure 7 and Figure 8 As described in .

[0179] Alternatively, the group identifier 207 may be calculated based on the QLC threshold level number 0, 1, 2, . . . , 15.

[0180] To read 213 the data bits (e.g., LP bit 261, UP bit 263, XP bit 265, and TP bit 267) back from the corresponding memory cell 137 into the latch 145, the memory device 130 may determine a subset of the data bits (e.g., LP bit 261 and UP bit 263) based on testing the threshold voltage 221 of the corresponding memory cell 137 at a read voltage identified according to the group identifier. For example, the read voltage V R00 、V R10 and V R20 For group 0, read the voltage V R01 、V R11 and V R21 For group 1, read the voltage V R02 、V R12 and V R22 For group 2, and read the voltage V R03 、V R13 and V R23 For group 3. Based on the subset (e.g., LP bit 261 and UP bit 263) and the group identifier 207, the memory device 130 can calculate the value of at least two of the data bits. For example, when the group identifier 207 has bits 272 and 274, the TP bit 267 and the XP bit 265 can be calculated based on the group identifier 207 and the remaining bits read 213 from the corresponding memory cell 137.

[0181] When data groups 151, 157, ..., 159 are coarsely programmed in memory cell group 131, the group identification (e.g., 207) of each memory cell (e.g., 137) in memory cell group 131 identifies a threshold level subset containing the first level 203 of the corresponding memory cell (e.g., 137). On the other hand, a given group identification (e.g., 207) identifies a subset of memory cells (e.g., 137) in memory cell group 131 that are coarsely programmed to the threshold levels represented by the corresponding threshold level group.

[0182] The memory device 130 can buffer the group identification 207 in at least two second memory cells in a single-level cell (SLC) mode. To read the coarsely programmed memory cell 137, the memory device 130 reads the at least two second memory cells in the SLC mode to retrieve the group identification 207 before fine threshold programming 229 of the threshold voltage 225 of the memory cell 137.

[0183] At block 347 , program manager 113 instructs read / write circuitry 143 to ramp voltages applied to the page of memory cells to a sequence of read voltages in increasing order to retrieve multiple pages of data bits from the page of memory cells, with multiple groups of read voltages interleaved in the sequence.

[0184] Since the read voltages from different groups are interleaved and arranged in increasing order for sequential application to a page of memory cells, the waveform of the voltages applied to the memory cells resembles a staircase. The voltage increases over time and remains at the level of each read voltage for a period of time during which sensing is performed to determine whether the threshold voltage 221 of the corresponding memory cell 137 is higher than the read voltage.

[0185] Some of the read voltages in the sequence are not relevant to reading corresponding memory cells 137 and / or some of the data page, but may be used to read other memory cells in the page of memory cells having a different group identification 207 than memory cell 137 .

[0186] At block 349 , program manager 113 instructs read / write circuitry 143 to determine whether the threshold voltage 221 of the corresponding memory cell 137 is lower than the read voltage in the sequence when the read voltage applied to the page of memory cells is associated with the first group, as identified by the group identification 207 of the memory cell 137 .

[0187] For example, it may be determined whether the threshold voltage 221 of the corresponding memory cell 137 is lower than the read voltage in the sequence by sensing whether the current through the corresponding memory cell 137 subjected to the read voltage is higher than a threshold.

[0188] For example, as an initial assumption, the bit of the number of data pages to be read from the page of memory cells may be set / initialized to the value identified by the lowest threshold level in the group identified by the group identification of the memory cells.

[0189] In response to determining that the threshold voltage 221 of the corresponding memory cell 137 is lower than the read voltage associated with the first group of the corresponding memory, the value of the bit in each of the at least two pages of data bits can be set, confirmed, accepted, or finalized when reading back from the memory cell page to prevent further changes in subsequent read voltages of the first group.

[0190] In response to determining that the threshold voltage 221 of the corresponding memory cell 137 is higher than the read voltage associated with the first group of the corresponding memory, the value of the bit in each of the at least two pages of data bits to be read back from the memory cell page can be inverted / updated as an updated hypothesis.

[0191] After retrieving the data bits 161, 163, ..., 165 from the corresponding memory cell 137 back into the latch 145, the programming manager 113 instructs the read / write circuit 143 to fine-program the threshold voltage 225 of the corresponding memory cell 137 to a second level 223 representing the combination of values ​​of the data bits obtained from reading the first memory cell based on a second mapping 217 between the combination of values ​​of the bits and the threshold levels.

[0192] Optionally, the second map 217 may be the same as the first map 201, and the second level 223 may be the same as the first level 203. A second threshold programming pass 229 is performed to reduce the width of the threshold distribution region so that the corresponding memory cells 137 can be read according to the second map 217 without the aid of the group identifier 207. After the second threshold programming pass 229, the group identifier 207 may be discarded.

[0193] Figure 13 An example machine illustrating a computer system 400 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or may be used to perform operations of the program manager 113 (e.g., execute instructions to perform operations corresponding to the reference Figures 1 to 12 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0194] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0195] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 418 that communicate with each other via a bus 430 (which may include multiple buses).

[0196] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communicating over a network 420.

[0197] The data storage system 418 may include a machine-readable medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution of the instructions by the computer system 400, with the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0198] In one embodiment, instructions 426 include instructions for implementing instructions corresponding to program manager 113 (e.g., referring to Figures 1 to 12 The machine-readable storage medium 424 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0199] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means used by those skilled in the data processing arts to convey the essence of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, or otherwise manipulated. It has proven convenient at times, primarily for reasons of commonality, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0200] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0201] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for a particular purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0202] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Based on the teachings herein, various general-purpose systems can be used with the program, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will be described below. Additionally, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0203] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0204] In this description, various functions and operations are described as being performed by or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such expressions mean that the functions are generated by the execution of computer instructions by one or more controllers or processors (e.g., microprocessors). Alternatively, or in combination, dedicated circuitry with or without software instructions may be used to implement the functions and operations, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Therefore, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0205] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method implemented in a memory device, comprising: receiving a plurality of data bit pages; programming a threshold voltage of each respective memory cell in a page of memory cells to a respective first level representing a combination of bit values ​​based on a first mapping between combinations of bit values ​​and threshold levels, each bit value being from one of the plurality of pages of data bits, each of the threshold levels being in one of a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having an associated set of read voltages separating the threshold levels in the subset; calculating a group identifier of the corresponding memory cell, the group identifier identifying a first group among the plurality of groups, the first group containing the corresponding first level, the group identifier having at least two bits; ramping a voltage applied to the page of memory cells to a sequence of read voltages in increasing order to retrieve the plurality of pages of data bits from the page of memory cells, wherein the plurality of groups of read voltages are interleaved in the sequence; and When the read voltage applied to the page of memory cells is associated with the first group, it is determined whether the threshold voltage of the corresponding memory cell is lower than a read voltage in the sequence.

2. The method according to claim 1, further comprising: In response to a determination that the threshold voltage of the corresponding memory cell is below the read voltage, a value of a bit in each of at least two of the plurality of pages of data bits is set.

3. The method according to claim 1, further comprising: Bits in a respective one of the plurality of pages of data bits are initialized, the bits stored in the respective memory cells and initialized to have values ​​represented by a lowest threshold level in the first group of the respective page.

4. The method according to claim 3, further comprising: Responsive to a determination that the threshold voltage of the corresponding memory cell is above the read voltage, the value of the bit is inverted.

5. The method according to claim 3, further comprising: In response to a determination that the threshold voltage of the corresponding memory cell is below the read voltage, the value is accepted as stored in the corresponding memory cell of the bit to prevent further changes at subsequent read voltages.

6. The method of claim 5 , wherein the determining whether the threshold voltage of the corresponding memory cell is lower than the read voltage comprises: A sense is then made as to whether a current passing through the corresponding memory cell exceeds a threshold value.

7. The method of claim 6, wherein between each pair of closest threshold levels in each corresponding group in the plurality of groups, there is a threshold level, each threshold level being in a group in the plurality of groups other than the corresponding group.

8. The method according to claim 7, further comprising: The threshold voltages of the respective memory cells in the page of memory cells are programmed to respective second levels representing the combinations of bit values ​​according to a second mapping between the combinations of bit values ​​and threshold levels.

9. The method of claim 8, wherein the first mapping and the second mapping are configured to program the voltage thresholds of the respective memory cells to store data in a quad level cell (QLC) mode.

10. The method of claim 8, wherein the second mapping is the same as the first mapping; and the second level is equal to the first level.

11. A memory device comprising: an integrated circuit package enclosing the memory device; a plurality of pages of memory cells formed on at least one integrated circuit die; and latch; wherein in response to a command identifying a page of memory cells within the plurality of pages of memory cells, the memory device is configured to, receiving a plurality of pages of data bits in the latch; programming, in a first pass, a threshold voltage of each respective memory cell in the page of memory cells to a respective first level representing a combination of bit values ​​according to a mapping between combinations of bit values ​​and threshold levels, each bit value being from one of the plurality of pages of data bits, the threshold levels being divided into a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having an associated set of read voltages separating the threshold levels in the subset; calculating at least two pages of bits of a group identifier, the corresponding memory cell having a group identifier having one bit in each of the at least two pages, the group identifier of the corresponding memory cell identifying a first group among the plurality of groups, the first group having the corresponding first level to which the corresponding memory cell was programmed in the first pass; increasing a voltage applied to the page of memory cells to a sequence of read voltages in increasing order to read the page of memory cells, wherein the plurality of groups of read voltages are interleaved in the sequence; determining the plurality of pages of data bits read into the latch based on whether the threshold voltage of the corresponding memory cell is lower than the read voltage in the sequence when the read voltage applied to the page of memory cells is associated with the first group; and In a second pass, the threshold voltages of the respective memory cells in the page of memory cells are programmed to the respective first levels representing the combination of bit values ​​according to the mapping.

12. The memory device of claim 11 , wherein between each pair of closest threshold levels in each respective one of the plurality of groups, there is a threshold level, each threshold level being in one of the plurality of groups other than the respective one; and the memory device is configured to sense whether a current through the respective memory cell exceeds a threshold value to determine whether the threshold voltage of the respective memory cell is lower than the read voltage.

13. The memory device of claim 12 , wherein the memory device is configured to initialize the latch to a bit in a page of the plurality of pages of data bits to a value represented by a lowest threshold level in a respective group identified by a respective group identification of memory cells in the page of memory cells.

14. The memory device of claim 13, wherein the memory device is configured to ultimately determine a value of a bit in at least one of the plurality of pages of data bits in response to a determination that the threshold voltage of the corresponding memory cell is below the read voltage.

15. The memory device of claim 14, wherein the memory device is configured to invert a value read for a bit in at least one of the plurality of pages of data bits in response to a determination that the threshold voltage of the corresponding memory cell is above the read voltage.

16. A memory subsystem comprising: processing device; and at least one memory device having a plurality of pages of memory cells, including a first page of memory cells and at least two second pages of memory cells; wherein the processing device is configured to provide a plurality of pages of data to the memory device and identify the first page of memory cells to store the plurality of pages of data; wherein in response to the plurality of data pages, the memory device is configured to: performing a first programming pass on the first page of memory cells, wherein a threshold voltage of each respective memory cell in the first page of memory cells is programmed to a respective first level representing a combination of bit values ​​based on a mapping between combinations of bit values ​​and threshold levels, each bit value being from one of the plurality of data pages, the threshold levels being divided into a plurality of groups, each of the plurality of groups containing a subset of the threshold levels and having an associated set of read voltages separating the threshold levels in the subset; calculating at least two pages of bits of a group identifier, the corresponding memory cell having a group identifier having one bit in each of the at least two pages, the group identifier being calculated to identify a first group among the plurality of groups, the first group having the corresponding first level to which the corresponding memory cell was programmed in the first programming pass; buffering the at least two page bits of a group identification in the at least two second memory cell pages in a single level cell (SLC) mode; increasing a voltage applied to the page of memory cells to a sequence of read voltages in increasing order to read the first page of memory cells, wherein the plurality of groups of read voltages are staggered in the sequence; responsive to a determination that the read voltage applied to the page of memory cells is associated with the first group, determining bits of the plurality of pages of data based on whether the threshold voltage of the corresponding memory cell is below the read voltage in the sequence; and In a second pass, the threshold voltages of the respective memory cells in the first page of memory cells are programmed to the respective first levels representing the combination of bit values ​​according to the mapping.

17. The memory subsystem of claim 16, wherein between each pair of closest threshold levels in each respective one of the plurality of groups, there exists a threshold level, each threshold level being in a group other than the respective one of the plurality of groups.

18. The memory subsystem of claim 17, wherein the plurality of data pages is 4 pages of data; and the mapping is configured to program the voltage thresholds of the respective memory cells to store data in a quad level cell (QLC) mode.

19. The memory subsystem of claim 17, wherein the memory device is further configured to: Whether the current through the respective memory cell exceeds a threshold is determined as an indication of whether the threshold voltage of the respective memory cell is below the read voltage.

20. The memory subsystem of claim 19, wherein the memory device is further configured to: A value of a bit in each of at least two of the plurality of data pages is updated based on whether the threshold voltage of the corresponding memory is lower than the read voltage.

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