Wide bandgap semiconductor dual-sided heat spreading module package structure based on conductive metal ribbons

Abstract

The application discloses a kind of wide band gap semiconductor double-sided heat dissipation module packaging structures based on conductive metal strip, and the semiconductor power chip of different bridge arm is arranged on different power substrate, the volume of module is reduced, and the power density of module is greatly improved;Power gasket is arranged between top and bottom power substrate, and it plays a mechanical support and electrical connection role, provides additional heat dissipation path for each semiconductor power chip on the basis of double-sided heat dissipation, reduces the degree of thermal coupling between chips, achieves chip temperature uniformity effect, while improving chip heat dissipation environment;Driving circuit and commutation circuit are close to vertical in space, and the degree of electromagnetic coupling between circuits is greatly reduced, and the reliability of module is further improved;The conductive metal strip is used in commutation circuit to complete the electrical connection required by chip, and the numerical value of module parasitic inductance is greatly reduced, wherein the hole slot is opened in the connection of source conductive metal strip, which can improve the uniformity of parasitic inductance distribution, and achieve chip current sharing effect.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a wide-bandgap semiconductor double-sided heat dissipation module packaging structure based on a conductive metal belt. BACKGROUND

[0002] A power module is a module formed by re-packaging a plurality of power semiconductor chips according to certain functions. Compared with discrete power devices, the power module has high integration, and thus has great advantages in electrical performance, thermal performance, and economic considerations.

[0003] In recent years, with the rapid development of industries represented by new energy grid connection, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, and pulse power, the performance requirements of power electronic systems on semiconductor power modules are increasingly improved, promoting the development of power modules in the direction of miniaturization, low loss, high power density, high reliability, and high integration. Silicon carbide power devices, as a new generation of wide-bandgap semiconductor materials, have far superior performance than traditional silicon-based devices, so that modules using wide-bandgap semiconductor power chips such as silicon carbide have smaller size at the same voltage and current level, and can work at higher temperature and switching frequency. However, the silicon carbide device basically follows the packaging technology of silicon, which is becoming a bottleneck factor limiting the performance of the device, mainly manifested in:

[0004] 1. The traditional power module is designed for silicon-based power semiconductor chips with a larger area, and the number of chips arranged on the same metal area of the substrate is small and often requires anti-parallel power diodes. The area of the wide-bandgap semiconductor power chip represented by silicon carbide is much smaller than that of silicon, and the body diode has excellent characteristics, so that the anti-parallel diode can be selected and more chips can be integrated in the module.

[0005] 2. The thermal performance of the traditional power module cannot meet the requirements of the wide-bandgap semiconductor power chip. The traditional power module adopts a single-sided heat dissipation mode, and the semiconductor power chip is mainly dissipated through the single heat dissipation path of the bottom substrate and the heat sink. The thermal resistance from the chip to the surrounding environment is large, which is very unfavorable for the long-term reliable operation of the power module. At the same time, the traditional power module mostly uses aluminum bonding wires for electrical interconnection. In the case where heat cannot be well dissipated, connection failure easily occurs at the bonding point. Although the thermal conductivity of silicon carbide is higher than that of silicon, the chip area is much smaller than that of silicon, and the heat dissipation environment is more severe. The packaging material of the traditional module is selected to match the thermal expansion coefficient of silicon, but the thermal expansion coefficient of the wide-bandgap semiconductor material is quite different from that of silicon, and thermal reliability problems easily occur.

[0006] 3. Traditional power module is difficult to realize the current sharing of power chip, and this performance is crucial at high switching frequency. Different parasitic inductance can cause uneven dynamic current distribution of the chip, and temperature difference and thermal coupling of the chip can cause uneven static current distribution of the chip. Especially, the switching speed of wide bandgap power semiconductor chip is much higher than that of silicon, and in the dynamic switching process, the chip breakdown and temperature difference are more likely to occur, thereby further accelerating the failure process of the whole module.

[0007] In summary, the power chip based on wide bandgap semiconductor material is limited by the traditional packaging, and does not play the excellent electrical and thermal performance of the material itself. Therefore, a new module packaging suitable for wide bandgap semiconductor is needed to overcome the shortcomings and limitations of the traditional power module packaging structure, and to play the excellent performance of the wide bandgap power semiconductor chip. SUMMARY

[0008] The technical problem to be solved by the present application is to provide a wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strip to overcome the shortcomings of the prior art, which improves and extends the existing module heat dissipation technology and interconnection technology. The packaging form is particularly suitable for wide bandgap power semiconductor chips and is compatible with silicon-based devices. In addition, the present application is particularly suitable for half-bridge structure multi-chip, large current temperature equalization, high working temperature and high switching frequency.

[0009] The present application adopts the following technical scheme:

[0010] A wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strip, comprising a top power substrate and a bottom power substrate, a power gasket is arranged between the top power substrate and the bottom power substrate, the top power substrate and the bottom power substrate are respectively connected with power terminals, and a wide bandgap power semiconductor chip is arranged between the power terminal and the bottom power substrate and between the power terminal and the bottom power substrate. The wide bandgap power semiconductor chip is connected to the upper surface metal area of the bottom power substrate and the lower surface metal area of the top power substrate through the conductive metal strip, the upper surface metal area of the bottom power substrate is connected with the upper bridge arm driving terminal of the driving terminal, and the lower surface metal area of the top power substrate is connected with the lower bridge arm driving terminal of the driving terminal.

[0011] Specifically, the top power substrate comprises a top upper surface metal layer, a top insulating dielectric layer and a top lower surface metal layer from top to bottom.

[0012] Further, the top lower surface metal layer is sequentially provided with a top first metal area, a top second metal area, a top third metal area, a top fourth metal area and a top fifth metal area, the top second metal area is connected with a direct current side power gasket, and the top third metal area is a Kelvin source metal area.

[0013] The lower bridge arm driving terminal comprises a first lower bridge arm gate driving terminal, a first lower bridge arm source driving terminal, a second lower bridge arm gate driving terminal and a second lower bridge arm source driving terminal; the first lower bridge arm gate driving terminal and the second lower bridge arm gate driving terminal are arranged at two ends of the top fourth metal region, and the first lower bridge arm source driving terminal and the second lower bridge arm source driving terminal are arranged at two ends of the top third metal region.

[0014] Specifically, the bottom power substrate comprises, from top to bottom, a bottom upper surface metal layer, a bottom insulating dielectric layer and a bottom lower surface metal layer.

[0015] Further, the bottom upper surface metal layer is sequentially provided with a bottom first metal region, a bottom second metal region, a bottom third metal region and a bottom fourth metal region, and the bottom third metal region is a Kelvin source metal region.

[0016] The upper bridge arm driving terminal comprises a bottom first gate driving terminal, a bottom first source driving terminal, a bottom second gate driving terminal and a bottom second source driving terminal; the bottom first gate driving terminal and the bottom second gate driving terminal are arranged at two ends of the bottom second metal region, and the bottom first source driving terminal and the bottom second source driving terminal are arranged at two ends of the bottom third metal region.

[0017] Specifically, the wide bandgap power semiconductor chip comprises a plurality of semiconductor chips, and the plurality of semiconductor chips are connected in parallel in two groups to form an upper bridge arm and a lower bridge arm of a half-bridge structure; the chips at the upper bridge arm are arranged on the upper surface metal layer of the bottom power substrate, and the chips at the lower bridge arm are arranged on the lower surface metal layer of the top power substrate.

[0018] Further, the number of the two groups of semiconductor chips is the same, and the spacing between the semiconductor chips in the same group is the same.

[0019] Specifically, the conductive metal strip comprises a source conductive metal strip and a gate conductive metal strip; the wide bandgap power semiconductor chip is arranged on the drain metal region; the drain electrode region of the wide bandgap power semiconductor chip is connected with the drain metal region; the gate electrode region of the wide bandgap power semiconductor chip is connected with the gate metal region through the gate conductive metal strip; the source electrode region of the wide bandgap power semiconductor chip is connected with the Kelvin source metal region and the source metal region through the source conductive metal strip; and a hole groove is formed in the connection contact part of the source conductive metal strip, the wide bandgap power semiconductor chip, the Kelvin source metal region and the source metal region.

[0020] Specifically, the power terminal includes an alternating current power terminal and two direct current power terminals, the two direct current terminals are a direct current positive power terminal and a direct current negative power terminal, the direct current positive power terminal and the alternating current power terminal are arranged on the bottom power substrate, and the direct current negative power terminal is arranged on the top power substrate.

[0021] Further, the first decoupling capacitor and the second decoupling capacitor are arranged between the direct current positive power terminal and the direct current negative power terminal.

[0022] Compared with the prior art, the application has at least the following beneficial effects:

[0023] The application discloses a wide-bandgap semiconductor double-sided heat dissipation module packaging structure based on a conductive metal strip.

[0024] Further, the top power substrate is a typical three-layer structure, the upper surface metal layer is connected with a heat sink through a substrate or directly, heat dissipation of the module is realized, the middle ceramic layer is used for insulation and heat conduction, and the lower surface metal layer is divided into a plurality of metal regions and used for electrical connection and heat conduction of the semiconductor chips.

[0025] Further, the source metal region and the drain metal region of the lower surface metal layer of the top power substrate adopt large-area copper, current flow capacity and module heat conduction capacity are greatly enhanced, a Kelvin source metal region is separately arranged on the lower surface metal layer, gate Kelvin connection of a control loop is realized through cooperation of the conductive metal strip, common source inductance of a commutation loop and the control loop is greatly reduced, the driving terminal and the power terminal are separately led out, and interference influence of a power loop on a driving loop is further eliminated.

[0026] Further, similar to the top power substrate, the bottom power substrate is a typical three-layer structure, the upper surface metal layer is divided into a plurality of metal regions and used for electrical connection and heat conduction of the semiconductor chips, the middle ceramic layer is used for insulation and heat conduction, and the lower surface metal layer is connected with a heat sink through a substrate or directly, heat dissipation of the module is realized.

[0027] Further, similar to the top power substrate lower surface metal layer, the source metal region and the drain metal region of the bottom power substrate upper surface metal layer use large-area copper, greatly enhancing the current flow capacity and module heat dissipation capacity, and a Kelvin source metal region is separately provided on the upper surface metal layer, and the gate Kelvin connection of the control loop is realized through the conductive metal belt, greatly reducing the common source inductance of the commutation loop and the control loop, and simultaneously realizing the separate leading out of the driving terminal and the power terminal, further eliminating the interference influence of the power loop on the driving loop.

[0028] Further, the upper and lower bridge arm semiconductor chips are respectively arranged on different power substrates, which, compared to being arranged on the same power substrate, greatly improves the space utilization and realizes high power density of the module, and on the other hand, the number of heat generating chips of a single substrate is reduced by half, and the thermal performance of the module is further improved.

[0029] Further, the number of the two groups of semiconductor chips is the same, and the same group of semiconductor chips is arranged at the same spacing, and the purpose or benefit of arranging the two groups of semiconductor chips of the upper and lower bridge arms at the same spacing is that the number of the two groups of semiconductor chips is the same, and the same group of semiconductor chips is arranged at the same spacing, which ensures that each semiconductor chip in the module is in the same or similar electric and thermal stress environment when the module works, thereby realizing current sharing and temperature sharing of the module.

[0030] Further, the interconnection of the chip and the power substrate metal region is realized by using a metal belt, which has a larger cross-sectional area and a higher working temperature than an aluminum bonding wire, and has a larger current flow capacity while reducing the parasitic inductance of the commutation loop, and the source conductive metal belt is provided with a hole slot at the contact connection with the chip and the substrate metal region, and the size and position of the hole slot are adjusted flexibly to make the parasitic inductance of each chip more uniform, thereby realizing current sharing of the parallel multi-chips.

[0031] Further, the DC positive power terminal and the DC negative power terminal are arranged on the same side in space and are respectively arranged on the bottom power substrate and the top power substrate, and a laminated busbar structure can be easily designed, and the combination of multiple modules in series and parallel and the installation of decoupling capacitors can be realized; at the same time, this structure can realize the opposite direction of the upper and lower bridge arm currents in space, and the negative mutual inductance weakens the parasitic inductance.

[0032] Further, by arranging decoupling capacitors between the DC power terminals, the inductance other than the power terminals is avoided from being introduced into the loop when the module works, thereby effectively alleviating the voltage and current overshoot and oscillation phenomenon occurring when the module is in the switching state, and improving the stability of the module.

[0033] In summary, the application benefits from the optimized design of the power pad and the conductive metal strip, the decoupling design of the drive circuit and the commutation circuit, which greatly reduces the thermal coupling between the wide bandgap power semiconductor chips and the electromagnetic coupling between the circuits, and can greatly improve the thermal, electrical and mechanical performance of the module, thereby fully utilizing the excellent characteristics of the wide bandgap power semiconductor chips, so that the power module can reliably work in harsh or extreme environments.

[0034] The technical solutions of the application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 The overall structure of the embodiment of the application does not contain drive terminals and conductive metal strips;

[0036] Figure 2 The bottom power substrate layout and the upper bridge arm drive terminal structure in the embodiment of the application are shown in the schematic diagram;

[0037] Figure 3 The top power substrate layout and the lower bridge arm drive terminal structure in the embodiment of the application are shown in the schematic diagram;

[0038] Figure 4 The setting of the conductive metal strip in the embodiment of the application is shown in the schematic diagram;

[0039] Figure 5 The heat dissipation path of the semiconductor power chip in the embodiment of the application is shown in the schematic diagram;

[0040] Figure 6 The current flow path of the upper bridge arm drive circuit in the embodiment of the application is shown in the schematic diagram;

[0041] Figure 7 The current flow path of the lower bridge arm drive circuit in the embodiment of the application is shown in the schematic diagram;

[0042] Figure 8 The upper bridge arm part of the current flow path of the commutation circuit in the embodiment of the application is shown in the schematic diagram;

[0043] Figure 9 The lower bridge arm part of the current flow path of the commutation circuit in the embodiment of the application is shown in the schematic diagram;

[0044] Figure 10 The schematic diagram of the power module integrated decoupling capacitor and fin column heat sink in the embodiment of the application is shown in the schematic diagram. DETAILED DESCRIPTION

[0045] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are some of the embodiments of the present application but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0046] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "one side", "one end", "one edge" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] It should be understood that when used in the present specification and the appended claims, the terms "comprise" and "include" indicate the existence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or sets thereof.

[0049] It should also be understood that the terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, unless otherwise specified by the context, the singular form "a", "an" and "the" is intended to include the plural form.

[0050] It should be further understood that the term "and / or" as used in the specification and in claims of the application, means any one and / or all possible combinations of the associated listed items, and includes these combinations.

[0051] The various structural diagrams according to the disclosed embodiments of the application are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others omitted. The shapes and relative sizes of the various regions, layers, and their relative positions shown in the diagrams are merely exemplary, and in actuality can deviate due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0052] The application provides a wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips, in which semiconductor power chips with different bridge arms are arranged on different power substrates to reduce the volume of the module and greatly improve the power density of the module; power pads are arranged between the top and bottom power substrates to play a mechanical support and electrical connection role, provide an additional heat dissipation path for each semiconductor power chip on the basis of double-sided heat dissipation, reduce the degree of thermal coupling between the chips, achieve the effect of uniform temperature of the chips, and improve the chip heat dissipation environment; the driving circuit and the commutation circuit are nearly vertical in space, the degree of electromagnetic coupling between the circuits is greatly reduced, and the reliability of the module is further improved; the commutation circuit uses conductive metal strips to complete the electrical connection required by the chips, the parasitic inductance value of the module is greatly reduced, and among them, the source conductive metal strip is provided with a hole slot at the connection position, which can improve the uniformity of the parasitic inductance distribution and achieve the effect of uniform current of the chips.

[0053] Please refer to Figure 1 The application provides a wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips, in which semiconductor power chips with different bridge arms are arranged on different power substrates to reduce the volume of the module and greatly improve the power density of the module; power pads are arranged between the top and bottom power substrates to play a mechanical support and electrical connection role, provide an additional heat dissipation path for each semiconductor power chip on the basis of double-sided heat dissipation, reduce the degree of thermal coupling between the chips, achieve the effect of uniform temperature of the chips, and improve the chip heat dissipation environment; the driving circuit and the commutation circuit are nearly vertical in space, the degree of electromagnetic coupling between the circuits is greatly reduced, and the reliability of the module is further improved; the commutation circuit uses conductive metal strips to complete the electrical connection required by the chips, the parasitic inductance value of the module is greatly reduced, and among them, the source conductive metal strip is provided with a hole slot at the connection position, which can improve the uniformity of the parasitic inductance distribution and achieve the effect of uniform current of the chips.

[0054] The power pad is arranged between the top power substrate 100 and the bottom power substrate 200, the power terminal comprises an alternating current power terminal 211 and two direct current power terminals, the two direct current terminals are a direct current positive power terminal 210 and a direct current negative power terminal 110, the direct current positive power terminal 210 and the alternating current power terminal 211 are arranged on the bottom power substrate 200, and the direct current negative power terminal 110 is arranged on the top power substrate 100; the wide bandgap power semiconductor chip 400 comprises a plurality of bottom semiconductor chips and a plurality of top semiconductor chips, the plurality of bottom semiconductor chips and the plurality of top semiconductor chips jointly constitute an upper bridge arm and a lower bridge arm of a half-bridge structure, the bottom semiconductor chip is arranged between the power terminal and the bottom power substrate 200, and the top semiconductor chip is arranged between the power terminal and the top power substrate 100; the driving terminal comprises an upper bridge arm driving terminal and a lower bridge arm driving terminal, the upper bridge arm driving terminal is connected with the upper surface metal area of the bottom power substrate 200, and the lower bridge arm driving terminal is connected with the lower surface of the top power substrate 100; the wide bandgap power semiconductor chip 400 and the conductive metal area of the power substrate are connected through a conductive metal strip, the conductive metal strip comprises a source conductive metal strip 500 and a gate conductive metal strip 600, the source conductive metal strip 500 and the gate conductive metal strip 600 are arranged in a matched mode with the wide bandgap power semiconductor chip 400, and are used for realizing electrical connection between the wide bandgap power semiconductor chip 400 and the metal of the top power substrate 100 and the bottom power substrate 200.

[0055] The lower surface of the top power substrate 100 is provided with the direct current negative terminal 110, the first lower bridge arm driving terminal 111, the second lower bridge arm driving terminal 112, the third lower bridge arm driving terminal 113, the fourth lower bridge arm driving terminal 114, the first lower bridge arm wide bandgap power semiconductor chip 404, the second lower bridge arm wide bandgap power semiconductor chip 405 and the third lower bridge arm wide bandgap power semiconductor chip 406.

[0056] The upper surface of the bottom power substrate 200 is provided with the direct current positive power terminal 210, the alternating current power terminal 211, the first upper bridge arm gate driving terminal 212, the first upper bridge arm source driving terminal 213, the second upper bridge arm gate driving terminal 214, the second upper bridge arm source driving terminal 215, the first upper bridge arm wide bandgap power semiconductor chip 401, the second upper bridge arm wide bandgap power semiconductor chip 402 and the third upper bridge arm wide bandgap power semiconductor chip 403.

[0057] Please refer to Figure 2, the bottom power substrate 200 comprises, from top to bottom, a bottom upper surface metal layer 201, a bottom insulating dielectric layer 202 and a bottom lower surface metal layer 203, the bottom insulating dielectric layer is made of aluminum oxide, aluminum nitride or silicon nitride; the bottom upper surface metal layer 201 is made of copper, and the bottom lower surface metal layer 203 is made of copper or aluminum. The bottom upper surface metal layer 201 is provided with a plurality of metal regions, including a bottom first metal region 221, a bottom second metal region 222, a bottom third metal region 223 and a bottom fourth metal region 224, wherein the bottom third metal region 223 is a Kelvin source metal region.

[0058] The upper bridge arm driving terminals include a first upper bridge arm gate driving terminal 212, a first upper bridge arm source driving terminal 213, a second upper bridge arm gate driving terminal 214 and a second upper bridge arm source driving terminal 215. The first upper bridge arm gate driving terminal 212 and the second upper bridge arm gate driving terminal 214 are arranged at two ends of the bottom second metal region 222, and the first upper bridge arm source driving terminal 213 and the second upper bridge arm source driving terminal 215 are arranged at two ends of the bottom third metal region 223.

[0059] Please refer to Figure 1 and Figure 3 , the top power substrate 100 comprises, from top to bottom, a top upper surface metal layer 101, a top insulating dielectric layer 102 and a top lower surface metal layer 103, the top insulating dielectric layer is made of aluminum oxide, aluminum nitride or silicon nitride; the top lower surface metal layer 103 is made of copper, and the top upper surface metal layer 101 is made of copper or aluminum.

[0060] The top lower surface metal layer 103 is provided with a plurality of metal regions, including a top first metal region 121, a top second metal region 122, a top third metal region 123, a top fourth metal region 124 and a top fifth metal region 125, wherein the top second metal region 122 is connected to the direct current side power pad 301 for heat dissipation, and the top third metal region 123 is a Kelvin source metal region.

[0061] The Kelvin source metal region is arranged separately in the metal region of the power substrate, and the gate lead Kelvin connection of the control circuit is realized by the mode that the source conductive metal belt simultaneously connects the source metal region of the commutation loop and the Kelvin source metal region, which greatly reduces the common source inductance of the commutation loop and the control circuit, enhances the reliability of the module driving, and does not need to additionally arrange the electrical interconnection lead, thereby increasing the space utilization rate in the module.

[0062] The DC side power pad and the AC side main power pad arranged in the module are long columnar, which reliably mechanically support the module, the power pad is arranged close to the power semiconductor, which greatly reduces the thermal coupling between the chips and provides an additional heat dissipation path for each power semiconductor, further reduces the thermal resistance from the chip to the air on the basis of double-sided heat dissipation, realizes the temperature equalization of the power chip, and improves the reliability of the power module working in a high-temperature environment.

[0063] The lower bridge arm drive terminals include a first lower bridge arm gate drive terminal 112, a first lower bridge arm source drive terminal 113, a second lower bridge arm gate drive terminal 114, and a second lower bridge arm source drive terminal 115. The first lower bridge arm gate drive terminal 112 and the second lower bridge arm gate drive terminal 114 are arranged at both ends of the top fourth metal region 124, and the first lower bridge arm source drive terminal 211 and the second lower bridge arm source drive terminal 115 are arranged at both ends of the top third metal region 123.

[0064] Please refer to Figure 4 The conductive metal strips and the semiconductor chips are arranged according to the illustrated structure. The conductive metal strips are trapezoidal in shape, each including a source conductive metal strip 500 and a gate conductive metal strip 600. The wide-bandgap power semiconductor chip 400 is arranged on the drain metal region 700, the drain electrode region on the back of the wide-bandgap power semiconductor chip 400 is directly connected to the drain metal region 700, the gate electrode region on the upper surface of the wide-bandgap power semiconductor chip 400 is connected to the gate metal region 750 through the gate conductive metal strip 600, and the source electrode region on the upper surface of the wide-bandgap power semiconductor chip 400 is connected to the Kelvin source metal region 800 and the source metal region 850 through the source conductive metal strip 500. The connection contact part of the source conductive metal strip 500 with the wide-bandgap power semiconductor chip 400, the Kelvin source metal region 800, and the source metal region 850 is provided with a hole slot for controlling parasitic inductance. It is worth noting that, Figure 4 The reference numbers shown in the figure are collective reference numbers and do not represent a specific structure but a specific structure, such as 400 representing all wide-bandgap power semiconductor chips, and 500 representing the source conductive metal strip matched therewith. The specific corresponding relationship is given in detail in the embodiments.

[0065] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0066] Embodiment

[0067] Please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 , the packaging structure of the embodiment includes two power substrates, six wide-bandgap power semiconductor chips in two groups, four power pads, three power terminals, eight drive terminals and six groups of conductive metal strips.

[0068] Among them, the two power substrates are specifically a top power substrate 100 and a bottom power substrate 200.

[0069] The six wide-bandgap power semiconductor chips 400 are specifically a first upper bridge arm wide-bandgap power semiconductor chip 401, a second upper bridge arm wide-bandgap power semiconductor chip 402, a third upper bridge arm wide-bandgap power semiconductor chip 403, a first lower bridge arm wide-bandgap power semiconductor chip 404, a second lower bridge arm wide-bandgap power semiconductor chip 405 and a third lower bridge arm wide-bandgap power semiconductor chip 406.

[0070] The four power pads are specifically a direct current side power pad 301, an alternating current side main power pad 302, an alternating current side auxiliary power pad 303 and an alternating current side auxiliary power pad 304.

[0071] The three power terminals are specifically a direct current positive power terminal 210, a direct current negative power terminal 110 and an alternating current pole power terminal 211.

[0072] The eight drive terminals are specifically an upper bridge arm first gate drive terminal 212, an upper bridge arm first source drive terminal 213, an upper bridge arm second gate drive terminal 214, an upper bridge arm second source drive terminal 215, a lower bridge arm first gate drive terminal 112, a lower bridge arm first source drive terminal 111, a lower bridge arm second gate drive terminal 114 and a lower bridge arm second source drive terminal 113.

[0073] 6 groups of conductive metal strips are arranged in one-to-one correspondence with 6 wide-bandgap power semiconductor chips, and each group of conductive metal strips includes one source conductive metal strip and one gate conductive metal strip.

[0074] The embodiment includes two groups of 3 parallel wide-bandgap power semiconductor chips in total 6, and constitutes upper and lower bridge arm switching tubes of a classic half-bridge structure. In actual work, the number of parallel chips can be increased or decreased according to requirements to change the current-carrying capacity, or the number of series chips can be increased or decreased to change the withstand voltage capacity, or the number of anti-parallel diode chips can be increased according to requirements.

[0075] It should be particularly pointed out that the wide-bandgap semiconductor power chips mentioned in the present application can also be replaced by non-wide-bandgap semiconductor power chips according to actual requirements. The conductive metal strips serve to electrically connect the semiconductor chips and the substrate metal, wherein the source conductive metal strip has a hole slot at the connection with the chip and the substrate metal, and the material thereof is copper. The driving circuit adopts a Kelvin source mode, and flexible driving terminals are arranged to be cross-used, thereby further improving the stability of the driving circuit and the dynamic uniformity of the chip. The power gasket serves to electrically connect, mechanically support and conduct heat, and the material thereof can be single copper or other metals and alloys with good heat conduction and electrical conductivity, and different materials are selected according to the use environment and reliability requirements. The power substrate is usually a substrate including but not limited to a direct bonding copper ceramic substrate, an active metal brazing ceramic copper-clad substrate, etc. The insulating layer of the power substrate is usually a ceramic material such as aluminum oxide, aluminum nitride and silicon nitride, or other insulating medium, which serves the functions of insulation and heat conduction. The metal layers on the upper and lower surfaces of the power substrate are conductive metals, and one side of the semiconductor chip is arranged with copper and the other side is arranged with copper or aluminum. The metal layer on the upper surface of the top power substrate and the metal layer on the lower surface of the bottom power substrate can be directly or through a metal substrate connected to a heat sink to improve the heat dissipation efficiency. The metal layer on the lower surface of the top power substrate and the metal layer on the upper surface of the bottom power substrate mainly serve the function of electrical connection.

[0076] The power gasket and the chip space are arranged as follows:

[0077] Please refer to Figure 1 , the first upper bridge arm wide-bandgap power semiconductor chip 401, the second upper bridge arm wide-bandgap power semiconductor chip 402 and the third upper bridge arm wide-bandgap power semiconductor chip 403 constitute the upper bridge arm of the half-bridge structure, the first lower bridge arm wide-bandgap power semiconductor chip 404, the second lower bridge arm wide-bandgap power semiconductor chip 405 and the third lower bridge arm wide-bandgap power semiconductor chip 406 constitute the lower bridge arm of the half-bridge structure, and the upper bridge arm and the lower bridge arm constitute a double-sided heat dissipation module structure as a whole.

[0078] The first upper bridge arm wide band gap power semiconductor chip 401, the second upper bridge arm wide band gap power semiconductor chip 402 and the third upper bridge arm wide band gap power semiconductor chip 403 are equidistantly and side by side arranged on the upper surface metal area of the bottom power substrate 200, and the DC side power pad 301 is arranged close to the upper bridge arm group chip, and the DC side power pad 301 provides an additional heat conduction path for the upper bridge arm group chip while connecting and supporting the top and bottom power substrates.

[0079] The first lower bridge arm wide band gap power semiconductor chip 404, the second lower bridge arm wide band gap power semiconductor chip 405 and the third lower bridge arm wide band gap power semiconductor chip 406 are equidistantly and side by side arranged on the upper surface metal area of the top power substrate 100, and the AC side main power pad 302 is arranged close to the lower bridge arm group chip, and the AC side main power pad 302 provides an additional heat conduction path for the lower bridge arm group chip while connecting and supporting the top and bottom power substrates.

[0080] Meanwhile, the AC side first power pad 303 and the second power pad 304 are additionally arranged to strengthen the mechanical and electrical connection and improve the mechanical stability of the module.

[0081] The conductive metal strip and the semiconductor chip are matched

[0082] The conductive metal strip is in the shape of a trapezoid, and each conductive metal strip includes a source conductive metal strip and a gate conductive metal strip; the source conductive metal strip is provided with a hole slot at a contact position connected with the semiconductor chip and the source metal area, for controlling the parasitic inductance; the semiconductor chip is connected with the Kelvin source metal area through the source conductive metal strip to lead out the Kelvin source.

[0083] Please refer to Figure 4 In the embodiment, the conductive metal strip and the semiconductor chip are matched according to the structural relationship shown in the figure; including: Figure 4

[0084] The wide band gap power semiconductor chip 400, the source conductive metal strip 500, the gate conductive metal strip 600, the drain metal area 700, the gate metal area 750, the Kelvin source metal area 800 and the source metal area 850. The specific reference numbers are as follows:

[0085] ​6. The specific correspondence of the semiconductor chips and the conductive metal strips is as follows: the upper bridge arm wide bandgap power semiconductor chip 401, the source conductive metal strip 501, and the gate conductive metal strip 601; the second upper bridge arm wide bandgap power semiconductor chip 402, the source conductive metal strip 502, and the gate conductive metal strip 602; the third upper bridge arm wide bandgap power semiconductor chip 403, the source conductive metal strip 503, and the gate conductive metal strip 603; the first lower bridge arm wide bandgap power semiconductor chip 404, the source conductive metal strip 504, and the gate conductive metal strip 604; the second lower bridge arm wide bandgap power semiconductor chip 405, the source conductive metal strip 505, and the gate conductive metal strip 605; and the third lower bridge arm wide bandgap power semiconductor chip 406, the source conductive metal strip 506, and the gate conductive metal strip 606.

[0086] The first upper bridge arm wide bandgap power semiconductor chip 401, the second upper bridge arm wide bandgap power semiconductor chip 402, and the third upper bridge arm wide bandgap power semiconductor chip 403 share the same drain metal region (the middle bottom first metal region 221), the gate metal region (the middle bottom second metal region 222), the Kelvin source metal region (the middle bottom third metal region 223), and the source metal region (the middle bottom fourth metal region 224). Figure 2 Figure 2 Figure 2 Figure 2

[0087] The first lower bridge arm wide bandgap power semiconductor chip 404, the second lower bridge arm wide bandgap power semiconductor chip 405, and the third lower bridge arm wide bandgap power semiconductor chip 406 share the same drain metal region (the middle top fifth metal region 125), the gate metal region (the middle top fourth metal region 124), the Kelvin source metal region (the middle top third metal region 123), and the source metal region (the middle top first metal region 121). Figure 3 Figure 3 Figure 3 Figure 3

[0088] The heat conduction paths are as follows:

[0089] In the embodiment, each semiconductor chip has a main heat conduction path and a secondary heat conduction path. The main heat conduction path refers to the heat dissipation through the conductive metal region of the power substrate where the chip is located to the power substrate and the outside. The secondary heat conduction path refers to the heat dissipation through the heat conduction of the power pad in the same metal region as the chip to another power substrate and the corresponding outside. The heat conduction paths of the third upper bridge arm semiconductor chip 403 and the third lower bridge arm semiconductor chip 406 are taken as examples for illustration:

[0090] Please refer to Figure 5 ​​​​​​​​The heat conduction path of the third upper bridge arm semiconductor chip 403 is a first main heat conduction path 652 and a first secondary heat conduction path 651. The first main heat conduction path 652 starts from the third upper bridge arm semiconductor chip 403, directly vertically passes through the upper surface metal region, the insulating medium layer and the lower surface metal layer of the bottom power substrate 200 to conduct heat to the heat sink or the external environment; the first secondary heat conduction path 651 starts from the third upper bridge arm semiconductor chip 403, horizontally passes through part of the upper surface metal region of the bottom power substrate 200, then vertically passes through the direct current side power gasket 301, the lower surface metal region of the top power substrate 100, the insulating medium layer and the upper surface metal layer to conduct heat to the heat sink or the external environment.

[0091] Similarly, the heat conduction path of the third lower bridge arm semiconductor chip 406 is a second main heat conduction path 653 and a second secondary heat conduction path 654. The second main heat conduction path 653 starts from the third lower bridge arm semiconductor chip 406, directly vertically passes through the lower surface metal region, the insulating medium layer and the upper surface metal layer of the top power substrate 100 to conduct heat to the heat sink or the external environment; the second secondary heat conduction path 654 starts from the third lower bridge arm semiconductor chip 406, horizontally passes through part of the lower surface metal region of the top power substrate 100, then vertically passes through the alternating current side main power gasket 302, the upper surface metal region of the bottom power substrate 200, the insulating medium layer and the lower surface metal layer to conduct heat to the heat sink or the external environment.

[0092] The drive circuit is specifically as follows:

[0093] The Kelvin metal region is arranged to draw the Kelvin source from the source conductive metal strip. In the embodiment, each wide bandgap power semiconductor chip corresponds to two source drive terminals and two gate drive terminals, and the drive circuit is basically located in the substrate plane. In actual application, one source terminal and one gate terminal are optionally used, or two source drive terminals and two gate drive terminals are simultaneously used or cross-used. It is recommended to cross-use the drive terminals. By cross-using the drive terminals, the transmission difference of the drive signal caused by the different distances of the chips from the drive terminals is further reduced or eliminated, so as to enhance the stability of the drive circuit and help to realize the dynamic current sharing of the chips.

[0094] By arranging the specific power substrate metal region and the chips, the coupling between the drive circuit and the commutation circuit is greatly reduced. Specifically, the current flow path of the upper bridge arm drive circuit is located in the bottom power substrate plane, the current flow path of the lower bridge arm drive circuit is located in the top power substrate plane, and the commutation circuit current flows from the bottom power substrate to the top power substrate through the alternating current side power gasket. The planes where the flow paths are located are perpendicular to the power substrate, so that the drive circuit and the commutation circuit are basically perpendicular in space, thereby greatly reducing the area of electromagnetic coupling between the circuits and enhancing the reliability of the module.

[0095] Take the second upper bridge arm semiconductor chip 402, the second lower bridge arm semiconductor chip 405 as an example for further description:

[0096] Please refer to Figure 6 , the display drive opens the current flow path of the drive circuit of the second upper bridge arm semiconductor chip 402. When using the first upper bridge arm gate drive terminal 212 and the first upper bridge arm source drive terminal 213, the current flows from the first upper bridge arm gate drive terminal 212, reaches the gate conductive metal strip matched with the second upper bridge arm semiconductor chip 402 along the upper bridge arm first path 661, and then reaches the source Kelvin metal area of the power substrate along the upper bridge arm second path 662 through the gate conductive metal strip, the semiconductor chip and the source conductive metal strip in turn, and finally flows into the first upper bridge arm source drive terminal 213 along the upper bridge arm third path 663; when using the second upper bridge arm gate drive terminal 214 and the second upper bridge arm source drive terminal 215, the drive circuit path is composed of the upper bridge arm fourth path 664, the upper bridge arm second path 662 and the upper bridge arm fifth path 665; when using the first upper bridge arm gate drive terminal 212 and the second upper bridge arm source drive terminal 215 cross, the drive circuit path is composed of the upper bridge arm first path 661, the upper bridge arm second path 662 and the upper bridge arm fifth path 665.

[0097] Please refer to Figure 7 , the display drive opens the current flow path of the drive circuit of the second lower bridge arm semiconductor chip 405. When using the second lower bridge arm drive terminal 112 and the first lower bridge arm drive terminal 111, the current flows from the second lower bridge arm drive terminal 112, reaches the gate conductive metal strip matched with the second lower bridge arm semiconductor chip 405 along the lower bridge arm first path 671, and then reaches the source Kelvin metal area of the power substrate along the lower bridge arm second path 672 through the gate conductive metal strip, the semiconductor chip and the source conductive metal strip in turn, and finally flows into the first lower bridge arm drive terminal 111 along the lower bridge arm third path 673;

[0098] When using the second lower bridge arm gate drive terminal 114 and the first lower bridge arm source drive terminal 113, the drive circuit path is composed of the lower bridge arm fourth path 674, the lower bridge arm second path 672 and the lower bridge arm fifth path 675; when using the first lower bridge arm gate drive terminal 112 and the first lower bridge arm source drive terminal 113 cross, the drive circuit path is composed of the lower bridge arm first path 671, the lower bridge arm second path 672 and the lower bridge arm fifth path 675.

[0099] Please refer to Figure 8 and Figure 9 , the commutation loop is specifically:

[0100] Figure 8 and Figure 9The current flow paths of the parallel chips of the upper bridge arm and the lower bridge arm are shown respectively. Figure 8 The current flow paths of the parallel chips of the upper bridge arm are shown when the upper bridge arm is conducting, and the current flow paths of the parallel branches of the upper bridge arm are as follows:

[0101] The current is divided into three parts on the bottom first metal region 221 on the upper surface of the bottom power substrate 200 from the DC positive power terminal 210, and then flows into the three parallel wide-bandgap power semiconductor chips, and then flows into the bottom fourth metal region 224 through the source conductive metal strips, and finally flows into the AC power terminal 211 during the continuous conduction of the upper bridge arm.

[0102] Figure 9 The current flow paths of the parallel chips of the lower bridge arm are shown when the lower bridge arm is conducting, and the current flow paths of the parallel branches of the lower bridge arm are as follows:

[0103] During the continuous conduction of the lower bridge arm, the current flows from the AC side power terminal of the bottom power substrate 200 to the top fifth metal region 125 of the top power substrate 100 through the AC side main power gasket 302, and is divided into three parts, and then flows into the three parallel wide-bandgap power semiconductor chips, and then flows into the top first metal region 121 of the top power substrate 100 through the source conductive metal strips.

[0104] In the commutation loop, the upper and lower bridge arm currents are in opposite directions in space, and the negative mutual inductance weakens the parasitic inductance; the power terminals are arranged on the same side in space, so that the laminated busbar structure and the installation of the decoupling capacitor can be easily designed, and the external inductance of the power terminal when the module is applied is avoided to be introduced into the commutation loop, thereby greatly relieving the opening voltage oscillation and the turn-off current oscillation phenomenon.

[0105] Please refer to Figure 10 , the decoupling capacitor and the fin column type heat sink are as follows:

[0106] Figure 10 A schematic diagram of the module integrated decoupling capacitor and fin column type heat sink is shown, wherein the first decoupling capacitor 901 and the second decoupling capacitor 902 are arranged between the DC positive power terminal 210 and the DC negative power terminal 110. By arranging the decoupling capacitor, the influence of the parasitic inductance introduced by the external circuit of the power terminal on the power module can be reduced or eliminated, and the influence of the high-frequency electromagnetic interference of the power module on other components can be reduced. The module can be cooled in various forms, including but not limited to natural cooling, forced air cooling, liquid cooling, etc., and the fin column type heat sink given in the figure is suitable for forced liquid cooling. The top power substrate 100 is connected with the second heat sink 906 through the additionally arranged second metal substrate 904, and the bottom power substrate is connected with the second heat sink 905 through the additionally arranged first metal substrate 903, thereby further improving the heat dissipation capacity of the module.

[0107] After the decoupling capacitor and the fin-column heat sink are integrated, the electrical performance and the thermal performance of the module are further improved.

[0108] The principle of the wide-bandgap semiconductor double-sided heat dissipation module packaging structure based on the conductive metal strip is specifically as follows:

[0109] The application realizes a half-bridge structure, which can constitute but is not limited to a three-phase inverter full-bridge circuit, a synchronous rectifier, a single-phase inverter full-bridge and various power electronic conversion circuits. The packaging structure has very low parasitic inductance, high heat dissipation capacity and high power density. The semiconductor power chips of different bridge arms are arranged on different power substrates, so that the volume of the module is reduced and the power density of the module is greatly improved. The power gasket is arranged between the top and bottom power substrates, and plays a mechanical support and electrical connection role. On the basis of double-sided heat dissipation, an additional heat dissipation path is provided for each semiconductor power chip, the degree of thermal coupling between the chips is reduced, the chip temperature is uniform, and the chip heat dissipation environment is greatly improved. The drive circuit and the commutation circuit are nearly vertical in space, the degree of electromagnetic coupling between the circuits is greatly reduced, and the reliability of the module is further improved. The conductive metal strip is used in the commutation circuit to complete the electrical connection required by the chip, and the parasitic inductance value of the module is greatly reduced. The source conductive metal strip has a hole slot at the connection, which can improve the uniformity of the parasitic inductance and achieve the chip current sharing effect.

[0110] In summary, the wide-bandgap semiconductor double-sided heat dissipation module packaging structure based on the conductive metal strip can reliably work under very large current levels and very high switching frequencies, and can also work at a chip junction temperature of 200-350 DEG C (which also depends on the packaging material, the operating environment, etc.), so that the superior performance of the wide-bandgap power semiconductor is fully utilized.

[0111] The above content only illustrates the technical idea of the application, and cannot limit the protection scope of the application. Any modification made according to the technical idea of the application on the basis of the technical scheme falls within the protection scope of the claims of the application.

Claims

1. A packaging structure for a wide bandgap semiconductor double-sided heat dissipation module based on conductive metal strips, characterized in that, The system includes a top power substrate (100) and a bottom power substrate (200), with a power pad disposed between the top power substrate (100) and the bottom power substrate (200). Power terminals are connected to the top power substrate (100) and the bottom power substrate (200), respectively. Wide bandgap power semiconductor chips (400) are disposed between the power terminals and the bottom power substrate (200), and also between the power terminals and the bottom power substrate (200). The wide bandgap power semiconductor chips (400) are connected to the upper surface metal region of the bottom power substrate (200) and the lower surface metal region of the top power substrate (100) respectively via conductive metal strips. The upper surface metal region of the bottom (200) is connected to the upper bridge arm drive terminal of the drive terminal, and the lower surface metal region of the top power substrate (100) is connected to the lower bridge arm drive terminal of the drive terminal. The bottom power substrate (200) includes a bottom upper surface metal layer (201), a bottom insulating dielectric layer (202) and a bottom lower surface metal layer (203) from top to bottom. The bottom upper surface metal layer (201) is provided with a bottom first metal region (221), a bottom second metal region (222), a bottom third metal region (223) and a bottom fourth metal region (224) in sequence. The bottom third metal region (223) is a Kelvin source metal region. The upper bridge arm driving terminal includes a bottom first gate driving terminal (212), a bottom first source driving terminal (213), a bottom second gate driving terminal (214), and a bottom second source driving terminal (215); the bottom first gate driving terminal (212) and the bottom second gate driving terminal (214) are disposed at both ends of the bottom second metal region (222), and the bottom first source driving terminal (213) and the bottom second source driving terminal (215) are disposed at both ends of the bottom third metal region (223); The top power substrate (100) includes, from top to bottom, a top upper surface metal layer (101), a top insulating dielectric layer (102), and a top lower surface metal layer (103). The top lower surface metal layer (103) is provided with a top first metal region (121), a top second metal region (122), a top third metal region (123), a top fourth metal region (124), and a top fifth metal region (125). The top second metal region (122) is connected to the DC side power pad (301), and the top third metal region (123) is the Kelvin source metal region. The lower bridge arm driving terminals include a first lower bridge arm gate driving terminal (112), a first lower bridge arm source driving terminal (211), a second lower bridge arm gate driving terminal (114), and a second lower bridge arm source driving terminal (115); the first lower bridge arm gate driving terminal (112) and the second lower bridge arm gate driving terminal (114) are disposed at both ends of the top fourth metal region (124), and the first lower bridge arm source driving terminal (211) and the second lower bridge arm source driving terminal (115) are disposed at both ends of the top third metal region (123).

2. The wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips according to claim 1, characterized in that, The wide bandgap power semiconductor chip (400) includes several semiconductor chips. The several semiconductor chips are connected in parallel in two groups to form an upper bridge arm and a lower bridge arm of a half-bridge structure. The chip at the upper bridge arm is disposed on the upper surface metal layer of the bottom power substrate (200), and the chip at the lower bridge arm is disposed on the lower surface metal layer of the top power substrate (100).

3. The packaging structure of the wide bandgap semiconductor double-sided heat dissipation module based on conductive metal strips according to claim 2, characterized in that, The two groups of semiconductor chips have the same number of chips, and the spacing between the semiconductor chips in the same group is the same.

4. The wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips according to claim 1, characterized in that, The conductive metal strip includes a source conductive metal strip (500) and a gate conductive metal strip (600). A wide bandgap power semiconductor chip (400) is disposed on a drain metal region (700). The drain electrode region of the wide bandgap power semiconductor chip (400) is connected to the drain metal region (700). The gate electrode region of the wide bandgap power semiconductor chip (400) is connected to the gate metal region (750) through the gate conductive metal strip (600). The source electrode region of the bandgap power semiconductor chip (400) is connected to the Kelvin source metal region (800) and the source metal region (850) through the source conductive metal strip (500). The connection points between the source conductive metal strip (500) and the bandgap power semiconductor chip (400), the Kelvin source metal region (800), and the source metal region (850) are provided with slots.

5. The wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips according to claim 1, characterized in that, The power terminals include an AC power terminal (211) and two DC power terminals. The two DC terminals are a DC positive power terminal (210) and a DC negative power terminal (110). The DC positive power terminal (210) and the AC power terminal (211) are disposed on the bottom power substrate (200), and the DC negative power terminal (110) is disposed on the top power substrate (100).

6. The wide bandgap semiconductor double-sided heat dissipation module packaging structure based on conductive metal strips according to claim 5, characterized in that, A first decoupling capacitor (901) and a second decoupling capacitor (902) are provided between the DC positive power terminal (210) and the DC negative power terminal (110).

Images