Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a first transistor and a second transistor which are arranged side by side in a semiconductor layer and are separated by a first dielectric layer; the first transistor and the second transistor each comprise: a channel region; a source electrode; a drain electrode; a gate electrode; and a first doped region which is located in the first transistor and / or the second transistor, extends from a side in contact with the first dielectric layer to the gate electrode in a preset size, and has a doping type different from that of the source electrode and the drain electrode. In the embodiment of the application, when one of the first transistor and the second transistor is turned on, the channel region of the turned-on transistor becomes high-voltage. By arranging the first doped region, the electron is less likely to move to the first dielectric layer through the channel region of the turned-on transistor and enter the channel region of the other transistor to affect the other transistor, so that the coupling effect between the first transistor and the second transistor can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its manufacturing method. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell. The basic memory cell structure of DRAM consists of a transistor and a storage capacitor. Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0003] However, transistors in related technologies still have many problems that need to be improved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor structure, comprising:

[0006] A first transistor and a second transistor are arranged side-by-side in a semiconductor layer and separated by a first dielectric layer; both the first transistor and the second transistor include:

[0007] Channel area;

[0008] Source pole;

[0009] Drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer;

[0010] A gate is located on one side of the channel region; wherein the gate of the first transistor is located on the side of the first transistor away from the first dielectric layer, and the gate of the second transistor is located on the side of the second transistor away from the first dielectric layer; and,

[0011] The first doped region is located in the first transistor and / or the second transistor, in a region extending a predetermined size from the side contacting the first dielectric layer toward the gate, and the doping type of the first doped region is different from the doping types of the source and drain.

[0012] In the above scheme, the doping concentration of both the source and the drain is greater than the doping concentration of the first doped region.

[0013] In the above scheme, the semiconductor structure further includes a second doped region, a portion of which is located between the source and the channel region, and another portion is located between the drain and the channel region; wherein the doping concentration of the second doped region is less than the doping concentration of the first doped region.

[0014] In the above scheme, the ratio of the diameter of the first transistor / second transistor to the preset size is in the range of 2-7.

[0015] In the above scheme, the source and drain are N-type doped, and the first doped region is P-type doped.

[0016] In the above scheme, the first doped region is located in the first transistor and the second transistor, in a region extending a predetermined size from the side in contact with the first dielectric layer toward the gate direction, and in the semiconductor layer between the first transistor and the second transistor, in a region extending the predetermined size from the side in contact with the first dielectric layer toward the direction away from the first dielectric layer.

[0017] In a second aspect, embodiments of the present invention provide another semiconductor structure, the semiconductor structure comprising: a memory cell array; each memory cell in the memory cell array comprising a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; wherein, the vertical transistor comprises a first semiconductor body and a second semiconductor body disposed side by side in a semiconductor layer and spaced apart by a first dielectric layer and extending in a first direction, a gate located on one side of the first semiconductor body away from the first dielectric layer, and a gate located on one side of the second semiconductor body away from the first dielectric layer;

[0018] Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0019] Wherein, both the first semiconductor body and the second semiconductor body include:

[0020] Channel area;

[0021] Source pole;

[0022] Drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer;

[0023] The first doped region is located in the first semiconductor body and / or the second semiconductor body, in a region extending a predetermined size from the side contacting the first dielectric layer toward the gate direction, and the doping type of the first doped region is different from the doping types of the source and drain.

[0024] In the above scheme, the doping concentration of both the source and the drain is greater than the doping concentration of the first doped region.

[0025] In the above scheme, one of the source and the drain of the vertical transistor is coupled to the memory cell in the corresponding memory cell.

[0026] In the above scheme, the other of the source and drain of the vertical transistor is coupled to the corresponding bit line.

[0027] Thirdly, embodiments of the present invention provide a method for manufacturing a semiconductor structure, the method comprising:

[0028] A semiconductor layer is provided, wherein at least one active pillar and gates located on both sides of the active pillar are formed therein;

[0029] The active pillar is etched from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar;

[0030] A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction;

[0031] The first dielectric layer is filled into the first groove;

[0032] The source and drain of the first transistor and the second transistor are formed at opposite ends along the thickness direction of the semiconductor layer, respectively; the first and second sub-active pillars between the source and the drain respectively constitute the channel regions of the first transistor and the second transistor.

[0033] The doping type of the first doped region is different from the doping types of the source and drain.

[0034] In the above scheme, the doping concentration of both the source and the drain is greater than the doping concentration of the first doped region.

[0035] The method in the above scheme further includes:

[0036] A portion of a second doped region is formed between the source and the channel region; and another portion of a second doped region is formed between the drain and the channel region; wherein the doping concentration of the second doped region is less than the doping concentration of the first doped region.

[0037] In the above scheme, the ratio of the diameter of the first transistor / second transistor to the preset size is in the range of 2-7.

[0038] In the above scheme, forming the first doped region includes:

[0039] The first doped region is formed using diffusion or ion implantation processes.

[0040] In the above scheme, forming the source and drain of the first transistor and the second transistor at opposite ends along the semiconductor layer thickness direction of the first sub-active pillar and the second sub-active pillar respectively includes:

[0041] Ion implantation is performed from the first surface of the semiconductor layer to form the sources of the first transistor and the second transistor;

[0042] The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the ends of the first and second sub-active pillars away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0043] Ion implantation is performed at the ends of the first and second sub-active pillars that are away from the first surface of the semiconductor layer to form the drains of the first and second transistors.

[0044] Fourthly, embodiments of the present invention provide another method for manufacturing a semiconductor structure, the method comprising:

[0045] Multiple memory cell arrays are formed; each memory cell in the memory cell array includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor;

[0046] Multiple bit lines are formed; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0047] The method for manufacturing the vertical transistor includes: providing a semiconductor layer in which at least one active pillar and gates located on both sides of the active pillar are formed;

[0048] The active pillar is etched from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar;

[0049] A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction;

[0050] The first dielectric layer is filled into the first groove;

[0051] The source and drain of the first transistor and the second transistor are formed at opposite ends along the thickness direction of the semiconductor layer, respectively; the first and second sub-active pillars between the source and the drain respectively constitute the channel regions of the first transistor and the second transistor.

[0052] This invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a first transistor and a second transistor arranged side-by-side in a semiconductor layer and spaced apart by a first dielectric layer; each of the first transistor and the second transistor includes: a channel region; a source; and a drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer; a gate is located on one side of the channel region; wherein the gate of the first transistor is located on the side of the first transistor away from the first dielectric layer, and the gate of the second transistor is located on the side of the second transistor away from the first dielectric layer; and a first doped region is located in the first transistor and / or the second transistor, extending a predetermined size from the side contacting the first dielectric layer toward the gate, and the doping type of the first doped region is different from the doping types of the source and the drain. In this embodiment of the invention, by setting a first doped region of a predetermined size in the first transistor and / or the second transistor extending from the side contacting the first dielectric layer toward the gate direction, which is different from the doping type of the source and drain, when one of the first transistors and the second transistor is turned on, the channel region of the turned-on transistor becomes high voltage. By setting the first doped region, a barrier layer is formed, which makes it difficult for electrons to move through the channel region of the turned-on transistor to the first dielectric layer and enter the channel region of the other transistor to affect the other transistor, thereby improving the coupling effect between the first transistor and the second transistor in the semiconductor structure. Attached Figure Description

[0053] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0054] Figure 1 This is a schematic diagram of the circuit connection of a transistor provided in an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0056] Figure 3a This is another schematic diagram of a semiconductor structure provided in an embodiment of the present invention. Figure 1 ;

[0057] Figure 3b This is another schematic diagram of a semiconductor structure provided in an embodiment of the present invention. Figure 2 ;

[0058] Figure 3c This is another schematic diagram of a semiconductor structure provided in the embodiments of the present invention;

[0059] Figure 3d This is another schematic diagram of a semiconductor structure provided in an embodiment of the present invention. Figure 4 ;

[0060] Figure 3e This is another schematic diagram of a semiconductor structure provided in the embodiments of the present invention. Figure 5 ;

[0061] Figure 4 A three-dimensional structural diagram of a memory provided in an embodiment of the present invention;

[0062] Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method provided in an embodiment of the present invention;

[0063] Figures 6a to 6f This is a schematic diagram of the process of fabricating a semiconductor structure according to an embodiment of the present invention;

[0064] Figure 7 This is a schematic diagram illustrating the implementation process of a memory fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0065] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0066] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0067] It is understood that the meanings of “on”, “above” and “over” in this invention should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0068] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0069] In embodiments of the invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0070] In embodiments of the invention, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0071] In this embodiment of the invention, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0072] The semiconductor structure involved in this embodiment of the invention is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0073] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0074] In practical applications, regardless of whether it is a planar transistor, a recessed gate array transistor, a buried transistor, or a vertical gate transistor, dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0075] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source of transistor T is electrically connected to one of the electrode plates of capacitor C, the other electrode plate of capacitor C is grounded through the ground terminal (GND), and the gate of transistor T is connected to the word line (WL). The voltage applied through the word line WL controls the transistor T to be turned on or off. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0076] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention; the present invention provides a semiconductor structure, such as... Figure 2 As shown, the semiconductor structure includes:

[0077] A first transistor 21 and a second transistor 22 are arranged side-by-side in a semiconductor layer and spaced apart by a first dielectric layer 201; both the first transistor 21 and the second transistor 22 include:

[0078] Ditch area 202;

[0079] Source 203;

[0080] Drain 204; wherein the source 203 and the drain 204 are respectively located at opposite ends of the channel region 202 along the thickness direction of the semiconductor layer;

[0081] Gate 205 is located on one side of the channel region 202; wherein, the gate 205 of the first transistor 21 is located on the side of the first transistor 21 away from the first dielectric layer 201, and the gate 205 of the second transistor 22 is located on the side of the second transistor 22 away from the first dielectric layer 201.

[0082] Research has found that when using the single-gate vertical transistor structure as described above, the first transistor 21 and the second transistor 22 in a semiconductor structure are prone to coupling effects. For example, when the first transistor 21 is turned on, the channel region becomes high voltage, and electrons will enter the first dielectric layer 201 through the channel region 202 of the first transistor 21, and then enter the channel region 202 of the second transistor 22. In other words, when the first transistor 21 is turned on, there is an interference problem with the second transistor 22.

[0083] In response to one or more of the above-mentioned problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same, and a memory and a method for fabricating the same.

[0084] Figure 3a A schematic diagram of a semiconductor structure provided in an embodiment of the present invention is shown below. Figure 3a As shown, the semiconductor structure includes:

[0085] A first transistor 21 and a second transistor 22 are arranged side-by-side in a semiconductor layer and spaced apart by a first dielectric layer 201; both the first transistor 21 and the second transistor 22 include:

[0086] Ditch area 202;

[0087] Source 203;

[0088] Drain 204; wherein the source 203 and the drain 204 are respectively located at opposite ends of the channel region 202 along the thickness direction of the semiconductor layer;

[0089] Gate 205 is located on one side of the channel region 202; wherein, the gate 205 of the first transistor 21 is located on the side of the first transistor 21 away from the first dielectric layer 201, and the gate 205 of the second transistor 22 is located on the side of the second transistor 22 away from the first dielectric layer 201; and,

[0090] The first doped region 206 is located in the first transistor 21 and / or the second transistor 22, in a region extending a predetermined size from the side contacting the first dielectric layer 201 toward the gate 205, and the doping type of the first doped region 206 is different from the doping type of the source 203 and the drain 204.

[0091] In some specific examples, the semiconductor layer may include a substrate. Here, the substrate may include a substrate of a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0092] Here, the material of the first dielectric layer 201 includes, but is not limited to, silicon oxide.

[0093] Here, the first transistor 21 and the second transistor 22 are arranged side by side in the semiconductor layer. For example, the orientation of the side-by-side arrangement of the first transistor 21 and the second transistor 22 can be as follows: Figures 3a-3c The X-axis direction is shown in the figure.

[0094] In practical applications, the first transistor 21 and the second transistor 22 provided in this embodiment of the invention have a vertical channel (i.e., channel region 202). The source 203 is located at the first end of the channel region 202, and the drain 204 is located at the second end of the channel region 202, wherein the first end and the second end are opposite ends of the channel region 202 in the semiconductor layer thickness direction. That is, the source 203 and drain 204 of the first transistor 21 and the second transistor 22 are respectively located at opposite ends of the vertical channel. The positions of the source 203 and drain 204 are interchangeable; that is, the first end and the second end are opposite ends of the channel region 202 in the semiconductor layer thickness direction that can be interchanged.

[0095] For example, the semiconductor layer thickness direction can be as follows: Figures 3a-3c As shown in the Z-axis direction, the parallel arrangement of the channel region 202, source 203, and drain 204 can be parallel to the Z-axis direction.

[0096] Here, the material of the gate 205 includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. The conductive metal may include tungsten or copper, etc.

[0097] Figure 3b This is a schematic diagram of another semiconductor structure provided in an embodiment of the present invention. Figure 3c This is a schematic diagram of another semiconductor structure provided in an embodiment of the present invention.

[0098] Here, the first doped region 206 is located in the first transistor 21 and / or the second transistor 22, in a region extending by a predetermined size from the side contacting the first dielectric layer 201 toward the gate 205. (Refer to...) Figures 3a-3c It is understood that the position of the first doped region 206 in the semiconductor structure provided in this embodiment of the invention may include three cases: one, as... Figure 3a As shown, regions of a predetermined size are located in the first transistor 21 and the second transistor 22 extending from the side contacting the first dielectric layer 201 toward the gate 205; secondly, as... Figure 3b As shown, the region of a predetermined size located in the first transistor 21 extending from the side contacting the first dielectric layer 201 towards the gate 205; third, as... Figure 3c As shown, the region in the second transistor 22 extends by a predetermined size from the side that contacts the first dielectric layer 201 toward the gate 205.

[0099] Understandably, when the position of the first doped region 206 is in the first case described above, when the gate 205 of the second transistor 22 is turned on, the channel region 202 of the second transistor 22 is in a high-voltage state. Due to the obstruction of the doped layer 206 in the first transistor 21 and the second transistor 22, electrons are less likely to move through the channel region 202 of the second transistor 22 to the first dielectric layer 201 and affect the first transistor 21, thereby improving the coupling effect between the first transistor 21 and the second transistor 22 in the semiconductor structure. When the position of the first doped region 206 is in the second case described above, when the gate 205 of the second transistor 22 is turned on, the channel region 202 of the second transistor 22 is in a high-voltage state. Due to the obstruction of the doped layer 206 in the first transistor 21, electrons are less likely to move through the channel region 202 of the second transistor 22 to the first dielectric layer 201 and affect the first transistor 21. Even if electrons can move through the channel region 202 of the second transistor 22 to the first dielectric layer 201, they are unlikely to enter the channel region 202 of the first transistor 21 and affect the first transistor 21, thereby improving the coupling effect between the first transistor 21 and the second transistor 22 in the semiconductor structure. When the position of the first doped region 206 is in the third case described above, when the gate 205 of the second transistor 22 is turned on, the channel region 202 of the second transistor 22 is in a high voltage state. Due to the obstruction of the doped layer 206 in the second transistor 22, electrons are unlikely to move through the channel region 202 of the second transistor 22 to the first dielectric layer 201 and affect the first transistor 21, thereby improving the coupling effect between the first transistor 21 and the second transistor 22 in the semiconductor structure.

[0100] In practical applications, the preset size W is mainly related to the diameter of the first transistor 21 and the second transistor 22. The larger the diameter of the first transistor 21 and the second transistor 22, the larger the preset size W can be set.

[0101] In some embodiments, the ratio of the diameter of the first transistor 21 / second transistor 22 to the preset size W ranges from 2 to 7.

[0102] For example, when the diameter of the first transistor 21 and the second transistor 22 is 10nm-20nm, the preset size can be 1nm-10nm.

[0103] It should be noted that the ratio range of the diameter and width of the first transistor 21 / second transistor 22 to the preset size is merely an illustrative example and is not intended to limit the ratio range of the diameter and width of the first transistor 21 / second transistor 22 to the preset size in the embodiments of the present invention.

[0104] In practical applications, the concentration of the first doped region 206 can be adjusted according to actual needs.

[0105] In some embodiments, the doping concentrations of the source 203 and the drain 204 are both greater than the doping concentration of the first doped region 206.

[0106] In practical applications, the doping concentrations of the source 203 and drain 204 are typically similar, i.e., N1; the doping concentration of the first doped region 206 is N2. Here, the doping concentration N1 of the source 203 and drain 204 is greater than the doping concentration N2 of the first doped region 206, i.e., N1 > N2. For example, the doping concentration range of the source 203 and drain 204 can be: 1e20 atom / cm². 3 Up to 1e21atom / cm 3 The doping concentration range of the first doped region 206 can be: 1e18atom / cm³. 3 Up to 1e19atom / cm 3 Here, the atom / cm 3 This indicates the number of atoms contained in each cubic centimeter.

[0107] In some specific examples, after the source 203, drain 204, and first doped region 206 are formed, the doping concentrations of the source 203, drain 204, and first doped region 206 in the overlapping region may differ from the relationship described above where the doping concentrations of the source 203 and drain 204 are both greater than the doping concentration of the first doped region 206. However, its influence on the role of the first doped region 206 in the transistor can be ignored.

[0108] It should be noted that the doping concentration ranges of the source 203, drain 204 and the first doped region 206 mentioned above are merely illustrative examples and are not intended to limit the doping concentrations of the source 203, drain 204 and the first doped region 206 in the embodiments of the present invention.

[0109] In practical applications, such as Figures 3a-3c As shown, a gate oxide layer 208 is also disposed between the gate 205 and the channel region 202 for electrically isolating the channel region 202 and the gate 205. Here, the material of the gate oxide layer 208 may include, but is not limited to, silicon oxide.

[0110] Specifically, the gate oxide layer 208 can be used to sense different electric fields and apply them to the surface of the channel region 202, so that minority carriers of the semiconductor layer are adsorbed onto the surface of the channel region 202 and accumulate and invert, making the gate oxide layer 208 the same as the source 203 and the drain 204, thereby realizing the conduction between the source 203 and the drain 204.

[0111] It is understandable that after applying a gate voltage to the gate 205, i.e. generating a strong electric field, electrons drift and accelerate continuously along the direction of the electric field, thus gaining a large amount of kinetic energy. When these electrons travel from the source 203 to the drain 204, they collide with the gate oxide layer 208 and are injected into the gate oxide layer 208, thereby generating a hot carrier effect. This hot carrier effect has a significant impact on the reliability of the transistor.

[0112] Based on this, the embodiments of the present invention propose the following technical solutions to improve the hot carrier effect.

[0113] In some embodiments, the semiconductor structure further includes a second doped region 207, a portion of which is located between the source 203 and the channel region 202, and another portion of which is located between the drain 204 and the channel region 202; wherein the doping concentration of the second doped region 207 is less than the doping concentration of the first doped region 206.

[0114] Here, the doping concentration of the second doped region 207 is N3, meaning the doping concentration N2 of the first doped region 206 is greater than the doping concentration N3 of the second doped region 207; therefore, N2 > N3. For example, the doping concentration range of the second doped region 207 can be: 1e17atom / cm³. 3 Up to 1e18atom / cm 3 .

[0115] It should be noted that the range of doping concentration of the second doped region 207 described above is merely an illustrative example and is not intended to limit the doping concentration of the second doped region 207 in the embodiments of the present invention.

[0116] Here, the second doped region 207 is a structure adopted by the device to reduce the drain electric field and improve the hot carrier effect. That is, a low-doped region is set in the channel region 202 near the drain 204, so that the second doped region 207 also bears part of the voltage, thereby reducing the hot carrier effect.

[0117] In practical applications, a second doped region 207 can be provided only between the channel region 202 and the drain 204 to reduce the hot carrier effect; alternatively, a second doped region 207 can be provided both between the channel region 202 and the drain 204 and between the channel region 202 and the source 203 to reduce the hot carrier effect.

[0118] Here, the doping type of the first doped region 206 is different from the doping types of the source 203 and the drain 204. The specific doping types of the source 203, the drain 204, and the first doped region 206 are illustrated below.

[0119] In some embodiments, the source 203 and the drain 204 are N-type doped, and the first doped region 206 is P-type doped.

[0120] In practical applications, the first transistor 21 and the second transistor 22 can be N-type transistors or P-type transistors.

[0121] In an N-type transistor, the source 203, drain 204, and second doped region 207 are all N-type doped; while the first doped region 206 is P-type doped.

[0122] In a P-type transistor, the source 203, drain 204, and second doped region 207 are all P-type doped; while the first doped region 206 is N-type doped.

[0123] Figure 3d This is a schematic diagram of another semiconductor structure provided in an embodiment of the present invention.

[0124] like Figure 3d As shown, in some embodiments, the first doped region 206 is located in the first transistor 21 and the second transistor 22, in a region extending a predetermined size W from the side contacting the first dielectric layer 201 toward the gate 205, and in the semiconductor layer between the first transistor 21 and the second transistor 22, in a region extending a predetermined size W from the side contacting the first dielectric layer 201 toward the direction away from the first dielectric layer 201.

[0125] Figure 3e This is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present invention. For example... Figure 3e As shown, the semiconductor structure also includes a bit line 213 connected to the source 203 and a storage capacitor 212 connected to the drain 204. The first electrode of the storage capacitor 212 is connected to the drain 204 through a storage capacitor contact 211, and the second electrode of the storage capacitor 212 is connected to a common terminal (not shown in the figure). The storage capacitor 212 is used to store data written to the semiconductor device. In this embodiment of the invention, a first doped region 206 is formed in the first transistor 21 and / or the second transistor 22 by extending a predetermined size from the side contacting the first dielectric layer 201 toward the gate 205. This forms a thinner well region on the side of the first transistor 21 and / or the second transistor 22 away from the gate 205, which can suppress the movement of electrons through the channel region 202 to the first dielectric layer 201, thereby reducing the impact on adjacent transistors in the semiconductor structure.

[0126] This invention provides a semiconductor structure, including: a first transistor 21 and a second transistor 22 arranged side-by-side and spaced apart by a first dielectric layer 201 in a semiconductor layer; each of the first transistor 21 and the second transistor 22 includes: a channel region 202; a source 203; and a drain 204; wherein the source 203 and the drain 204 are located at opposite ends of the channel region 202 along the thickness direction of the semiconductor layer; a gate 205 located on one side of the channel region 202; wherein the gate 205 of the first transistor 21 is located on the side of the first transistor 21 away from the first dielectric layer 201, and the gate 205 of the second transistor 22 is located on the side of the second transistor 22 away from the first dielectric layer 201; and a first doped region 206 located in the first transistor 21 and / or the second transistor 22 extending a predetermined size from the side contacting the first dielectric layer 201 toward the gate 205, and the doping type of the first doped region 206 is different from the doping types of the source 203 and the drain 204. In this embodiment of the invention, a first doped region 206 of a different doping type than that of the source 203 and the drain 204 is provided in a region of a predetermined size extending from the side contacting the first dielectric layer 201 toward the gate 205 in the first transistor 21 and / or the second transistor 22. When one of the first transistors 21 and the second transistor 22 is turned on, the channel region 202 of the turned-on transistor becomes high voltage. By providing the first doped region 206, a barrier layer is formed, which makes it difficult for electrons to move through the channel region 202 of the turned-on transistor to the first dielectric layer 201 and enter the channel region 202 of the other transistor to affect the other transistor. This improves the coupling effect between the first transistor 21 and the second transistor 22 in the semiconductor structure.

[0127] This invention also provides another semiconductor structure. Figure 4 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present invention; as shown below. Figure 4 As shown, the semiconductor structure includes:

[0128] A memory cell array; each memory cell in the memory cell array includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; wherein the vertical transistor includes a first semiconductor body and a second semiconductor body arranged side by side in a semiconductor layer and spaced apart by a first dielectric layer and extending in a first direction, a gate located on one side of the first semiconductor body away from the first dielectric layer, and a gate located on one side of the second semiconductor body away from the first dielectric layer.

[0129] Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0130] Wherein, both the first semiconductor body and the second semiconductor body include:

[0131] Channel area;

[0132] Source pole;

[0133] Drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer;

[0134] The first doped region is located in the first semiconductor body and / or the second semiconductor body, in a region extending a predetermined size from the side contacting the first dielectric layer toward the gate direction, and the doping type of the first doped region is different from the doping types of the source and drain.

[0135] Here, for reference Figure 4 The first direction is the Z-axis direction; the second direction is the X-axis direction.

[0136] In some embodiments, the doping concentrations of both the source and the drain are greater than the doping concentration of the first doped region.

[0137] In some embodiments, one of the source and drain of the vertical transistor is coupled to the memory cell in the corresponding memory cell.

[0138] In some embodiments, the other of the source and drain of the vertical transistor is coupled to a corresponding bit line.

[0139] In some embodiments, the semiconductor structure includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0140] In some embodiments, the semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor;

[0141] One end of the storage capacitor is connected to the source 203 of the first semiconductor body and the second semiconductor body in the semiconductor structure;

[0142] The bit line BL is connected to the drain 204 of the first semiconductor body and the second semiconductor body.

[0143] In practical applications, the storage capacitor can take on various structures. In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0144] For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), and a pillar-shaped capacitor (PIL). Each of the cup-shaped capacitor (CUP), the cylindrical capacitor (CYL), and the pillar-shaped capacitor (PIL) includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

[0145] It should be noted that the bottom electrode is connected to the source 203 of a transistor in the semiconductor structure, the top electrode of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0146] It should be noted that, when the bottom electrode areas of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode area of ​​the cylindrical capacitor (CYL) is the largest, followed by the top electrode areas of the cylindrical capacitor (CYL) and pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for improving the integration density of the memory.

[0147] In the embodiments of the present invention, some common memories are merely exemplified and the scope of protection of the present invention is not limited thereto. Any memory that includes the semiconductor structure provided in the embodiments of the present invention is within the scope of protection of the present invention.

[0148] In practical applications, the memory also includes: resistors;

[0149] The resistor is connected between the bit line BL and the source 203 of the transistor, or the resistor is connected between the bit line BL and the drain 204 of the transistor. The resistor is used to adjust the state of the data stored in the memory cell by the bit line BL voltage provided by the bit line BL.

[0150] Figure 5 This is a schematic flowchart illustrating a semiconductor structure manufacturing method according to an embodiment of the present invention. Figure 5 As shown, the semiconductor structure manufacturing method provided in this embodiment of the invention includes the following steps:

[0151] Step 501: Provide a semiconductor layer, wherein at least one active pillar and gates located on both sides of the active pillar are formed in the semiconductor layer;

[0152] Step 502: Etch the active pillar from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar;

[0153] Step 503: A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction;

[0154] Step 504: Fill the first groove with a first dielectric layer;

[0155] Step 505: The source and drain of the first transistor and the second transistor are formed at opposite ends of the first sub-active pillar and the second sub-active pillar along the thickness direction of the semiconductor layer, respectively; the first sub-active pillar and the second sub-active pillar between the source and the drain respectively constitute the channel region of the first transistor and the second transistor.

[0156] The doping type of the first doped region is different from the doping types of the source and drain.

[0157] Figures 6a to 6f This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present invention. It should be understood that... Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 5 , Figures 6a to 6f The manufacturing method of the semiconductor structure provided in the embodiments of the present invention will be described in detail.

[0158] First, such as Figure 6a As shown, in step 501, the main task is to provide a semiconductor layer.

[0159] The semiconductor layer contains at least one active pillar 209 and gates 205 located on both sides of the active pillar 209.

[0160] Here, the extension direction of the active pillar 209 is the thickness direction of the semiconductor layer.

[0161] In some specific examples, the semiconductor layer includes a substrate. The substrate material may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrates, etc.; in some specific embodiments, the substrate may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); in practical applications, the substrate can be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0162] In practical applications, dry etching processes, such as plasma etching or reactive ion etching, can be used to etch the semiconductor layer to form active pillars 209 on the semiconductor layer.

[0163] In practical applications, such as Figure 6a As shown, gate oxide layers 208 are formed on both sides of the active pillar 209; wherein, the gate oxide layer 208 can be used to suppress short-channel effects. Furthermore, setting the thickness of the gate oxide layer 208 to different thicknesses can solve the matching problem of the semiconductor structure under different voltage requirements. Here, the thickness of the gate oxide layer 208 can be set according to the actual requirements of the transistor.

[0164] Next, a gate 205 is formed on the side of the gate oxide layer 208 away from the active pillar 209.

[0165] Here, the material of the gate 205 includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. The conductive metal may include tungsten or copper, etc.

[0166] In practical applications, the methods for forming the gate 205 include, but are not limited to, PVD, CVD, ALD, etc.

[0167] In step 502, as Figure 6b As shown, the main process involves forming the first sub-active column 209-1 and the second sub-active column 209-2.

[0168] Here, the method for etching the active pillar 209 to form the first groove 210 includes, but is not limited to, dry plasma etching.

[0169] In step 503, as Figure 6c As shown, the main feature is the formation of the first doped region 206.

[0170] In some embodiments, forming the first doped region 206 includes:

[0171] The first doped region 206 is formed using a diffusion process or an ion implantation process.

[0172] It should be noted that the methods for forming the first doped region 206 include, but are not limited to, diffusion processes or ion implantation processes.

[0173] In some embodiments, the doping concentrations of the source 203 and the drain 204 are both greater than the doping concentration of the first doped region 206.

[0174] In some embodiments, the ratio of the diameter of the first transistor / second transistor to the preset size is in the range of 2-7.

[0175] In practical applications, the doping types of the source 203, drain 204, and first doped region 206 can be selected according to specific circumstances. When the first transistor and the second transistor are N-type transistors, the source 203 and drain 204 are both N-type doped, while the first doped region 206 is P-type doped. When the first transistor and the second transistor are P-type transistors, the source 203 and drain 204 are both P-type doped, while the first doped region 206 is N-type doped.

[0176] For example, when the doping type of the first doped region 206 is P-type doping, the P-type impurity source can be boron, boron difluoride, or indium, and the P-type impurity source is not limited to these. Here, when the first doped region 206 is formed using a diffusion process, the preset size of the first doped region can be controlled by rapid thermal annealing, laser annealing, or the like.

[0177] In step 504, as Figure 6d As shown, the main feature is that the first dielectric layer 201 is filled in the first groove 210.

[0178] Here, the methods for filling the first dielectric layer 201 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0179] In step 505, as Figure 6e As shown, the main components are source 203 and drain 204.

[0180] In some embodiments, forming the source 203 and drain 204 of the first transistor 21 and the second transistor 22 at opposite ends along the semiconductor layer thickness direction of the first sub-active pillar 209-1 and the second sub-active pillar 209-2 respectively includes:

[0181] Ion implantation is performed from the first surface of the semiconductor layer to form the source 203 of the first transistor 21 and the second transistor 22;

[0182] The semiconductor layer is thinned from its second surface and along a direction perpendicular to the semiconductor layer to expose the ends of the first sub-active pillar 209-1 and the second sub-active pillar 209-2 away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0183] Ion implantation is performed at the ends of the first sub-active pillar 209-1 and the second sub-active pillar 209-2 that are away from the first surface of the semiconductor layer to form the drain 204 of the first transistor 21 and the second transistor 22.

[0184] In practical applications, the doping methods for source 203 and drain 204 include ion implantation or diffusion processes, but are not limited to these.

[0185] In practical applications, the processes for thinning semiconductor layers include, but are not limited to, etching processes and chemical mechanical polishing processes.

[0186] Here, for reference Figure 6f When thinning the semiconductor layer, a first doped region 206 of predetermined size W can be retained on the side of the semiconductor layer between the first transistor 21 and the second transistor 22 that is in contact with the first dielectric layer 201 and extends away from the first dielectric layer 201; Reference Figure 6e Alternatively, a first doped region 206 of a predetermined size can be removed from the semiconductor layer between the first transistor 21 and the second transistor 22, on the side that is in contact with the first dielectric layer 201, and extends away from the first dielectric layer 201.

[0187] In some embodiments, the method further includes:

[0188] A portion of a second doped region 207 is formed between the source 203 and the channel region 202; and another portion of the second doped region 207 is formed between the drain 204 and the channel region 202; wherein the doping concentration of the second doped region 207 is less than the doping concentration of the first doped region 206.

[0189] In practical applications, the doping methods for the second doped region 207 include ion implantation or diffusion processes, but are not limited to these.

[0190] In addition, embodiments of the present invention also provide another method for manufacturing a semiconductor structure. Figure 7 This is a schematic diagram illustrating the implementation flow of the semiconductor structure manufacturing method provided in the embodiments of the present invention, as shown below. Figure 7 As shown, the method includes the following steps:

[0191] Step 701: Form a plurality of memory cell arrays; each memory cell in the memory cell array includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor;

[0192] The method for manufacturing the vertical transistor includes: providing a semiconductor layer in which at least one active pillar and gates located on both sides of the active pillar are formed;

[0193] The active pillar is etched from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar;

[0194] A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction;

[0195] The first dielectric layer is filled into the first groove;

[0196] The source and drain of the first transistor and the second transistor are formed at opposite ends along the thickness direction of the semiconductor layer, respectively; the first and second sub-active pillars between the source and the drain respectively constitute the channel regions of the first transistor and the second transistor.

[0197] Step 702: Forming multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0198] In step 701, the method for forming the vertical transistor has already been described and will not be repeated here.

[0199] Forming multiple memory cells may include the following steps: forming memory cell contact holes on the source 203; filling the memory cell contact holes with metal material to form memory cell contacts; forming memory cell holes on the memory cell contacts; and forming memory cells in the memory cell holes, such as forming memory capacitors.

[0200] In step 702, bit lines are formed by forming metal lines at preset bit line locations. The metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0201] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0202] The features disclosed in the several method or device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0203] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, include: A first transistor and a second transistor arranged side-by-side in a semiconductor layer and spaced apart by a first dielectric layer; Both the first transistor and the second transistor include: Channel area; Source pole; Drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer; A gate is located on one side of the channel region; wherein the gate of the first transistor is located on the side of the first transistor away from the first dielectric layer, and the gate of the second transistor is located on the side of the second transistor away from the first dielectric layer; and, The first doped region is located in the first transistor and / or the second transistor, in a region extending a predetermined size from the side contacting the first dielectric layer toward the gate, and the doping type of the first doped region is different from the doping types of the source and drain.

2. The semiconductor structure of claim 1, wherein, The doping concentrations of both the source and the drain are greater than the doping concentration of the first doped region.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further includes a second doped region, a portion of which is located between the source and the channel region, and another portion of which is located between the drain and the channel region; wherein the doping concentration of the second doped region is less than the doping concentration of the first doped region.

4. The semiconductor structure of claim 1, wherein, The ratio of the diameter of the first transistor to the width of the second transistor to the preset size is in the range of 2-7.

5. The semiconductor structure of claim 1, wherein, The source and drain are N-type doped, and the first doped region is P-type doped.

6. The semiconductor structure of claim 1, wherein, The first doped region is located in the first transistor and the second transistor, in a region extending a predetermined size from the side in contact with the first dielectric layer toward the gate direction, and in the semiconductor layer between the first transistor and the second transistor, in a region extending the predetermined size from the side in contact with the first dielectric layer toward the direction away from the first dielectric layer.

7. A semiconductor structure, characterized in that, include: Memory cell array; Each memory cell in the memory cell array includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; wherein the vertical transistor includes a first semiconductor body and a second semiconductor body arranged side by side in a semiconductor layer and spaced apart by a first dielectric layer and extending in a first direction, a gate located on one side of the first semiconductor body away from the first dielectric layer, and a gate located on one side of the second semiconductor body away from the first dielectric layer. Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction; Wherein, both the first semiconductor body and the second semiconductor body include: Channel area; Source pole; Drain; wherein the source and the drain are located at opposite ends of the channel region along the thickness direction of the semiconductor layer; The first doped region is located in the first semiconductor body and / or the second semiconductor body, in a region extending a predetermined size from the side contacting the first dielectric layer toward the gate direction, and the doping type of the first doped region is different from the doping types of the source and drain.

8. The semiconductor structure according to claim 7, characterized in that, The doping concentrations of both the source and the drain are greater than the doping concentration of the first doped region.

9. The semiconductor structure of claim 7, wherein, One of the source and drain of the vertical transistor is coupled to the memory cell in the corresponding memory cell.

10. The semiconductor structure of claim 9, wherein, The source and drain of the vertical transistor are coupled to the corresponding bit line.

11. The semiconductor structure of claim 7, wherein, The semiconductor structure includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

12. The semiconductor structure of claim 11, wherein, The semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor. One end of the storage capacitor is connected to the source of the first semiconductor body and the second semiconductor body in the semiconductor structure; The bit line is connected to the drain of the first semiconductor body and the second semiconductor body.

13. A method for manufacturing a semiconductor structure, characterized in that, The method includes: A semiconductor layer is provided, wherein at least one active pillar and gates located on both sides of the active pillar are formed therein; The active pillar is etched from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar; A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction; The first dielectric layer is filled into the first groove; The source and drain of the first transistor and the second transistor are formed at opposite ends along the thickness direction of the semiconductor layer, respectively; the first and second sub-active pillars between the source and the drain respectively constitute the channel regions of the first transistor and the second transistor. The doping type of the first doped region is different from the doping types of the source and drain.

14. The method of claim 13, wherein, The doping concentrations of both the source and the drain are greater than the doping concentration of the first doped region.

15. The method of claim 14, wherein, The method further includes: A portion of a second doped region is formed between the source and the channel region; and another portion of a second doped region is formed between the drain and the channel region; wherein the doping concentration of the second doped region is less than the doping concentration of the first doped region.

16. The method of claim 13, wherein, The ratio of the diameter of the first transistor to the width of the second transistor to the preset size is in the range of 2-7.

17. The method of claim 13, wherein, The formation of the first doped region includes: The first doped region is formed using diffusion or ion implantation processes.

18. The method of claim 13, wherein, The method of forming the source and drain of the first transistor and the second transistor at opposite ends along the semiconductor layer thickness direction of the first sub-active pillar and the second sub-active pillar respectively includes: Ion implantation is performed from the first surface of the semiconductor layer to form the sources of the first transistor and the second transistor; The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the ends of the first and second sub-active pillars away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface. Ion implantation is performed at the ends of the first and second sub-active pillars that are away from the first surface of the semiconductor layer to form the drains of the first and second transistors.

19. A method of manufacturing a semiconductor structure, characterized by, The method includes: Multiple memory cell arrays are formed; each memory cell in the memory cell array includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; Multiple bit lines are formed; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction; The method for manufacturing the vertical transistor includes: providing a semiconductor layer in which at least one active pillar and gates located on both sides of the active pillar are formed; The active pillar is etched from the first surface of the semiconductor layer and along a direction perpendicular to the semiconductor layer to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar; A first doped region is formed in the first sub-active pillar and / or the second sub-active pillar, extending a predetermined size from the side contacting the first groove toward the gate direction; The first dielectric layer is filled into the first groove; The source and drain of the first transistor and the second transistor are formed at opposite ends along the thickness direction of the semiconductor layer, respectively; the first and second sub-active pillars between the source and the drain respectively constitute the channel regions of the first transistor and the second transistor.

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