Electronic device and control method thereof

Abstract

The present disclosure provides an electronic device and a control method. The electronic device includes a sensing pixel. The sensing pixel includes a photosensitive unit, a first transistor, a second transistor, and a third transistor. The first transistor is coupled to the photosensitive unit and configured to receive a reset signal. The second transistor is coupled to the photosensitive unit. The third transistor is coupled to the second transistor and configured to receive a scan signal. During a reset period, a reset signal waveform of the reset signal and a first scan signal waveform of the scan signal at least partially overlap. The electronic device and the control method of the present disclosure can improve output loss of the sensing pixel of the electronic device.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, to an electronic device and a method for controlling the same. Background Technology

[0002] For general image sensors, when multiple transistors of the sensing pixel switch between different operating modes, some circuit nodes in the sensing pixel circuitry can become floating, causing the voltage of some circuit nodes to become unstable and susceptible to leakage current or capacitive coupling effects from the transistors. Therefore, general image sensors typically suffer from output loss problems. In view of this, several embodiments are presented below. Summary of the Invention

[0003] The electronic device disclosed herein includes a sensing pixel. The sensing pixel includes a photosensitive unit, a first transistor, a second transistor, and a third transistor. The first transistor is coupled to the photosensitive unit and is used to receive a reset signal. The second transistor is coupled to the photosensitive unit. The third transistor is coupled to the second transistor and is used to receive a scan signal. During a reset cycle, the reset signal waveform of the reset signal and the first scan signal waveform of the scan signal at least partially overlap.

[0004] The control method disclosed herein is used in an electronic device including a sensing pixel. The control method includes the steps of: providing a reset signal to the sensing pixel during a reset cycle; and providing a scan signal to the sensing pixel during the reset cycle. The reset signal waveform of the reset signal and the first scan signal waveform of the scan signal at least partially overlap.

[0005] The electronic device disclosed herein includes a sensing pixel. The sensing pixel includes a photosensitive unit, a first transistor, a second transistor, a third transistor, and a clamping circuit. The first transistor is coupled to the photosensitive unit and is used to receive a reset signal. The second transistor is coupled to the photosensitive unit. The third transistor is coupled to the second transistor. The clamping circuit is coupled to the second transistor.

[0006] Based on the above, the electronic device and control method for the electronic device disclosed herein can improve the output loss of the sensing pixels of the electronic device.

[0007] To make the foregoing more understandable, several embodiments of the accompanying drawings are described in detail below. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1AA schematic diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0010] Figure 1B A schematic diagram of a sensing pixel according to a first embodiment of the present disclosure is shown;

[0011] Figure 2A A timing diagram illustrating the operation of an electronic device according to an embodiment of the present disclosure is shown;

[0012] Figure 2B The image shows a state in darkness according to an embodiment of this disclosure. Figure 1B Timing diagram of the operation of the sensing pixels;

[0013] Figure 2C The image shown is in a bright state according to an embodiment of the present disclosure. Figure 1B Timing diagram of the operation of the sensing pixels;

[0014] Figure 2D A flowchart illustrating a control method according to an embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic diagram of a sensing pixel according to a second embodiment of the present disclosure is shown;

[0016] Figure 4A The illustration shows a state without light according to an embodiment of the present disclosure. Figure 3 Timing diagram of the operation of the sensing pixels;

[0017] Figure 4B The illustration shows an object in a state of illumination according to an embodiment of the present disclosure. Figure 3 Timing diagram of the operation of the sensing pixels;

[0018] Figure 5A This illustrates a state without light according to another embodiment of the present disclosure. Figure 3 Timing diagram of the operation of the sensing pixels;

[0019] Figure 5B This illustrates a state of illumination according to another embodiment of the present disclosure. Figure 3 Timing diagram of the operation of the sensing pixels;

[0020] Figure 6 A schematic diagram of a sensing pixel according to a third embodiment of the present disclosure is shown;

[0021] Figure 7A The illustration shows a state without light according to an embodiment of the present disclosure. Figure 6 Timing diagram of the operation of the sensing pixels;

[0022] Figure 7B The illustration shows an object in a state of illumination according to an embodiment of the present disclosure. Figure 6 Timing diagram of the operation of the sensing pixels;

[0023] Figure 8A This illustrates a state without light according to another embodiment of the present disclosure. Figure 6 Timing diagram of the operation of the sensing pixels;

[0024] Figure 8B This illustrates a state of illumination according to another embodiment of the present disclosure. Figure 6 Timing diagram of the operation of the sensing pixels;

[0025] Figure 9 A schematic diagram of a sensing pixel according to a fourth embodiment of the present disclosure is shown.

[0026] Explanation of icon numbers

[0027] 100: Electronic devices;

[0028] 110: Panel;

[0029] 111, 111_1…111_M, 311, 611, 911: Sensing pixels;

[0030] 120: Reset circuit;

[0031] 121, 121_1…121_N, 321, 621, 921: Reset signal lines;

[0032] 130: Scan drive circuit;

[0033] 131, 131_1…131_N, 331, 631, 931: Scan signal lines;

[0034] 140: Readout circuit;

[0035] 141, 141_1…141_P, 341, 641, 941: Output signal lines;

[0036] BE, P: Nodes;

[0037] CC: Clamping circuit;

[0038] CD: Clamping diode;

[0039] Cs: Storage capacitor;

[0040] D1: Row direction;

[0041] D2: Column direction;

[0042] EP1, EP2: Exposure periods;

[0043] F1, F2: Sensing frames;

[0044] FG1: Frame Interval Period;

[0045] M1: First transistor;

[0046] M2: Second transistor;

[0047] M3: Third transistor;

[0048] PD: Photosensitive unit;

[0049] RP1, RP2: Reset cycle;

[0050] RS, RS_1…RS_N: Reset signals;

[0051] RW, RW_1…RW_N: Reset signal waveforms;

[0052] S210, S220: Steps;

[0053] SP1, SP2: Scan cycle;

[0054] SS, SS_1…SS_N: Scan signals;

[0055] SW: Scan signal waveform;

[0056] SW1, SW1_1…SW1_N: First scan signal waveform;

[0057] SW2, SW2_1…SW2_N: Second scan signal waveforms;

[0058] V_BE, V_P: Node voltages;

[0059] Vdata1, Vdata2: Data voltage;

[0060] VDD: Power supply voltage;

[0061] Vrst: Reset voltage. Detailed Implementation

[0062] Throughout this disclosure and the appended claims, specific terms are used to refer to designated components. Those skilled in the art will understand that display device manufacturers may use different names to refer to the same components. The specification is not intended to distinguish between components that have the same function but different names. In the following specification and claims, the words "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0063] In some embodiments of this disclosure, terms such as "coupled," "interconnected," etc., are used. References to joining and connecting, unless explicitly defined, mean either two structures in direct contact or two structures not in direct contact, with other structures provided to be disposed between the two structures. Terms related to joining and connecting may also include cases where both structures are movable or both structures are fixed. Additionally, the term "coupled" may include any direct or indirect electrical connection.

[0064] The ordinal numbers used in this specification and claims, such as "first," "second," etc., are used to modify components, and these ordinal numbers do not imply or indicate that the component or these components have any of the aforementioned ordinal numbers, nor do they indicate the order of the components and other components or the order of the manufacturing methods. These ordinal numbers are used only to clearly distinguish a component with a certain name from another component with the same name. The terminology used in the claims and this specification need not be identical, and therefore, a first component provided in this specification may be a second component in the claims. It should be understood that in the following embodiments, technical features of several different embodiments may be replaced, rearranged, and combined to achieve other embodiments without departing from the spirit of this disclosure.

[0065] The transistors disclosed herein (e.g.) Figure 1B Transistors M1 to M3, etc., may comprise semiconductor materials, such as amorphous silicon, low-temperature poly-silicon (LTP), or metal oxide. The transistor may be a thin-film transistor, comprising a top gate, a bottom gate, or a dual gate / double gate, or a combination of the above materials, and this disclosure is not limited thereto. In some embodiments, the thin-film transistor may have the different semiconductor materials described above. Additionally, the transistors of this disclosure (e.g., Figure 1B The first terminal, second terminal, and control terminal of transistors M1 to M3, etc., can be the drain, source, and gate, respectively, but this disclosure is not limited thereto. The first terminal and second terminal of diodes (e.g., photosensitive unit PD and clamping diode CD, etc.) of this disclosure can be the cathode and anode, respectively, but this disclosure is not limited thereto.

[0066] Figure 1A A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown. Reference Figure 1AThe electronic device 100 includes a panel 110, a reset circuit 120, a scan drive circuit 130, and a readout circuit 140. The panel 110 includes a plurality of sensing pixels 111_1 to 111_M, which are arranged to form a sensing array, where M is a positive integer. The plurality of sensing pixels 111_1 to 111_M can be arranged in an array, including a plurality of rows extending along a row direction D1 and a plurality of columns extending along a column direction D2. In embodiments of this disclosure, the reset circuit 120 is coupled to the sensing pixels 111_1 to 111_M via a plurality of reset signal lines 121_1 to 121_N, where N is a positive integer. Each of the reset signal lines 121_1 to 121_N is coupled to the sensing pixel 111_1 to 111_M of the corresponding row. The scan driving circuit 130 is coupled to sensing pixels 111_1 to 111_M via multiple scan signal lines 131_1 to 131_N. Each of the scan signal lines 131_1 to 131_N is coupled to the sensing pixels 111_1 to 111_M in the corresponding row. The readout circuit 140 is coupled to sensing pixels 111_1 to 111_M via multiple output signal lines 141_1 to 141_P, where P is a positive integer. Each of the output signal lines 141_1 to 141_P is coupled to the sensing pixels 111_1 to 111_M in the corresponding column. In embodiments of this disclosure, each row of sensing pixels 111_1 to 111_M may receive reset signals RS_1 to RS_N with different waveforms within a time period, but this disclosure is not limited thereto. In one embodiment of this disclosure, reset signals RS_1 to RS_N may be the same common reset signals provided by reset circuit 120, and each row of sensing pixels 111_1 to sensing pixels 111_M may simultaneously receive reset signals RS_1 to RS_N with the same signal waveform within a time period.

[0067] In embodiments of this disclosure, the electronic device 100 may be an image sensing device, and the image sensing device may be, for example, an X-ray image sensor, a fingerprint sensor, or a light sensor. In other words, sensing pixels 111_1 to 111_M may be configured to sense visible light, or visible light converted to X-rays or other invisible light. In some embodiments, such as Figure 1AAs shown, the reset circuit 120, scan drive circuit 130, and readout circuit 140 may be arranged outside the panel 110. Alternatively, in embodiments of this disclosure, although not shown in the figures, the reset circuit 120, scan drive circuit 130, and readout circuit 140 may be disposed in the peripheral area of ​​the panel 110. This disclosure does not limit the arrangement position of the reset circuit 120, scan drive circuit 130, and readout circuit 140 in the peripheral area of ​​the panel 110. Furthermore, in one embodiment of this disclosure, the reset circuit 120, scan drive circuit 130, and readout circuit 140 may be integrated into an integrated circuit or an on-glass circuit.

[0068] Figure 1B A schematic diagram of a sensing pixel according to a first embodiment of the present disclosure is shown. Reference Figure 1B , Figure 1A The circuit architecture of each of the sensing pixels 111_1 to 111_M can be compared with Figure 1B The sensing pixel 111 has the same circuit architecture. The sensing pixel 111 includes at least three transistors (i.e., a first transistor M1, a second transistor M2, and a third transistor M3) and a photosensitive unit PD. For example, the photosensitive unit PD can be a photodiode. In embodiments of this disclosure, the sensing pixel 111 can be a 3T architecture of an active pixel sensor (APS), but this disclosure is not limited thereto. In embodiments of this disclosure, the first transistor M1 can be coupled to the photosensitive unit PD and can receive a reset signal (RS). The second transistor M2 can be coupled to the photosensitive unit PD. The third transistor M3 can be coupled to the second transistor M2 and can receive a scan signal (SS). Specifically, the first terminal of transistor (reset transistor) M1 is coupled to a reset voltage Vrst, and the second terminal of transistor M1 is coupled to the first terminal of the photosensitive unit PD. The control terminal of transistor M1 is coupled to a reset signal line 121, wherein the reset signal line 121 can be... Figure 1A One of the reset signal lines 121_1 to 121_N. The second terminal of the photosensitive unit PD is coupled to ground voltage. The control terminal of transistor M2 is coupled to the first terminal of the photosensitive unit PD, and the first terminal of transistor M2 is coupled to the power supply voltage (VDD), but this disclosure is not limited thereto. The first terminal of transistor (select transistor) M3 is coupled to the second terminal of transistor M2, and the control terminal of transistor M3 is coupled to scan signal line 131, wherein scan signal line 131 may be... Figure 1A One of the scan signal lines 131_1 to 131_N. The second terminal of transistor M3 is coupled to output signal line 141, wherein output signal line 141 can be... Figure 1A One of the output signal lines 141_1 to 141_P.

[0069] Specifically, in embodiments of this disclosure, the control terminal of transistor M1 can be configured to receive a reset signal via reset signal line 121 to reset the node voltages of photosensitive unit PD and node BE, wherein node BE is located between the first terminal of photosensitive unit PD and the control terminal of transistor M2. The control terminal of transistor M3 can be configured to receive a scan signal via scan signal line 131. Scan signal line 131 can be coupled to a third transistor M3 to provide a scan signal to the third transistor M3. According to some embodiments, when transistor M3 is turned on, transistor M2 operates as a source follower circuit, and the node voltage of node P (output node) can be read from output signal line 141 via transistor M3, wherein node P is located between the second terminal of transistor M2 and the first terminal of transistor M3. Output signal line 141 can be coupled to a third transistor M3 to output a sensing signal. Node P can be referred to as the readout node. In embodiments of this disclosure, the node voltage of node P depends on the node voltage of node BE. When transistors M1 and M3 are disconnected, the node voltage of node P can rise because node P is in a floating state and leakage current can flow from the first terminal of transistor M2 to the second terminal. (This is for the NMOS case. In the PMOS case, node P can have the opposite state.) Due to the capacitive coupling effect between the control terminal and the second terminal of transistor M2, the node voltage of node BE can also rise due to the voltage coupling of node P.

[0070] Figure 2A A timing diagram illustrating the operation of an electronic device according to an embodiment of the present disclosure is shown. (See reference...) Figures 1A to 2A Each row of sensing pixels 111_1 to 111_M can receive multiple reset signals RS_1 to RS_N respectively through reset signal lines 121_1 to 121_N, and each row of sensing pixels 111_1 to 111_M can receive multiple scan signals SS_1 to SS_N respectively through scan signal lines 131_1 to 131_N. More precisely, as... Figure 2A As shown, the sensing frame F1 (one frame) includes a reset period RP1, an exposure period EP1, a scan period SP1, and a frame gap period FG1. During the reset period RP1, multiple rows of sensing pixels 111_1 to 111_M can receive multiple reset signal waveforms RW_1 to RW_N from reset signals RS_1 to RS_N in a time-division multiplexing and sequential manner, and multiple rows of sensing pixels 111_1 to 111_M can receive multiple first scan signal waveforms SW1_1 to SW1_N from scan signals SS_1 to SS_N in a time-division multiplexing and sequential manner. Specifically, referring to... Figure 2ADuring the reset cycle RP1, the reset signal waveform of the reset signal RS (e.g., RW1) and the first scan signal waveform of the scan signal SS (e.g., SW1) at least partially overlap, but this disclosure is not limited thereto. According to some embodiments, at least overlap of two waveforms means that one waveform and the other waveform appear simultaneously during at least one time period. Taking the two waveforms RW_1 and SW1_1 as examples, the reset signal waveform RW_1 of the reset signal RS and the first scan signal waveform SW_1 of the scan signal SS_1 appear simultaneously during the time period from time t0 to time t01.

[0071] In some embodiments, during the reset cycle RP1, two or more reset signal waveforms of the reset signal RS and two or more first scan signal waveforms (e.g., SW1) of the scan signal SS respectively at least partially overlap. For example, during the reset cycle RP1, the reset signal waveform RW_1 of the reset signal RS and the first scan signal waveform SW_1 at least partially overlap, and the reset signal waveform RW_2 of the reset signal RS and the first scan signal waveform SW_2 at least partially overlap.

[0072] In some embodiments, reference Figure 1A and Figure 2A During the reset cycle RP1, the reset circuit 120 provides a reset signal RS_1 to the sensing pixels (including sensing pixel 111_1) in the first row via reset signal line 121_1, and provides a reset signal RS_2 to the sensing pixels (including sensing pixel 111_2) in the second row via reset signal line 121_2. Specifically, the reset circuit 120 is coupled to sensing pixel 111_1 and another sensing pixel 111_2, and configured to provide reset signals RS_1 and RS_2 to sensing pixel 111_1 and the other sensing pixel 111_2, respectively. Sensing pixel 111_1 and the other sensing pixel 111_2 can be located in adjacent rows, meaning that the sensing pixels are not located between sensing pixel 111_1 and the other sensing pixel 111_2 along the column direction D2. According to some embodiments, see reference... Figure 2ADuring the reset period RP1, the reset signal waveform RW_1 of reset signal RS_1 and the other reset signal waveform RW_2 of another reset signal RS_2 do not overlap, but this disclosure is not limited thereto. According to some embodiments, the non-overlapping of two waveforms means that the two waveforms do not occur simultaneously. Specifically, any point in time of one waveform does not occur simultaneously with any point in time of the other waveform. Taking two waveforms RW_1 and RW_2 as examples, during the reset period RP1, the waveform RW_1 of reset signal RS_1 and the other waveform RW_2 of another reset signal RS_2 do not occur simultaneously. Specifically, in some embodiments, the rising edge of the other waveform RW_2 of the other reset signal RS_2 occurs later than the falling edge of the waveform RW_1 of reset signal RS_1. In some embodiments, the rising edge of the other waveform RW_2 of the other reset signal RS_2 occurs simultaneously with the falling edge of the waveform RW_1 of reset signal RS_1.

[0073] In some embodiments, each row of sensing pixels 111_1 to 111_M can simultaneously receive a corresponding reset signal waveform and a corresponding scan signal waveform. During exposure cycle EP1, sensing pixels 111_1 to 111_M can perform exposure operations at the same time or at different times. During scan cycle SP1, each row of sensing pixels 111_1 to 111_M can receive multiple scan signals SS_1 to SS_N and second scan signal waveforms SW2_1 to SW2_N in a time-division and sequential manner. Therefore, the readout circuit 140 can read multiple sensing signals from sensing pixels 111_1 to 111_M in a time-division and sequential manner via output signal lines 141_1 to 141_P. According to some embodiments, see reference. Figure 2A The scan signal SS_1 includes the second scan signal waveform SW2_1, and during the sensing frame F1, the first scan signal waveform SW1_1 and the second scan signal waveform SW2_1 do not overlap.

[0074] Similarly, after the inter-frame period FG1, sensing pixels 111_1 to 111_M can receive, in the same manner, a plurality of other reset signal waveforms, including reset signals RS_1 to RS_N, and a plurality of other first scan signal waveforms, including SW1_1 to SW1_N, during the reset period RP2 of sensing frame F2 (the following frame).

[0075] Figure 2B The illustration shows a state without light according to an embodiment of the present disclosure. Figure 1B Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 1B as well as Figure 2B The following examples will be based on a state without light exposure. Figure 1B Taking a sensing pixel 111 as an example. In embodiments of this disclosure, the control terminal of transistor M1 receives a reset signal RS, and the control terminal of transistor M3 receives a scan signal SS. During sensing frame F1, the first scan signal waveform SW1 and the second scan signal waveform SW2 of scan signal SS do not overlap. In embodiments of this disclosure, the time length between the rising and falling edges of the reset signal waveform RW of reset signal RS may be less than the time length between the rising and falling edges of the first scan signal waveform SW1 of scan signal SS. In other words, as... Figure 2A As shown, the waveform width of the reset signal waveform RW of the reset signal RS is smaller than the waveform width of the first scan signal waveform SW1 of the scan signal SS. Furthermore, in embodiments of this disclosure, during the reset cycle RP1, the first transistor M1 and the third transistor M3 can be turned on first and then turned off. The first transistor M1 can be turned off faster than the transistor M3. Therefore, in... Figure 2A During the time period shown, the falling edge of the reset signal waveform RW of the reset signal RS may occur earlier than the falling edge of the first scan signal waveform SW1 of the scan signal SS. Additionally, in embodiments of this disclosure, during the scan period SP1 of the sensing frame F1, the control terminal of the transistor M3 receives the second scan signal waveform SW2 of the scan signal SS.

[0076] Specifically, during the reset cycle RP1 of sensing frame F1, transistors M1 and M3 are turned on during the period from time t0 to time t1. The node voltage V_BE of node BE is reset to the reset voltage Vrst, and the node voltage V_P of node P is charged to the data voltage Vdata1 (in the unilluminated state). When sensing pixel 111 is in the unilluminated state, the data voltage Vdata1 is the output voltage of node P. Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Furthermore, since sensing pixel 111 is in the unilluminated state, the photosensitive unit PD does not generate photocurrent. There may be a leakage current from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period from time t1 to time t4. During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower, and the node voltage V_P of node P can be recharged to the data voltage Vdata1. That is, as shown in the following equation (1), the voltage difference (parameter ΔV) between the node voltage V_P of node P and the reset period RP1 and the scan period SP1. P This can be offset because of the parameter V. P_resetand parameter V P_scan All are equal to the data voltage Vdata1. In the following equation (1), the parameter V P_reset This represents the node voltage V_P at node P during reset cycle RP1, and the parameter V P_scan V_P represents the node voltage V_P of node P during the scan period SP1.

[0077] ΔV P =V P_reset -V P_scan ...Equation (1)

[0078] Furthermore, as shown in equation (2) below, due to the voltage difference (parameter ΔV) between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1, BE The voltage difference (parameter ΔV) depends on the node voltage V_P of node P between the reset period RP1 and the scan period SP1. P Therefore, the parameter ΔV that causes output loss BE It can also be offset or reduced because of the parameter ΔV P It can be equal to zero. In the following equation (2), the parameter ΔV BE The term V_BE represents the voltage difference between the node voltage V_BE at node BE during the reset period RP1 and the scan period SP1 (caused by the coupling of node P). In the following equation (2), parameter M2_Cgs is the parasitic capacitance between the control terminal and the second terminal of transistor M2, and parameter C PD This refers to the intrinsic capacitance formed by the structure of the photosensitive unit (PD).

[0079]

[0080] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. There may be leakage current from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period from time t5 to time t8. In the next reset period RP2 of the next sensing frame F2, since transistors M1 and M3 are turned on during the period from time t8 to time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be recharged to the data voltage Vdata1. In other words, since the node voltage V_P of node P can be charged to the data voltage Vdata1 during the period from time t8 to time t9, the effect of the leakage current from time t5 to time t8 on the node voltage V_P of node P can be mitigated. Therefore, the output loss of the sensing pixel 111 operating in an unilluminated state can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0081] Figure 2C The illustration shows an object in a state of illumination according to an embodiment of the present disclosure. Figure 1B Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 1B as well as Figure 2C The following examples will be based on a state of illumination. Figure 1B Taking a sensing pixel 111 as an example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 2BThe above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistors M1 and M3 are turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the data voltage Vdata1. Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 111 is in an illuminated state, the photosensitive unit PD can generate a photocurrent reaching node BE, causing the node voltage V_BE to decrease. Correspondingly, since the node voltage V_P of node P is coupled to the node voltage V_BE of node BE, the node voltage V_P of node P also decreases. In embodiments of this disclosure, during the time period from time t1 to time t4, the voltage difference of node voltage V_P of node P is mainly affected by the capacitive coupling effect of the voltage difference of node voltage V_BE of node BE, and is not affected by the leakage current from the first terminal to the second terminal of transistor M2.

[0082] During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower and outputs the node voltage V_P of node P, where the node voltage V_P of node P can be charged to the data voltage Vdata2 (illumination state). Therefore, the readout circuit 140 can read the sensing result (data) based on the data voltage Vdata2, where the sensing result (data) corresponds to the voltage difference between the data voltage Vdata2 and the data voltage Vdata1 between the reset period RP1 and the scan period SP1 (as parameter ΔV). P_exposure In addition, with Figure 2B The unlit state of the above embodiments is similar, as shown in the following equation (3), where the parameter ΔV P They can be canceled out, and only the parameter ΔV is retained. P_exposure .

[0083] ΔV P +ΔV P_exposure =V P_reset -V P_scan ...Equation (3)

[0084] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. There may be leakage current from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. During the reset period RP2 of sensing frame F2, since transistors M1 and M3 are turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be recharged to the data voltage Vdata1. In other words, since the node voltage V_P of node P can be charged to the data voltage Vdata1 during the period between time t8 and time t9, the effect of the leakage current from time t5 to time t8 on the node voltage V_P of node P can be mitigated. Therefore, the output loss of sensing pixel 111 operating under illumination can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0085] Figure 2D A flowchart illustrating a control method according to an embodiment of the present disclosure is shown. Figure 1A Each of the sensing pixels 111_1 to 111_M may perform the following steps S210 and S220 to improve output loss. (See reference...) Figure 1B , Figure 2B as well as Figure 2D The following examples will be based on a state without light exposure. Figure 1BTaking a sensing pixel 111 as an example. In step S210, during the reset cycle RP1, a reset signal RS is provided to the sensing pixel 111. During the reset cycle RP1, the control terminal of the first transistor M1 can receive the reset signal RS having a reset signal waveform RW. In step S220, during the reset cycle RP1, a scan signal SS is provided to the sensing pixel 111. During the reset cycle RP1, the control terminal of the third transistor M3 can receive the scan signal SS having a first scan signal waveform SW1. In embodiments of this disclosure, the reset signal waveform RW of the reset signal RS and the first scan signal waveform SW1 of the scan signal SS at least partially overlap. That is, the sensing pixel 111 can effectively mitigate the effect of leakage current from the first terminal to the second terminal of the transistor M2 so as to charge the node voltage of node P to the data voltage Vdata1, and the node voltage of node P can be lower than the node voltage of node BE. In embodiments of this disclosure, during the scan cycle SP1, the control terminal of the third transistor M3 can receive the scan signal SS having a second scan signal waveform SW2. Therefore, since the voltage difference between the node voltage of node P during the reset period RP1 and the scan period SP1 (caused by leakage current) can be canceled or reduced, and the voltage difference between the node voltage of node BE during the reset period RP1 and the scan period SP1 (caused by the coupling of node P, resulting in output loss) can also be canceled or reduced, the output loss of the sensing pixel 111 operating in the unilluminated state can be effectively improved. Furthermore, Figure 2D The control method can also be adapted to, for example Figure 2C The sensing pixel 111 in the above embodiment is in an illuminated state. Therefore, Figure 1A Each of the sensing pixels 111_1 to 111_M may perform the following steps S210 and S220 to improve the output loss in the unlit state or the illuminated state.

[0086] Specifically, in some embodiments, references Figure 2B and Figure 2D The sensing frame F1 (one frame) includes a reset period RP1, an exposure period EP1, a scan period SP1, and a frame gap period FG1. During the sensing frame F1, the method further includes providing a scan signal SS to the sensing pixel, and the scan signal SS includes a second scan signal waveform SW2 that does not overlap with the first scan signal waveform SW1. In some embodiments, during the scan period SP1, the method further includes reading out the sensing signal from a third transistor M3.

[0087] Figure 3 A schematic diagram of a sensing pixel according to a second embodiment of the present disclosure is shown. Reference Figure 3 , Figure 1AThe circuit architecture of each of the sensing pixels 111_1 to 111_M can be compared with Figure 3 The sensing pixel 311 has the same circuit architecture. The sensing pixel 311 includes at least three transistors (i.e., a first transistor M1, a second transistor M2, and a third transistor M3), a photosensitive unit PD, and a clamping circuit CC. The clamping circuit CC includes a clamping diode CD. In embodiments of this disclosure, the sensing pixel 311 may be a 3T architecture of an active pixel sensor, but this disclosure is not limited thereto. In embodiments of this disclosure, the first terminal of transistor M1 is coupled to a reset voltage Vrst, and the second terminal of transistor M1 is coupled to the first terminal of the photosensitive unit PD. The control terminal of transistor M1 is coupled to a reset signal line 321, wherein the reset signal line 321 may be... Figure 1A One of the reset signal lines 121_1 to 121_N. The second terminal of the photosensitive unit PD is coupled to ground voltage. The control terminal of transistor M2 is coupled to the first terminal of the photosensitive unit PD, and the first terminal of transistor M2 is coupled to the power supply voltage (VDD), but this disclosure is not limited thereto. In one embodiment of this disclosure, the first terminal of transistor M2 may be coupled to the power supply voltage. The first terminal of transistor M3 is coupled to the second terminal of transistor M2, and the control terminal of transistor M3 is coupled to scan signal line 331, wherein scan signal line 331 may be... Figure 1A One of the scan signal lines 131_1 to 131_N. The second terminal of transistor M3 is coupled to output signal line 341, wherein output signal line 341 can be... Figure 1A One of the output signal lines 141_1 to 141_P. The first terminal of the clamping diode CD is coupled to the reset voltage Vrst. The second terminal of the clamping diode CD is coupled to the second terminal of transistor M2 and the first terminal of transistor M3. The clamping diode CD is coupled between the reset voltage Vrst and the second transistor M2. Alternatively, in one embodiment of this disclosure, the sensing pixel 311 may include other clamping circuitry coupled to the second terminal of transistor M2, instead of the clamping diode CD.

[0088] Specifically, in embodiments of this disclosure, the control terminal of transistor M1 can be configured to receive a reset signal via reset signal line 321 to reset the node voltages of photosensitive unit PD and node BE, wherein node BE is located between the first terminal of photosensitive unit PD and the control terminal of transistor M2. The control terminal of transistor M3 can be configured to receive a scan signal via scan signal line 331. According to some embodiments, when transistor M3 is turned on, transistor M2 operates as a source follower circuit, and the node voltage of node P can be read from output signal line 341 via transistor M3, wherein node P is located between the second terminal of transistor M2 and the first terminal of transistor M3. In embodiments of this disclosure, the node voltage of node P depends on the node voltage of node BE. When transistors M1 and M3 are turned off, the node voltage of node P can increase because node P is in a floating state and there may be leakage current from the first terminal to the second terminal of transistor M2. In some embodiments, the node voltage of node P is less than the clamping voltage Vrst + VF. VF is the voltage of clamping circuit CD. The node voltage of node BE can also be limited to increase due to the coupling of the voltage of node P.

[0089] Figure 4A The illustration shows a state without light according to an embodiment of the present disclosure. Figure 3 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 3 as well as Figure 4A The following examples will be based on a state without light exposure. Figure 3 Taking a sensing pixel 311 as an example. In embodiments of this disclosure, the control terminal of transistor M1 receives a reset signal RS, and the control terminal of transistor M3 receives a scan signal SS. During the reset period RP1 of sensing frame F1, the reset signal RS has the waveform width of the reset signal waveform RW. During the scan period SP1 of sensing frame F1, the scan signal SS has the waveform width of the scan signal waveform SW.

[0090] Specifically, during the reset cycle RP1 of sensing frame F1, since transistor M1 is turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be clamped with a clamping voltage Vrst+VF or less than Vrst+VF, where the clamping voltage Vrst+VF is less than the power supply voltage VDD. Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 311 is in an unilluminated state, the photosensitive unit PD does not generate photocurrent. However, there may be leakage current from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period from the falling edge of the scan signal waveform SW of the previous sensing frame to time t4. The node voltage V_P of node P is still clamped with a clamp voltage Vrst+VF or less than Vrst+VF.

[0091] During the scan cycle SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower, and the node voltage V_P of node P can be charged to the data voltage Vdata1. That is, the voltage difference between the node voltage V_P of node P and the scan cycle SP1 (compared to the parameter ΔV mentioned above) P (The definition is the same) can be effectively suppressed by the clamping diode CD. Furthermore, due to the voltage difference between the node voltage V_BE at node BE during the reset period RP1 and the scan period SP1 (which is the same as the parameter ΔV mentioned above), BE (The same definition applies) depends on the voltage difference between the node voltage V_P of node P during the reset period RP1 and the scan period SP1. Therefore, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively reduced, thus effectively reducing the impact of output loss.

[0092] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period from time t5 to time t8. The node voltage V_P of node P is still clamped by a clamping voltage Vrst+VF or less than Vrst+VF. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period from time t8 to time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst again, and the node voltage V_P of node P can still be clamped by a clamping voltage Vrst+VF or less than Vrst+VF, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of the sensing pixel 311 operating in the unlit state can be effectively improved. Furthermore, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, and therefore will not be repeated here.

[0093] Figure 4B The illustration shows an object in a state of illumination according to an embodiment of the present disclosure. Figure 3 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 3 as well as Figure 4B The following examples will be based on a state of illumination. Figure 3 Taking a sensing pixel 311 as an example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 4A The above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistor M1 is turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be clamped with a clamping voltage Vrst+VF or less than Vrst+VF, where the clamping voltage Vrst+VF is less than the power supply voltage VDD. Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 311 is in an illuminated state, photosensitive unit PD can generate photocurrent reaching node BE, causing the node voltage V_BE to decrease. Correspondingly, since the node voltage V_P of node P depends on the node voltage V_BE of node BE, the node voltage V_P of node P also decreases.

[0094] During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower and outputs the node voltage V_P of node P, which can be charged to the data voltage Vdata2 (illumination state). Therefore, the readout circuit 140 can read the sensing result (data) based on the data voltage Vdata2, where the sensing result corresponds to the voltage change of the node voltage V_P of node P at time t4. Furthermore, with... Figure 4A Similar to the unilluminated state of the above embodiments, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively suppressed. The voltage difference is caused by the capacitive coupling effect of the node voltage V_P of node P.

[0095] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. The node voltage V_P of node P must not exceed the clamping voltage Vrst+VF. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can still be clamped with a clamping voltage Vrst+VF or less than Vrst+VF, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of sensing pixel 311 operating under illumination can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0096] Figure 5A This illustrates a state without light according to another embodiment of the present disclosure. Figure 3 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 3 as well as Figure 5A The following examples will be based on a state without light exposure. Figure 3 Taking a sensing pixel 311 as an example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 2BThe above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistors M1 and M3 are turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the reset voltage Vdata1 (unilluminated state). Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 311 is in an unilluminated state, the photosensitive unit PD does not generate photocurrent. However, there may be leakage current from the first terminal to the second terminal of transistor M2, so that the node voltage V_P of node P may rise during the period from time t1 to time t4. The node voltage V_P of node P must not exceed the clamping voltage Vrst + VF.

[0097] During the scan cycle SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower, and the node voltage V_P of node P can be charged to the data voltage Vdata1. That is, the voltage difference between the node voltage V_P of node P and the scan cycle SP1 (compared to the parameter ΔV mentioned above) P (The definition is the same) can be effectively suppressed by the clamping diode CD. Furthermore, due to the voltage difference between the node voltage V_BE at node BE during the reset period RP1 and the scan period SP1 (which is the same as the parameter ΔV mentioned above), BE (The same definition applies) depends on the voltage difference between the node voltage V_P of node P during the reset period RP1 and the scan period SP1. Therefore, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be correspondingly canceled or reduced, thus canceling or mitigating the effect of output loss.

[0098] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, there may be leakage current from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period from time t5 to time t8. The node voltage V_P of node P must not exceed the clamping voltage Vrst + VF. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period from time t8 to time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be recharged to the data voltage Vdata1. In other words, since the node voltage V_P of node P can be charged to the data voltage Vdata1 during the period from time t8 to time t9, the effect of the leakage current from time t5 to time t8 on the node voltage V_P of node P can be mitigated. Therefore, the output loss of the sensing pixel 311 operating in the unlit state can be effectively improved. Furthermore, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, and therefore will not be repeated here.

[0099] Figure 5B This illustrates a state of illumination according to another embodiment of the present disclosure. Figure 3 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 3 as well as Figure 5B The following examples will be based on a state of illumination. Figure 3 One of the sensing pixels, 311, is another example. < In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 2CThe above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistors M1 and M3 are turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the reset voltage Vdata1 (unilluminated state). Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 311 is in an illuminated state, photosensitive unit PD can generate photocurrent reaching node BE, causing the node voltage V_BE to decrease. Correspondingly, since the node voltage V_P of node P depends on the node voltage V_BE of node BE, the node voltage V_P of node P also decreases. According to some embodiments, in the embodiments of this disclosure, the voltage difference of node voltage V_P of node P during the time period from time t1 to time t4 is mainly affected by the capacitive coupling effect of the voltage difference of node voltage V_BE of node BE during the time period from time t1 to time t4, and is not affected by the leakage current from the first terminal to the second terminal of transistor M2.

[0100] During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower and outputs the node voltage V_P of node P, which can be charged to the data voltage Vdata2 (illumination state). Therefore, the readout circuit 140 can read the sensing result (data) based on the data voltage Vdata2, where the sensing result corresponds to the voltage change of the node voltage V_P of node P at time t4. Furthermore, with... Figure 5A Similar to the unilluminated state of the above embodiments, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively suppressed. The voltage difference is caused by the capacitive coupling effect of the node voltage V_P of node P.

[0101] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. The node voltage V_P of node P must not exceed the clamping voltage Vrst + VF. Furthermore, during the reset period RP2 of sensing frame F2, since transistors M1 and M3 are turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the data voltage Vdata1, effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of sensing pixel 311 operating under illumination can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0102] Figure 6 A schematic diagram of a sensing pixel according to a third embodiment of the present disclosure is shown. Reference Figure 6 , Figure 1A The circuit architecture of each of the sensing pixels 111_1 to 111_M can be compared with Figure 6 The sensing pixel 611 has the same circuit architecture. The sensing pixel 611 includes at least three transistors M1 to M3, a photosensitive unit PD, and a clamping circuit CC. The clamping circuit CC includes a storage capacitor Cs. In embodiments of this disclosure, the sensing pixel 611 may be a 3T architecture of an active pixel sensor, but this disclosure is not limited thereto. In embodiments of this disclosure, the first terminal of transistor M1 is coupled to a reset voltage Vrst, and the second terminal of transistor M1 is coupled to the first terminal of the photosensitive unit PD. The control terminal of transistor M1 is coupled to a reset signal line 621, wherein the reset signal line 621 may be... Figure 1A One of the reset signal lines 121_1 to 121_N. The second terminal of the photosensitive unit PD is coupled to ground voltage. The control terminal of transistor M2 is coupled to the first terminal of the photosensitive unit PD, and the first terminal of transistor M2 is coupled to the power supply voltage (VDD), but this disclosure is not limited thereto. In one embodiment of this disclosure, the first terminal of transistor M2 may be coupled to the power supply voltage. The first terminal of transistor M3 is coupled to the second terminal of transistor M2, and the control terminal of transistor M3 is coupled to scan signal line 631, wherein scan signal line 631 may be... Figure 1A One of the scan signal lines 131_1 to 131_N. The second terminal of transistor M3 is coupled to output signal line 641, wherein output signal line 641 can be... Figure 1A One of the output signal lines 141_1 to 141_P. The first terminal of the storage capacitor Cs is coupled to the second terminal of transistor M2 and the first terminal of transistor M3. The second terminal of the storage capacitor Cs is coupled to ground voltage. The storage capacitor Cs is coupled between the second transistor M3 and ground voltage.

[0103] Specifically, in embodiments of this disclosure, the control terminal of transistor M1 can be configured to receive a reset signal via reset signal line 621 to reset the node voltages of photosensitive unit PD and node BE, wherein node BE is located between the first terminal of photosensitive unit PD and the control terminal of transistor M2. The control terminal of transistor M3 can be configured to receive a scan signal via scan signal line 631. According to some embodiments, when transistor M3 is turned on, transistor M2 operates as a source follower circuit, and the node voltage of node P can be read from output signal line 641 via transistor M3, wherein node P is located between the second terminal of transistor M2 and the first terminal of transistor M3. In embodiments of this disclosure, the node voltage of node P depends on the node voltage of node BE. When transistors M1 and M3 are turned off, the node voltage of node P may rise because node P is in a floating state and there may be leakage current from the first terminal to the second terminal of transistor M2, but the storage capacitor Cs can effectively suppress the rise in the node voltage of node P. Based on the capacitance characteristics of the storage capacitor Cs, the storage capacitor Cs can effectively reduce the voltage variation of the node voltage, and the node voltage of node BE can also be limited to increase due to the voltage coupling of node P.

[0104] Figure 7A The illustration shows a state without light according to an embodiment of the present disclosure. Figure 6 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 6 as well as Figure 7A The following examples will be based on a state without light exposure. Figure 6 Taking a sensing pixel 611 as an example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 4AThe above embodiments are the same, and therefore will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistor M1 is turned on during the time period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can rise due to the leakage current from the first terminal to the second terminal of transistor M2, but the storage capacitor Cs can effectively suppress the rise of the node voltage V_P of node P. Then, during the time period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since the sensing pixel 611 is in an unilluminated state, the photosensitive unit PD does not generate photocurrent. In the embodiments of this disclosure, there may be a leakage current from the first terminal to the second terminal of transistor M2, but the node voltage V_P of node P can rise in a limited manner during the time period from time t1 to time t4. In addition, the node voltage V_BE of node BE can also be limited to increase during the time period from time t1 to time t4.

[0105] During the scan cycle SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower, and the node voltage V_P of node P can be charged to the data voltage Vdata1. That is, the voltage difference between the node voltage V_P of node P and the scan cycle SP1 (compared to the parameter ΔV mentioned above) P (The definition is the same) can be effectively suppressed by the storage capacitor Cs. Furthermore, due to the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 (and the parameter ΔV mentioned above)... BE (The same definition applies) depends on the voltage difference between the node voltage V_P of node P during the reset period RP1 and the scan period SP1. Therefore, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively reduced, thus effectively reducing the impact of output loss.

[0106] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. Due to the influence of the storage capacitor Cs, the node voltage V_P of node P also rises only to a limited extent. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can still rise only to a limited extent, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of sensing pixel 611 operating in the unilluminated state can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0107] Figure 7B The illustration shows an object in a state of illumination according to an embodiment of the present disclosure. Figure 6 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 6 as well as Figure 7B The following examples will be based on a state of illumination. Figure 6 Taking a sensing pixel 611 as an example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 4AThe above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistor M1 is turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can increase due to the leakage current from the first terminal to the second terminal of transistor M2, but the storage capacitor Cs can effectively suppress the increase of the node voltage V_P of node P. Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 611 is in an illuminated state, photosensitive unit PD can generate photocurrent reaching node BE, causing the node voltage V_BE to decrease. Correspondingly, since the node voltage V_P of node P depends on the node voltage V_BE of node BE, the node voltage V_P of node P also decreases. According to some embodiments, in the embodiments of this disclosure, the voltage difference of node voltage V_P of node P during the time period from time t1 to time t4 is mainly affected by the capacitive coupling effect of the voltage difference of node voltage V_BE of node BE during the time period from time t1 to time t4, and is not affected by the leakage current from the first terminal to the second terminal of transistor M2.

[0108] During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower and outputs the node voltage V_P of node P, where the node voltage V_P of node P can be charged to the data voltage Vdata2 (illumination state). Therefore, the readout circuit 140 can read the sensing result (data) based on the data voltage Vdata2, where the sensing result corresponds to the voltage change of node voltage V_P at time t4. Furthermore, with... Figure 7A Similar to the unilluminated state of the above embodiments, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively suppressed. The voltage difference is caused by the capacitive coupling effect of the node voltage V_P of node P.

[0109] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. Due to the influence of the storage capacitor Cs, the node voltage V_P of node P also rises only to a limited extent. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can still rise only to a limited extent, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of sensing pixel 611 operating under illumination can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0110] Figure 8A This illustrates a state without light according to another embodiment of the present disclosure. Figure 6 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 6 as well as Figure 8A The following examples will be based on a state without light exposure. Figure 6 One sensing pixel 611 is used as another example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 2B The above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistors M1 and M3 are turned on during the time period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the reset voltage Vdata1 (unilluminated state). Then, during the time period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since the sensing pixel 611 is in an unilluminated state, the photosensitive unit PD does not generate photocurrent. In the embodiments of this disclosure, there may be leakage current from the first terminal to the second terminal of transistor M2, but the node voltage V_P of node P can be limited to increase during the time period from time t1 to time t4. In addition, the node voltage V_BE of node BE can also be limited to increase during the time period from time t1 to time t4.

[0111] During the scan cycle SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower, and the node voltage V_P of node P can be charged to the data voltage Vdata1. That is, the voltage difference between the node voltage V_P of node P and the scan cycle SP1 (compared to the parameter ΔV mentioned above) P (The definition is the same) can be effectively suppressed by the storage capacitor Cs. Furthermore, due to the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 (and the parameter ΔV mentioned above)... BE (The same definition applies) depends on the voltage difference between the node voltage V_P of node P during the reset period RP1 and the scan period SP1. Therefore, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively reduced, thus effectively reducing the impact of output loss.

[0112] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. Due to the influence of the storage capacitor Cs, the node voltage V_P of node P also rises only to a limited extent. Furthermore, during the reset period RP2 of sensing frame F2, since transistor M1 is turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be recharged to the data voltage Vdata1, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the output loss of sensing pixel 611 operating in the unilluminated state can be effectively improved. In addition, the voltage changes of node voltage V_BE at node BE and node voltage V_P at node P from time t9 to time t13 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0113] Figure 8B This illustrates a state of illumination according to another embodiment of the present disclosure. Figure 6 Timing diagram of the sensor pixel operation. (Reference) Figure 1A , Figure 3 as well as Figure 8B The following examples will be based on a state of illumination. Figure 6 One sensing pixel 611 is used as another example. In embodiments of this disclosure, the timing of the reset signal RS and the scan signal SS is... Figure 2CThe above embodiments are the same, so they will not be repeated here. Specifically, during the reset cycle RP1 of sensing frame F1, since transistors M1 and M3 are turned on during the period from time t0 to time t1, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the reset voltage Vdata1 (unilluminated state). Then, during the period between time t1 and time t4 (including the exposure cycle EP1 between time t2 and time t3), transistors M1 and M3 are turned off, and nodes BE and P are in a floating state. Since sensing pixel 311 is in an illuminated state, photosensitive unit PD can generate photocurrent reaching node BE, causing the node voltage V_BE to decrease. Correspondingly, since the node voltage V_P of node P depends on the node voltage V_BE of node BE, the node voltage V_P of node P also decreases. According to some embodiments, in the embodiments of this disclosure, the voltage difference of node voltage V_P of node P during the time period from time t1 to time t4 is mainly affected by the capacitive coupling effect of the voltage difference of node voltage V_BE of node BE during the time period from time t1 to time t4, and is not affected by the leakage current from the first terminal to the second terminal of transistor M2.

[0114] During the scan period SP1 of sensing frame F1, since transistor M3 is turned on and transistor M1 is turned off from time t4 to time t5, transistor M2 operates as a source follower and outputs the node voltage V_P of node P, which can be charged to the data voltage Vdata2 (illumination state). Therefore, the readout circuit 140 can read the sensing result (data) based on the data voltage Vdata2, where the sensing result corresponds to the voltage change of the node voltage V_P of node P at time t4. Furthermore, with... Figure 8A Similar to the unilluminated state of the above embodiments, the voltage difference between the node voltage V_BE of node BE during the reset period RP1 and the scan period SP1 can be effectively suppressed. The voltage difference is caused by the capacitive coupling effect of the node voltage V_P of node P.

[0115] Next, during the period between time t5 and time t8 (including the frame gap period FG1 between time t6 and time t7), transistors M1 and M3 are turned off, and nodes BE and P are again in a floating state. However, leakage current may exist from the first terminal to the second terminal of transistor M2, causing the node voltage V_P of node P to rise during the period between time t5 and time t8. Due to the influence of the storage capacitor Cs, the node voltage V_P of node P also rises only to a limited extent. Furthermore, during the reset period RP2 of sensing frame F2, since transistors M1 and M3 are turned on during the period between time t8 and time t9, the node voltage V_BE of node BE can be reset to the reset voltage Vrst, and the node voltage V_P of node P can be charged to the data voltage Vdata1, thus effectively suppressing the effect of capacitive coupling between nodes BE and P. Therefore, the sensing image output loss during operation under illumination can be effectively improved. In addition, the voltage changes of node voltage V_BE of node BE and node voltage V_P of node P from time t9 to time t13 of time element 611 are similar to the description above regarding time t1 to time t5, so they will not be repeated here.

[0116] Figure 9 A schematic diagram of a sensing pixel according to a fourth embodiment of the present disclosure is shown. (See reference...) Figure 9 , Figure 1A The circuit architecture of each of the sensing pixels 111_1 to 111_M can be compared with Figure 9 The sensing pixel 911 has the same circuit architecture. The sensing pixel 911 includes at least three transistors M1 to M3, a photosensitive unit PD, and a clamping circuit CC. The clamping circuit CC may include a clamping diode CD and a storage capacitor Cs. In embodiments of this disclosure, the sensing pixel 911 may be a 3T architecture of an active pixel sensor, but this disclosure is not limited thereto. In embodiments of this disclosure, the first terminal of transistor M1 is coupled to a reset voltage Vrst, and the second terminal of transistor M1 is coupled to the first terminal of the photosensitive unit PD. The control terminal of transistor M1 is coupled to a reset signal line 921, wherein the reset signal line 921 may be... Figure 1A One of the reset signal lines 121_1 to 121_N. The second terminal of the photosensitive unit PD is coupled to ground voltage. The control terminal of transistor M2 is coupled to the first terminal of the photosensitive unit PD, and the first terminal of transistor M2 is coupled to the power supply voltage (VDD), but this disclosure is not limited thereto. In one embodiment of this disclosure, the first terminal of transistor M2 may be coupled to the power supply voltage. The first terminal of transistor M3 is coupled to the second terminal of transistor M2, and the control terminal of transistor M3 is coupled to scan signal line 931, wherein scan signal line 931 may be... Figure 1AOne of the scan signal lines 131_1 to 131_N. The second terminal of transistor M3 is coupled to output signal line 941, wherein output signal line 941 can be... Figure 1A One of the output signal lines 141_1 to 141_P. The first terminal of the clamping diode CD is coupled to the reset voltage Vrst. The second terminal of the clamping diode CD is coupled to the second terminal of transistor M2 and the first terminal of transistor M3. The first terminal of the storage capacitor Cs is coupled to the second terminal of transistor M2 and the first terminal of transistor M3. The second terminal of the storage capacitor Cs is coupled to ground.

[0117] According to some embodiments, the timing of the reset signal and scan signal of the sensing pixel 911 can be adapted to... Figure 2B or Figure 4A The above embodiments, etc. Therefore, it is possible to obtain... Figures 1A to 8B The description of the embodiments provides sufficient teaching and suggestions regarding the implementation methods and technical effects of the sensing pixel 911 in the embodiments, and its details are not repeated.

[0118] In summary, in some embodiments, the electronic device and control method of this disclosure can simultaneously turn on the first transistor (reset transistor) and the third transistor (selection transistor) during the reset cycle of the sensing pixel. In some embodiments, a clamping circuit is disposed at the output node (node ​​P) of the sensing pixel. Therefore, in some embodiments, the leakage current or capacitive coupling effect of the transistor can have a smaller impact, and the voltage at the output node can be more stable, thus improving the output loss of the sensing pixel.

[0119] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A control method for an electronic device, the electronic device comprising sensing pixels, characterized in that, The sensing pixel includes a photosensitive unit, a first transistor, a second transistor, a third transistor, and a clamping circuit. The first transistor and the second transistor are coupled to the photosensitive unit, the third transistor is coupled to the second transistor, and the clamping circuit is coupled to the second transistor. The control method includes: During the reset cycle, a reset signal is provided to the first transistor of the sensing pixel; and During the reset cycle, a scan signal is provided to the third transistor of the sensing pixel. The reset signal waveform of the reset signal and the first scan signal waveform of the scan signal at least partially overlap. The clamping circuit includes at least one of a clamping diode and a storage capacitor, wherein the clamping diode is coupled between the reset voltage and the second transistor.

2. The control method for an electronic device according to claim 1, characterized in that, The falling edge of the reset signal waveform occurs earlier than the falling edge of the first scan signal waveform of the scan signal.

3. The control method for an electronic device according to claim 1, characterized in that, The waveform width of the reset signal is less than the waveform width of the first scan signal waveform of the scan signal.

4. The control method for an electronic device according to claim 1, characterized in that, Also includes: During a sensing frame, the scanning signal is provided to the sensing pixel, wherein the scanning signal includes a second scanning signal waveform that does not overlap with the first scanning signal waveform.

5. The control method for an electronic device according to claim 4, characterized in that, Also includes: During the scan cycle, the sensing signal is read out from the third transistor.

6. An electronic device, characterized in that, include: Sensing pixels, including: Photosensitive unit; A first transistor is coupled to the photosensitive unit and is used to receive a reset signal; The second transistor is coupled to the photosensitive unit; The third transistor is coupled to the second transistor; and A clamping circuit, coupled to the second transistor, the clamping circuit including at least one of a clamping diode and a storage capacitor, the clamping diode being coupled between a reset voltage and the second transistor.

7. The electronic device according to claim 6, characterized in that, The storage capacitor is coupled between the second transistor and the ground voltage.

8. The electronic device according to claim 6, characterized in that, During the reset cycle, the reset signal waveform of the reset signal and the first scan signal waveform of the scan signal received by the third transistor at least partially overlap.

9. The electronic device according to claim 6, characterized in that, The falling edge of the reset signal waveform occurs earlier than the falling edge of the first scan signal waveform received by the third transistor.

10. The electronic device according to claim 9, characterized in that, The waveform width of the reset signal is less than the waveform width of the first scan signal waveform of the scan signal.

11. The electronic device according to claim 6, characterized in that, The scan signal received by the third transistor includes a first scan signal waveform and a second scan signal waveform, and the first scan signal waveform and the second scan signal waveform do not overlap during the sensing frame.

12. The electronic device according to claim 8, characterized in that, Including: Another sensing pixel; as well as A reset circuit, coupled to the sensing pixel and the other sensing pixel, is configured to provide the reset signal to the sensing pixel and another reset signal to the other sensing pixel. During the reset cycle, the reset signal waveform of the reset signal and the other reset signal waveform of the other reset signal do not overlap.

13. The electronic device according to claim 6, characterized in that, The control terminal of the second transistor is coupled to the photosensitive unit, and the first terminal of the second transistor is coupled to the power supply voltage.

14. The electronic device according to claim 6, characterized in that, The storage capacitor is coupled between the second transistor and the ground voltage.

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