Semiconductor device and process for forming the semiconductor device

Abstract

A field-effect transistor (FET) type semiconductor device, primarily made of nitride semiconductor material, is disclosed. The FET includes a nitride semiconductor stack comprising: a main active region and an auxiliary active region, and a passive region surrounding the active regions; a source electrode, a drain electrode, and a gate electrode; an insulating film covering the electrodes and the semiconductor stack; and a field plate on the insulating film. The FET of this invention is characterized in that the field plate is electrically contacted with the auxiliary active region through an opening in the insulating film.

Description

[0001] This application is a divisional application of Chinese patent application No. 2018111385932, filed on September 28, 2018, entitled "Semiconductor Device and Process for Forming the Semiconductor Device". Technical Field

[0002] The present invention relates to a field-effect transistor (FET) type semiconductor device and the process for forming the semiconductor device. Background Technology

[0003] Japanese Patent Application Publication No. JP-2017-107942A discloses a semiconductor device, specifically a field-effect transistor (FET) with a field plate electrically connected to a source electrode.

[0004] FETs, primarily made of nitride semiconductor materials, typically feature a field plate that partially overlaps with the gate electrode. An insulating film is inserted between the field plate and the gate electrode to weaken the induced electric field at the edge of the gate electrode. The field plate also suppresses the reduction in leakage current due to the so-called current collapse inherent in nitride semiconductor devices. Furthermore, the field plate can suppress coupling between the drain and gate electrodes.

[0005] Typically, a field plate is formed by metal evaporation and a subsequent stripping process. Specifically, the field plate is typically formed by the following steps: (a) first forming a mask with openings corresponding to the field plate on an insulating film covering the gate electrode; (b) evaporating the metal for the field plate; and (c) removing residual metal deposited on the mask by a stripping process. Thus, the field plate exists independently on the insulating film after its formation and is electrically isolated from any conductive material. Therefore, charges induced during subsequent processes can easily accumulate within the field plate. Excessive charge accumulation in the field plate can sometimes lead to electrostatic discharge, causing a short circuit between the field plate and the gate electrode. For example, when the stripping process used to remove residual metal left on the mask utilizes a solvent jet spray on the mask, the solvent sprayed onto the field plate causes friction and charge accumulation in the field plate. Excessive charge accumulation can sometimes lead to arc discharge against the gate electrode, causing a short circuit thereto. When the field plate is electrically connected to the source electrode, a short circuit between the gate electrode and the field plate means a short circuit between the gate electrode and the source electrode, rendering the FET unusable. Summary of the Invention

[0006] One aspect of the present invention relates to a field-effect transistor (FET) type semiconductor device, which is primarily made of a nitride semiconductor material. The semiconductor device includes: a nitride semiconductor stack; source, drain, and gate electrodes, all disposed on the nitride semiconductor stack in a main active region; an insulating film covering the electrodes and the nitride semiconductor stack exposed between the electrodes; and a field plate disposed on the insulating film. The nitride semiconductor stack has a main active region, an auxiliary active region, and a passive region surrounding the main and auxiliary active regions. An opening is provided in the auxiliary region of the insulating film. The semiconductor device of the present invention is characterized in that the field plate is in electrical contact with the auxiliary active region through the opening provided in the insulating film.

[0007] Another aspect of the present invention relates to a process for forming a field-effect transistor made primarily of a nitride semiconductor material. The process includes the steps of: (a) forming a semiconductor stack; (b) forming a main active region, an auxiliary active region, and a passive region in the semiconductor stack; (c) forming a drain electrode, a source electrode, and a gate electrode on the semiconductor stack in the main active region; (d) depositing an insulating film on the source electrode, drain electrode, and gate electrode, and on the semiconductor stack exposed between the electrodes; (e) forming an opening in the insulating film in the auxiliary active region; and forming a field plate on the insulating film. The process of the present invention is characterized in that the field plate is formed to overlap with the gate electrode and to contact the auxiliary active region through the opening in the insulating film. Attached Figure Description

[0008] The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of preferred embodiments of the invention with reference to the accompanying drawings, in which:

[0009] Figure 1 This is a plan view illustrating a transistor according to an embodiment of the present invention;

[0010] Figure 2 It is along Figure 1 The cross-sectional view of the transistor taken by line II-II shown;

[0011] Figure 3 The auxiliary active region located outside the main active region has been enlarged;

[0012] Figure 4 It is along Figure 3 The cross-sectional view of the auxiliary active region intercepted by line IV-IV is shown in the figure.

[0013] Figures 5A to 5C yes Figure 2 The diagram shows cross-sectional views of the transistor at various steps in the process of forming the transistor.

[0014] Figure 6A and Figure 6B yes Figure 2 The transistor shown is in Figure 5C Cross-sectional views at each step following the steps shown;

[0015] Figure 7A and Figure 7B yes Figure 2 The transistor shown is in Figure 6B Cross-sectional views at each step following the steps shown;

[0016] Figures 8A to 8D It is an auxiliary active region in formation Figure 2 Cross-sectional views of the transistor at various stages shown; and

[0017] Figure 9 This shows the failure ratio of a transistor relative to the area of ​​the auxiliary active region as a percentage of the total area of ​​the field plate. Detailed Implementation

[0018] Embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention is not limited to the described embodiments and has the scope defined in the claims, as well as all variations and modifications equivalent to the claims. In the description of the drawings, identical or similar numbers or symbols refer to identical or similar elements and are not repeated.

[0019] Figure 1 This is a plan view illustrating transistor 1A according to an embodiment of the present invention; and Figure 2 It is along Figure 1 The cross-sectional view of transistor 1A taken by line II-II is shown.

[0020] The transistor 1A of this embodiment comprises a substrate 11, a semiconductor stack 18 on the substrate 11, and a drain electrode 31, a source electrode 32, and a gate electrode 33, all disposed on the semiconductor stack 18. The semiconductor stack 18 includes a nitride semiconductor layer. The transistor 1A of this embodiment is of the so-called High Electron Mobility Transistor (HEMT) type. That is, the semiconductor stack 18 includes a channel layer 12, a barrier layer 13, and a capping layer 14, wherein a two-dimensional electron gas (2DEG) is induced in the channel layer 12 at the junction between the channel layer 12 and the barrier layer 13. The 2DEG serves as a channel for transporting charge carriers (i.e., electrons) therein. The HEMT 1A may also include an insulating film 20 and a field plate 34 on the insulating film 20, wherein the insulating film 20 covers the electrodes 31 to 33 and the semiconductor stack 18, and the field plate 34 is disposed on the insulating film 20 to partially overlap with the gate electrode 33. The insulating film 20 in this embodiment includes a first insulating film 21 on the semiconductor laminate 18 and a second insulating film 22 on the first insulating film 21.

[0021] The substrate 11 on which the nitride semiconductor layer is epitaxially grown can be made of silicon (Si), silicon carbide (SiC), sapphire (Al2O3), diamond (C), etc., wherein in this embodiment, a substrate 11 made of SiC is provided. The substrate 11 can have a thickness of, for example, 500 μm. The channel layer 12 epitaxially grown on the substrate 11 can be made of gallium nitride (GaN) and has a channel at the junction with the barrier layer 13 as described above. The channel layer 12 can have a thickness of, for example, 500 nm.

[0022] The barrier layer 13 epitaxially grown on the channel layer 12 can be made of a nitride semiconductor material having a greater electron affinity than the channel layer 12. The barrier layer 13 can be made of aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and / or indium aluminum gallium nitride (InAlGaN). The barrier layer can have a thickness of, for example, 20 nm. Although the barrier layer 13 is set as an undoped layer in this embodiment, it can be doped with an n-type dopant and exhibit n-type conductivity. The capping layer 14 epitaxially grown on the barrier layer 13 can be made of GaN and has a thickness of, for example, 5 nm. The capping layer 14 can also exhibit n-type conductivity.

[0023] Refer again Figure 1 The semiconductor stack 18 includes a main active region A1 and an inactive region B1 outside the main active region A1. The main active region A1 can operate as a transistor, and can be controlled by introducing ions (typically argon ions). + The passive region B1 formed by injecting into the main active region A1 can electrically isolate transistor 1A from those transistors formed nearby. In this embodiment, the main active region A1 is accompanied by an auxiliary active region A2 in the passive region B1. The passive region B1 can electrically isolate the main active region A1 from the auxiliary active region A2, which is arranged side by side with the current active region A1.

[0024] Drain electrodes 31 and source electrodes 32 are formed in the main active region A1, wherein, in this embodiment, two drain electrodes 31 and one source electrode 32 are disposed in the main active region A1. The two drain electrodes 31 and the source electrode 32 are arranged on the semiconductor stack 18 in such a sequence that the two drain electrodes 31 sandwich the source electrode 32 between them. The drain electrodes 31 and the source electrode 32 (which are ohmic electrode types) can be formed by a stacked metal that allows tantalum (Ta) and aluminum (Al). A stacked metal including additional tantalum (Ta) on Al can be used as the original material for the ohmic electrodes 31 and 32. The two drain electrodes 31 are interconnected via drain electrodes (…). Figure 1 (not shown in the image) but electrically connected to each other.

[0025] Reference Figure 2In this embodiment, the drain electrode 31 and source electrode 32 are in contact with the capping layer 14; however, those electrodes 31 and 32 can be formed on the barrier layer 13, or can be in contact with or around the interface between the channel layer 12 and the barrier layer 13 by forming recesses in the capping layer 14 and the barrier layer 13. Figure 2 In the illustrated embodiment, the drain electrode 31 and the source electrode 32 are covered by a first insulating film 21 and a second insulating film 22. In an alternative, the drain electrode 31 and the source electrode 32 are covered only by the second insulating film 22. That is, the ohmic electrodes 31 and 32 can contact the semiconductor stack 18 through various openings formed in the first insulating film 21. The ohmic electrodes 31 and 32 may have a thickness of approximately 300 nm.

[0026] Refer again Figure 1 A gate electrode 33 is disposed in the main active region A1. In this embodiment, two gate electrodes 33 are arranged in the main active region A1, one of which is disposed between one of the drain electrodes 31 and the source electrode 32, and the other gate electrode 33 is disposed between the other of the drain electrodes 31 and the source electrode 32. The gate electrode 33 has a multilayer metal of nickel (Ni) and gold (Au) with a total thickness of, for example, 350 nm. The Ni contacts the semiconductor stack 18 through an opening in the first insulating film 21 to form a Schottky contact. A portion of the gate electrode 33 extends on the first insulating film 21 around the opening in the first insulating film 21. The gate electrode 33 is completely covered by the second insulating film 22. The two gate electrodes 33 in the main active region A1 are connected to each other by a gate interconnect 36 disposed in the passive region B1.

[0027] A first insulating film 21 covers the semiconductor stack 18 exposed between electrodes 31 and 33. As described above, the first insulating film 21 has openings that expose the semiconductor stack 18 and fill the gate electrode 33 therein. The first insulating film 21 can be made of an inorganic material containing silicon (Si) (typically silicon nitride (SiN), silicon oxide (SiO2), etc.) and has a thickness of, for example, 60 nm. The first insulating film 21 made of SiN can be formed using low-pressure chemical vapor deposition (LPCVD) technology, which is popular in the field of semiconductor manufacturing processes.

[0028] A second insulating film 22 in contact with the first insulating film 21 can cover the first insulating film 21 and the electrodes 31 to 33. Specifically, the second insulating film 22 covers the top 33a and side 33b of the gate electrode 33 in the portion extending on the first insulating film 21. Therefore, the second insulating film 22 forms a step 22a of the cross-section of the reaction gate electrode 33 and a planar portion 22b extending from the step 22a towards the drain electrode 31. The second insulating film 22 can also be made of an inorganic material containing Si, typically SiN with a thickness of 100 to 500 nm, wherein this embodiment provides a second insulating film 22 with a thickness of 400 nm. When the first insulating film 21 is formed by LPCVD technology, the second insulating film 22 can preferably be formed by plasma-assisted chemical vapor deposition (p-CVD) technology to chemically separate the second insulating film 22 from the first insulating film 21.

[0029] The field plate 34 has a laminated metal of Ni and Au, or Ti and Au, wherein Ni or Ti is in contact with the second insulating film 22. This embodiment provides two field plates 34 corresponding to the two gate electrodes 33. One field plate 34 is disposed between one of the gate electrodes 33 and one of the drain electrodes 31 (the drain electrode partially overlaps with the gate electrode 33 on the side closest to the drain electrode 31); while the other field plate 34 is disposed between the other of the gate electrodes 33 and the other of the drain electrodes 31 (which partially overlaps with the other of the gate electrodes 33).

[0030] Reference Figure 2 The field plate 34 extends from step 22a towards the planar portion 22b between the drain electrode 31 and the gate electrode 33. The field plate 34, which can be electrically connected to the source electrode 32, can reduce the coupling between the gate electrode 33 and the drain electrode 31, and weaken the field strength at the edge of the gate electrode 33. The field plate 34 can have a total thickness of 100 to 600 nm. Figure 2 The example shown has a thickness of 300 nm.

[0031] In this embodiment, the two field plates 34 are connected to the source electrode 34 via a source interconnect, indicating that the field plates 34 have the same potential as the source electrode 32. In an alternative, the field plates 34 may be electrically floating, that is, the field plates 34 may not be electrically connected to any other location.

[0032] Figure 3 The auxiliary active region A2 outside the main active region A1 was enlarged, and Figure 4 It is along Figure 3The diagram shows a cross-sectional view of the auxiliary active region A2 taken along line IV-IV. The auxiliary active region A2 is arranged side-by-side with respect to the source electrode 32, with the passive region B1 located between them; that is, the two active regions A1 and A2 are arranged side-by-side with the passive region B1 located between them. In an alternative, the two active regions A1 and A2 may be continuous without the passive region B1 located between them.

[0033] The auxiliary active region A2 has a rectangular planar shape, with a length of, for example, 30 μm along the main active region A1 and a width of, for example, 11 μm along the direction connecting the active regions A1 and A2. The auxiliary active region A2 has an area smaller than that of the main active region A1, which can be adjusted to take into account the total area of ​​the field plates 34, wherein the total area includes the area of ​​the two field plates 34 and the area of ​​the interconnect 37, the interconnect 37 including a narrow portion 37b connecting the field plates 34 to the auxiliary active region A2 and a wide portion 37a overlapping the auxiliary active region A2, which may be referred to as a pad. The auxiliary active region A2 preferably has an area ratio of 0.5 to 2.0 relative to the total area of ​​the field plates 34. The auxiliary active region A2 preferably exhibits an area ratio of less than 10. -2 Resistivity in Ωcm.

[0034] Similarly, as Figure 4 As shown, the insulating film 20 (specifically, the first insulating film 21 and the second insulating film 22) has an opening 20a that exposes the top of the semiconductor stack 18. The opening 20a overlaps with the pads 37a in the interconnect 37, that is, the opening 20a completely overlaps with the auxiliary active region A2. The opening 20a in the insulating film 20 can expose the capping layer 14, the barrier layer 13, and / or the channel layer 12. The opening 20a can be a rectangular planar shape and is disposed within the auxiliary active region A2.

[0035] The two field plates 34 are connected to each other by interconnects 37, which may be made of substantially the same metal as the field plates 34. The interconnects 37, extending from the passive region B1 to the auxiliary active region A2, are disposed on an insulating film 20 in the passive region B1, and fall within an opening 20a in the auxiliary active region A2, where they contact the semiconductor stack 18; that is, the interconnects 37 may contact the capping layer 14, the barrier layer 13, and the channel layer 12. More specifically, Ni, Ti, or Au in the interconnects 37 may contact the semiconductor stack 18. The interconnects 37 may have a thickness substantially the same as the thickness of the field plates 34.

[0036] Interconnect 37 can contact semiconductor stack 18 at pad 37a, i.e., opening 20a in insulating film 20 substantially overlaps with pad 37a in interconnect 37. Pad 37a has a longitudinal length of, for example, 5 μm along the main active region A1. The area of ​​contact between interconnect 37 and semiconductor stack 18, i.e., the area of ​​opening 20a in insulating film 20, can be adjusted by taking into account the total area of ​​field plate (i.e., the area of ​​field plate 34 excluding the area of ​​interconnect 37). Specifically, the area ratio of opening 20a to the total area of ​​field plate 34 and interconnect 37 is preferably set to be greater than 0.6.

[0037] Next, we will refer to Figures 5A to 7B The process of forming transistor 1A according to this embodiment is described, wherein the figures are cross-sectional views of transistor 1A at various steps of the process of forming transistor 1A. The process of forming auxiliary active region A2 will be described later.

[0038] First, such as Figure 5A As shown, this process forms a semiconductor stack 18 by sequentially growing a channel layer 12, a barrier layer 13, and a capping layer 14 on a substrate 11. Epitaxial growth can be performed using a technique known as metal-organic chemical vapor deposition (MOCVD), popular in the field of semiconductor processing (especially processes for forming compound semiconductor devices). Subsequently, a mask covering the regions to be formed as the main active region A1 and the auxiliary active region A2, respectively, can be used to deposit ions (e.g., argon ions). + The passive region B1 is formed by subsequent steps of injecting semiconductor stack 18 into the region exposed by the mask. Thus, the passive region B1 can be formed.

[0039] After that, as Figure 5B As shown, a drain electrode 31 and a source electrode 32 are formed on the capping layer 14. Specifically, another mask with openings is formed in the regions corresponding to the drain electrode 31 and the source electrode 32; subsequently, titanium (Ti) and aluminum (Al) metals are stacked within the openings; finally, the stacked metals are fused at a temperature higher than 500°C, thereby forming ohmic electrodes for the drain electrode 31 and the source electrode 32 on the capping layer 14. Subsequently, as... Figure 5C As shown, a first insulating film 21 covers the drain electrode 31, the source electrode 32, and the semiconductor stack 18 exposed between the drain electrode 31 and the source electrode 32. The first insulating film can be formed by chemical vapor deposition (CVD) technology (specifically, plasma-enhanced CVD (p-CVD) technology or low-pressure chemical vapor deposition (LPCVD) technology).

[0040] In one alternative, the drain electrode 31 and the source electrode 32 can be formed in the following order: first, a first insulating film 21 is deposited; openings are formed in the first insulating film 21 at positions corresponding to the drain electrode 31 and the source electrode 32; metal is deposited; and finally, the deposited metal is fused together.

[0041] Subsequently, a sequence of photolithography, etching of the first insulating film 21, and metal evaporation can form the gate electrode 33. Specifically, photolithography forms a patterned photoresist with openings corresponding to the gate electrode 33. Then, reactive ion etching (RIE) can form openings in the first insulating film 21, and metal evaporation with a lift-off technique can form the gate electrode 33. Subsequently, a second insulating film 22 is deposited on the drain electrode 31, source electrode 32, gate electrode 33, and the first insulating film 21 using CVD technology, as shown below. Figure 6A As shown.

[0042] After that, as Figure 6B As shown, two patterned masks M1 and M2 are fabricated on the second insulating film 22, wherein the first mask M1 is formed to be thicker than the second mask M2. Specifically, the first mask M1 has a thickness at least greater than the total thickness of the gate electrode 33 and the field plate 34. When masks M1 and M2 are of a positive photoresist type (i.e., the irradiated portion becomes soluble in the developer), the second mask M2 is selected to have a lower photosensitivity than the first mask M1. Figure 6B As shown, masks M1 and M2 have respective openings M1a and M2a, wherein the first opening M1a is wider than the second opening M2a due to the difference in photosensitivity of the respective materials of masks M1 and M2. Therefore, the second mask M2 can form a pendant relative to the first mask M1. The second opening M2a partially overlaps with the gate electrode 33 (specifically, on one side of the drain electrode 31). Thus, the second opening M2a is formed above the second insulating film 22 in a position adjacent to its step 22a and on top of the gate electrode 33.

[0043] After that, as Figure 7A As shown, the metal for the field plate 34 is deposited, for example, by vacuum evaporation. The metal can accumulate not only on the insulating film 22 but also on the second mask M2. The field plate 34 is left on the second insulating film 22 after the masks NM1 and M2, with residual metal 35 thereon, are removed by a stripping technique. The stripping technique can be accompanied by a spray jet of a solvent such as isopropanol (IPA) at a pressure of 5 to 50 MPa.

[0044] Next, we will refer to Figures 8A to 8D The process for forming the arrangement around the auxiliary active region A2 is described in detail, and these figures are cross-sectional views of the auxiliary active region A2 at each step. First, as... Figure 8AAs shown, a photoresist mask M3 is patterned to cover the region that will be converted into an auxiliary active region A2. Ion implantation performed after mask formation can deliver ions (e.g., positive argon ions (Ar)). + The injection is applied to the region exposed from mask M3, which forms a passive region B1 surrounding the main active region A1 and the auxiliary active region A2. Therefore, two active regions A1 and A2 can be formed in one step.

[0045] After that, as Figure 8B As shown, an insulating film 20, including insulating films 21 and 22, is formed on the semiconductor stack 18. The first insulating film 21 can be... Figure 5C The second insulating film 22 is formed at the step shown, and can be formed at the step shown. Figure 6A The gate electrode 33 is formed at the step shown. That is, the gate electrode 33 is formed after the formation of the first insulating film 21 but before the formation of the second insulating film 22.

[0046] After that, as Figure 8C As shown, another patterned mask M4 is formed on the insulating film 20, wherein the mask M4 is provided with an opening M4a corresponding to the auxiliary active region A2, wherein the mask M4 positions the opening M4a outside the source electrode 32, specifically, outside the side edge of the source electrode 32. That is, the opening M4a has a longitudinal edge extending along the side edge of the source electrode 32, with gaps therebetween. The insulating film 20 exposed within the opening M4a is removed, for example, by reactive ion etching (RIE), to form the opening M4a therein. Furthermore, the opening M4a is located inside the auxiliary active region A2; that is, the auxiliary active region A2 completely covers the opening M4a in the mask M4. Figure 6A After the deposition of the second insulating film 22 at the step shown, but... Figure 6B Before forming the field plate at the step shown, an opening 20a is formed in the insulating film 20.

[0047] Subsequently, a narrow portion 37b connecting the pad 37a, which completely covers the opening 20a in the insulating film 20, to the field plate 34 can be formed simultaneously with the formation of the field plate 34. That is, the first mask M1 and the second mask M2 have patterns corresponding to the pad 37a and the interconnect 37b in addition to the pattern for the field plate 34. The deposition of metal for the field plate 34 and the removal of residual metal 35 deposited on the mask M2 by a stripping technique can form the pad 37a and the narrow portion 37b simultaneously with the formation of the field plate 34. The field plate 34 can contact the auxiliary active region A2 just after the metal deposition; therefore, even when the stripping technique uses solvent spraying, the charge induced by the friction of the solvent relative to the field plate 34 can be easily discharged into the auxiliary active region A2. When the auxiliary active region A2 is continuous with the main active region A1, the induced charge can also be easily discharged into the entire active region. After the field plate 34 is formed, another insulating film made of, for example, silicon nitride (SiN) can be applied to the narrow portion 37b and the pad 37a, which can enhance the reliability of resisting moisture or water intrusion into the main active region A1.

[0048] Finally, openings are formed in the insulating film 20 in the corresponding portions above the drain electrode 31 and the source electrode 32, and interconnects made mainly of gold (Au) are formed (each connected to the drain electrode 31 and the source electrode 32) to connect the source electrode 32 to the field plate 34, thus completing the process of forming the transistor 1A of this embodiment.

[0049] The advantages of transistor 1A and the process for forming transistor 1A will be described. This process forms the field plate 34 by a stripping technique including solvent spraying. That is, residual metal 35 accumulated on masks M1 and M2 is removed by dissolving masks M1 and M2 with a solvent. In conventional transistor arrangements with field plates, the field plates are electrically isolated from the insulating film 20 immediately after their formation. Therefore, charges induced by friction can easily accumulate in the field plate 34. For example, the solvent spraying used to dissolve the photoresist in masks M1 and M2 causes friction relative to the field plate 34 and charges the field plate 34. Excessive charge accumulation in the field plate 34 can sometimes cause arcing between the field plate 34 and the gate electrode 33, resulting not only in a short circuit between the field plate 34 and the gate electrode 33, but also in a short circuit between the source electrode 32 and the gate electrode 33. Therefore, transistor 1A no longer behaves as a signal amplification device.

[0050] A thicker insulating film 22 can suppress arcing caused by excessive charge accumulation in the field plate 34. However, a thicker insulating film 22 will reduce the functionality of the field plate 34, i.e., the electric field strength at the edge of the gate electrode 33 will decrease. Therefore, the insulating film 22 must have a maximum thickness limit.

[0051] The process according to this embodiment allows the field plate 34 to contact the semiconductor stack 18 during its formation, indicating that even if the formation of the field plate results in excess charge therein, the charge can be easily discharged into the semiconductor stack 18. Not only the field plate 34 itself, but also the auxiliary active region A2 in the semiconductor stack 18 can accumulate charge, which greatly reduces the threshold for arcing between the field plate 34 and the gate electrode 33.

[0052] Figure 9 The failure ratio is shown relative to the area ratio (S). A2 / S FP The behavior of ), specifically, the area ratio is the area of ​​the auxiliary active region A2 relative to the area of ​​the entire field plate 34 including the narrow portion 37b and the pad 37a. (Refer to...) Figure 9 The failure ratio increases with the area ratio (S) A2 / S FP It decreases as the area ratio (S) increases, especially when the area ratio (S) increases. A2 / S FP When the area ratio exceeds 0.6, the failure ratio becomes less than 0.5%, which is the design limit for transistor 1A. Furthermore, in the case where the field plate 34 is not in contact with the auxiliary active region A2 (i.e., when the area ratio is zero), the failure ratio is approximately 1 / 10. A larger area ratio (S...) A2 / S FP This indicates that the auxiliary active region A2 has a sufficiently large area compared to the total area of ​​field plates 34, 37a, and 37b, which allows it to accumulate more charge that will be induced in field plate 34.

[0053] Field plate 34 can be formed by removing masks M1 and M2 through a solvent spraying process. The spraying induces charges through friction between the solvent and field plate 34, but these charges can be easily discharged into the auxiliary active region A2. Therefore, excessive charge accumulation within field plate 34 can be prevented. The solvent can be sprayed at pressures ranging from 5 to 50 MPa. Pressures above 5 MPa can completely remove masks M1 and M2; while pressures below 50 MPa effectively prevent the field plate 34 and interconnect 37 from peeling off.

[0054] The second insulating film 22 covering the gate electrode 33 can have a thickness of 100 to 500 nm to effectively exhibit the function of the field plate 34, even if the field strength weakens at the edge of the gate electrode 33. Because the transistor 1A in this embodiment contacts the field plate 34 with the auxiliary active region A2, the insulating film 22 can be thinner than 500 nm. Furthermore, the field plate 34 can be formed on the thinned insulating film 22; therefore, coupling between the drain electrode 31 and the gate electrode 33 can be effectively suppressed. An insulating film 22 thicker than 100 nm can reduce the gate leakage current through the insulating film 22.

[0055] The auxiliary active region A2 can be isolated from the main active region A1, that is, the passive region B1 can exist between the two active regions A1 and A2. This can reduce the drain current flowing from the drain electrode 31 to the source electrode 32 through the auxiliary active region A2 and the passive region B2 outside the gate electrode 33.

[0056] In the foregoing detailed description, transistors according to the invention and the process of forming transistors have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and variations can be made thereto without departing from the broad spirit and scope of the invention. For example, the embodiments focus on high electron mobility transistor (HEMT) type transistors, but the invention can be applied to other types of transistors implementing field plates. Additionally, an auxiliary active region A2 is disposed at a position parallel to the source electrode 32 along its longitudinal direction. However, the auxiliary active region A2 is not limited to this position. The auxiliary active region A2 can be formed anywhere outside the main active region A1. Furthermore, the embodiments provide auxiliary active regions A2 for a plurality of field plates 34, i.e., two field plates 34 contact one auxiliary active region A2. However, the field plates 34 may each have their own auxiliary active region A2. Therefore, this specification and the accompanying drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A semiconductor device of a field effect transistor type mainly made of a nitride semiconductor material, the semiconductor device comprising: a nitride semiconductor layer stack having a main active region, an auxiliary active region, and a passive region surrounding the main active region and the auxiliary active region, the main active region being electrically isolated from the auxiliary active region; a source electrode, a drain electrode, and a gate electrode each provided on the nitride semiconductor layer stack in the main active region; an insulating film covering the source electrode, the drain electrode, and the gate electrode and the nitride semiconductor layer stack exposed between the electrodes, the insulating film providing an opening in the auxiliary active region; and a field plate provided on the insulating film and overlapping the gate electrode, wherein the field plate is in electrical contact with the auxiliary active region through the opening provided in the insulating film.

2. The semiconductor device according to claim 1, wherein the insulating film has a thickness of 100 nm to 500 nm in a portion covering the gate electrode.

3. The semiconductor device according to claim 1, wherein a ratio of an area where the field plate is in contact with the auxiliary active region with respect to a total area of the field plate is greater than 0.

6.

4. The semiconductor device according to claim 1, wherein the main active region is electrically isolated from the auxiliary active region by the passive region.

5. The semiconductor device according to claim 4, wherein the source electrode, drain electrode, and gate electrode extend along respective longitudinal directions, the auxiliary active region existing outside the source electrode along the respective longitudinal directions.

6. The semiconductor device according to claim 1, wherein said auxiliary active region has a resistivity of less than 10 -2 Ωcm.

7. The semiconductor device according to claim 1, wherein a width of a region where the field plate is in contact with the auxiliary active region is greater than a width of the field plate over the gate electrode.

8. The semiconductor device according to claim 1, wherein a length of the field plate over the gate electrode in a longitudinal direction is greater than lengths of the source electrode and the drain electrode in the longitudinal direction.

9. The semiconductor device according to claim 1, wherein the field plate covers at least a portion of the gate electrode in a lateral direction of the field plate.

10. The semiconductor device according to claim 1, wherein a width of the auxiliary active region is greater than a width of the source electrode in a lateral direction.

11. The semiconductor device according to claim 7, wherein the width of the region of the field plate is smaller than the width of the source electrode in a lateral direction.

12. The semiconductor device according to claim 1, wherein a plurality of the field effect transistors each having the field plate connected to each other.

13. The semiconductor device according to claim 12, wherein, each of the field plates is connected in an auxiliary active region.

14. The semiconductor device according to claim 12, wherein the main active region is provided to span over a plurality of the field effect transistors.

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