Method for fabricating semiconductor structures with capacitor landing pads

Abstract

This disclosure provides a method for fabricating a semiconductor structure having multiple capacitor landing pads. The fabrication method includes the following steps: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing an upper surface of the landing pad layer; forming a trench in the landing pad layer to form multiple capacitor landing pads; forming an air gap in one sidewall of the bit line structure; and filling the trench with a first dielectric layer to seal the air gap.

Description

Technical Field

[0001] This disclosure claims priority and benefits to U.S. Official Application No. 17 / 129,063, filed December 21, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor structure with a capacitor landing pad. In particular, it relates to a method for fabricating a semiconductor memory element structure with a capacitor landing pad. Background Technology

[0003] In the semiconductor industry, products are trending towards miniaturization. Memory cell designs are also evolving towards higher integration and density. To achieve higher density and integration, pitch sizes are being designed to be increasingly smaller. However, smaller pitch sizes result in higher aspect ratios. In other words, these memory elements are designed with higher aspect ratios. On the other hand, high aspect ratios can cause structural stability issues during manufacturing, affecting throughput. Therefore, it is necessary to improve the stability of components as aspect ratios increase.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0005] One embodiment of this disclosure provides a method for fabricating a semiconductor structure having multiple capacitor landing pads. The method includes providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing an upper surface of the landing pad layer; forming a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling the trench with a first dielectric layer to seal the air gap.

[0006] In some embodiments, the step of forming the trench in the landing pad layer to form the capacitor landing pad includes: depositing a plurality of mask layers on the landing pad layer; performing forward double patterning on the plurality of mask layers to form a hard mask on the landing pad layer; and etching the landing pad layer according to the hard mask to form the trench.

[0007] In some embodiments, the step of depositing the plurality of masking layers on the landing pad includes: depositing a first carbon layer on the landing pad; and depositing a second dielectric layer on the first carbon layer.

[0008] In some embodiments, the step of depositing the plurality of masking layers on the landing pad includes: forming a second carbon layer on the second dielectric layer; forming a third dielectric layer on the second carbon layer; forming a third carbon layer on the third dielectric layer; and forming a fourth dielectric layer on the third carbon layer.

[0009] In some embodiments, the first carbon layer has a height approximately equal to 90 nm, the second dielectric layer comprises silicon nitride, the third dielectric layer is a silicon-containing dielectric antireflective coating, and the fourth dielectric layer is an oxygen-containing dielectric antireflective coating.

[0010] In some embodiments, the step of performing forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer includes: patterning the fourth dielectric layer and the third dielectric layer; and etching the fourth dielectric layer, the third carbon layer, the third dielectric layer and the second carbon layer to form a plurality of carbon rods in the second carbon layer.

[0011] In some embodiments, the step of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer further includes: depositing an oxide layer to cover the plurality of carbon rods.

[0012] In some embodiments, the oxide layer is deposited using an atomic layer deposition (ALD) technique.

[0013] In some embodiments, the step of performing the forward double patterning on the plurality of masking layers to form the hard mask on the landing pad layer further includes: planarizing an upper surface of the oxide layer, wherein the upper surface of the oxide layer is coplanar with an upper surface of the plurality of carbon rods. The remaining oxide layer forms an upper portion of the hard mask.

[0014] In some embodiments, the step of performing the forward double patterning on the plurality of mask layers to form the hard mask on the landing pad layer further includes: etching the plurality of carbon rods, the second dielectric layer and the first carbon layer according to the remaining oxide layer to form the hard mask.

[0015] In some embodiments, the step of etching the landing pad layer according to the hard mask to form the trench includes: etching a portion of the sidewall of the bit line structure and a portion of a nitride layer of the bit line structure to expose an upper surface of the sidewall of the bit line structure.

[0016] In some embodiments, the step of etching the landing pad layer to form the trench according to the hard mask further includes: etching the landing pad layer to reach an upper surface of the bit line structure; and etching a portion of an adhesive layer of the bit line structure, wherein the adhesive layer comprises titanium nitride.

[0017] In some embodiments, the step of forming the trench in the landing pad layer to form the capacitor landing pad further includes performing an ashing etching to remove the plurality of masking layers.

[0018] In some embodiments, the sidewall of the bitline structure includes an inner dielectric layer, an outer dielectric layer, and an intermediate oxide layer, the intermediate oxide layer being disposed between the inner dielectric layer and the outer dielectric layer. The step of forming the air gap within the sidewall of the bitline structure includes etching the intermediate oxide layer.

[0019] In some embodiments, the intermediate oxide layer is etched using gaseous hydrofluoric acid.

[0020] In some embodiments, the fabrication method further includes: planarizing the first dielectric layer, wherein the first dielectric layer and the capacitor landing pads are coplanar; and depositing a fifth dielectric layer on the first dielectric layer and the capacitor landing pads. The fifth dielectric layer comprises silicon nitride.

[0021] In some embodiments, the trench portion is aligned with the bit line structure.

[0022] In some embodiments, the semiconductor substrate includes a first active region, a second active region, and an insulating region, the insulating region being disposed between the first active region and the second active region. A bit line contact structure is formed to contact the first active region.

[0023] In some embodiments, the fabrication method further includes: forming a landing pad contact point structure to couple the second active region of the semiconductor substrate; and forming a cobalt silicide layer to couple the landing pad contact point structure.

[0024] In some embodiments, each capacitor landing pad has a stepped shape. The width of an upper portion of the capacitor landing pad is greater than the width of a lower portion of the capacitor landing pad.

[0025] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the claims. Attached Figure Description

[0026] A more complete understanding of this disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0027] Figure 1 A schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure is shown.

[0028] Figure 2 Examples of some implementations of this disclosure are shown below. Figure 1 The diagram shows a process flow chart for fabricating the semiconductor structure.

[0029] Figure 3 Examples of some embodiments of this disclosure are shown in, for example Figure 2 The flowchart shown illustrates the multiple steps in the preparation method.

[0030] Figure 4 Examples of some embodiments of this disclosure are shown in, for example Figure 2 The flowchart shown illustrates the multiple steps in the preparation method.

[0031] Figure 5 Examples of some embodiments of this disclosure are shown in, for example Figure 2 The flowchart shown illustrates the multiple steps in the preparation method.

[0032] Figure 6 Examples of some embodiments of this disclosure are shown in, for example Figure 2 The flowchart shown illustrates the multiple steps in the preparation method.

[0033] Figure 7 Examples of some embodiments of this disclosure are shown in, for example Figure 2 The flowchart shown is a step diagram of one of the preparation methods.

[0034] Figure 8 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0035] Figure 9 Examples of some embodiments of this disclosure are shown in, for example Figure 1A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0036] Figure 10 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0037] Figure 11 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0038] Figure 12 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0039] Figure 13 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0040] Figure 14 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0041] Figure 15 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0042] Figure 16 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0043] Figure 17 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0044] Figure 18 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0045] Figure 19 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0046] Figure 20 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0047] Figure 21 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0048] Figure 22 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0049] Figure 23 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0050] Figure 24 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0051] Figure 25 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0052] Figure 26 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0053] Figure 27 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0054] Figure 28 Examples of some embodiments of this disclosure are shown in, for example Figure 1 A schematic diagram of one step in the fabrication method of the semiconductor structure shown.

[0055] Explanation of reference numerals in the attached figures:

[0056] 10: Semiconductor Structure

[0057] 20: Preparation method

[0058] 100: Semiconductor substrate

[0059] 101: Active Zone

[0060] 102: Active Zone

[0061] 103: Active Zone

[0062] 104: Insulation Zone

[0063] 105: Insulation Zone

[0064] 200: Bitline Structure

[0065] 201: Metal layer

[0066] 202: Dielectric layer

[0067] 203: Adhesive layer

[0068] 204: Contact point structure

[0069] 205: Adhesive layer

[0070] 210: Sidewall

[0071] 211: Inner Dielectric Layer

[0072] 212: Outer dielectric layer

[0073] 213: Air gap

[0074] 214: Upper surface

[0075] 216: Intermediate oxide layer

[0076] 300: Capacitor Landing Pad

[0077] 310: Landing cushion layer

[0078] 400: Dielectric layer

[0079] 500: Dielectric layer

[0080] 600: Adhesive layer

[0081] 700: Contact point structure

[0082] C1: Carbon layer

[0083] C2: Carbon layer

[0084] C2R: Carbon rod

[0085] C3: Carbon layer

[0086] D1: Dielectric layer

[0087] D2: Dielectric layer

[0088] D3: Dielectric layer

[0089] HM: Hard Mask

[0090] ML: Masking layer

[0091] OX: Oxide layer

[0092] S201: Steps

[0093] S202: Steps

[0094] S203: Steps

[0095] S204: Steps

[0096] S205: Steps

[0097] S206: Steps

[0098] S207: Steps

[0099] S208: Steps

[0100] S209: Steps

[0101] S210: Steps

[0102] S211: Steps

[0103] S2071: Steps

[0104] S2072: Steps

[0105] S2073: Steps

[0106] S2074: Steps

[0107] S2081: Steps

[0108] S20711: Steps

[0109] S20712: Steps

[0110] S20713: Steps

[0111] S20714: Steps

[0112] S20715: Steps

[0113] S20716: Steps

[0114] S20721: Steps

[0115] S20722: Steps

[0116] S20723: Steps

[0117] S20724: Steps

[0118] S20725: Steps

[0119] S20731: Steps

[0120] S20732: Steps

[0121] S20733: Steps

[0122] TC: Trench

[0123] V8: Diagram

[0124] V9: Schematic Diagram

[0125] V10: Schematic Diagram

[0126] V11: Schematic Diagram

[0127] V12: Schematic Diagram

[0128] V13: Schematic Diagram

[0129] V14: Diagram

[0130] V15: Illustration

[0131] V16: Diagram

[0132] V17: Illustration

[0133] V18: Illustration

[0134] V19: Illustration

[0135] V20: Schematic Diagram

[0136] V21: Schematic Diagram

[0137] V22: Schematic Diagram

[0138] V23: Diagram

[0139] V24: Illustration

[0140] V25: Illustration

[0141] V26: Diagram

[0142] V27: Illustration

[0143] V28: Diagram

[0144] W1: Width

[0145] W2: Width Detailed Implementation

[0146] The following detailed discussion of various embodiments of the present disclosure and their use is provided. However, it should be understood that these embodiments provide many applicable inventive concepts that can be implemented in a wide range of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of making and using these embodiments and do not limit the scope of the present disclosure. In various views and exemplary embodiments, the same element numbers are used to denote the same elements. Reference will now be made in detail to the exemplary embodiments shown in the accompanying drawings. Where possible, the same element numbers are used in the drawings and description to denote the same or similar elements. In the drawings, shapes and thicknesses may be exaggerated for clarity and convenience. This description will be directed particularly toward elements forming part of or more directly cooperating with an apparatus according to the present disclosure. It should be understood that elements not specifically shown or described may take various forms. Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that the following figures are not drawn to scale; rather, the element numbers are for illustrative purposes only.

[0147] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0148] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0149] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0150] Figure 1 A schematic diagram of a semiconductor structure 10, illustrating some embodiments of the present disclosure, is shown. The semiconductor structure 10 has a semiconductor substrate 100, a plurality of equibit line structures 200, a plurality of capacitor landing pads 300, a dielectric layer 400, and a dielectric layer 500. The equibit line structures 200 protrude from the semiconductor substrate 100. The capacitor landing pads 300 are disposed between the equibit line structures 200. The dielectric layer 400 fills the spaces between the capacitor landing pads 300 to insulate them from each other. The dielectric layer 500 is disposed on the capacitor landing pads 300 and the dielectric layer 400. Figure 1 As shown, the capacitor landing pad 300 and the dielectric layer 400 are coplanar.

[0151] exist Figure 1In this embodiment, the semiconductor structure 10 further includes an adhesive layer 600 and a contact structure 700. The contact structure 700 is electrically coupled to the active region 101. In some embodiments, the contact structure 700 is configured to provide an ohmic contact between the active region 101 and the capacitor landing pad 300. In other words, the contact structure 700 is configured to enhance the transport of a plurality of electrical carriers located between the active region 101 and the capacitor landing pad 300. The adhesive layer 600 is disposed between the capacitor landing pad 300 and the contact structure 700. In some embodiments, the adhesive layer 600 is configured to provide better adhesion between the contact structure 700 and the capacitor landing pad 300. The capacitor landing pad 300 is electrically coupled to the active region 101 via the adhesive layer 600 and the contact structure 700. In some embodiments, the adhesive layer 600 comprises cobalt silicide (Co2Si). In some embodiments, the contact structure 700 comprises polycrystalline silicon.

[0152] The semiconductor substrate 100 includes a plurality of conductive regions and a plurality of insulating regions, and the insulating regions are configured to insulate the conductive regions from each other. Figure 1 As shown, the semiconductor substrate 100 includes an active region 101, an active region 102, an active region 103, an insulating region 104, and an insulating region 105. The insulating region 104 is disposed between the active region 101 and the active region 102, and the insulating region 105 is disposed between the active region 102 and the active region 103.

[0153] In some embodiments, active regions 101, 102, and 103 are silicon doped with multiple dopants. In some embodiments, active regions 101, 102, and 103 have the same doping type, for example, N-type. In some embodiments, insulating regions 104 and 105 are shallow trench isolation (STI). In some embodiments, insulating regions 104 and 105 are also configured to prevent the capacitor landing pads 300 from being electrically coupled to active region 102.

[0154] To help understand, Figure 1 Only one bitline structure 200 is described and indicated by component number. Bitline structure 200 is electrically coupled to active region 102. Figure 1 In the middle, the bit line structure 200 includes a metal layer 201, a dielectric layer 202, an adhesive layer 203, a contact point structure 204, an adhesive layer 205, and a sidewall 210.

[0155] Metal layer 201, dielectric layer 202, adhesive layer 203, and contact structure 204 are sandwiched between sidewalls 210. Dielectric layer 202 is disposed on metal layer 201 and contacts metal layer 201 and dielectric layer 400. Metal layer 201 is coupled to contact structure 204 via adhesive layer 203. Contact structure 204 is disposed on active region 102 of semiconductor substrate 100 to form an electrical contact between metal layer 201 and active region 102. In some embodiments, contact structure 204 is configured to provide an ohmic contact between active region 102 and metal layer 201. Adhesive layer 205 is formed to cover sidewalls 210 and dielectric layer 202 and contacts dielectric layer 400 and capacitor landing pads 300.

[0156] In some embodiments, metal layer 201 comprises tungsten. In some embodiments, dielectric layer 202 comprises a nitride, for example, silicon nitride (SiN). In some embodiments, adhesive layer 203 comprises titanium nitride (TiN). In some embodiments, adhesive layer 205 comprises TiN.

[0157] Sidewall 210 is configured to insulate metal layer 201 from capacitor landing pad 300. Sidewall 210 is a multilayer structure including an inner dielectric layer 211, an outer dielectric layer 212, and an air gap 213. Air gap 213 is disposed between inner dielectric layer 211 and outer dielectric layer 212. Inner dielectric layer 211 contacts dielectric layer 202, metal layer 201, adhesive layer 203, contact point structure 204, active region 102, and dielectric layer 400. Outer dielectric layer 212 contacts adhesive layer 205, adhesive layer 600, contact point structure 700, insulating region 104, and dielectric layer 400. An upper surface of sidewall 210 is covered by dielectric layer 400. In some embodiments, air gap 213 is configured to reduce the capacitance value of parasitic capacitance in semiconductor structure 10.

[0158] The capacitor landing pad 300 has an adhesive layer 205 and a dielectric layer 400 for contact bit line structure 200. For example... Figure 1 As shown, the capacitor landing pad 300 has a stepped shape. In some embodiments, the width W1 of an upper portion of the capacitor landing pad 300 is greater than the width W2 of a lower portion of the capacitor landing pad 300. In some embodiments, the capacitor landing pad 300 comprises tungsten (W).

[0159] For illustrative purposes, the above-described architecture of the semiconductor structure 10 is provided. Various different architectures of the semiconductor structure 10 are contemplated within the scope of this disclosure. For example, in various embodiments, the semiconductor structure 10 includes other suitable materials to form the capacitor landing pad 300, the contact structure 700, and the contact structure 204.

[0160] In some embodiments, the semiconductor structure 10 is part of a memory element, for example, a dynamic random access memory (DRAM). The memory element includes at least one transistor having a gate, a source / drain, and another source / drain. The gate is coupled to a word line of the memory element, the source / drain is coupled to a bit line of the memory element, and the other source / drain is coupled to a capacitor of the memory element. The source / drain coupled to the bit line corresponds to an active region 102 of the bit line structure 200. The source / drain coupled to the capacitor corresponds to an active region 101 of the capacitor landing pad 300. In other embodiments, the semiconductor structure 10 also includes a recess (not shown) located in the semiconductor substrate 100. The gate of the memory element corresponds to the recess of the semiconductor structure 10.

[0161] Figure 2 Examples of some implementations of this disclosure are shown below. Figure 1 The schematic diagram shows the process flow of the method 20 for fabricating the semiconductor structure 10. The fabrication method 20 includes steps S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, and S211. Figures 3 to 7 Examples of some implementations of this disclosure are shown below. Figure 2 The detailed flowchart of each step of preparation method 20 is shown. Figures 8 to 28 Examples of some implementations of this disclosure are shown below. Figure 1 A schematic diagram of the manufacturing process of the semiconductor structure 10 is shown. Furthermore, in Figures 2 to 7 Preparation method 20 corresponds to Figures 8 to 28 The diagrams V8 to V28 are used for description, and for ease of understanding, as shown below. Figures 8 to 28 Similar components shown are used in Figure 1 They are represented by the same component number.

[0162] Please refer to Figure 2 and Figure 8 In step S201, a semiconductor substrate 100 is provided. In step S202, a bit line structure 200 is formed to protrude from the semiconductor substrate 100. In step S203, a landing pad contact point structure 700 is formed and coupled to the active region 101 of the semiconductor substrate 100. In step S204, a cobalt silicide layer 600 (i.e., an adhesive layer 600) is formed and coupled to the landing pad contact point structure 700.

[0163] like Figure 8As shown in schematic diagram V8, the semiconductor substrate 100 provides active regions 101, 102, 103, insulating regions 104, and insulating regions 105. The bit line structure 200 forms bit line contact point structures 204, a metal layer 201, a dielectric layer 202, an adhesive layer 203, sidewalls 210, and an adhesive layer 205. The sidewalls 210 form an inner dielectric layer 211, an outer dielectric layer 212, and an intermediate oxide layer 216, with the intermediate oxide layer 216 disposed between the inner dielectric layer 211 and the outer dielectric layer 212.

[0164] Compared to semiconductor structure 10, the sidewall 210 in schematic diagram V8 has an intermediate oxide layer 216 within the sidewall 210, and does not include an air gap 213. The intermediate oxide layer 216 will be etched in a subsequent step to form the air gap 213. Details regarding step S208 will be described below.

[0165] Please refer to this again. Figure 9 In step S205, a landing cushion layer 310 is deposited to cover the bit line structure 200. In step S206, the upper surface of the landing cushion layer 310 is planarized. Figure 9 As shown in schematic V9, the landing pad layer 310 covers the contour of the bit line structure 200. After planarization, the landing pad layer 310 has a generally flat upper surface. The landing pad layer 310 will be etched in a subsequent step to form the capacitor landing pads 300. Therefore, the landing pad layer 310 and the capacitor landing pads 300 are made of the same material.

[0166] Please refer to this again. Figure 3 and Figures 10 to 24 In step S207, a plurality of trenches TC are formed in the landing pad layer 310, and the trenches TC are used to form the capacitor landing pad 300. In some embodiments, step S207 includes a step S2071, a step S2072, a step S2073 and a step S2074.

[0167] In step S2071, multiple masking layers ML are deposited on the landing pad layer 310. In step S2072, forward double patterning is performed on the masking layers ML to form a hard mask HM on the landing pad layer 310. In step S2073, the landing pad layer 310 is etched according to the hard mask HM to form the trenches TC. In step S2074, an ashing etching is performed to remove the masking layers ML.

[0168] In some embodiments, the masking layers ML include a plurality of carbon layers and a plurality of dielectric layers arranged in an alternating manner. The masking layers ML are configured to be etched to form a hard mask HM for forming the trenches TC. In some embodiments, step S2071 includes steps S20711, S20712, S20713, S20714, S20715, and S20716.

[0169] In step S20711, a carbon layer C1 is deposited on the landing cushion layer 310. Figure 10 In the diagram, schematic V10 shows a carbon layer C1 deposited on the landing pad layer 310. In some embodiments, the carbon layer C1 has a height approximately equal to 90 nm.

[0170] In step S20712, a dielectric layer D1 is deposited on the carbon layer C1. Figure 11 In the diagram, schematic V11 shows a dielectric layer D1 deposited on a carbon layer C1. In some embodiments, the dielectric layer D1 comprises SiN.

[0171] In step S20713, a carbon layer C2 is deposited on the dielectric layer D1. Figure 12 In the diagram, V12 shows the carbon layer C2 deposited on the dielectric layer D1.

[0172] In step S20714, a dielectric layer D2 is deposited on the carbon layer C2. Figure 13 In the diagram, schematic V13 shows a dielectric layer D2 deposited on a carbon layer C2. In some embodiments, the dielectric layer D2 comprises silicon (Si). In some embodiments, the dielectric layer D2 is a dielectric antireflective coating.

[0173] In step S20715, a carbon layer C3 is deposited on the dielectric layer D2. Figure 14 In the diagram, V14 shows carbon layer C3 deposited on dielectric layer D2.

[0174] In step S20716, a dielectric layer D3 is deposited on the carbon layer C3. Figure 15 In the diagram, schematic V15 shows a dielectric layer D3 deposited on a carbon layer C3. In some embodiments, the dielectric layer D3 contains oxygen (O). In some embodiments, the dielectric layer D3 is a dielectric antireflective coating.

[0175] In this embodiment, the masking layer ML includes carbon layers C1, C2, and C3, dielectric layers D1, D2, and D3. After the masking layer ML is formed, step S2072 is performed. In some embodiments, step S2072 includes steps S20721, S20722, S20723, S20724, and S20725.

[0176] In step S20721, dielectric layers D3 and D2 are patterned. Figure 16 In the diagram, V16 shows the patterned dielectric layer D3. Figure 17 In the diagram, schematic V17 shows a patterned dielectric layer D2. In some embodiments, patterned dielectric layer D2 and patterned dielectric layer D3 are not aligned. The architecture of patterned dielectric layer D2 and patterned dielectric layer D3 is provided for illustrative purposes only and is not intended to be limiting.

[0177] In step S20722, dielectric layer D3, dielectric layer D2, carbon layer C3, and carbon layer C2 are etched according to the patterned dielectric layer D2 and patterned dielectric layer D3 to form a plurality of carbon rods C2R in carbon layer C2. Figure 18 In the diagram V18, the carbon rods C2R are shown after etching carbon layers C2, C3, dielectric layer D2, and dielectric layer D3.

[0178] In step S20723, an oxide layer OX is deposited to cover the carbon rods C2R. In step S20724, an upper surface of the oxide layer OX is planarized. In some embodiments, step S20724 is performed by chemical mechanical polishing (CMP). In other embodiments, step S20724 is performed by etching back. In some embodiments, after step S20724, the upper surface of the oxide layer OX is coplanar with an upper surface of the carbon rods C2R. Figure 19 In the diagram, V19 shows the oxide layer OX filled between the carbon rods C2R, and after planarization, the oxide layer OX is coplanar with the carbon rods C2R.

[0179] In step S20725, the carbon rods C2R, dielectric layer D2, and carbon layer C1 are etched according to the remaining oxide layer OX to form a hard mask HM. During step S20725, the carbon rods C2R are etched. Additionally, during step S20725, a portion of the dielectric layer D1 corresponding to the carbon rods C2R and a portion of the carbon layer C1 corresponding to the carbon rods C2R are also etched. Figure 20 In the diagram V20, the carbon rods C2R are removed, and the oxide layer OX remains on the dielectric layer D1. Figure 21 In the diagram, schematic V21 shows the etched dielectric layer D1 corresponding to the etched carbon rod C2R. Figure 22 In the diagram, schematic V22 shows the etched carbon layer C1 corresponding to the etched carbon rod C2R and the etched dielectric layer D1. In some embodiments, the etched dielectric layer D1 and the etched carbon layer C1 are aligned with the carbon rod C2R. The hard mask HM thus includes the remaining oxide layer OX in the upper part, the remaining dielectric layer D1 in the middle part, and the remaining carbon layer C1 in the lower part.

[0180] After the hard mask HM is formed, step S2073 is performed. In some embodiments, step S2073 includes steps S20731, S20732, and S20733. In some embodiments, the trenches TC are partially aligned with the bitline structure 200. In some embodiments, the etched landing pad layer 320 (i.e., at the locations where the trenches TC will be located) overlaps a portion of the bitline structure 200. Therefore, during the etching of the landing pad layer 310, this portion of the bitline structure 200 is etched.

[0181] In step S20731, the landing pad layer 310 is etched to reach an upper surface of the bit line structure 200. Figure 23 In the diagram, V23 shows the etched landing pad 310 to have a bottom with an arrival bit line structure 200.

[0182] In step S20732, the adhesive layer 205 of the bit line structure 200 is etched. Figure 24 In the diagram, V24 shows a portion of the etched adhesive layer 205.

[0183] In step S20733, a portion of the sidewall 210 of the bit line structure 200 and a portion of the dielectric layer 202 are etched to expose the upper surface 214 of the sidewall 210 of the bit line structure 200. Figure 25 In the diagram, schematic V25 shows the formation of multiple capacitor landing pads 300 after etching the landing pad layer 310. Then, this portion of the sidewall 210 and this portion of the dielectric layer 202 are etched. Next, the upper surface 214 of the sidewall 210 is exposed. The upper surface 214 comprises three sections: an upper surface of the inner dielectric layer 211, an upper surface of the outer dielectric layer 212, and an upper surface of the intermediate oxide layer 216.

[0184] After performing steps S20731, S30732, and S30733, the trenches TC and the capacitor landing pads 300 are formed. This is achieved through... Figure 26 The step S2074 shown is to remove the hard mask HM (i.e., the remaining mask layers ML). In Figure 26 In the diagram V26, the formed capacitor landing pad 300 also shows that the upper width W1 is greater than the lower width W2. The width W1 is related to the dimension of the hard mask HM. The dimension of the hard mask HM is also related to the dimension of the carbon rods C2R. The dimension of the carbon rods C2R is controlled by the forward double patterning performed in step S2072. In other words, the width W1 is controlled by step S2072.

[0185] In step S208, an air gap 213 is formed within the sidewall 210 of the bitline structure 200. In some embodiments, step S208 includes a step S2081. In step S2081, the intermediate oxide layer 216 is etched, and the space occupied by the original intermediate oxide layer 213 becomes the air gap 213. Figure 27 In the diagram, schematic V27 shows the air gap 213 connected to the trenches TC. In some embodiments, the intermediate oxide layer 216 is etched using gaseous hydrofluoric acid. However, the etchant used in step S2081 is not limited to gaseous hydrofluoric acid. In other embodiments, step S2081 uses other suitable etchants to etch the intermediate oxide layer 216.

[0186] In step S209, the dielectric layer 400 fills the trenches TC to seal the air gap 213. In step S210, the dielectric layer 400 is planarized. Figure 28 In the diagram, schematic V28 shows that the upper surface 214 of the sidewall 210 is covered by the dielectric layer 400, and the air gap 213 is sealed by the filled dielectric layer 400. Furthermore, after planarization, the dielectric layer 400 is coplanar with the capacitor landing pads 300.

[0187] In step S211, a dielectric layer 500 is deposited on the capacitor landing pad 300. After step S211, a structure is formed as follows: Figure 1 The semiconductor structure 10 is shown.

[0188] In some embodiments, after step S211, a planarization process is performed to planarize the dielectric layer 500 in order to form additional capacitive cushions (not shown) on the dielectric layer 500 relative to the capacitor landing pads 300.

[0189] One embodiment of this disclosure provides a method for fabricating a semiconductor structure having multiple capacitor landing pads. The method includes providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing an upper surface of the landing pad layer; forming a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling the trench with a first dielectric layer to seal the air gap.

[0190] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0191] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A method for fabricating a semiconductor structure having multiple capacitor landing pads, comprising: Provide a semiconductor substrate; A one-bit line structure is formed, which protrudes from the semiconductor substrate; Deposit a landing cushion layer to cover the cellular structure; Flatten one upper surface of the landing pad; A groove is formed in the landing pad layer to form the plurality of capacitor landing pads; An air gap is formed within one side wall of the element-line structure; as well as A first dielectric layer is filled into the trench to seal the air gap; The formation of the trench in the landing pad layer to form the capacitor landing pad includes: Multiple shielding layers were deposited on the landing cushion layer; Perform a forward-facing double patterning on the multiple masking layers to form a hard mask on the landing pad layer; and The landing pad is etched according to the hard shield to form the trench; The deposition of the multiple shielding layers on the landing cushion includes: A first carbon layer was deposited on the landing cushion; and A second dielectric layer is deposited on the first carbon layer; The deposition of the multiple shielding layers on the landing cushion includes: A second carbon layer is formed on the second dielectric layer; A third dielectric layer is formed on the second carbon layer; A third carbon layer is formed on the third dielectric layer; and A fourth dielectric layer is formed on the third carbon layer; The process of performing forward dual patterning on the multiple masking layers to form the hard mask on the landing pad layer includes: Patterning the fourth dielectric layer and the third dielectric layer; and The fourth dielectric layer, the third carbon layer, the third dielectric layer, and the second carbon layer are etched to form a plurality of carbon rods in the second carbon layer.

2. The preparation method according to claim 1, wherein the height of the first carbon layer is equal to 90 nm, the second dielectric layer comprises silicon nitride, the third dielectric layer is a silicon-containing dielectric antireflective coating, and the fourth dielectric layer is an oxygen-containing dielectric antireflective coating.

3. The preparation method of claim 1, wherein performing the forward dual patterning on the plurality of mask layers to form the hard mask on the landing pad layer further comprises: An oxide layer is deposited to cover the multiple carbon rods.

4. The preparation method according to claim 3, wherein the oxide layer is deposited by an atomic layer deposition technique.

5. The preparation method of claim 3, wherein performing the forward dual patterning on the plurality of mask layers to form the hard mask on the landing pad layer further comprises: Planarize an upper surface of the oxide layer, wherein the upper surface of the oxide layer is coplanar with an upper surface of the plurality of carbon rods, wherein the remaining oxide layer is an upper part of the hard mask.

6. The preparation method of claim 5, wherein performing the forward dual patterning on the plurality of mask layers to form the hard mask on the landing pad layer further comprises: The remaining oxide layer is used to etch the plurality of carbon rods, the second dielectric layer, and the first carbon layer to form the hard mask.

7. The preparation method of claim 6, wherein etching the landing pad layer according to the hard mask to form the trench comprises: A portion of the sidewall of the bitline structure and a portion of a nitride layer of the bitline structure are etched to expose an upper surface of the sidewall of the bitline structure.

8. The preparation method of claim 7, wherein etching the landing pad layer according to the hard mask to form the trench further comprises: The landing pad is etched to reach an upper surface of the bit line structure; as well as A portion of an adhesive layer of the bit line structure is etched, wherein the adhesive layer comprises titanium nitride.

9. The preparation method of claim 1, wherein forming the trench in the landing pad layer to form the capacitor landing pad further comprises: Perform an ashing etch to remove the multiple mask layers.

10. The fabrication method of claim 1, wherein the sidewall of the bit line structure comprises an inner dielectric layer, an outer dielectric layer, and an intermediate oxide layer, the intermediate oxide layer being disposed between the inner dielectric layer and the outer dielectric layer, wherein, The air gap formed within the sidewall of the bitline structure includes: The intermediate oxide layer is etched.

11. The preparation method of claim 10, wherein the intermediate oxide layer is etched by gaseous hydrofluoric acid.

12. The preparation method according to claim 1, further comprising: Planarize the first dielectric layer, wherein the first dielectric layer and the plurality of capacitor landing pads are coplanar; and A fifth dielectric layer is deposited on the first dielectric layer and the plurality of capacitor landing pads, wherein the fifth dielectric layer comprises silicon nitride.

13. The preparation method according to claim 1, wherein the trench portion is aligned with the bit line structure.

14. The fabrication method of claim 1, wherein the semiconductor substrate comprises a first active region, a second active region, and an insulating region, the insulating region being disposed between the first active region and the second active region, wherein, A bit-line contact point structure is formed to contact the first active region.

15. The preparation method according to claim 14, further comprising: A landing pad contact point structure is formed to couple the second active region of the semiconductor substrate; as well as A cobalt silicide layer is formed to couple the landing pad contact point structure.

16. The preparation method of claim 1, wherein each capacitor landing pad has a stepped shape, wherein, The width of the upper portion of the plurality of capacitor landing pads is greater than the width of the lower portion of the plurality of capacitor landing pads.

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