A high-precision voltage-mode relaxation oscillator

Abstract

The present invention discloses a high-precision voltage-mode relaxation oscillator, comprising: a reference current source; a bandgap reference voltage source; a three-terminal input and dual-output comparator, wherein the three-terminal input includes a positive terminal input connected to a reference voltage V REF and two negative terminal inputs respectively connected to the positive terminals of capacitors C1 and C2. The comparison results of the two negative terminal inputs with the positive terminal input are respectively the two output signals of the comparator. Two capacitors C1 and C2, whose negative terminals are both grounded, and whose positive terminals are respectively connected to the two negative terminal inputs of the comparator; a digital control circuit, which consists of a latch formed by two NOR gates and two inverters. The comparator adopted by the voltage-mode relaxation oscillator has a dual-output structure, and there is no need to additionally adopt a D flip-flop for sampling and frequency division. The control logic only adopts a latch formed by two NOR gates and two inverters, which improves the output frequency of the voltage-mode relaxation oscillator, reduces the power consumption and layout area of the circuit.

Description

Technical Field

[0001] The present invention relates to a high-precision voltage-mode relaxation oscillator, specifically a resistor with complementary positive and negative temperature coefficients, a three-terminal input and dual-output comparator structure, and the digital control circuit only includes one latch and two inverters, belonging to the technical field of analog integrated circuit design. Background Art

[0002] The types of on-chip crystal oscillators mainly include crystal oscillators, ring oscillators, LC oscillators, and relaxation oscillators. The output frequency of crystal oscillators is the most accurate among the other three types of oscillators. However, crystal oscillators have high costs, high power consumption, and low frequencies, and are usually used in fields with high requirements for oscillator frequency accuracy. The circuit of ring oscillators is relatively simple, easy to oscillate and integrate, but its frequency accuracy is not high. Therefore, it is often used as a clock source and widely used in low-frequency or medium-frequency communication systems. LC oscillators are composed of capacitors and inductors. Since inductors are not easy to integrate in integrated circuits, LC oscillators are mainly used in the radio frequency field. The relaxation oscillator circuit charges and discharges a capacitor with a constant current, and the oscillation frequency can be adjusted by changing the charging current or the size of the capacitor. At the same time, a comparator structure is adopted in the relaxation oscillator, which can well reduce the non-linearity of the switch and has good temperature stability. Therefore, the relaxation oscillator is often the first choice for the clock source, and the present invention will also optimize and design the relaxation oscillator.

[0003] Relaxation oscillators are further divided into current-mode relaxation oscillators and voltage-mode relaxation oscillators. Although current-mode relaxation oscillators require less power consumption, their stability is lower than that of voltage-mode relaxation oscillators because current-mode relaxation oscillators do not adopt a comparator structure. Voltage-mode relaxation oscillators are convenient for on-chip integration, have high output frequency stability, simple structures, and are easy to implement. The present invention mainly studies voltage-mode relaxation oscillators.

[0004] The structure of traditional voltage-mode relaxation oscillators is as Figure 1 . The circuit mainly consists of constant current sources I1 and I2, switching transistors MP1 and MN1, a high-threshold comparator COMP1, a low-threshold comparator COMP2, and a logic control circuit.

[0005] Its working principle is as follows: When power is first applied, the circuit is in a charging state, and the charge stored in capacitor C is 0. Therefore, there is V C <V L . At this time, switching transistor MP1 is turned on, MN1 is turned off, current source I2 does not work, and current source I1 starts to charge capacitor C. When the charge reaches V C >V HWhen a = 0 and b = 1, the control logic will make Q = 1. At this time, the oscillator circuit starts to enter the discharge state. The switching transistor MP1 is turned off, and MN1 is turned on. The current source I1 stops working, and the current source I2 starts to extract the charge on the capacitor C, and V C gradually decreases. When V C < V L , it enters the charging state again. In this way, by continuously charging and discharging the capacitor, the output Q will also correspondingly generate a square wave signal, which is also the output signal of the voltage-mode relaxation oscillator circuit.

[0006] Traditional voltage-mode relaxation oscillators require low-threshold voltage and high-threshold voltage generation circuits. Therefore, the circuit not only needs a bandgap reference circuit to generate the reference voltage, but also needs to add circuits to generate the high-threshold voltage and low-threshold voltage, resulting in an increase in chip power consumption, area, and cost. To solve the above problems, Mu Xinhua et al. proposed to only use one reference voltage to compare with the voltages at both ends of two charging capacitors with the same capacitance value respectively to obtain the output oscillation signal, such as Figure 2 .

[0007] Figure 2 In it, V REF is generated by the bandgap reference voltage source, providing the flip threshold for the oscillation circuit. I bias is the temperature-independent current generated by the reference circuit. M17 and M18 adopt the structure of a current mirror to provide the tail current for the comparator. M7 and M8 are the reverse ends of the differential pair transistors of the three-port comparator, and M11, M12 and M13, M14 are the forward ends.

[0008] When the circuit starts to work, CLK2 is at a low level and CLK1 is at a high level. The capacitor C2 starts to store charge, and the capacitor C1 starts to release charge. When the voltage at the upper end of the capacitor C2 is greater than V REF , the gate voltage of M4 is quickly pulled low, and the output voltage of the comparator is high (point A becomes high level). Since the output signal of the comparator is shaped and used as the clock signal of the D flip-flop, when A is at a high level, the D flip-flop flips. The RS flip-flop sets CLK1 to a low level and CLK2 to a high level. The capacitor C2 starts to release charge, and the capacitor C1 starts to store charge. When the voltage at the upper end of the capacitor C1 is greater than V REF , the gate voltage of M4 is quickly pulled low, and the output voltage of the comparator is high again, realizing the oscillation in the lower half cycle. By continuously charging and discharging the capacitor, the output signal of the oscillator is finally formed as CLK1.

[0009] Although the voltage - type relaxation oscillator proposed by Mu Xinhua et al. optimizes the comparator, and the comparator adopts a three - terminal input and single - terminal output structure, its output is single - terminal. Compared with the double - terminal differential output comparator, the output pole frequency is low and the output swing is small. At the same time, the actual output signal is a divided - by - two signal of the oscillation signal, reducing the available frequency range. And the logic control circuit of the circuit uses a Schmitt inverter and a D - flip - flop, increasing the power consumption of the circuit and the area of the layout. Therefore, a more optimized high - precision voltage - type relaxation oscillator is proposed. Summary of the Invention

[0010] In view of the problems described in the background art, in order to increase the output signal swing, improve the output signal frequency, and avoid the use of D - flip - flops and Schmitt inverters, the present invention proposes a high - precision voltage - type relaxation oscillator. Based on a three - terminal input and double - terminal output comparison structure, it only uses one input reference voltage V REF , and there is no need to add an extra D - flip - flop in the digital control logic to generate a divided - by - two signal. When the power consumption and the charge - discharge capacitors are the same as those of the voltage - type relaxation oscillator proposed by Mu Xinhua et al., the output frequency of the voltage - type relaxation oscillator proposed by the present invention can reach twice that of the voltage - type relaxation oscillator proposed by Mu Xinhua et al., and the control logic only uses a latch composed of two NOR gates and two inverters, greatly simplifying the logic control structure compared with the voltage - type relaxation oscillator proposed by Mu Xinhua et al.

[0011] To achieve the above object, the present invention adopts the following scheme: A high - precision voltage - type relaxation oscillator, characterized by comprising: a reference current source, a band - gap reference voltage source, and a three - terminal input and double - terminal output comparator. Among them, the three - terminal input includes a positive - terminal input connected to the reference voltage V REF , and two negative - terminal inputs respectively connected to the positive terminals of capacitors C1 and C2. The comparison results of the two negative - terminal inputs with the positive - terminal input are respectively the two output signals of the comparator; two capacitors C1 and C2, their negative terminals are both grounded, and their positive terminals are respectively connected to the two negative - terminal inputs of the comparator; a digital control circuit, composed of a latch composed of two NOR gates and two inverters. Among them, the two NOR gates are I1 and I2 respectively. The output terminal of NOR gate I1 is connected to one input terminal of NOR gate I2. One input terminal of NOR gate I1 is connected to the output terminal of NOR gate I2. The output terminal of NOR gate I1 is the output terminal of the final latch to form a latch. The other end of NOR gate I1 is connected to the positive terminal of capacitor C2 and the output signal after comparison with V REF , and the other end of NOR gate I2 is connected to the positive terminal of capacitor C1 and the output signal after comparison with V REF .

[0012] When the circuit starts to work, the charges on both ends of capacitors C1 and C2 are 0, the two outputs of the comparator are both 0, the latch maintains its original working state unchanged, the current source starts to charge capacitor C1, and capacitor C2 discharges rapidly; when the voltage difference across capacitor C1 reaches V REF , the positive terminal branch of the comparator connected to V REF is compared with the negative terminal branch connected to capacitor C1, the output signal flips, the input signals of the latch are 0 and 1 respectively, the output signal is 1, the control switch transistor rapidly discharges capacitor C1, and the reference current is used to charge C2; when the voltage difference across capacitor C2 reaches V REF , the positive terminal branch of the comparator connected to V REF is compared with the negative terminal branch connected to capacitor C2, the output signal of the comparator flips, the input signals of the latch are 1 and 0 respectively, the output signal is 0, the control switch transistor rapidly discharges capacitor C2, and the reference current is used to charge C1. The obtained output signal of the latch passes through two inverters to shape and control the charge and discharge of the capacitor and generate the output signal of the oscillator.

[0013] Furthermore, the reference current source uses positive and negative temperature complementary resistors to reduce the current deviation caused by temperature effects.

[0014] Furthermore, the bandgap reference voltage source uses a first-order bandgap reference voltage source. Based on a negative feedback loop, the voltage difference between the emitter-base voltages of two BJT transistors with different current densities is obtained. The voltage difference has a first-order linear positive temperature coefficient, and the voltage difference is used to compensate the first-order negative temperature term of the emitter-base voltage of the BJT transistor.

[0015] Furthermore, the comparator uses a three-terminal input and dual-output comparison structure, only using one input reference voltage V REF , and the three-terminal input and dual-output comparison structure can increase the output pole frequency and output swing compared with the three-terminal input and single-output comparison structure.

[0016] Furthermore, the digital control circuit uses a latch and two inverters. There is no need to add an additional D flip-flop in the digital control logic to generate a divided-by-two signal, which can increase the output frequency and simplify the digital control logic.

[0017] The beneficial effects of the present invention are as follows:

[0018] First, the present invention proposes a reference current source with positive and negative temperature complementary resistors to reduce the current deviation caused by temperature effects; second, the present invention proposes only one reference voltage V REFA comparator with a three-terminal input and two-terminal output can increase the output pole frequency and output swing. Finally, the present invention proposes a simple digital control circuit, which only uses one latch and two inverters, avoiding the use of D flip-flops, can increase the output frequency, and reduce the layout area and circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a traditional voltage-mode relaxation oscillator structure;

[0020] Figure 2 is a schematic diagram of a voltage-mode relaxation oscillator circuit using only one reference voltage;

[0021] Figure 3 is a schematic diagram of the structure of the voltage-mode relaxation oscillator proposed by the present invention;

[0022] Figure 4 is a schematic diagram of the working state of the voltage-mode relaxation oscillator proposed by the present invention;

[0023] Figure 5 is a schematic diagram of the circuit of the voltage-mode relaxation oscillator state 1 proposed by the present invention;

[0024] Figure 6 is a schematic diagram of the circuit of the voltage-mode relaxation oscillator state 2 proposed by the present invention;

[0025] Figure 7 is a schematic diagram of the reference voltage and reference current generation module;

[0026] Figure 8 is a schematic diagram of the output signal waveform of the voltage-mode relaxation oscillator proposed by the present invention under the TT process corner;

[0027] Figure 9 is a schematic diagram of the output signal waveform of the voltage-mode relaxation oscillator proposed by the present invention under the SS process corner;

[0028] Figure 10 is a schematic diagram of the output signal waveform of the voltage-mode relaxation oscillator proposed by the present invention under the FF process corner. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of the claims of the present invention. Those not detailed in this technical solution are all well-known technologies.

[0030] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments:

[0031] The voltage-type relaxation oscillator structure designed by the present invention is as Figure 3 , where V generated by the bandgap reference voltage source REF is the flip threshold of the oscillation circuit, I1 and I2 are temperature-independent currents generated by the reference circuit, and MN1 to MN4 form a current mirror. The gate of MN8 is the negative terminal of the three-terminal input comparator, and the gates of MN7 and MN9 are the positive terminals of the three-terminal input comparator respectively. MP1, MN2 and MP5, MN4 form the second-stage operational amplifier of the comparator. The gain of the entire comparator is: g MN7 (r ON7 / / r OP2 )g MP1 (r OP1 / / r ON2 ), which is increased by g MP1 (r OP1 / / r ON2 ) times compared with the single-stage operational amplifier. The larger gain can increase the output swing of the output signals A1 and B1 of the comparator.

[0032] The working state diagram of the voltage-type relaxation oscillator is as Figure 4 . Where A is the voltage of the upper plate of capacitor C1, B is the voltage of the upper plate of capacitor C2, and OSCOUT is the output signal of the voltage-type relaxation oscillator designed by the present invention.

[0033] State 1: When the circuit starts to work, as Figure 5 , the charges stored at both ends of capacitors C1 and C2 are 0. is at a low level, is at a high level. At this time, the current source I2 starts to charge capacitor C1. When the voltage at both ends of C1 reaches V REF , the circuit jumps to state 2 and stops charging C1. Therefore, the duration of state 1, that is, the charging time T1 of C1 is;

[0034]

[0035] State 2: When the upper plate of capacitor C1 is charged to be greater than V REF , the circuit will enter State 2, as shown in Figure 6 . At this time, the voltage at point A is greater than V REF , the output voltage of A1 is high level, the output voltage of B1 remains low level, the output voltage is high level, the output voltage is low level. At this time, MN5 quickly discharges C1, and at the same time the current source I2 starts to charge the capacitor C2. Similarly, when the voltage difference across the capacitor C2 is greater than V REF , the circuit will jump out of State 2, and the duration of State 2, that is, the charging time T2 of C2 is:

[0036]

[0037] Finally, the circuit switches between State 1 and State 2. From formulas (1) and (2), the frequency of the oscillator can be obtained as:

[0038]

[0039] In actual design, the charging and discharging current of the capacitor will change with temperature. Therefore, in order to obtain a current source I2 that does not change with temperature in the present invention, during the design of the bandgap reference voltage source, resistors with complementary positive and negative temperature coefficients are used to obtain a capacitor charging and discharging current I2 that is independent of temperature at the same time, as shown in Figure 7 . Among them, the resistor R1 is a positive temperature coefficient resistor, R2 is a negative temperature coefficient resistor, and the voltage V REF generated by the bandgap reference is 1.2V, and I REF can be obtained as:

[0040]

[0041] The designed relaxation oscillator is designed based on the SMIC 180nm standard CMOS process and simulated using Cadence Spectre. The post-simulation results are as follows.

[0042] The simulation waveform in the TT process corner is as shown in Figure 8 . It can be seen that when the temperature is -40°C, the output signal period of the oscillator is 253.0978ns; when the temperature is 25°C, the output signal period of the oscillator is 249.0877ns; when the temperature is 85°C, the output signal period of the oscillator is 249.3479ns; when the temperature is 125°C, the output signal period of the oscillator is 248.3096ns; it can be obtained that the error of the oscillator output frequency under the TT process corner is about 1.9%.

[0043] The simulation waveform in the SS process corner is as shown in Figure 9, it can be seen that when the temperature is -40°C, the output signal period of the oscillator is 251.7255 ns; when the temperature is 25°C, the output signal period of the oscillator is 251.0746 ns; when the temperature is 85°C, the output signal period of the oscillator is 247.5652 ns; when the temperature is 125°C, the output signal period of the oscillator is 248.3610 ns; it can be obtained that the maximum error of the oscillator output frequency at the SS process corner compared to the TT process corner at a temperature of 25°C is 1.05%.

[0044] The simulation waveform of the FF process corner is as Figure 10 , it can be seen that when the temperature is -40°C, the output signal period of the oscillator is 251.6011 ns; when the temperature is 25°C, the output signal period of the oscillator is 251.1238 ns; when the temperature is 85°C, the output signal period of the oscillator is 248.8081 ns; when the temperature is 125°C, the output signal period of the oscillator is 247.0087 ns; it can be obtained that the error of the oscillator output signal period at the FF process corner is approximately 1.00%.

[0045] Thus, a voltage - type relaxation oscillator of the present invention is realized, with an output frequency of 4 MHz, an output signal frequency error of 1.9% when the temperature varies in the range of -40°C to 125°C. It is based on a three - terminal input and two - terminal output comparison structure and only uses one input reference voltage V REF , and there is no need to add an additional D - flip - flop in the digital control logic to generate a divided - by - two signal. It can be seen that in Figure 3 , after adopting the three - terminal input and two - terminal output comparison structure composed of MN7 to MN9 and MP2 to MP4, the circuit only needs to use one input reference voltage V REF , and it avoids introducing an additional divided - by - two circuit in the digital control logic, improves the output frequency, and reduces the circuit power consumption. The design of a high - precision and low - cost voltage - type relaxation oscillator is realized.

[0046] The above - mentioned is only the preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution of the present invention and its inventive concept, makes equivalent substitutions or changes, and all should be covered within the protection scope of the present invention.

Claims

1. A high-precision voltage-mode relaxation oscillator, characterized in that, Including: Reference current source, bandgap reference voltage source, three-terminal input and dual-terminal output comparator. The three-terminal input includes a positive terminal input connected to the reference voltage V REF and two negative terminal inputs respectively connected to the positive terminals of capacitors C1 and C2. The comparison results of the two negative terminal inputs with the positive terminal input are respectively the two output signals of the comparator; two capacitors C1 and C2, whose negative terminals are both grounded and positive terminals are respectively connected to the two negative terminal inputs of the comparator; digital control circuit, consisting of a latch composed of two NOR gates and two inverters. Among them, the two NOR gates are I1 and I2 respectively. The output terminal of NOR gate I1 is connected to one of the input terminals of NOR gate I2. One of the input terminals of NOR gate I1 is connected to the output terminal of NOR gate I2. The output terminal of NOR gate I1 is the output terminal of the final latch, thus forming a latch. The other end of NOR gate I1 is connected to the positive terminal of capacitor C2 and V REF after comparison output signal, and the other end of NOR gate I2 is connected to the positive terminal of capacitor C1 and V REF after comparison output signal; When the circuit starts to work, the charges on both ends of capacitors C1 and C2 are 0, the two outputs of the comparator are both 0, the latch maintains its original working state unchanged, the current source starts to charge capacitor C1, and capacitor C2 discharges quickly; when the voltage difference across capacitor C1 reaches V REF , the positive terminal branch of the comparator connected to V REF is compared with the negative terminal branch connected to capacitor C1, the output signal flips, the input signals of the latch are 0 and 1 respectively, the output signal is 1, the control switch transistor quickly discharges capacitor C1, and charges C2 with the reference current; when the voltage difference across capacitor C2 reaches V REF , the positive terminal branch of the comparator connected to V REF is compared with the negative terminal branch connected to capacitor C2, the output signal of the comparator flips, the input signals of the latch are 1 and 0 respectively, the output signal is 0, the control switch transistor quickly discharges capacitor C2, and charges C1 with the reference current, and the output signal of the obtained latch is shaped by two-stage inverters to control the charging and discharging of the capacitor and generate the output signal of the oscillator.

2. The high-precision voltage-mode relaxation oscillator according to claim 1, characterized in that The reference current source uses resistors with complementary positive and negative temperature characteristics.

3. A high-precision voltage-mode relaxation oscillator according to claim 1, characterized in that, The bandgap reference voltage source uses a first-order bandgap reference voltage source. Based on a negative feedback loop, the voltage difference between the emitter-base of two BJT transistors with different current densities is obtained. The voltage difference has a first-order linear positive temperature coefficient, and the voltage difference is used to compensate the first-order negative temperature term of the emitter-base voltage of the BJT transistor.

4. A high-precision voltage-mode relaxation oscillator according to claim 1, characterized in that, The comparator adopts a comparison structure with three-terminal input and two-terminal output, and only uses one input reference voltage V REF .

5. A high-precision voltage-mode relaxation oscillator according to claim 1, wherein The digital control circuit uses one latch and two inverters.

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