Doherty amplifier

Abstract

The first transistor chip (3) has a first drain pad (5). The second transistor chip (4) has a second drain pad (6). A transmission line (9) and a first capacitor (C1) are formed on the resin substrate (1). A first bonding wire (7) connects the first drain pad (5) to one end of the transmission line (9). A second bonding wire (10) connects the second drain pad (6) to one end of the first capacitor (C1). An output terminal (OUT) is connected to the other end of the transmission line (9) and the other end of the first capacitor (C1). The capacitance value of the first capacitor (C1) is selected to resonate with the inductance of the second bonding wire (10).

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier. Background Art

[0002] In mobile communications, power amplifiers for transmission are generally required to have high efficiency and low distortion. In addition, in order to cope with the high-speed and large-capacity communications in recent years, modulated wave signals with high PAPR (Peak Average Power Ratio) are used. When a signal with high PAPR is amplified by a power amplifier, in order to meet the distortion standard, the power amplifier is operated at a lower average output power that is backed off relative to the saturated output power. Generally, the back-off amount and efficiency have an inverse relationship, so high efficiency cannot be expected when using high PAPR. However, the above problem can be solved by using an amplifier called a Doherty amplifier. Therefore, Doherty amplifiers are widely used, mainly in communication base stations.

[0003] In a Doherty amplifier, a main amplifier biased in class AB or class B and a peaking amplifier biased in class C are combined in parallel using a λ / 4 line. The λ / 4 line is placed at the output of one amplifier and at the input of the other. With large input signals, the two amplifiers operate identically and combine in phase, exhibiting characteristics similar to two combined amplifiers and achieving high saturation power. On the other hand, with small input signals, only the main amplifier operates, and the λ / 4 line connected to the output of the main amplifier functions as an impedance inverter, achieving high efficiency despite high load impedance. Consequently, the Doherty amplifier achieves high efficiency over a wide output power range.

[0004] However, the Doherty amplifier has the following problem: it is difficult to achieve broadband due to the frequency characteristics of the matching circuit from the transistors of the main amplifier and the peak amplifier to the synthesis point. In order to solve this problem, a Doherty amplifier is proposed: by using the parasitic capacitance Cds between the source terminal and the drain terminal of the transistor and a line with an electrical length shorter than the 90-degree delay line, a 90-degree delay circuit is equivalently formed. This circuit does not require the matching circuit from the transistor to the synthesis point required in the past, and can achieve broadband. In addition, a Doherty amplifier is proposed: using bonding wires in part of the 90-degree delay circuit, only transistors are formed on an expensive transistor chip, and the remaining circuits are formed on a cheap substrate such as a resin substrate, and they are connected with bonding wires (for example, refer to Patent Document 1). This can reduce costs.

[0005] Patent Document 1: Japanese Patent Application No. 2017-501662

[0006] However, there is a problem that the frequency characteristics of the Doherty amplifier deteriorate due to the inductance of the bonding wire. Specifically, two situations are conceivable depending on the position of the signal synthesis point.

[0007] The first is when the synthesis point is at the peak amplifier's pad end. In this case, the bonding wire toward the main amplifier and two bonding wires toward the output terminal are connected to the peak amplifier's pad. Due to the limited size of the pad, the load impedance becomes uneven depending on the position of the transistors that make up the peak amplifier, resulting in unbalanced operation of the transistors. This unbalanced operation can lead to reduced output power, gain, and efficiency, as well as oscillation. Furthermore, the proximity of the two bonding wires in the layout creates the problem of mutual inductance and frequency deviation of the load impedance.

[0008] The second type is when the synthesis point is at the end of a cable pad on a resin substrate. In this case, the inductance of the bonding wire causes frequency variations in the load impedance. These frequency variations and unbalanced operation hinder the high efficiency and wideband characteristics of the Doherty amplifier, and therefore require improvement. Summary of the Invention

[0009] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a Doherty amplifier capable of achieving high efficiency and wideband characteristics.

[0010] The Doherty amplifier of the present invention is characterized in that it comprises: a first transistor chip having a first drain pad; a second transistor chip having a second drain pad; a transmission line; a first capacitor; a first bonding wire connecting the first drain pad to one end of the transmission line; a second bonding wire connecting the second drain pad to one end of the first capacitor; and an output terminal connected to the other end of the transmission line and the other end of the first capacitor, the capacitance value of the first capacitor being selected to resonate with the inductance of the second bonding wire.

[0011] In the present invention, the capacitance value of the first capacitor is selected to resonate with the inductance of the second bonding wire. As a result, the synthesis point of the signals output from the first and second transistor chips is not at the second drain pad end of the second transistor chip, but is moved to the resin substrate on which the circuit is integrated. Therefore, even when the first and second bonding wires are used to connect the first and second transistor chips to the circuit on the resin substrate, the frequency characteristics do not deteriorate, and high efficiency and broadband characteristics can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a circuit diagram showing a Doherty amplifier according to the first embodiment.

[0013] Figure 2 1 is a layout diagram showing a Doherty amplifier according to the first embodiment.

[0014] Figure 3 This is a circuit diagram of the Doherty amplifier according to the first embodiment, in which the portion from the transistor to the combining point is extracted.

[0015] Figure 4 is with Figure 3 Equivalent circuit diagram.

[0016] Figure 5 is with Figure 3 Equivalent circuit diagram.

[0017] Figure 6 3 is a layout diagram showing an electromagnetic field calculation model of the structure of Comparative Example 1.

[0018] Figure 7 3 is a layout diagram of an electromagnetic field calculation model showing the structure of Comparative Example 2.

[0019] Figure 8 This is a layout diagram of an electromagnetic field calculation model showing the configuration of the first embodiment.

[0020] Figure 9 These are the frequency characteristics of the 3dB gain compression point and drain efficiency of the Doherty amplifier calculated using a commonly used nonlinear transistor model.

[0021] Figure 10 This is a graph showing the 3 dB gain compression point and the minimum value of the drain efficiency in the 400 MHz band.

[0022] Figure 11 This is a graph showing the 3 dB gain compression point and the minimum value of the drain efficiency in the 400 MHz band when the resonant frequency is normalized by the center frequency.

[0023] Figure 12 This is a circuit diagram showing a Doherty amplifier according to a second embodiment.

[0024] Figure 13 This is a layout diagram showing a Doherty amplifier according to the second embodiment.

[0025] Figure 14 This is a circuit diagram showing a Doherty amplifier according to a third embodiment.

[0026] Figure 15 This is a circuit diagram showing a Doherty amplifier according to a fourth embodiment.

[0027] Figure 16 This is a graph comparing the 3 dB gain compression point and drain efficiency of Embodiments 1 and 4.

[0028] Figure 17 This is a circuit diagram showing a Doherty amplifier according to a fifth embodiment. DETAILED DESCRIPTION

[0029] The Doherty amplifier according to the embodiment will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and overlapping descriptions may be omitted.

[0030] Implementation method 1.

[0031] Figure 1 This is a circuit diagram showing a Doherty amplifier according to the first embodiment. Figure 2 1 is a layout diagram showing a Doherty amplifier according to the first embodiment.

[0032] A die pad 2 is formed on a resin substrate 1. Transistor chips 3 and 4 are soldered to the die pad 2. Resin substrate 1 is made of a material such as FR4. The thickness of resin substrate 1 is 200 to 500 μm. By selecting a thinner substrate material, the thermal resistance of transistor chips 3 and 4 can be reduced. Furthermore, a thicker resin substrate 1 can improve circuit integration through multi-layer wiring, achieving miniaturization and cost reduction.

[0033] Transistor chips 3 and 4 are devices such as GaN-HEMTs. A main amplifier is formed on transistor chip 3. A peak amplifier is formed on transistor chip 4. Alternatively, transistor chips 3 and 4 may be the same chip.

[0034] Transistor chips 3 and 4 have drain pads 5 and 6, respectively. Transistor chips 3 and 4 have parasitic capacitances Csd1 and Csd2 between their sources and drains, respectively. Parasitic capacitances Csd1 and Csd2 include not only the intrinsic capacitance of the transistors but also capacitance at drain pads 5 and 6.

[0035] The drain pad 5 of transistor chip 3 is connected to a bias circuit 8 and one end of a transmission line 9 via a bonding wire 7. The drain pad 6 of transistor chip 4 is connected to one end of a capacitor C1 and a bias circuit 11 via a bonding wire 10. Multiple bonding wires 7 and 10 are arranged in parallel according to the size of drain pads 5 and 6. The height of bonding wires 7 and 10 relative to the surface of transistor chips 3 and 4 is preferably set to be relatively low, ranging from approximately 50 μm to 200 μm.

[0036] The other end of capacitor C1 is connected to the other end of transmission line 9 and to output terminal OUT via impedance conversion circuit 12 and capacitor C2. Capacitor C1 is, for example, a surface-mount multilayer ceramic capacitor. Bias circuits 8 and 11, transmission line 9, impedance conversion circuit 12, capacitors C1 and C2, and output terminal OUT are integrated on resin substrate 1.

[0037] Bias circuit 8 includes a 90-degree line 13 and a grounding capacitor C3. Bias circuit 11 includes a 90-degree line 14 and a grounding capacitor C4. However, bias circuits 8 and 11 are not limited to this configuration; any configuration that achieves the same function may be used. Impedance conversion circuit 12 also includes a 90-degree line, but this is not limiting; any configuration that can achieve the desired impedance conversion may be used.

[0038] The electrical length and characteristic impedance of transmission line 9 are set so that the electrical length from drain pad 5 to drain pad 6 is 90 degrees. The capacitance value of capacitor C1 is selected so that it resonates with the equivalent inductance of bonding wire 10 at the center frequency of the operating frequency. As a result, the synthesis point X of the signals output from transistor chips 3 and 4 is not located at the drain pad 6 end of transistor chip 4, but is moved to the resin substrate 1 on which the circuit is integrated.

[0039] Figure 3 This is a circuit diagram showing the Doherty amplifier according to the first embodiment, from the transistors to the combining point. Figure 4 and Figure 5 is with Figure 3 The capacitance value of capacitor C1 is set to resonate with the inductance of bonding wire 10, so Figure 3 Can Figure 4 In the equivalent circuit, the synthesis point X and the drain pad 6 end are the same node.

[0040] By appropriately selecting the length and width of the transmission line 9, it is possible to form a transmission line 9 with a 90-degree electrical length and a characteristic impedance Zc. Figure 5 The circuit shown is equivalent to the circuit shown. In addition, the selection of Zc is usually a design matter, but it is often set to the impedance corresponding to the real component among multiple impedances of power matching obtained by LP evaluation, etc. Figure 5 As can be seen, the electrical length from the drain pad 5 of the main amplifier to the signal combining point X is 90 degrees, and the electrical length from the drain pad 6 of the peak amplifier to the combining point X is 0 degrees. This is equivalent to the circuit diagram of a conventional Doherty amplifier. Therefore, even with a configuration where transistor chips 3 and 4 are connected to the circuit on resin substrate 1 using bonding wires 7 and 10, frequency characteristics do not deteriorate, achieving high efficiency and broadband characteristics.

[0041] In order to clarify the effects of the first embodiment, calculations were performed on the RF characteristics of the Doherty amplifier. Figure 6 3 is a layout diagram showing an electromagnetic field calculation model of the structure of Comparative Example 1. Figure 7 3 is a layout diagram of an electromagnetic field calculation model showing the structure of Comparative Example 2. Figure 8 This is a layout diagram of an electromagnetic field calculation model showing the configuration of Embodiment 1. In addition, the bias circuits 8 and 11 and the impedance conversion circuit 12 are omitted.

[0042] Figure 6 This is the case where the synthesis point X is on the resin substrate. Figure 7 This is the case where the synthetic point X is the drain pad 6 . Figure 6 、 Figure 7 The electrical length from drain pad 5 to drain pad 6 is designed to be 90 degrees. Calculations were performed using commonly used electromagnetic field calculation CAD software, taking into account the effects of layout. Resin substrate 1 has a substrate thickness of 330 μm and a relative dielectric constant of 4.3. Transmission line 9 has a line width of 150 μm. Transistor chips 3 and 4 have a thickness of 100 μm. Bonding wires 7 and 10 have a height of 150 μm relative to the top surfaces of transistor chips 3 and 4. Bonding wires 7 and 10 are arranged at 100 μm intervals. Figure 8 The capacitance value of capacitor C1 in the transmission line 9 is set to 2.9 pF. The line length of the transmission line 9 is adjusted so that the characteristic impedance Zc of the equivalent 90-degree delay circuit is 52Ω.

[0043] Figure 9 The frequency characteristics of the 3dB gain compression point and drain efficiency of the Doherty amplifier, calculated using a commonly used nonlinear transistor model, show that both the 3dB gain compression point (3dB Compression Output Power) and the drain efficiency (Drain Efficiency) are the widest and most efficient in implementation 1.

[0044] In the present embodiment, the electrical length from the drain pad 5 to the drain pad 6 is 90 degrees, but in practice, sufficiently good characteristics can be obtained if the electrical length is approximately ±10 degrees. Figure 10 This graph shows the 3dB gain compression point and the minimum drain efficiency in the 400MHz band. It can be seen that if the electrical length is within ±10 degrees relative to 90 degrees, the effect on the 3dB gain compression point is minimal, and the drain efficiency decreases by approximately -4 to 5 points.

[0045] Furthermore, the capacitor C1 and the bonding wire 10 do not strictly need to resonate at the center frequency of the operating frequency. Even if the resonant frequency deviates by approximately ±30% from the center frequency of the operating frequency, a sufficiently wide bandwidth and high efficiency can be achieved. Figure 11 This graph shows the 3dB gain compression point and the minimum drain efficiency in the 400MHz band, when the resonant frequency is normalized by the center frequency. It can be seen that even with a 30% deviation in the resonant frequency, the degradation in the 3dB gain compression point is only approximately 0.3dB, and the reduction in drain efficiency is less than 3 points, achieving sufficiently good characteristics.

[0046] In addition, in this embodiment, the description is based on the premise of a symmetric Doherty in which two transistors have the same size, but an asymmetric Doherty in which transistors have different sizes may also be used.

[0047] Implementation method 2.

[0048] Figure 12 This is a circuit diagram showing a Doherty amplifier according to a second embodiment. Figure 13 1 is a layout diagram showing a Doherty amplifier according to Embodiment 2. Compared with Embodiment 1, inductors L1 and L2 and capacitors C5 and C6 are added.

[0049] One end of inductor L1 is connected to the connection point between bonding wire 7 and transmission line 9. One end of inductor L2 is connected to the connection point between bonding wire 10 and capacitor C1. The other end of inductor L1 is grounded via capacitor C5. The other end of inductor L2 is grounded via capacitor C6.

[0050] Inductors L1 and L2 are, for example, surface-mount chip components or high-impedance lines formed on resin substrate 1. Capacitors C5 and C6 are used for RF grounding and are therefore selected to have sufficiently low impedance at the operating frequency. The inductance of inductors L1 and L2 is set to a value greater than the value that would cause parallel resonance with parasitic capacitances Csd1 and Csd2.

[0051] To implement Embodiment 1, the electrical length from drain pad 5 to drain pad 6 must be 90 degrees. Therefore, the capacitance values of parasitic capacitances Csd1 and Csd2 have an upper limit depending on the operating frequency. Therefore, if parasitic capacitances Csd1 and Csd2 are large, Embodiment 1 cannot be implemented.

[0052] In contrast, in the second embodiment, inductors L1 and L2 are connected in parallel with parasitic capacitances Csd1 and Csd2, effectively reducing the magnitude of the parasitic capacitance. Consequently, even when parasitic capacitances Csd1 and Csd2 are large, the same characteristics as those of the first embodiment can be achieved. By setting the inductances of inductors L1 and L2 as high as possible within the range of the circuit configuration, broadband characteristics can be achieved.

[0053] When constructing a bias circuit using 90-degree lines on resin substrate 1, even with the minimum achievable line width, it is impossible to achieve a sufficiently high characteristic impedance, which significantly increases circuit loss. To address this issue, connecting bias circuits 8 and 11 to the ground points of inductors L1 and L2 can suppress the increase in circuit loss caused by the connection of bias circuits 8 and 11.

[0054] As long as the capacitors C5 and C6 connected in parallel have a sufficiently low impedance in a frequency band twice the operating frequency, the bias circuits 8 and 11 may be omitted. In this case, the power supply is provided at the connection point between the capacitors C5 and C6 and the inductors L1 and L2.

[0055] Implementation method 3.

[0056] Figure 14 This is a circuit diagram of a Doherty amplifier according to Embodiment 3. Compared to Embodiment 2, the grounding of inductors L1 and L2 is made common by capacitor C5, and the bias circuit is made common by bias circuit 8. This allows for circuit miniaturization. Other configurations and effects are the same as those of Embodiment 2.

[0057] Implementation method 4.

[0058] Figure 15 This is a circuit diagram of a Doherty amplifier according to Embodiment 4. Compared to Embodiment 1, a parallel resonant circuit 15 consisting of capacitors C7 and C8 and inductor L3 is connected to the synthesis point X. Capacitor C8 is a grounding capacitor, and is selected to have sufficiently low impedance within the operating frequency band. Capacitor C7 and inductor L3 are selected so as to achieve parallel resonance at the center frequency of the operating frequency.

[0059] The frequency characteristics of parallel resonant circuit 15 have opposite polarity to the frequency characteristics of the equivalent 90-degree delay circuit from drain pad 5 to synthesis point X. Consequently, the circuit's frequency characteristics are reduced. Therefore, Embodiment 4 can be expected to exhibit characteristics with a wider bandwidth than Embodiment 1. The functions and effects of this circuit have already been demonstrated in prior art, so detailed descriptions are omitted. To achieve this effect, parallel resonant circuit 15 must be connected to the synthesis point of the signal. Therefore, the synthesis point is located on resin substrate 1, not at the drain pad end. This allows for achieving this without causing unbalanced operation, which is advantageous compared to prior art.

[0060] In order to clarify the effects of the fourth embodiment, the RF characteristics of the Doherty amplifier were calculated. Figure 16 This graph compares the 3dB gain compression point and drain efficiency of Embodiments 1 and 4. In Embodiment 4, capacitor C7 is 1.67pF, capacitor C8 is 7pF, and inductor L3 is 1.294nH. It can be seen that both the 3dB gain compression point and drain efficiency of Embodiment 4 are wider and more efficient than those of Embodiment 1.

[0061] This embodiment can be combined with the structures of Embodiments 2 or 3. Furthermore, if capacitor C7 is a surface-mount chip capacitor, circuit loss can be reduced by connecting two chip capacitors in parallel. The sum of the capacitance values of the two chip capacitors is selected to be the same as that of capacitor C7.

[0062] Implementation method 5.

[0063] Figure 17 This is a circuit diagram of a Doherty amplifier according to Embodiment 5. Compared to Embodiment 1, the connection position of bias circuit 8 is changed to synthesis point X. When the impedance of bias circuit 8 is observed from synthesis point X, it exhibits the same frequency characteristics as the parallel resonant circuit of Embodiment 4. Therefore, the frequency characteristics of the circuit are reduced due to the opposite polarity to the frequency characteristics of the 90-degree delay circuit from drain pad 5 to synthesis point X. This achieves the same effects as Embodiment 4, while also eliminating the parallel resonant circuit in Embodiment 4, enabling miniaturization. Furthermore, this embodiment can be combined with the structure of Embodiment 2.

[0064] Description of Reference Numerals

[0065] 1…resin substrate; 3…transistor chip (first transistor chip); 4…transistor chip (second transistor chip); 5…drain pad (first drain pad); 6…drain pad (second drain pad); 7…bonding wire (first bonding wire); 8…bias circuit (first bias circuit); 9…transmission line; 10…bonding wire (second bonding wire); 11…bias circuit (second bias circuit); 15…parallel resonant circuit; C1…capacitor (first capacitor); C5…capacitor (second capacitor); C6…capacitor (third capacitor); L1…inductor (first inductor); L2…inductor (second inductor); OUT…output terminal.

Claims

1. A Doherty amplifier, characterized in that: have: A first transistor chip having a first drain pad; a second transistor chip having a second drain pad; Resin substrate; a transmission line formed on the resin substrate; a first capacitor formed on the resin substrate; a first bonding wire connecting the first drain pad to one end of the transmission line; a second bonding wire connecting the second drain pad to one end of the first capacitor; and an output terminal connected to the other end of the transmission line and the other end of the first capacitor, The capacitance value of the first capacitor is selected to resonate with the inductance of the second bond wire, The parasitic capacitance between the source and the drain of the first transistor chip, the parasitic capacitance between the source and the drain of the second transistor chip, the transmission line, and the first bonding wire equivalently constitute a 90-degree delay circuit.

2. The Doherty amplifier according to claim 1, wherein: A resonant frequency of the first capacitor and the second bonding wire is within a range of ±30% of a center frequency of an operating frequency of the Doherty amplifier.

3. The Doherty amplifier according to claim 1 or 2, characterized in that Also features: a first bias circuit connected to one end of the transmission line; A second bias circuit is connected to one end of the first capacitor.

4. The Doherty amplifier according to claim 1 or 2, characterized in that Also features: a first inductor having one end connected to a connection point between the first bonding wire and the transmission line and the other end connected to ground via a second capacitor; A second inductor has one end connected to a connection point between the second bonding wire and the first capacitor, and the other end connected to ground via a third capacitor. The first inductor has an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the first transistor chip at an operating frequency. The second inductor has an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the second transistor chip at the operating frequency. The first inductor and the second inductor, together with the parasitic capacitance between the source and the drain of the first transistor chip, the parasitic capacitance between the source and the drain of the second transistor chip, the transmission line and the first bonding wire, constitute the 90-degree delay circuit.

5. The Doherty amplifier according to claim 4, wherein: Also features: a first bias circuit connected to the other end of the first inductor; A second bias circuit is connected to the other end of the second inductor.

6. The Doherty amplifier according to claim 1 or 2, characterized in that Also features: a first inductor having one end connected to a connection point between the first bonding wire and the transmission line and the other end connected to ground via a second capacitor; a second inductor having one end connected to a connection point between the second bonding wire and the first capacitor and the other end connected to ground via the second capacitor; a bias circuit connected to the other end of the first inductor and the other end of the second inductor, The first inductor has an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the first transistor chip at an operating frequency. The second inductor has an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the second transistor chip at the operating frequency. The first inductor and the second inductor, together with the parasitic capacitance between the source and the drain of the first transistor chip, the parasitic capacitance between the source and the drain of the second transistor chip, the transmission line, and the first bonding wire, constitute the 90-degree delay circuit.

7. The Doherty amplifier according to any one of claims 1, 2 and 5, characterized in that: A parallel resonant circuit is further provided. The parallel resonant circuit is connected between the other end of the transmission line and the other end of the first capacitor and a ground point, and performs parallel resonance at a center frequency of the operating frequency of the Doherty amplifier.

8. The Doherty amplifier according to claim 1 or 2, characterized in that Also features: a first bias circuit connected to the other end of the transmission line and the other end of the first capacitor; A second bias circuit is connected to one end of the first capacitor.

9. A Doherty amplifier, characterized in that have: A first transistor chip having a first drain pad; a second transistor chip having a second drain pad; Resin substrate; a transmission line formed on the resin substrate; a first capacitor formed on the resin substrate; a first bonding wire connecting the first drain pad to one end of the transmission line; a second bonding wire connecting the second drain pad to one end of the first capacitor; an output terminal connected to the other end of the transmission line and the other end of the first capacitor; a first inductor having one end connected to a connection point between the first bonding wire and the transmission line and the other end connected to ground via a second capacitor, and having an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the first transistor chip at an operating frequency; as well as a second inductor having one end connected to a connection point between the second bonding wire and the first capacitor and the other end connected to ground via a third capacitor, and having an inductance greater than an inductance that resonates in parallel with the parasitic capacitance between the source and drain of the second transistor chip at the operating frequency; The capacitance value of the first capacitor is selected to resonate with the inductance of the second bond wire, The first inductor effectively reduces the magnitude of the parasitic capacitance between the source and the drain of the first transistor chip. The second inductor effectively reduces the magnitude of the parasitic capacitance between the source and the drain of the second transistor chip. The parasitic capacitance between the source and the drain of the first transistor chip, the parasitic capacitance between the source and the drain of the second transistor chip, the transmission line, and the first bonding wire equivalently constitute a 90-degree delay circuit.

10. The Doherty amplifier according to claim 9, characterized in that Also features: a first bias circuit connected to the other end of the first inductor; A second bias circuit is connected to the other end of the second inductor.

11. The Doherty amplifier according to claim 9 or 10, characterized in that A resonant frequency of the first capacitor and the second bonding wire is within a range of ±30% of a center frequency of an operating frequency of the Doherty amplifier.

12. The Doherty amplifier according to claim 9 or 10, characterized in that A parallel resonant circuit is further provided. The parallel resonant circuit is connected between the other end of the transmission line and the other end of the first capacitor and a ground point, and performs parallel resonance at a center frequency of the operating frequency of the Doherty amplifier.

13. A Doherty amplifier, characterized in that: have: A first transistor chip having a first drain pad; a second transistor chip having a second drain pad; Resin substrate; a transmission line formed on the resin substrate; a first capacitor formed on the resin substrate; a first bonding wire connecting the first drain pad to one end of the transmission line; a second bonding wire connecting the second drain pad to one end of the first capacitor; an output terminal connected to the other end of the transmission line and the other end of the first capacitor; a first inductor having one end connected to a connection point between the first bonding wire and the transmission line and the other end connected to ground via a second capacitor, and having an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between a source and a drain of the first transistor chip at an operating frequency; a second inductor having one end connected to a connection point between the second bonding wire and the first capacitor and the other end connected to ground via the second capacitor, and having an inductance greater than an inductance that resonates in parallel with a parasitic capacitance between the source and the drain of the second transistor chip at the operating frequency; as well as a bias circuit connected to the other end of the first inductor and the other end of the second inductor, The capacitance value of the first capacitor is selected to resonate with the inductance of the second bond wire, The first inductor effectively reduces the magnitude of the parasitic capacitance between the source and the drain of the first transistor chip. The second inductor effectively reduces the magnitude of the parasitic capacitance between the source and the drain of the second transistor chip. The parasitic capacitance between the source and the drain of the first transistor chip, the parasitic capacitance between the source and the drain of the second transistor chip, the transmission line, and the first bonding wire equivalently constitute a 90-degree delay circuit.

14. The Doherty amplifier according to claim 13, wherein: A resonant frequency of the first capacitor and the second bonding wire is within a range of ±30% of a center frequency of an operating frequency of the Doherty amplifier.

15. The Doherty amplifier according to claim 13 or 14, characterized in that A parallel resonant circuit is further provided. The parallel resonant circuit is connected between the other end of the transmission line and the other end of the first capacitor and a ground point, and performs parallel resonance at a center frequency of the operating frequency of the Doherty amplifier.

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