Pixel signal output method and readout circuit of infrared focal plane detector

Abstract

The present application relates to a pixel signal output method and a readout circuit for an infrared focal plane detector. The method includes: dividing the pixel integration time into a pixel combined integration time and a pixel independent integration time; completing a combined integration of all pixels in each pixel block within the pixel combined integration time; completing an independent integration of each pixel in each pixel block within the pixel independent integration time; obtaining a corresponding combined integration signal based on the combined integration, and obtaining a corresponding independent integration signal based on the independent integration; performing an algorithm based on the combined integration signal and the independent integration signal to output a pixel digital signal. The solution provided by the present invention can improve the charge processing capability and detection sensitivity of infrared focal plane detectors with small pixel areas.

Description

Technical Field

[0001] The present application relates to the field of infrared detection technology, and in particular to a pixel signal output method and a readout circuit of an infrared focal plane detector. Background Art

[0002] Infrared focal plane detectors (IFPDs) convert invisible infrared radiation into measurable signals (such as voltage and current). They offer advantages such as low detection rates, strong anti-interference capabilities, high environmental adaptability, strong target recognition capabilities, and compact size and light weight. Consequently, they are widely used in fields such as geological resource exploration, astronomical exploration, and medical treatment. In recent years, the increasing application of infrared technology has led to the demand for IFPDs with high resolution, high sensitivity, ultra-high charge handling capabilities, and intelligent miniaturization. This has driven the continuous development of IFPDs.

[0003] Digital infrared focal plane detectors, a typical third-generation infrared focal plane detector, are distinguished by their use of a digital infrared readout circuit that converts the input photocurrent signal into a digital signal with strong interference immunity at the detector's input source. The readout circuit then performs computations on the digital signal and ultimately outputs the detected signal in a digital format. This reduces the complex signal processing from the infrared focal plane detector to the circuit board level, eliminating the potential for noise introduction from external circuitry. Furthermore, the digital infrared readout circuit is less restricted by pixel area, enabling the detector to achieve exceptionally high charge processing capabilities with long integration times, significantly improving detector sensitivity. Furthermore, the digital signal is more flexible in participating in on-chip computations, making it easier to implement a large number of on-chip signal processing functions within the digital infrared focal plane readout circuit, enabling intelligent and miniaturized infrared focal plane detectors. Furthermore, the long integration time significantly improves the detector's charge processing capacity, signal-to-noise ratio, and sensitivity. Currently, the development of pixel-level digital infrared detectors is in full swing. The realization of pixel-level digital readout circuits is due to the continuous improvement and maturity of CMOS integrated circuit manufacturing processes and the continuous reduction of process feature sizes, which also makes it possible for pixel-level digital readout circuits to have large charge processing capabilities, high resolution, and high integration.

[0004] Digital infrared detectors with small pixel areas have small photocurrents and need to obtain more charge signals by extending the integration time to achieve higher detection sensitivity. However, digital infrared focal plane detectors with small pixel areas are not applicable for those with specific frame rate requirements and cannot obtain more charge signals and high sensitivity by extending the integration time. Summary of the Invention

[0005] The present application provides a pixel signal output method and a readout circuit for an infrared focal plane detector to solve the technical problem of poor charge processing capability and detection sensitivity of a small pixel area digital infrared focal plane detector that cannot obtain more charge signals and high sensitivity by extending the integration time when a specific frame rate requirement is met.

[0006] In a first aspect, the present application provides a pixel signal output method, the method comprising:

[0007] The pixel integration time is divided into pixel combined integration time and pixel independent integration time;

[0008] Complete the merged integration of all pixels in each pixel block within the pixel merge integration time;

[0009] Complete the independent integration of each pixel in each pixel block within the independent pixel integration time;

[0010] Obtaining a corresponding combined integral signal according to the combined integral, and obtaining a corresponding independent integral signal according to the independent integral;

[0011] An algorithm operation is performed based on the combined integral signal and the independent integral signal to output a pixel digital signal.

[0012] In one embodiment, before completing the combined integration of all pixels in each pixel block within the pixel combined integration time, the method further includes:

[0013] The adjacent 2*2 pixels are regarded as a pixel block.

[0014] In one embodiment, obtaining a corresponding combined integral signal according to the combined integral includes:

[0015] According to the combined integration, an analog-to-digital converter is used to obtain a corresponding combined integration signal.

[0016] In one embodiment, obtaining a corresponding independent integral signal according to the independent integral comprises:

[0017] According to the independent integration, an analog-to-digital converter is used to obtain a corresponding independent integration signal.

[0018] In one embodiment, performing an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal includes:

[0019] The combined integrated signal of each pixel block is used as a reference signal;

[0020] The independent integrated signal of each pixel in each pixel block is used as the difference signal;

[0021] The reference signal and the difference signal are operated and a pixel digital signal of each pixel is output.

[0022] In one embodiment, after outputting the pixel digital signal, the method further includes:

[0023] Blind pixel replacement and non-uniformity correction algorithm are designed for the pixel digital signal, and the replaced and corrected pixel digital signal is output.

[0024] In one embodiment, the blind pixel replacement algorithm design includes an adjacent pixel replacement method.

[0025] In one embodiment, the non-uniformity correction algorithm design includes a gain compensation method.

[0026] In a second aspect, the present application provides a readout circuit for an infrared focal plane detector, the readout circuit for the infrared focal plane detector comprising:

[0027] A dividing circuit, used for dividing the pixel integration time into a pixel combined integration time and a pixel independent integration time;

[0028] A merging circuit, used for completing the merging integration of all pixels in each pixel block within the pixel merging integration time;

[0029] An independent circuit is used to complete the independent integration of each pixel in each pixel block within the independent pixel integration time;

[0030] an obtaining circuit, configured to obtain a corresponding combined integral signal according to the combined integral, and obtain a corresponding independent integral signal according to the independent integral;

[0031] The output circuit is used to perform an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal.

[0032] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0033] The method provided in the embodiment of the present application can improve the charge processing capability and detection sensitivity of an infrared focal plane detector with a small pixel area. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 A schematic flow chart of a pixel signal output method provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of a 2×2 pixel block combination allocation for a full focal plane array provided in an application embodiment of the present application;

[0038] Figure 3 A schematic diagram showing the principle of integration of adjacent 2×2 pixel blocks provided in an embodiment of the present application;

[0039] Figure 4 A schematic structural diagram of an infrared focal plane detector provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] Figure 1 This is a flow chart of a pixel signal output method provided in an embodiment of the present application. Figure 1 As shown, the method includes:

[0042] Step 101: dividing the pixel integration time into pixel combined integration time and pixel independent integration time;

[0043] Step 102: completing the merging integration of all pixels in each pixel block within the pixel merging integration time;

[0044] Step 103: completing independent integration of each pixel in each pixel block within the pixel independent integration time;

[0045] Step 104: obtaining a corresponding combined integral signal according to the combined integral, and obtaining a corresponding independent integral signal according to the independent integral;

[0046] Step 105: performing an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal.

[0047] The method of this embodiment is applicable to a small pixel area infrared focal plane readout circuit in which the integration time cannot be extended due to a fixed frame rate.

[0048] Specifically, this embodiment divides the pixel integration time into pixel combined integration time and pixel independent integration time; within the pixel combined integration time, the combined integration of all pixels in each pixel block is completed; within the pixel independent integration time, the independent integration of each pixel in each pixel block is completed; the pixel digital signal output of the pixel is realized through combined integration and independent integration.

[0049] Here, the allocation of pixel merging integration time and pixel independent integration time can be set based on the actual application conditions of the focal plane detector, such as the size of the detector photocurrent signal, the number of noise electrons, the detector sensitivity, etc.

[0050] Specifically, in one embodiment, before completing the combined integration of all pixels in each pixel block within the pixel combined integration time, the method further includes:

[0051] The adjacent 2*2 pixels are regarded as a pixel block.

[0052] Of course, in actual applications, the size of the pixel block can be set based on the actual situation and is not limited to the size of adjacent 2*2 pixels.

[0053] In one embodiment, obtaining a corresponding combined integral signal according to the combined integral includes:

[0054] According to the combined integration, an analog-to-digital converter is used to obtain a corresponding combined integration signal.

[0055] Here, a charge counting ADC can be used to complete the digital signal conversion. Each pixel block is connected to a charge counting ADC, and the combined integrated signal of each pixel block is stored in the charge counting ADC.

[0056] In one embodiment, obtaining a corresponding independent integral signal according to the independent integral comprises:

[0057] According to the independent integration, an analog-to-digital converter is used to obtain a corresponding independent integration signal.

[0058] In this case, you can choose a charge counting ADC to complete the digital signal conversion. Each pixel is connected to a charge counting ADC, and the independent integrated signal of each pixel is stored in the charge counting ADC.

[0059] In one embodiment, performing an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal includes:

[0060] The combined integrated signal of each pixel block is used as a reference signal;

[0061] The independent integrated signal of each pixel in each pixel block is used as the difference signal;

[0062] The reference signal and the difference signal are operated and a pixel digital signal of each pixel is output.

[0063] In practical applications, to achieve ultra-high charge processing capability for each pixel within a limited integration time, the reference signal can be added to the difference signal, and the added signal can be used as the pixel digital signal for each pixel. During output, the pixel digital signal for each pixel in the pixel block can be output sequentially. This output can be performed via an output bus.

[0064] In one embodiment, after outputting the pixel digital signal, the method further includes:

[0065] Blind pixel replacement and non-uniformity correction algorithm are designed for the pixel digital signal, and the replaced and corrected pixel digital signal is output.

[0066] Specifically, the blind pixel replacement algorithm design includes an adjacent pixel replacement method.

[0067] Blind pixels are replaced by adjacent pixel replacement, and blind pixel positioning is achieved through the Serial Peripheral Interface (SPI). Using the SPI to replace blind pixels reduces the area consumed by the physical circuit layout.

[0068] In addition, the non-uniformity correction algorithm design includes a gain compensation method. The non-uniformity correction algorithm design processes the digitized integrated signals of all pixels in the full array and then outputs them. The use of the non-uniformity correction algorithm can effectively improve the consistency of the integrated signals of each pixel in the infrared detector.

[0069] The method provided in this embodiment can further improve the charge processing capability and detection sensitivity of an infrared focal plane detector with a small pixel area within a limited integration time.

[0070] The pixel signal output method provided in the embodiment of the present application divides the pixel integration time into a pixel combined integration time and a pixel independent integration time; within the pixel combined integration time, the combined integration of all pixels in each pixel block is completed; within the pixel independent integration time, the independent integration of each pixel in each pixel block is completed; a corresponding combined integration signal is obtained based on the combined integration, and a corresponding independent integration signal is obtained based on the independent integration; an algorithm is performed based on the combined integration signal and the independent integration signal to output a pixel digital signal. The solution provided in the embodiment of the present application can improve the charge processing capability and detection sensitivity of infrared focal plane detectors with small pixel areas.

[0071] Hereinafter, the present application will be described in detail with reference to application examples.

[0072] This embodiment provides a method for implementing a small pixel area digital infrared focal plane readout circuit. This embodiment adopts a pixel integration method of pixel time-sharing multiplexing merging-independent integration, and completes pixel AD conversion through a charge packet counting ADC. Finally, combined with on-chip signal processing technology, it realizes a readout circuit design of an infrared focal plane detector with ultra-large charge processing capacity, high sensitivity, and high integration. This design method is not only easy to understand in principle, but also simpler in subsequent layout design, and very easy to implement.

[0073] Specifically, the implementation method of the small pixel area digital infrared focal plane readout circuit may include the following steps:

[0074] Step A: Rationally divide the integration time of the infrared focal plane detector (i.e., each pixel) into two parts: the integration time of pixel combined integration and the integration time of independent integration;

[0075] Step B: During the merging integration time, the four adjacent pixels in the 2×2 pixel block are merged and integrated and the digital conversion is completed;

[0076] Step C: After the combined integral, each pixel in the focal plane is individually integrated and digitally converted within the independent integration time;

[0077] Step D: Using 2×2 pixels as the processing unit, the digital signals of the combined integral and independent integral of each pixel are cumulatively processed;

[0078] Step E: Perform blind pixel replacement and non-uniformity correction algorithm design on the pixels, and output the replaced and corrected pixel digital signals in sequence.

[0079] In step A, the limited focal plane integration time is rationally divided into two parts: the first part is the combined integration time for a 2×2 pixel block consisting of four adjacent pixels, and the second part is the independent integration time for each pixel. When allocating these two time parts, the actual application conditions of the focal plane detector, including the detector photocurrent signal size, noise electron count, and detector sensitivity, should be fully considered. Furthermore, the pixel block size can be varied during the specific design based on factors such as detector size, pixel spacing, and target characteristics; it is not limited to a 2×2 pixel block size.

[0080] In step B, the four adjacent pixels in the 2×2 pixel block are combined and integrated within the combined integration time, and the combined integration signals of the four pixels in each 2×2 pixel block are converted into digital signals through a charge counting ADC.

[0081] Wherein, in said step C, within the independent integration time, each pixel is independently integrated, and the respective integrated signals are converted into digital signals through a multi-bit counter in a charge counting ADC. In this step, each pixel has a separate set of ADCs.

[0082] In addition, in step D, taking the 2×2 pixels that are combined and integrated in step B as a unit, the digitized signal of the combined integration of the four adjacent pixels is used as a common reference signal for the four pixels, and the digitized signal of the independent integration of the four pixels is used as a difference signal. After the reference signal and the difference signal of each pixel are calculated, the result is used as the pixel digital output signal of each pixel.

[0083] In addition, in step E, a blind pixel replacement algorithm is designed to replace the blind pixel signal by replacing adjacent pixels. Blind pixel positioning is achieved via a serial peripheral interface (SPI). In step E, a non-uniformity correction algorithm is also designed. The digitized integrated signal of all pixels in the full array is processed and outputted by the algorithm. Using this non-uniformity correction algorithm can effectively improve the consistency of the integrated signal of each pixel in the infrared detector.

[0084] According to the implementation method of the small pixel area digital infrared focal plane readout circuit of the present invention, time-sharing multiplexing merging and independent integration of each pixel are realized within a limited integration time. The integrated signal of each pixel completes low-noise, high-linearity AD conversion and accumulation operation of the combined signal and the independent signal within the pixel unit. The blind pixel replacement and non-uniformity correction functions are realized through algorithm design, further improving the charge processing capability, sensitivity and integration of the small pixel area infrared detector, and providing the possibility for the realization of very high sensitivity infrared focal plane detector within a limited integration time.

[0085] Also, see Figure 2 and Figure 3 , Figure 2 Block diagram for the combination and allocation of 2×2 pixel blocks for the full array of focal planes; Figure 3 A schematic block diagram illustrating the principle of integration of adjacent 2×2 pixel blocks designed for the present invention.

[0086] like Figure 2 As shown in the figure, four pixels in adjacent rows / columns form a 2×2 pixel block. The combined integral takes the 2×2 pixel block as the integration unit. The digital signal of the combined integral is used as the reference signal of the four pixels in the pixel block, and the digital signal of the independent integration is used as the difference signal of each independent pixel. The weight distribution between the reference signal and the difference signal should be considered according to the specific application context during design.

[0087] like Figure 3 As shown in the figure, in order to improve the charge processing capability of each pixel within a limited integration time and ensure that the readout circuit chip has ultra-large charge processing capability and high sensitivity, the following specific measures are taken in the design:

[0088] First, the finite integration time is divided into two parts: combined integration time and independent integration time.

[0089] Secondly, adjacent 2×2 pixels are combined and integrated as a pixel block. During the combined integration, the integrated signals of the four pixels pass through the same low-noise, high-linearity charge counting ADC to convert the analog domain current signal into a digital domain signal, and the combined integrated digitized signal is stored in a multi-bit register M as the reference signal of the four pixels.

[0090] Again, within the independent integration time, each pixel is integrated separately, and each pixel integration signal is converted into a digital domain signal through its own low-noise, high-linearity charge counting ADC, and each independent integration signal is stored in the multi-bit registers N1 to N4 respectively.

[0091] Then, in order to achieve ultra-large charge processing capability for each pixel within a limited integration time, the digital domain signal in register M is added to the digital domain signals in registers N1 to N4 respectively, and the added signals are output from the output bus in sequence as the output signals of the four pixels.

[0092] Finally, the blind pixel replacement and non-uniformity correction functions are realized through algorithm design combined with the serial external interface (SPI); in order to reduce the area consumption of the circuit physical implementation layout, the blind pixel replacement function adopts the adjacent pixel replacement method, and the non-uniformity correction algorithm adopts the gain compensation method.

[0093] This embodiment implements a small-pixel-area digital infrared focal plane readout circuit. This circuit implements time-sharing merging and independent integration for each pixel within a small pixel area, simultaneously completing A / D conversion and integrating the digitally integrated signals. It also utilizes on-chip signal processing algorithms to implement blind pixel replacement and non-uniformity correction. This significantly improves the charge handling capability and signal-to-noise ratio of the infrared focal plane detector within a limited integration time, resulting in higher sensitivity and greater integration for small-pixel-area infrared focal plane detectors. Furthermore, this design method is simple to understand, operate, and implement.

[0094] This embodiment provides a readout circuit of an infrared focal plane detector, and the readout circuit of the infrared focal plane detector includes:

[0095] A dividing circuit, used for dividing the pixel integration time into a pixel combined integration time and a pixel independent integration time;

[0096] A merging circuit, used for completing the merging integration of all pixels in each pixel block within the pixel merging integration time;

[0097] An independent circuit is used to complete the independent integration of each pixel in each pixel block within the independent pixel integration time;

[0098] an obtaining circuit, configured to obtain a corresponding combined integral signal according to the combined integral, and obtain a corresponding independent integral signal according to the independent integral;

[0099] The output circuit is used to perform an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal.

[0100] like Figure 4 As shown, the embodiment of the present application provides an infrared focal plane detector, including a processor 111, a communication interface 112, a memory 113 and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114.

[0101] In one embodiment of the present application, the processor 111 implements the steps of the method provided by any of the aforementioned method embodiments.

[0102] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0103] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A pixel signal output method, characterized in that: Applied to a digital infrared focal plane detector with a small pixel area where the integration time cannot be extended due to a fixed frame rate, the method comprises: The pixel integration time is divided into pixel combined integration time and pixel independent integration time; Determine the number of pixels in a pixel block based on the detector size, pixel spacing, and detection target characteristics; Complete the merged integration of all pixels in each pixel block within the pixel merge integration time; Complete the independent integration of each pixel in each pixel block within the independent pixel integration time; Obtaining a corresponding combined integral signal according to the combined integral, and obtaining a corresponding independent integral signal according to the independent integral; Performing an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal; Perform blind pixel replacement and non-uniformity correction algorithm design on the pixel digital signal, and output the replaced and corrected pixel digital signal; the blind pixel replacement algorithm design includes an adjacent pixel replacement method, which replaces the blind pixel signal by the adjacent pixel replacement method, and blind pixel positioning is achieved through a serial peripheral interface (SPI); the non-uniformity correction algorithm design includes a gain compensation method, which processes the digitized integrated signals of all pixels in the full array through the algorithm and outputs them; The performing of an algorithm operation based on the combined integral signal and the independent integral signal to output a pixel digital signal comprises: The combined integrated signal of each pixel block is used as a reference signal; The independent integrated signal of each pixel in each pixel block is used as the difference signal; The reference signal and the difference signal are operated and a pixel digital signal of each pixel is output.

2. The method according to claim 1, characterized in that The method of determining the number of pixels in a pixel block according to the detector size, pixel spacing, and detection target characteristics includes: The adjacent 2*2 pixels are regarded as a pixel block.

3. The method according to claim 1, characterized in that The obtaining of a corresponding combined integral signal according to the combined integral comprises: According to the combined integration, an analog-to-digital converter is used to obtain a corresponding combined integration signal.

4. The method according to claim 1, wherein The obtaining of the corresponding independent integral signal according to the independent integral comprises: According to the independent integration, an analog-to-digital converter is used to obtain a corresponding independent integration signal.

5. A readout circuit for an infrared focal plane detector, characterized in that: The invention is applied to a digital infrared focal plane detector with a small pixel area, where the integration time cannot be extended due to a fixed frame rate. The readout circuit of the infrared focal plane detector includes: A dividing circuit, used for dividing the pixel integration time into a pixel combined integration time and a pixel independent integration time; A determination circuit for determining the number of pixels in a pixel block based on detector size, pixel spacing, and detection target characteristics; A merging circuit, used for completing the merging integration of all pixels in each pixel block within the pixel merging integration time; An independent circuit is used to complete the independent integration of each pixel in each pixel block within the independent pixel integration time; an obtaining circuit, configured to obtain a corresponding combined integral signal according to the combined integral, and obtain a corresponding independent integral signal according to the independent integral; an output circuit, configured to perform an algorithm operation based on the combined integral signal and the independent integral signal, and output a pixel digital signal; A correction circuit is configured to perform blind pixel replacement and non-uniformity correction algorithm design on the pixel digital signal, and output the replaced and corrected pixel digital signal; the blind pixel replacement algorithm design includes an adjacent pixel replacement method, which replaces the blind pixel signal using the adjacent pixel replacement method, and blind pixel positioning is achieved through a serial peripheral interface (SPI); the non-uniformity correction algorithm design includes a gain compensation method, which processes the digitized integrated signals of all pixels in the entire array through the algorithm and outputs them; The output circuit is specifically used to use the combined integral signal of each pixel block as a reference signal; use the independent integral signal of each pixel in each pixel block as a difference signal; operate on the reference signal and the difference signal, and output the pixel digital signal of each pixel.

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