Message Processing Method, Apparatus, Device, and Readable Medium for a Flash Channel Controller

Abstract

The present invention discloses a message processing method for a flash channel controller, including the following steps: receiving a read request message, and sending a memory address application message to a cache controller based on the read request message; performing a read operation based on the read request message, and determining whether the application for a memory address to the cache controller is successful; and in response to the successful application for a memory address to the cache controller, performing a data transfer operation based on the memory address. The present invention also discloses a message processing device, a computer device, and a readable storage medium for a flash channel controller. The present invention adopts the method of applying for a memory address in advance, adds a judgment on whether the memory address application is successful before data transfer, realizes parallel processing of read commands and memory address applications, saves the memory address application time, reduces the read time consumption, and improves the product performance.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and particularly to a message processing method, apparatus, device, and readable medium for a flash channel controller. Background Art

[0002] The process for an existing FCC (Flash channel controller) to implement a command includes:

[0003] Receiving and parsing a message by a LUN (Logical Unit Number), and initializing a context according to the message content;

[0004] If the flash channel controller needs to apply for a memory address (buffer) by itself, a content address application request is sent to a buffer manager (BM);

[0005] The buffer manager applies for a memory address and returns the applied memory address to the flash channel controller;

[0006] The flash channel controller continues to execute the corresponding command according to the message content;

[0007] After the execution is completed, a completion message is returned, and the next request is continuously obtained and processed.

[0008] During the period from applying for a memory address to receiving a memory address application completion message, the flash channel controller is in an idle state, that is, it must wait for the memory address application to be completed before continuing to execute the command. This greatly increases the total time consumed by the flash channel controller to process requests, has a greater impact on the clock cycles (Latency) required for the flash channel controller to fully execute an instruction, and further affects other key performance indicators of the product, such as IOPS (Input / Output Operations Per Second) and bandwidth. Summary of the Invention

[0009] In view of this, the purpose of the embodiments of the present invention is to provide a message processing method, apparatus, device, and readable medium for a flash channel controller. By adopting the method of applying for a memory address in advance and adding a judgment on whether the memory address application is successful before data transmission, parallel processing of read commands and memory address applications is realized, the memory address application time is saved, the read time consumption is reduced, and the product performance is improved.

[0010] For the above purposes, an aspect of an embodiment of the present invention provides a message processing method for a flash channel controller, including the following steps: receiving a read request message, and sending a memory address application message to a cache controller based on the read request message; performing a read operation based on the read request message, and determining whether the application for a memory address to the cache controller is successful; and in response to the successful application for a memory address to the cache controller, performing a data transfer operation based on the memory address.

[0011] In some embodiments, the method further includes: in response to the unsuccessful application for a memory address to the cache controller, returning a memory address application failure exception.

[0012] In some embodiments, the method further includes: in response to the unsuccessful application for a memory address to the cache controller, re-sending a memory address application message to the cache controller based on the read request message, and re-determining whether the application for a memory address to the cache controller is successful.

[0013] In some embodiments, receiving a read request message and sending a memory address application message to a cache controller based on the read request message includes: receiving a read request message, and checking whether the read request message is legal; if the read request message is legal, sending a memory address application message to the cache controller based on the read request message.

[0014] In some embodiments, performing a read operation based on the read request message and determining whether the application for a memory address to the cache controller is successful includes: performing a read operation based on the read request message, and determining whether the read operation is completed; if the read operation is completed, further determining whether the application for a memory address to the cache controller is successful.

[0015] In some embodiments, determining whether the read operation is completed includes: determining whether data has been transferred from memory to a register; in response to the data being transferred from memory to a register, confirming that the read operation is completed.

[0016] In some embodiments, the method further includes: if the read operation is not completed, waiting for the read operation to complete and then further determining whether the application for a memory address to the cache controller is successful.

[0017] Another aspect of an embodiment of the present invention further provides a message processing device for a flash channel controller, including: a first module configured to receive a read request message and send a memory address application message to a cache controller based on the read request message; a second module configured to perform a read operation based on the read request message and determine whether the application for a memory address to the cache controller is successful; and a third module configured to, in response to the successful application for a memory address to the cache controller, perform a data transfer operation based on the memory address.

[0018] In some embodiments, the apparatus further includes a fourth module configured to: return a memory address application failure exception in response to an unsuccessful application for a memory address from the cache controller.

[0019] In some embodiments, the apparatus further includes a fourth module configured to: in response to an unsuccessful application for a memory address from the cache controller, resend a memory address application message to the cache controller based on the read request message, and re-determine whether the application for a memory address from the cache controller is successful.

[0020] In some embodiments, the first module is further configured to: receive a read request message and check whether the read request message is legal; if the read request message is legal, send a memory address application message to the cache control based on the read request message.

[0021] In some embodiments, the second module is further configured to: perform a read operation based on the read request message and determine whether the read operation is completed; if the read operation is completed, further determine whether the application for a memory address from the cache controller is successful.

[0022] In some embodiments, the second module is further configured to: determine whether data has been transferred from memory to a register; in response to the data being transferred from memory to the register, confirm that the read operation is completed.

[0023] In some embodiments, the second module is further configured to: if the read operation is not completed, wait for the read operation to complete and then further determine whether the application for a memory address from the cache controller is successful.

[0024] In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions that can be run on the processor, and the steps implemented by the processor when executing the instructions include: receiving a read request message and sending a memory address application message to the cache controller based on the read request message; performing a read operation based on the read request message and determining whether the application for a memory address from the cache controller is successful; and in response to a successful application for a memory address from the cache controller, performing a data transfer operation based on the memory address.

[0025] In some embodiments, the steps further include: returning a memory address application failure exception in response to an unsuccessful application for a memory address from the cache controller.

[0026] In some embodiments, the steps further include: in response to an unsuccessful application for a memory address from the cache controller, re-sending a memory address application message to the cache controller based on the read request message, and re-determining whether the application for a memory address from the cache controller is successful.

[0027] In some embodiments, receiving a read request message and sending a memory address application message to the cache controller based on the read request message includes: receiving a read request message and checking whether the read request message is legal; if the read request message is legal, sending a memory address application message to the cache controller based on the read request message.

[0028] In some embodiments, performing a read operation based on the read request message and determining whether the application for a memory address from the cache controller is successful includes: performing a read operation based on the read request message and determining whether the read operation is completed; if the read operation is completed, further determining whether the application for a memory address from the cache controller is successful.

[0029] In some embodiments, determining whether the read operation is completed includes: determining whether data has been transferred from memory to a register; in response to the data being transferred from memory to a register, confirming that the read operation is completed.

[0030] In some embodiments, the steps further include: if the read operation is not completed, waiting for the read operation to complete and then further determining whether the application for a memory address from the cache controller is successful.

[0031] Another aspect of the embodiments of the present invention further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above method steps.

[0032] The present invention has at least the following beneficial technical effects: By adopting the method of applying for a memory address in advance, adding a judgment on whether the memory address application is successful before data transmission, realizing parallel processing of read commands and memory address applications, saving the memory address application time, reducing the read time consumption, and improving the product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0034] Figure 1 It is a schematic diagram of an embodiment of the message processing method for a flash channel controller provided by the present invention;

[0035] Figure 2 Schematic diagram of an embodiment of the message processing device of the flash channel controller provided by the present invention;

[0036] Figure 3 Schematic diagram of an embodiment of the computer device provided by the present invention;

[0037] Figure 4 Schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the following further describes the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0039] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different, so it can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be repeated in the subsequent embodiments.

[0040] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of the message processing method of the flash channel controller is proposed. Figure 1 Shown is a schematic diagram of an embodiment of the message processing method of the flash channel controller provided by the present invention. As Figure 1 shown, the message processing method of the flash channel controller in the embodiments of the present invention includes the following steps:

[0041] 001. Receive a read request message, and send a memory address application message to the cache controller based on the read request message;

[0042] 002. Perform a read operation based on the read request message, and determine whether the application for a memory address to the cache controller is successful; and

[0043] 003. In response to the successful application for a memory address to the cache controller, perform a data transfer operation based on the memory address.

[0044] In this embodiment, the message processing process of the prior art is optimized. Instead of waiting for the cache controller to complete the message after sending the memory address application to the cache controller, subsequent commands are continued to be executed. During the execution of the read command, the read time consumption of the flash channel controller is crucial for performance parameters such as the number of read and write operations per second and the bandwidth of the product. By adopting the method of applying for a memory address in advance and adding a judgment on whether the memory address application is successful before data transfer, parallel processing of the read command and the memory address application is realized, saving the memory address application time, reducing the read time consumption, and improving the product performance.

[0045] In this embodiment, after sending a memory address request to the cache controller, it no longer waits for the cache controller to complete the message, but continues to execute subsequent commands. The tR time is relatively long during the execution of the read command, and the memory address is not used until after tR is completed. Therefore, before preparing to use the memory address, it is necessary to add a judgment on whether the memory address request is successful. If successful, the data transfer (BDT, Bulk Data Transfer) operation is continued; if failed, a failure is directly returned. In this way, the time for memory address request is saved, and the efficiency of message processing by the flash channel controller can be increased.

[0046] In some embodiments of the present invention, the method further includes: in response to the unsuccessful application for a memory address from the cache controller, returning an exception of failure in memory address application.

[0047] In some embodiments of the present invention, the method further includes: in response to the unsuccessful application for a memory address from the cache controller, resending a memory address application message to the cache controller based on the read request message, and re-judging whether the application for a memory address from the cache controller is successful.

[0048] In some embodiments of the present invention, receiving a read request message and sending a memory address application message to the cache controller based on the read request message includes: receiving a read request message and checking whether the read request message is legal; if the read request message is legal, sending a memory address application message to the cache controller based on the read request message.

[0049] In some embodiments of the present invention, performing a read operation based on the read request message and judging whether the application for a memory address from the cache controller is successful includes: performing a read operation based on the read request message and judging whether the read operation is completed; if the read operation is completed, further judging whether the application for a memory address from the cache controller is successful.

[0050] In some embodiments of the present invention, judging whether the read operation is completed includes: judging whether the data has been transferred from the memory to the register; in response to the data being transferred from the memory to the register, confirming that the read operation is completed.

[0051] In some embodiments of the present invention, the method further includes: if the read operation is not completed, waiting for the read operation to be completed and then further judging whether the application for a memory address from the cache controller is successful.

[0052] The following further elaborates on the specific implementation manner of the present invention according to specific embodiments. Specifically, it includes:

[0053] Upon receiving a read request message and determining that the read request message is legal, a memory address application message is sent to the cache controller;

[0054] After sending the memory address application message, the read operation continues. After the read command is executed, that is, when the data has been transferred from the memory (NAND) to the register (register), the data transfer is ready to start;

[0055] Determine whether the memory address application is successful. If successful, continue with the data transfer operation; if not successful, do not perform the data transfer and directly return an exception with the status of memory address application failure.

[0056] It should be specifically noted that each step in the various embodiments of the above-mentioned message processing method of the flash channel controller can be cross - referenced, replaced, added, or deleted with each other. Therefore, these reasonable permutations and combinations also belong to the protection scope of the present invention for the message processing method of the flash channel controller, and the protection scope of the present invention should not be limited to the embodiments.

[0057] For the above purpose, in the second aspect of the embodiments of the present invention, a message processing device of a flash channel controller is proposed. Figure 2 Shown is a schematic diagram of an embodiment of the message processing device of the flash channel controller provided by the present invention. As Figure 2 shown, the message processing device of the flash channel controller in the embodiments of the present invention includes the following modules: a first module 011 configured to receive a read request message and send a memory address application message to the cache controller based on the read request message; a second module 012 configured to perform a read operation based on the read request message and determine whether the memory address application to the cache controller is successful; and a third module 013 configured to, in response to the memory address application to the cache controller being successful, perform a data transfer operation based on the memory address.

[0058] In some embodiments of the present invention, the device further includes a fourth module configured to: in response to the memory address application to the cache controller being unsuccessful, return an exception of memory address application failure.

[0059] In some embodiments of the present invention, the device further includes a fourth module configured to: in response to the memory address application to the cache controller being unsuccessful, re - send a memory address application message to the cache controller based on the read request message and re - determine whether the memory address application to the cache controller is successful.

[0060] In some embodiments of the present invention, the first module 011 is further configured to: receive a read request message and check whether the read request message is legal; if the read request message is legal, send a memory address application message to the cache control based on the read request message.

[0061] In some embodiments of the present invention, the second module 012 is further configured to: perform a read operation based on the read request message, and determine whether the read operation is completed; if the read operation is completed, further determine whether the application for a memory address from the cache controller is successful.

[0062] In some embodiments of the present invention, the second module 012 is further configured to: determine whether data has been transferred from memory to a register; in response to the data being transferred from memory to a register, confirm that the read operation is completed.

[0063] In some embodiments of the present invention, the second module 012 is further configured to: if the read operation is not completed, wait for the read operation to complete and then further determine whether the application for a memory address from the cache controller is successful.

[0064] Based on the above object, in the third aspect of the embodiments of the present invention, a computer device is proposed. Figure 3 Shown is a schematic diagram of an embodiment of the computer device provided by the present invention. As Figure 3 shown, the computer device of the embodiments of the present invention includes the following devices: at least one processor 021; and a memory 022, where the memory 022 stores computer instructions 023 that can be run on the processor, and the steps implemented by the instructions when executed by the processor include: receiving a read request message, and sending a memory address application message to the cache controller based on the read request message; performing a read operation based on the read request message, and determining whether the application for a memory address from the cache controller is successful; and in response to the application for a memory address from the cache controller being successful, performing a data transfer operation based on the memory address.

[0065] In some embodiments of the present invention, the steps further include: in response to the application for a memory address from the cache controller being unsuccessful, returning a memory address application failure exception.

[0066] In some embodiments of the present invention, the steps further include: in response to the application for a memory address from the cache controller being unsuccessful, re-sending a memory address application message to the cache controller based on the read request message, and re-determining whether the application for a memory address from the cache controller is successful.

[0067] In some embodiments of the present invention, receiving a read request message and sending a memory address application message to the cache controller based on the read request message includes: receiving a read request message, and checking whether the read request message is legal; if the read request message is legal, sending a memory address application message to the cache controller based on the read request message.

[0068] In some embodiments of the present invention, performing a read operation based on the read request message and determining whether a memory address application to the cache controller is successful includes: performing a read operation based on the read request message and determining whether the read operation is completed; if the read operation is completed, further determining whether a memory address application to the cache controller is successful.

[0069] In some embodiments of the present invention, determining whether the read operation is completed includes: determining whether data has been transferred from memory to a register; in response to data being transferred from memory to a register, confirming that the read operation is completed.

[0070] In some embodiments of the present invention, the steps further include: if the read operation is not completed, waiting for the read operation to complete and then further determining whether a memory address application to the cache controller is successful.

[0071] The present invention also provides a computer-readable storage medium. Figure 4 Shown is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. As Figure 4 shown, the computer-readable storage medium 031 stores a computer program 032 that, when executed by a processor, performs the following method. The method includes: receiving a read request message and sending a memory address application message to a cache controller based on the read request message; performing a read operation based on the read request message and determining whether a memory address application to the cache controller is successful; and in response to a successful memory address application to the cache controller, performing a data transfer operation based on the memory address.

[0072] In some embodiments of the present invention, the method further includes: in response to an unsuccessful memory address application to the cache controller, returning a memory address application failure exception.

[0073] In some embodiments of the present invention, the method further includes: in response to an unsuccessful memory address application to the cache controller, re-sending a memory address application message to the cache controller based on the read request message and re-determining whether a memory address application to the cache controller is successful.

[0074] In some embodiments of the present invention, receiving a read request message and sending a memory address application message to a cache controller based on the read request message includes: receiving a read request message and checking whether the read request message is legal; if the read request message is legal, sending a memory address application message to the cache controller based on the read request message.

[0075] In some embodiments of the present invention, performing a read operation based on the read request message and determining whether a memory address application to the cache controller is successful includes: performing a read operation based on the read request message and determining whether the read operation is completed; if the read operation is completed, further determining whether a memory address application to the cache controller is successful.

[0076] In some embodiments of the present invention, determining whether the read operation is completed includes: determining whether data has been transferred from memory to a register; in response to the data being transferred from memory to a register, confirming that the read operation is completed.

[0077] In some embodiments of the present invention, the method further includes: if the read operation is not completed, waiting for the read operation to complete and then further determining whether a memory address application to the cache controller is successful.

[0078] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program of the message processing method of the flash channel controller can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0079] In addition, the method disclosed according to the embodiments of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiments of the present invention are executed.

[0080] In addition, the above method steps and system units can also be implemented by using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above step or unit functions.

[0081] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, a general description of the functions of various illustrative components, blocks, modules, circuits, and steps has been given. Whether this function is implemented as software or hardware depends on the specific application and the design constraints imposed on the overall system. The functions that those skilled in the art can implement in various ways for each specific application, but this implementation decision should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0082] In one or more exemplary designs, the functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. The storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, the computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. In addition, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0083] The above are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of the present disclosure defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements of the embodiments of the present disclosure may be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0084] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular forms "a" and "an" are intended to also include the plural forms. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0085] The serial numbers of the above disclosed embodiments of the present invention are merely for description and do not represent the superiority or inferiority of the embodiments.

[0086] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0087] Those of ordinary skill in the art should understand that the discussion of any above embodiment is only exemplary, and is not intended to imply that the scope (including the claims) disclosed by the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, and they are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A message processing method for a flash channel controller, characterized in that, Including the following steps: Receiving a read request message, and sending a memory address application message to a cache controller based on the read request message; Before successfully applying for a memory address from the cache controller in response to the read request message, performing a read operation based on the read request message to implement parallel processing of a read command and a memory address application, and determining whether the read operation is completed. If the read operation is completed, further determining whether the application for a memory address from the cache controller is successful; and In response to successfully applying for a memory address from the cache controller, performing a data transfer operation based on the memory address; Wherein, determining whether the read operation is completed includes: determining whether data has been transferred from a NAND memory to a register; in response to the data being transferred from the NAND to the register, confirming that the read operation is completed.

2. The message processing method of the flash memory channel controller according to claim 1, wherein Further including: In response to the application for a memory address from the cache controller being unsuccessful, returning a memory address application failure exception.

3. The message processing method of the flash memory channel controller according to claim 1, wherein Further including: In response to the application for a memory address from the cache controller being unsuccessful, re-sending a memory address application message to the cache controller based on the read request message, and re-determining whether the application for a memory address from the cache controller is successful.

4. The message processing method of the flash memory channel controller according to claim 1, wherein Receiving a read request message, and sending a memory address application message to a cache controller based on the read request message includes: Receiving a read request message, and checking whether the read request message is legal; If the read request message is legal, sending a memory address application message to the cache control based on the read request message.

5. The message processing method of the flash memory channel controller according to claim 1, wherein Further including: If the read operation is not completed, waiting for the read operation to complete and then further determining whether the application for a memory address from the cache controller is successful.

6. A message processing device for a flash memory channel controller, characterized in that, Including: A first module configured to receive a read request message, and send a memory address application message to a cache controller based on the read request message; A second module configured to, before successfully applying for a memory address from the cache controller in response to the read request message, perform a read operation based on the read request message to implement parallel processing of a read command and a memory address application, and determine whether the read operation is completed. If the read operation is completed, further determine whether the application for a memory address from the cache controller is successful. Wherein, determining whether the read operation is completed includes: determining whether data has been transferred from a NAND memory to a register; in response to the data being transferred from the NAND to the register, confirming that the read operation is completed; and A third module configured to, in response to successfully applying for a memory address from the cache controller, perform a data transfer operation based on the memory address.

7. A computer device, characterized in that, Including: At least one processor; And A memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, implementing the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, implementing the steps of the method according to any one of claims 1-5.

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