Display control module, method and display device

Abstract

The present invention provides a display control module, method and display device. The display control module includes a gating control signal generating circuit and a first switch circuit; the gating control signal generating circuit controls the provision of a first gating control signal and controls the provision of a second gating control signal; the first switch circuit, under the control of the first gating control signal and the second gating control signal, controls the source driver to provide a data voltage to the data line, or the first DC voltage terminal to provide a first DC voltage to the data line. The display control module, method and display device described in the embodiments of the present invention can well maintain the potential of the first node by reducing leakage when the image signal to be displayed remains unchanged, thereby ensuring excellent display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display control module, method and display device. Background Art

[0002] When the image signal to be displayed in the display device remains unchanged or substantially unchanged, the pixels can be driven at a low speed to reduce the power consumption of the display device. However, the image quality may be degraded. For example, in the low-speed driving mode, the potential of the gate of the driving transistor may leak due to the transistor electrically connected to the gate, causing the user to feel a flickering phenomenon. Summary of the invention

[0003] The main purpose of the present invention is to provide a display control module, method and display device to solve the problem that when the image signal to be displayed remains unchanged, the potential of the first node (the first node is a node electrically connected to the gate of the driving transistor) cannot be well maintained by reducing leakage.

[0004] In order to achieve the above object, an embodiment of the present invention provides a display control module, which is applied to a display device, wherein the display device includes a display panel, and the display panel includes a plurality of data lines; the display control module includes a gating control signal generating circuit and a first switch circuit;

[0005] The gating control signal generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the first gating control terminal and the second gating control terminal respectively, and is used to control the first gating control terminal to provide a first gating control signal and control the second gating control terminal to provide a second gating control signal under the control of the first control signal provided by the first control terminal, the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal;

[0006] The first switching circuit is electrically connected to the first selection control terminal, the second selection control terminal, the first DC voltage terminal, the source driver and the data line, respectively, and is used to control the source driver to provide a data voltage to the data line, or the first DC voltage terminal to provide a first DC voltage to the data line under the control of the first selection control signal and the second selection control signal.

[0007] Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further includes a second switch circuit;

[0008] The second switching circuit is electrically connected to the first selection control terminal, the second selection control terminal, the second DC voltage terminal, the source driver and the reference voltage line, respectively, and is used to control the source driver to provide a reference voltage to the reference voltage line, or to control the second DC voltage terminal to provide a second DC voltage to the reference voltage line under the control of the first selection control signal and the second selection control signal.

[0009] Optionally, the gating control signal generating circuit includes a first generating circuit and a second generating circuit;

[0010] The first generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the first gating control terminal and the first voltage terminal respectively, and is used to control the first gating control terminal to be connected to the first clock signal terminal under the control of the first control signal, and to control the first gating control terminal to be connected to the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal;

[0011] The second generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the second gating control terminal and the first voltage terminal, respectively, and is used to control the connection between the second gating control terminal and the second clock signal terminal under the control of the first control signal, and to control the connection between the second gating control terminal and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal.

[0012] Optionally, the first generating circuit includes a first transistor, a second transistor and a first capacitor;

[0013] The control electrode of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first selection control terminal;

[0014] The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first gating control terminal, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0015] The first end of the first capacitor is electrically connected to the first control end, and the second end of the first capacitor is electrically connected to the first gating control end;

[0016] The second generating circuit includes a third transistor, a fourth transistor and a second capacitor;

[0017] The control electrode of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the second selection control terminal, and the second electrode of the third transistor is electrically connected to the second clock signal terminal;

[0018] The control electrode of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second gating control terminal;

[0019] The first end of the second capacitor is electrically connected to the first control end, and the second end of the second capacitor is electrically connected to the second selection control end.

[0020] Optionally, the first switch circuit includes a first switch unit circuit and a second switch unit circuit, the display device includes N data lines, N is a positive integer; the first switch unit circuit includes N first switch transistors, the second switch unit circuit includes N second switch transistors; n is a positive integer less than or equal to N;

[0021] A control electrode of the nth first switch transistor is electrically connected to the first selection control terminal, a first electrode of the nth first switch transistor is electrically connected to the nth data line, and a second electrode of the nth first switch transistor is electrically connected to the source driver;

[0022] The control electrode of the nth second switch transistor is electrically connected to the second selection control terminal, the first electrode of the nth second switch transistor is electrically connected to the nth data line, and the second electrode of the nth second switch transistor is electrically connected to the first DC voltage terminal.

[0023] Optionally, the N first switch transistors and the N second switch transistors are all n-type transistors, or the N first switch transistors and the N second switch transistors are all p-type transistors.

[0024] Optionally, the second switch circuit includes a third switch unit circuit and a fourth switch unit circuit, the display device includes P reference voltage lines, P is a positive integer; the third switch unit circuit includes P third switch transistors, the fourth switch unit circuit includes P fourth switch transistors; p is a positive integer less than or equal to P;

[0025] A control electrode of a p-th third switch transistor is electrically connected to the first selection control terminal, a first electrode of the p-th third switch transistor is electrically connected to a p-th reference voltage line, and a second electrode of the p-th third switch transistor is electrically connected to the source driver;

[0026] The control electrode of the pth fourth switch transistor is electrically connected to the second selection control terminal, the first electrode of the pth fourth switch transistor is electrically connected to the pth reference voltage line, and the second electrode of the pth fourth switch transistor is electrically connected to the second DC voltage terminal.

[0027] Optionally, the P third switch transistors and the P fourth switch transistors are both n-type transistors, or the P third switch transistors and the P fourth switch transistors are both p-type transistors.

[0028] Optionally, a DC module is also included;

[0029] The DC module is electrically connected to the first DC voltage terminal and the second DC voltage terminal respectively, and is used to provide a first DC voltage to the first DC voltage terminal and a second DC voltage to the second DC voltage terminal.

[0030] An embodiment of the present invention further provides a display control method, which is applied to the above-mentioned display control module. The display control method includes:

[0031] The source driver receives the image signal to be displayed, and determines whether the image signal to be displayed changes when the display cycle starts;

[0032] When the image signal to be displayed does not change, it is detected that the display control module enters a low-speed driving mode, and the display cycle is set to include a refresh frame and at least one hold frame that are set successively;

[0033] In the refresh frame, the first control signal, the first clock signal and the second clock signal are controlled so that the gating control signal generating circuit provides a first first gating control signal and a first second gating control signal, and the first switch circuit controls the source driver to provide a corresponding data voltage to the data line under the control of the first first gating control signal and the first second gating control signal;

[0034] In the holding frame, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a second first selection control signal and a second second selection control signal, and the first switching circuit controls the first DC voltage terminal to provide the first DC voltage to the data line under the control of the second first selection control signal and the second second selection control signal.

[0035] Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further includes a second switch circuit; and the display control method further includes:

[0036] In the refresh frame, the second switch circuit controls the source driver to provide the reference voltage to the reference voltage line under the control of the first first gating control signal and the first second gating control signal;

[0037] In the holding frame, the second switch circuit controls the second DC voltage terminal to provide the second DC voltage to the reference voltage line under the control of the second first selection control signal and the second second selection control signal.

[0038] Optionally, the display control method described in at least one embodiment of the present invention further includes:

[0039] When the image signal to be displayed changes, in the display period, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a first first selection control signal and a first second selection control signal, and the first switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide corresponding data voltages to multiple data lines respectively, and the second switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide reference voltages to multiple reference voltage lines respectively.

[0040] An embodiment of the present invention further provides a display device, comprising the above-mentioned display control module.

[0041] The display control module, method and display device described in the embodiments of the present invention can well maintain the potential of the first node by reducing leakage when the image signal to be displayed remains unchanged, thereby ensuring excellent display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a structural diagram of a display control module according to at least one embodiment of the present invention;

[0043] Figure 2 is a structural diagram of a display control module according to at least one embodiment of the present invention;

[0044] Figure 3 is a circuit diagram of at least one embodiment of a pixel circuit in the mth row and nth column in a display device according to the present invention;

[0045] Figure 4 The present invention is Figure 3 An operation timing diagram of at least one embodiment of the pixel circuit shown in the normal driving mode;

[0046] Figure 5 is a structural diagram of at least one embodiment of a gating control signal generating circuit in a display control module according to the present invention;

[0047] Figure 6 is a circuit diagram of at least one embodiment of a gating control signal generating circuit in a display control module according to the present invention;

[0048] Figure 7 is a circuit diagram of a display control module according to at least one embodiment of the present invention;

[0049] Figure 8 is a working timing diagram of the display control module according to at least one embodiment of the present invention;

[0050] Fig. 9 is a circuit diagram of a display control module according to at least one embodiment of the present invention;

[0051] Fig.10 is a circuit diagram of a display control module according to at least one embodiment of the present invention;

[0052] Fig.11 is a circuit diagram of a display control module according to at least one embodiment of the present invention;

[0053] Fig.12 is a flow chart of a display control method according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0056] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0057] The display control module described in the embodiment of the present invention is applied to a display device, wherein the display device includes a display panel P0, and the display panel P0 includes a plurality of data lines; Figure 1 As shown, the display control module may include a gating control signal generating circuit 11 and a first switching circuit 12;

[0058] The gating control signal generating circuit 11 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the first voltage terminal V1, the first gating control terminal SELA and the second gating control terminal SELB respectively, and is used to control the first gating control terminal SELA to provide a first gating control signal and control the second gating control terminal SELA to provide a second gating control signal under the control of the first control signal provided by the first control terminal COE, the first clock signal provided by the first clock signal terminal CKA and the second clock signal provided by the second clock signal terminal CKB;

[0059] The first switching circuit 12 is electrically connected to the first selection control terminal SELA, the second selection control terminal SELB, the first DC voltage terminal VZ1, the source driver S1 and the data line, respectively, and is used to control the source driver S1 to provide a data voltage to the data line, or the first DC voltage terminal VZ1 to provide a first DC voltage VDC1 to the data line under the control of the first selection control signal and the second selection control signal.

[0060] exist Figure 1 In the embodiment of the display control module, the line labeled D1 is the first data line, the line labeled D2 is the second data line, the line labeled DN is the Nth data line, and N is a positive integer.

[0061] In a specific implementation, the display device may include M rows and N columns of pixel circuits, the pixel circuits in the same column are electrically connected to the corresponding data line, and M and N are positive integers.

[0062] In at least one embodiment of the present invention, the first voltage terminal V1 may be a low voltage terminal, but is not limited thereto.

[0063] The present invention Figure 1 When the embodiment of the display control module shown is working, the source driver S1 receives the image signal to be displayed, and at the beginning of each display cycle, determines whether the image signal to be displayed changes;

[0064] When the image signal to be displayed does not change, the first control signal, the first clock signal and the second clock signal are controlled so that the selection control signal generating circuit 11 provides a first first selection control signal and a first second selection control signal. The first switching circuit 12 controls the first DC voltage terminal VZ1 to provide the first DC voltage VDC1 to the data line under the control of the first first selection control signal and the first second selection control signal.

[0065] The present invention Figure 1When the embodiment of the display control module shown is working, when the source driver S1 determines that the image signal to be displayed does not change, it enters a low-speed driving mode, that is, the display screen basically does not change, and the data voltage does not need to be updated, but the luminous state needs to be maintained. Then, the first switch circuit 12 is controlled by the selection control signal generating circuit 11, so that the first DC voltage terminal VZ1 provides the first DC voltage VDC1 to the data line, so that the potential of the source of the data writing transistor is not much different from the potential of the drain of the data writing transistor, thereby reducing the leakage effect of the data writing transistor on the first node (the first node is the node with the gate of the driving transistor), thereby improving the display quality.

[0066] Optionally, the voltage value of the first DC voltage VDC1 may be greater than or equal to 0V and less than or equal to 16V, but is not limited thereto.

[0067] In at least one embodiment of the present invention, the display panel further includes a plurality of reference voltage lines; the display control module may further include a second switch circuit;

[0068] The second switching circuit is electrically connected to the first selection control terminal, the second selection control terminal, the second DC voltage terminal, the source driver and the reference voltage line, respectively, and is used to control the source driver to provide a reference voltage to the reference voltage line, or to control the second DC voltage terminal to provide a second DC voltage to the reference voltage line under the control of the first selection control signal and the second selection control signal.

[0069] In a specific implementation, the display control device module may further include a second switching circuit. When the image signal to be displayed does not change, the second switching circuit controls the second DC voltage terminal to provide a second DC voltage to the reference voltage line under the control of the first first selection control signal and the first second selection control signal.

[0070] like Figure 2 As shown, the display control module may further include a second switch circuit 21; the second switch circuit 21 is electrically connected to the gating control signal generating circuit 11;

[0071] The gating control signal generating circuit 11 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the first voltage terminal V1, the first gating control terminal SELA and the second gating control terminal SELB respectively, and is used to control the first gating control terminal SELA to provide a first gating control signal and control the second gating control terminal SELA to provide a second gating control signal under the control of the first control signal provided by the first control terminal COE, the first clock signal provided by the first clock signal terminal CKA and the second clock signal provided by the second clock signal terminal CKB;

[0072] The second switching circuit 21 is electrically connected to the first selection control terminal SELA, the second selection control terminal SELB, the second DC voltage terminal VZ2, the source driver S1 and the reference voltage line, respectively, and is used to control the source driver S1 to provide the reference voltage line with a reference voltage Vref, or the second DC voltage terminal VZ2 to provide the second DC voltage Vref_h to the reference voltage line under the control of the first selection control signal and the second selection control signal.

[0073] exist Figure 2 In the figure, the one labeled P0 is a display panel, the one labeled R1 is a first reference voltage line, the one labeled R2 is a second reference voltage line, the one labeled RP is a Pth reference voltage line, and P is a positive integer.

[0074] In a specific implementation, the display device may include M rows and N columns of pixel circuits, the pixel circuits in the same column are electrically connected to the corresponding reference voltage line, and M and N are positive integers.

[0075] The present invention Figure 2 When the embodiment of the display control module shown is working, the source driver S1 receives the image signal to be displayed, and at the beginning of each display cycle, determines whether the image signal to be displayed changes;

[0076] When the image signal to be displayed does not change, the second switch circuit 21 controls the second DC voltage terminal VZ2 to provide the second DC voltage Vref_h to the reference voltage line under the control of the first first selection control signal and the first second selection control signal.

[0077] exist Figure 2 In the figure, the line labeled R1 is the first reference voltage line, the line labeled R2 is the second reference voltage line, and the line labeled RP is the Pth reference voltage line.

[0078] The present invention Figure 2 When the embodiment of the display control module shown is working, when the source driver S1 determines that the image signal to be displayed does not change, it enters a low-speed driving mode, that is, the display screen basically does not change, and the data voltage does not need to be updated, but the luminous state needs to be maintained. Then, the second switch circuit 21 is controlled by the selection control signal generating circuit 11, so that the second DC voltage terminal VZ2 provides the second DC voltage Vref_h to the reference voltage line, so that the potential of the source of the compensation control transistor is not much different from the potential of the drain of the data writing transistor, thereby reducing the leakage effect of the compensation control transistor on the first node (the first node is the node with the gate of the driving transistor), thereby improving the display quality.

[0079] Optionally, a voltage value of the second DC voltage Vref_h may be greater than or equal to 0V and less than or equal to 16V, but is not limited thereto.

[0080] Figure 1 The embodiment of the display control module shown in the figure includes a gate control signal generating circuit, which can be used with Figure 2 The embodiment of the display control module shown includes a strobe control signal generating circuit which is the same strobe control signal generating circuit, or, Figure 1 The embodiment of the display control module shown in the figure includes a gate control signal generating circuit, which can be used with Figure 2 The strobe control signal generating circuits included in the embodiment of the display control module shown are different strobe control signal generating circuits.

[0081] In at least one embodiment of the present invention, Figure 3 As shown, the pixel circuit of the mth row and nth column in the display device may include a driving transistor T0, a data writing transistor T1, a compensation control transistor T2, a storage capacitor Cst, a light emitting control transistor T3, a reset transistor T4 and an organic light emitting diode O1;

[0082] The gate of T1 is electrically connected to the first scan line G1, the source of T1 is electrically connected to the nth data line Dn, the drain of T1 is electrically connected to the first node N1; the first node N1 is electrically connected to the gate of T0;

[0083] The gate of T2 is electrically connected to the second scan line G2, the source of T2 is electrically connected to the pth reference voltage line Rp, and the drain of T2 is electrically connected to the first node N1;

[0084] The gate of T3 is electrically connected to the light emitting control line EM, the source of T3 is electrically connected to the high voltage line VDD, and the drain of T3 is electrically connected to the drain of T0;

[0085] The gate of T4 is electrically connected to the third scan line G3, the source of T4 is electrically connected to the sensing line Sense, and the drain of T4 is electrically connected to the source of T0;

[0086] The source of T0 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low voltage line VSS;

[0087] A first end of Cst is electrically connected to the first node N1, and a second end of Cst is electrically connected to the source of T0.

[0088] In at least one embodiment of the present invention, m and n are positive integers, m is less than or equal to M, n is less than or equal to N, and p is a positive integer.

[0089] In the related art, when Figure 3When at least one embodiment of the pixel circuit shown is working, if during low-speed driving, the potential of the first node N1 decreases due to the leakage current of T1 and T2, resulting in reduced display quality. Based on this, the display control module described in the embodiment of the present invention can reduce the leakage current of T1 and the leakage current of T2 during low-speed driving to ensure excellent display quality.

[0090] Figure 4 The present invention is Figure 3 FIG. 1 is a timing diagram showing an operation of at least one embodiment of a pixel circuit in a normal driving mode.

[0091] Optional, such as Figure 5 As shown, at least one embodiment of the gating control signal generating circuit may include a first generating circuit 41 and a second generating circuit 42;

[0092] The first generating circuit 41 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the first gate control terminal SELA and the first voltage terminal V1 respectively, and is used to control the first gate control terminal SELA to be connected to the first clock signal terminal CKA under the control of the first control signal, and control the first gate control terminal SELA to be connected to the first voltage terminal V1 under the control of the second clock signal provided by the second clock signal terminal CKB;

[0093] The second generating circuit 42 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the second selection control terminal SELB and the first voltage terminal V1, respectively, and is used to control the connection between the second selection control terminal SELB and the second clock signal terminal CKB under the control of the first control signal, and to control the connection between the second selection control terminal SELB and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKA.

[0094] In a specific implementation, the selection control signal generating circuit may include a first generating circuit 41 and a second generating circuit 42. The first generating circuit 41 controls the first selection control signal provided by the first selection control terminal SELA under the control of the first control signal and the second clock signal. The second generating circuit 42 controls the second selection control signal provided by the second selection control terminal SELB under the control of the first control signal and the first clock signal.

[0095] Optionally, the first generating circuit includes a first transistor, a second transistor and a first capacitor;

[0096] The control electrode of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first selection control terminal;

[0097] The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first gating control terminal, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0098] The first end of the first capacitor is electrically connected to the first control end, and the second end of the first capacitor is electrically connected to the first gating control end;

[0099] The second generating circuit includes a third transistor, a fourth transistor and a second capacitor;

[0100] The control electrode of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the second selection control terminal, and the second electrode of the third transistor is electrically connected to the second clock signal terminal;

[0101] The control electrode of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second gating control terminal;

[0102] The first end of the second capacitor is electrically connected to the first control end, and the second end of the second capacitor is electrically connected to the second selection control end.

[0103] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the gating control signal generating circuit shown, the first generating circuit 41 includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0104] The gate of the first transistor T1 is electrically connected to the first control terminal COE, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and the drain of the first transistor T1 is electrically connected to the first selection control terminal SELA;

[0105] The gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, the source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and the drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0106] A first end of the first capacitor C1 is electrically connected to the first control end COE, and a second end of the first capacitor C1 is electrically connected to the first selection control end SELA;

[0107] The second generating circuit 42 includes a third transistor T3, a fourth transistor T4 and a second capacitor C2;

[0108] The gate of the third transistor T3 is electrically connected to the first control terminal COE, the source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and the drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;

[0109] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, the source of the fourth transistor T4 is electrically connected to the low voltage terminal, and the drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;

[0110] A first end of the second capacitor C2 is electrically connected to the first control end COE, and a second end of the second capacitor C2 is electrically connected to the second selection control end SELB.

[0111] In such Figure 6 In at least one embodiment of the gate control signal generating circuit shown, lossless output can be achieved through signal matching, thereby enhancing the driving capability of the gate thin film transistor. In specific implementation, the high voltage value of the first control signal output by the COE can be set to be greater than the high voltage value of the first clock signal provided by the first clock signal terminal CKA, and the high voltage value of the first control signal output by the COE can be set to be greater than the high voltage value of the second clock signal provided by the second clock signal terminal CKB, so that the high voltage value of the first gate control signal provided by the first gate control terminal SELA and the high voltage value of the second gate control signal provided by the second gate control terminal SELB are higher, which can enhance the driving capability.

[0112] exist Figure 6 In at least one embodiment of the gate control signal generating circuit shown, T1 , T2 , T3 and T4 may be n-type thin film transistors, but the present invention is not limited thereto.

[0113] like Figure 6 At least one embodiment of the gate control signal generating circuit shown in FIG.

[0114] In the refresh frame, COE provides a high voltage signal, CKA provides a high voltage signal, CKB provides a low voltage signal, T1 is turned on, T2 is turned off, T3 is turned on, T4 is turned on, SELA outputs a high voltage signal, and SELB outputs a low voltage signal;

[0115] In the hold frame, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, T1 is turned on, T2 is turned on, SELA outputs a low voltage signal, T3 is turned on, T4 is turned off, and SELB outputs a high voltage signal.

[0116] In at least one embodiment of the present invention, when COE provides a high voltage signal, the voltage value of the high voltage signal provided by COE can be set to be greater than the high voltage value of the first clock signal provided by CKA, and the voltage value of the high voltage signal provided by COE can be set to be greater than the high voltage value of the second clock signal provided by CKB, thereby making the high voltage value of the first selection control signal output by SELA and the high voltage value of the second selection control signal output by SELB higher, thereby enhancing the driving capability.

[0117] In at least one embodiment of the present invention, the first switch circuit includes a first switch unit circuit and a second switch unit circuit, the display device includes N data lines, N is a positive integer; the first switch unit circuit includes N first switch transistors, the second switch unit circuit includes N second switch transistors; n is a positive integer less than or equal to N;

[0118] A control electrode of the nth first switch transistor is electrically connected to the first selection control terminal, a first electrode of the nth first switch transistor is electrically connected to the nth data line, and a second electrode of the nth first switch transistor is electrically connected to the source driver;

[0119] The control electrode of the nth second switch transistor is electrically connected to the second selection control terminal, the first electrode of the nth second switch transistor is electrically connected to the nth data line, and the second electrode of the nth second switch transistor is electrically connected to the first DC voltage terminal.

[0120] Optionally, the N first switch transistors and the N second switch transistors are all n-type transistors, or the N first switch transistors and the N second switch transistors are all p-type transistors.

[0121] like Figure 7 As shown, in Figure 1 Based on at least one embodiment of the display control module shown, the gating control signal generating circuit 11 includes a first generating circuit and a second generating circuit;

[0122] The first generating circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0123] The gate of the first transistor T1 is electrically connected to the first control terminal COE, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and the drain of the first transistor T1 is electrically connected to the first selection control terminal SELA;

[0124] The gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, the source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and the drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0125] A first end of the first capacitor C1 is electrically connected to the first control end COE, and a second end of the first capacitor C1 is electrically connected to the first selection control end SELA;

[0126] The second generating circuit includes a third transistor T3, a fourth transistor T4 and a second capacitor C2;

[0127] The gate of the third transistor T3 is electrically connected to the first control terminal COE, the source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and the drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;

[0128] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, the source of the fourth transistor T4 is electrically connected to the low voltage terminal, and the drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;

[0129] A first end of the second capacitor C2 is electrically connected to the first control end COE, and a second end of the second capacitor C2 is electrically connected to the second selection control end SELB;

[0130] The first switch circuit includes a first switch unit circuit 71 and a second switch unit circuit 72. The display panel P0 in the display device includes N data lines, where N is a positive integer.

[0131] The first switch unit circuit 71 includes N first switch transistors, and the second switch unit circuit 72 includes N second switch transistors;

[0132] exist Figure 7 In the embodiment, the transistor labeled T11 is the first first switch transistor, the transistor labeled T12 is the second first switch transistor, and the transistor labeled T1N is the Nth first switch transistor; the transistor labeled T21 is the first second switch transistor, the transistor labeled T22 is the second second switch transistor, and the transistor labeled T2N is the Nth second switch transistor;

[0133] The gate of T11 is electrically connected to the first selection control terminal SELA, the source of T11 is electrically connected to the first data line D1, and the drain of T11 is electrically connected to the source driver S1;

[0134] The gate of T12 is electrically connected to the first selection control terminal SELA, the source of T11 is electrically connected to the second data line D2, and the drain of T11 is electrically connected to the source driver S1;

[0135] The gate of T1N is electrically connected to the first selection control terminal SELA, the source of T1N is electrically connected to the Nth data line DN, and the drain of T1N is electrically connected to the source driver S1;

[0136] The gate of T21 is electrically connected to the second selection control terminal SELB, the source of T21 is electrically connected to the first data line D1, and the drain of T21 is electrically connected to the first DC voltage terminal VZ1;

[0137] The gate of T22 is electrically connected to the second selection control terminal SELB, the source of T21 is electrically connected to the second data line D2, and the drain of T21 is electrically connected to the first DC voltage terminal VZ1;

[0138] The gate of T2N is electrically connected to the second selection control terminal SELA, the source of T2N is electrically connected to the Nth data line DN, and the drain of T2N is electrically connected to the first DC voltage terminal VZ1; the first DC voltage terminal VZ1 is used to provide a first DC voltage VDC1.

[0139] In the present invention, Figure 7 In at least one embodiment of the display control module shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0140] The present invention Figure 7 At least one embodiment of the display control module shown in FIG. Figure 8 As shown, when at least one embodiment of the display control module operates in the low-speed driving mode, the display cycle may include a refresh frame F1, a first hold frame F21, a second hold frame F22, a third hold frame F23 and a fourth hold frame F24;

[0141] In the refresh frame F1, COE outputs a high voltage signal, CKA outputs a high voltage signal, CKB outputs a low voltage signal, SELA outputs a high voltage signal, SELB outputs a low voltage signal, T11, T12 and T1N are turned on, T21, T22 and T2N are turned off, and the source driver S1 provides corresponding data voltages for each data line;

[0142] In the first holding frame F21, the second holding frame F22, the third holding frame F23 and the fourth holding frame F24, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, SELA outputs a low voltage signal, SEB outputs a high voltage signal, T11, T12 and T1N are turned off, T21, T22 and T2N are turned on, and the first DC voltage terminal VZ1 provides the first DC voltage VDC1 for each data line, thereby reducing the leakage effect of the data writing transistor on the first node (the first node is the node with the gate of the driving transistor), thereby improving the display quality;

[0143] In the first holding frame F21, the second holding frame F22, the third holding frame F23 and the fourth holding frame F24, the display image is substantially unchanged, the data voltage does not need to be updated, and the light-emitting state needs to be maintained.

[0144] In at least one embodiment of the present invention, the second switch circuit includes a third switch unit circuit and a fourth switch unit circuit, the display device includes P reference voltage lines, P is a positive integer; the third switch unit circuit includes P third switch transistors, the fourth switch unit circuit includes P fourth switch transistors; p is a positive integer less than or equal to P;

[0145] A control electrode of a p-th third switch transistor is electrically connected to the first selection control terminal, a first electrode of the p-th third switch transistor is electrically connected to a p-th reference voltage line, and a second electrode of the p-th third switch transistor is electrically connected to the source driver;

[0146] The control electrode of the pth fourth switch transistor is electrically connected to the second selection control terminal, the first electrode of the pth fourth switch transistor is electrically connected to the pth reference voltage line, and the second electrode of the pth fourth switch transistor is electrically connected to the second DC voltage terminal.

[0147] Optionally, the P third switch transistors and the P fourth switch transistors are both n-type transistors, or the P third switch transistors and the P fourth switch transistors are both p-type transistors.

[0148] like Fig. 9 As shown, in Figure 2 Based on at least one embodiment of the display control module shown, the gating control signal generating circuit 11 includes a first generating circuit and a second generating circuit;

[0149] The first generating circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0150] The gate of the first transistor T1 is electrically connected to the first control terminal COE, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and the drain of the first transistor T1 is electrically connected to the first selection control terminal SELA;

[0151] The gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, the source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and the drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0152] A first end of the first capacitor C1 is electrically connected to the first control end COE, and a second end of the first capacitor C1 is electrically connected to the first selection control end SELA;

[0153] The second generating circuit includes a third transistor T3, a fourth transistor T4 and a second capacitor C2;

[0154] The gate of the third transistor T3 is electrically connected to the first control terminal COE, the source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and the drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;

[0155] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, the source of the fourth transistor T4 is electrically connected to the low voltage terminal, and the drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;

[0156] A first end of the second capacitor C2 is electrically connected to the first control end COE, and a second end of the second capacitor C2 is electrically connected to the second selection control end SELB;

[0157] The second switch circuit includes a third switch unit circuit 83 and a fourth switch unit circuit 84, and the display device includes P reference voltage lines, where P is a positive integer;

[0158] The third switch unit circuit 83 includes P third switch transistors, and the fourth switch unit circuit includes P fourth switch transistors;

[0159] exist Fig. 9 , the first third switch transistor is labeled T31, the second third switch transistor is labeled T32, and the Pth third switch transistor is labeled T3P; the first fourth switch transistor is labeled T41, the second fourth switch transistor is labeled T42, and the Pth fourth switch transistor is labeled T4P;

[0160] The gate of T31 is electrically connected to the first selection control terminal SELA, the source of T31 is electrically connected to the first reference voltage line R1, and the drain of T31 is electrically connected to the source driver S1;

[0161] The gate of T32 is electrically connected to the first selection control terminal SELA, the source of T32 is electrically connected to the second reference voltage line R2, and the drain of T32 is electrically connected to the source driver S1;

[0162] The gate of T3P is electrically connected to the first gate control terminal SELA, the source of T3P is electrically connected to the Pth reference voltage line RP, and the drain of T3P is electrically connected to the source driver S1;

[0163] The gate of T41 is electrically connected to the second selection control terminal SELB, the source of T41 is electrically connected to the first reference voltage line R1, and the drain of T41 is electrically connected to the second DC voltage terminal VZ2;

[0164] The gate of T42 is electrically connected to the second selection control terminal SELB, the source of T42 is electrically connected to the second reference voltage line R2, and the drain of T42 is electrically connected to the second DC voltage terminal VZ2;

[0165] The gate of T4P is electrically connected to the second selection control terminal SELB, the source of T4P is electrically connected to the Pth reference voltage line RP, and the drain of T4P is electrically connected to the second DC voltage terminal VZ2.

[0166] exist Fig. 9 In at least one embodiment of the display control module shown, all transistors are n-type thin film transistors, but the present invention is not limited thereto.

[0167] The present invention Fig. 9 At least one embodiment of the display control module shown in FIG. Figure 8 As shown, when at least one embodiment of the display control module enters the low-speed driving mode, the display cycle may include a refresh frame F1, a first hold frame F21, a second hold frame F22, a third hold frame F23, and a fourth hold frame F24;

[0168] In the refresh frame F1, COE outputs a high voltage signal, CKA outputs a high voltage signal, CKB outputs a low voltage signal, SELA outputs a high voltage signal, SELB outputs a low voltage signal, T31, T32 and T3P are turned on, T41, T42 and T4P are turned off, and the source driver S1 provides corresponding data voltages for each reference voltage line;

[0169] In the first holding frame F21, the second holding frame F22, the third holding frame F23 and the fourth holding frame F24, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, SELA outputs a low voltage signal, SEB outputs a high voltage signal, T31, T32 and T3P are turned off, T41, T42 and T4P are turned on, and the second DC voltage terminal VZ2 provides a second DC voltage Vref_h for each reference voltage line, thereby reducing the leakage effect of the compensation control transistor on the first node (the first node is a node with the gate of the driving transistor), thereby improving the display quality;

[0170] During the first holding frame F21, the second holding frame F22, the third holding frame F23 and the fourth holding frame F24, a low-speed driving period is entered, that is, the display image is basically unchanged, the data voltage does not need to be updated, and the luminous state needs to be maintained.

[0171] The display control module described in at least one embodiment of the present invention may also include a DC module;

[0172] The DC module is electrically connected to the first DC voltage terminal and the second DC voltage terminal respectively, and is used to provide a first DC voltage to the first DC voltage terminal and a second DC voltage to the second DC voltage terminal.

[0173] like Fig.10 As shown, in Figure 7 Based on at least one embodiment of the display control module shown, the display control module described in at least one embodiment of the present invention further includes a direct current module DCB;

[0174] The DC module DCB is electrically connected to the first DC voltage terminal VZ1 and is used to provide a first DC voltage VDC1 to the first DC voltage terminal VZ1.

[0175] like Fig.11 As shown, in Fig. 9 Based on at least one embodiment of the display control module shown, the display control module described in at least one embodiment of the present invention further includes a direct current module DCB;

[0176] The DC module DCB is electrically connected to the second DC voltage terminal VZ2, and is used to provide a second DC voltage Vref_h to the second DC voltage terminal VZ2.

[0177] The display control method according to the embodiment of the present invention is applied to the above-mentioned display control module, and the display control method includes:

[0178] The source driver receives the image signal to be displayed, and determines whether the image signal to be displayed changes when the display cycle starts;

[0179] When the image signal to be displayed does not change, it is detected that the display control module enters a low-speed driving mode, and the display cycle is set to include a refresh frame and at least one hold frame that are set successively;

[0180] In the refresh frame, the first control signal, the first clock signal and the second clock signal are controlled so that the gating control signal generating circuit provides a first first gating control signal and a first second gating control signal, and the first switch circuit controls the source driver to provide a corresponding data voltage to the data line under the control of the first first gating control signal and the first second gating control signal;

[0181] In the holding frame, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a second first selection control signal and a second second selection control signal, and the first switching circuit controls the first DC voltage terminal to provide the first DC voltage to the data line under the control of the second first selection control signal and the second second selection control signal.

[0182] Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further includes a second switch circuit; and the display control method further includes:

[0183] In the refresh frame, the second switch circuit controls the source driver to provide the reference voltage to the reference voltage line under the control of the first first gating control signal and the first second gating control signal;

[0184] In the holding frame, the second switch circuit controls the second DC voltage terminal to provide the second DC voltage to the reference voltage line under the control of the second first selection control signal and the second second selection control signal.

[0185] In the display control method described in the embodiment of the present invention, Fig.12 As shown, at the beginning of the display cycle, it is determined whether the image signal to be displayed changes. If it changes, the normal driving mode is entered. If it does not change, the low-speed driving mode is entered. After entering the low-speed driving mode, the refresh frame is started first, and then the holding frame is entered. It is also determined whether the holding frame is terminated. If it is determined that the holding frame continues, the external power supply is entered, and the first DC voltage terminal provides a first DC voltage for each data line, and the second DC voltage terminal provides a second DC voltage for each reference voltage line. If it is determined that the holding frame is terminated, it continues to determine whether the low-speed driving mode is terminated. If it is not terminated, the refresh frame is entered again. If the low-speed driving mode is terminated, it ends and starts again.

[0186] The display control method according to at least one embodiment of the present invention further includes:

[0187] When the image signal to be displayed changes, in the display period, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a first first selection control signal and a first second selection control signal, and the first switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide corresponding data voltages to multiple data lines respectively, and the second switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide reference voltages to multiple reference voltage lines respectively.

[0188] In a specific implementation, when the image signal to be displayed changes, the conventional driving mode is entered, and the source driver provides corresponding data voltages to each data line, and the source driver provides reference voltages to each reference voltage line.

[0189] An embodiment of the present invention further provides a display device, comprising the above-mentioned display control module.

[0190] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0191] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display control module, applied to a display device, wherein the display device comprises a display panel, and the display panel comprises a plurality of data lines; characterized in that: The display control module includes a gating control signal generating circuit and a first switch circuit; The gating control signal generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the first gating control terminal and the second gating control terminal respectively, and is used to control the first gating control terminal to provide a first gating control signal and control the second gating control terminal to provide a second gating control signal under the control of the first control signal provided by the first control terminal, the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal; The first switching circuit is electrically connected to the first selection control terminal, the second selection control terminal, the first DC voltage terminal, the source driver and the data line, respectively, and is used to control the source driver to provide a data voltage to the data line, or the first DC voltage terminal to provide a first DC voltage to the data line under the control of the first selection control signal and the second selection control signal.

2. The display control module according to claim 1, characterized in that: The display panel further includes a plurality of reference voltage lines; the display control module further includes a second switch circuit; The second switching circuit is electrically connected to the first selection control terminal, the second selection control terminal, the second DC voltage terminal, the source driver and the reference voltage line, respectively, and is used to control the source driver to provide a reference voltage to the reference voltage line, or to control the second DC voltage terminal to provide a second DC voltage to the reference voltage line under the control of the first selection control signal and the second selection control signal.

3. The display control module according to claim 1, wherein: The gating control signal generating circuit includes a first generating circuit and a second generating circuit; The first generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the first gating control terminal and the first voltage terminal respectively, and is used to control the first gating control terminal to be connected to the first clock signal terminal under the control of the first control signal, and to control the first gating control terminal to be connected to the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal; The second generating circuit is electrically connected to the first control terminal, the first clock signal terminal, the second clock signal terminal, the second gating control terminal and the first voltage terminal, respectively, and is used to control the connection between the second gating control terminal and the second clock signal terminal under the control of the first control signal, and to control the connection between the second gating control terminal and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal.

4. The display control module according to claim 3, characterized in that: The first generating circuit includes a first transistor, a second transistor and a first capacitor; The control electrode of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first selection control terminal; The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first gating control terminal, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The first end of the first capacitor is electrically connected to the first control end, and the second end of the first capacitor is electrically connected to the first gating control end; The second generating circuit includes a third transistor, a fourth transistor and a second capacitor; The control electrode of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the second selection control terminal, and the second electrode of the third transistor is electrically connected to the second clock signal terminal; The control electrode of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second gating control terminal; The first end of the second capacitor is electrically connected to the first control end, and the second end of the second capacitor is electrically connected to the second selection control end.

5. The display control module according to claim 1, wherein: The first switch circuit includes a first switch unit circuit and a second switch unit circuit, the display device includes N data lines, N is a positive integer; the first switch unit circuit includes N first switch transistors, the second switch unit circuit includes N second switch transistors; n is a positive integer less than or equal to N; A control electrode of the nth first switch transistor is electrically connected to the first selection control terminal, a first electrode of the nth first switch transistor is electrically connected to the nth data line, and a second electrode of the nth first switch transistor is electrically connected to the source driver; The control electrode of the nth second switch transistor is electrically connected to the second selection control terminal, the first electrode of the nth second switch transistor is electrically connected to the nth data line, and the second electrode of the nth second switch transistor is electrically connected to the first DC voltage terminal.

6. The display control module according to claim 5, characterized in that: The N first switch transistors and the N second switch transistors are all n-type transistors, or the N first switch transistors and the N second switch transistors are all p-type transistors.

7. The display control module according to claim 2, characterized in that: The second switch circuit includes a third switch unit circuit and a fourth switch unit circuit, the display device includes P reference voltage lines, P is a positive integer; the third switch unit circuit includes P third switch transistors, the fourth switch unit circuit includes P fourth switch transistors; p is a positive integer less than or equal to P; A control electrode of a p-th third switch transistor is electrically connected to the first selection control terminal, a first electrode of the p-th third switch transistor is electrically connected to a p-th reference voltage line, and a second electrode of the p-th third switch transistor is electrically connected to the source driver; The control electrode of the pth fourth switch transistor is electrically connected to the second selection control terminal, the first electrode of the pth fourth switch transistor is electrically connected to the pth reference voltage line, and the second electrode of the pth fourth switch transistor is electrically connected to the second DC voltage terminal.

8. The display control module according to claim 7, characterized in that: The P third switch transistors and the P fourth switch transistors are both n-type transistors, or the P third switch transistors and the P fourth switch transistors are both p-type transistors.

9. The display control module according to any one of claims 2 to 8, characterized in that: Also includes DC modules; The DC module is electrically connected to the first DC voltage terminal and the second DC voltage terminal respectively, and is used to provide a first DC voltage to the first DC voltage terminal and a second DC voltage to the second DC voltage terminal.

10. A display control method, applied to the display control module according to any one of claims 1 to 9, characterized in that: The display control method comprises: The source driver receives the image signal to be displayed, and determines whether the image signal to be displayed changes when the display cycle starts; When the image signal to be displayed does not change, it is detected that the display control module enters a low-speed driving mode, and the display cycle is set to include a refresh frame and at least one hold frame that are set successively; In the refresh frame, the first control signal, the first clock signal and the second clock signal are controlled so that the gating control signal generating circuit provides a first first gating control signal and a first second gating control signal, and the first switch circuit controls the source driver to provide a corresponding data voltage to the data line under the control of the first first gating control signal and the first second gating control signal; In the holding frame, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a second first selection control signal and a second second selection control signal, and the first switching circuit controls the first DC voltage terminal to provide the first DC voltage to the data line under the control of the second first selection control signal and the second second selection control signal.

11. The display control method according to claim 10, characterized in that: The display panel further includes a plurality of reference voltage lines; the display control module further includes a second switch circuit; and the display control method further includes: In the refresh frame, the second switch circuit controls the source driver to provide the reference voltage to the reference voltage line under the control of the first first gating control signal and the first second gating control signal; In the holding frame, the second switch circuit controls the second DC voltage terminal to provide the second DC voltage to the reference voltage line under the control of the second first selection control signal and the second second selection control signal.

12. The display control method according to claim 11, characterized in that: Also includes: When the image signal to be displayed changes, in the display period, by controlling the first control signal, the first clock signal and the second clock signal, the selection control signal generating circuit provides a first first selection control signal and a first second selection control signal, and the first switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide corresponding data voltages to multiple data lines respectively, and the second switching circuit, under the control of the first first selection control signal and the first second selection control signal, controls the source driver to provide reference voltages to multiple reference voltage lines respectively.

13. A display device, characterized in that: The device comprises a display control module as claimed in any one of claims 1 to 9.

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