Magnetic random access memory, memory arrays and electronic devices

Abstract

A magnetic random access memory (MRAM), a memory array, and an electronic device are disclosed. The MRAM includes: a drive signal module for providing a read signal; a memory array comprising multiple arrayed memory cells, each memory cell including a magnetic tunnel junction (MTJ) with a magnetically fixed layer and a magnetically free layer disposed opposite to each other; a data cell for loading the read signal and outputting a data voltage; a reference cell including a parallel-state reference cell and an anti-parallel-state reference cell; the magnetically free layer of the parallel-state reference cell is coupled to the magnetically fixed layer of the anti-parallel-state reference cell to form a reference output terminal; the reference cell is used to load the read signal and output a reference voltage through the reference output terminal; and a comparator circuit for reading data from the data cell based on the relative magnitude of the data voltage and the reference voltage. This invention helps reduce the possibility of the reference cell's resistive state flipping during read operations, ensuring the reliability of the reference cell and improving the performance of the MRAM.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and more particularly to a magnetic random access memory, a memory array, and an electronic device. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory. MRAM devices possess the high-speed read / write capabilities of Static Random Access Memory (SRAM) and the high integration density of Dynamic Random Access Memory (DRAM). Furthermore, they can be rewritten virtually an unlimited number of times, making MRAM a "fully kinetic" solid-state memory. Due to its high read / write speeds, long lifespan, and non-volatility, MRAM is considered the most widely used "general-purpose" processor of the future and is expected to dominate the next-generation memory market.

[0003] In MRAM devices, data is stored through the magnetic state of the storage element. An MRAM cell typically consists of a transistor and a magnetic tunnel junction (MTJ). The MTJ structure includes at least two electromagnetic layers and an insulating layer to isolate them. The two electromagnetic layers maintain two magnetic polarization fields separated by the insulating layer. One is a fixed magnetic layer with a fixed polarization direction, while the other is a freely rotating magnetic layer whose polarization direction can change with variations in the external field. When the polarization directions of the two electromagnetic layers are parallel, the tunneling current flowing through the MTJ structure reaches its maximum value, resulting in a lower resistance. When the polarization directions of the two magnetic layers are antiparallel, the tunneling current flowing through the MTJ structure reaches its minimum value, resulting in a higher resistance. Information is read by measuring the resistance of the MRAM cell; this is the operating principle of the MTJ structure.

[0004] However, the reliability of MRAM currently needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a magnetic random access memory, a memory array, and an electronic device that reduces the possibility of the resistive state of the reference cell flipping during a read operation and improves the reliability of the MRAM.

[0006] To address the aforementioned problems, this invention provides a magnetic random access memory (MRM), comprising: a drive signal module for providing a read signal; a storage array including multiple arrayed storage cells, each storage cell including a magnetic tunnel junction (MTJ) with a magnetically fixed layer and a magnetically free layer disposed opposite to each other; a storage cell for which data to be read is defined as a data cell, the data cell being loaded with the read signal and outputting a data voltage; a storage cell for which data is used as a reference for data reading is defined as a reference cell, the reference cell including a parallel-state reference cell and an anti-parallel-state reference cell; the magnetically free layer of the parallel-state reference cell and the magnetically fixed layer of the anti-parallel-state reference cell are coupled to form a reference output terminal, the reference cell being loaded with the read signal and outputting a reference voltage through the reference output terminal; and a comparison circuit for reading data from the data cell based on the relative magnitude of the data voltage and the reference voltage.

[0007] Accordingly, this invention also provides a storage array applied to a magnetic random access memory (MRM). The MRM includes: a drive signal module for providing a read signal to the storage array; a comparison circuit for reading data from the storage array based on the relative magnitude of a data voltage output by the storage array and a reference voltage; the storage array includes: a plurality of storage cells arranged in an array, each storage cell including a magnetic tunnel junction, the magnetic tunnel junction including a magnetically fixed layer and a magnetically free layer disposed opposite to each other; a storage cell for which data to be read is defined as a data cell, the data cell being used to load the read signal and output the data voltage; a storage cell for which data is used as a reference for reading is defined as a reference cell, the reference cell including a parallel-state reference cell and an anti-parallel-state reference cell; the magnetically free layer of the parallel-state reference cell is coupled to the magnetically fixed layer of the anti-parallel-state reference cell to form a reference output terminal, the reference cell being used to load the read signal and output the reference voltage through the reference output terminal.

[0008] Accordingly, embodiments of the present invention also provide an electronic device, including: a magnetic random access memory provided in embodiments of the present invention.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the magnetic random access memory provided in this embodiment of the invention, the reference cell includes a parallel-state reference cell and an anti-parallel-state reference cell. The magnetic free layer of the parallel-state (P-state) reference cell is coupled to the magnetic fixed layer of the anti-parallel-state (AP-state) reference cell to form a reference output terminal. The reference cell is used to load the read signal and output a reference voltage through the reference output terminal. In MRAM, the memory cell is written as a high-impedance state (R...H The current direction in the antiparallel state is consistent with the direction from the magnetic fixed layer to the magnetic free layer, and the memory cell is written as a low-resistance state (R). L In this embodiment of the invention, the magnetic free layer of the parallel reference unit and the magnetic fixed layer of the antiparallel reference unit are coupled to form a reference output terminal. Therefore, during a read operation, the direction of the read current through the antiparallel reference unit is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, and the direction of the read current through the parallel reference unit is consistent with the direction of the magnetic free layer pointing to the magnetic fixed layer. That is to say, the direction of the read current through the antiparallel reference unit is consistent with the direction of the write 1 current, and the direction of the read current through the parallel reference unit is consistent with the direction of the write 0 current. This ensures that after a long period of read operation, the resistance states of both the antiparallel and parallel reference units are not prone to flipping, reducing the possibility of the resistance state of the reference unit flipping during the read operation. Consequently, a more reliable reference resistor is provided for the data reading of the data unit, ensuring the reliability of the reference unit, thereby improving the data reading accuracy of the MRAM and improving the reliability of the MRAM.

[0011] In the memory array provided in this embodiment of the invention, the reference unit includes a parallel-state reference unit and an anti-parallel-state reference unit. The magnetic free layer of the parallel-state reference unit is coupled to the magnetic fixed layer of the anti-parallel-state reference unit to form a reference output terminal. The reference unit is used to load the read signal and output the reference voltage through the reference output terminal. Therefore, during a read operation, the direction of the read current through the anti-parallel-state reference unit is consistent with the direction from the magnetic fixed layer to the magnetic free layer, and the direction of the read current through the parallel-state reference unit is consistent with the direction from the magnetic free layer to the magnetic fixed layer. That is, the direction of the read current through the anti-parallel-state reference unit is consistent with the direction of the write 1 current, and the direction of the read current through the parallel-state reference unit is consistent with the direction of the write 0 current. This ensures that after a long period of read operation, the resistance states of both the anti-parallel-state and parallel-state reference units are not prone to flipping, reducing the possibility of the resistance state of the reference unit flipping during the read operation. Correspondingly, this provides a more reliable reference resistance for the data reading of the data unit, ensuring the reliability of the reference unit, thereby improving the data reading accuracy of the MRAM and the reliability of the MRAM.

[0012] The electronic device provided in this embodiment of the invention includes the aforementioned magnetic random access memory (MRAM). The resistance state of the reference cell in the MRAM is unlikely to flip during a read operation, thus providing a more reliable reference resistor for data reading of the data cell, ensuring the reliability of the reference cell, and thereby improving the data reading accuracy and reliability of the MRAM. Consequently, the performance of the electronic device provided in this embodiment of the invention is also improved, for example, by increasing the data reading accuracy, which is beneficial for optimizing the user experience and perception. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a magnetic random access memory.

[0014] Figures 2 to 4 This is a schematic diagram of the structure of an embodiment of the magnetic random access memory of the present invention;

[0015] Figure 5 This is a schematic diagram of another embodiment of the magnetic random access memory of the present invention. Detailed Implementation

[0016] As can be seen from the background technology, the reliability of MRAM currently needs to be improved.

[0017] Analysis revealed that the standard MRAM reference resistor read strategy uses multiple reference cells with magnetic tunnel junctions in antiparallel (i.e., high-resistance) and parallel (i.e., low-resistance) states as references for data reading. Generally, the number of times reference cells are read far exceeds the number of times data cells are read. Without special handling, after prolonged read operations, the resistance state of the reference cells is prone to flipping, causing changes in the reference resistance value, a rapid increase in the data read error rate, and reduced MRAM reliability.

[0018] This paper analyzes the reasons why the reliability of MRAM needs to be improved by combining it with a magnetic random access memory. Figure 1 This is a schematic diagram of a magnetic random access memory.

[0019] like Figure 1As shown, the magnetic random access memory includes: a drive signal module 16 for providing a read signal; a storage array including multiple array-arranged storage cells, each storage cell including a magnetic tunnel junction 10, the magnetic tunnel junction 10 including a magnetic fixed layer 101 and a magnetic free layer 102 located on the magnetic fixed layer 101; a storage cell for reading data is defined as a data cell 11, and a storage cell for reading data is defined as a reference cell 12, the reference cell 12 including a high-resistivity (RH) reference cell 12H and a low-resistivity (RL) reference cell 12L, the magnetic free layers 102 of the high-resistivity reference cell 12H and the low-resistivity reference cell 12L are coupled to form a reference output terminal 13A; The load circuit 14 is coupled to the data unit 11 and to the reference output terminal 13A of the reference unit 13. The load circuit 14 is used to convert the read current of the data unit 11 into the data voltage Vdata and to convert the read current of the reference unit 13 into the reference voltage Vref. The comparator circuit 15 includes a first input terminal 151, a second input terminal 152 and an output terminal 153. The first input terminal 151 is coupled to the data unit 11 and the second input terminal 152 is coupled to the reference output terminal 13A. The comparator circuit 15 is used to read the information of the data unit 11 according to the relative magnitude of the data voltage Vdata and the reference voltage Vref. The output terminal 153 outputs the comparison result signal.

[0020] like Figure 1 As indicated by the direction of the dashed arrow, when reading from the magnetic random access memory, the read current first passes through the magnetic free layer 102 of MTJ 10 and then through the magnetic reference layer 101. The read current is opposite in direction to the write 1 (RH) current of the high-resistivity reference cell 12H, that is, it is in the same direction as the write current that writes the high-resistivity reference cell 12H from a high-resistivity state to a low-resistivity state. When in a data read state for a long time, the resistance state of MTJ 10 in the high-resistivity reference cell 12H is at high risk of flipping. In other words, MTJ 10 in the high-resistivity reference cell 12H is prone to flipping from the antiparallel (AP) state to the parallel (P) state, which causes the reference resistance value to change, reduces the accuracy of MRAM data reading, and thus reduces the reliability of MRAM.

[0021] One way to optimize the above problem is to set the reference cell's bit line voltage Vread(REF_BL) lower than the data cell's bit line voltage Vread(BL) during read operations. Since data writing typically requires a large write current, reducing the reference bit line voltage decreases the read current of the reference cell, thus reducing the risk of resistance state flipping in the high-resistivity reference cell.

[0022] However, this does not solve the problem of the reference cell's resistance state flipping; the reference cell's resistance state still has a certain possibility of flipping. Moreover, this will increase the complexity and difficulty of circuit design.

[0023] To address the aforementioned technical problem, this invention provides a magnetic random access memory (MRAM). The magnetic free layer of the parallel-state reference cell is coupled to the magnetic fixed layer of the antiparallel-state reference cell, forming a reference output terminal. Therefore, during a read operation, the direction of the read current through the antiparallel-state reference cell is consistent with the direction from the magnetic fixed layer to the magnetic free layer, and the direction of the read current through the parallel-state reference cell is consistent with the direction from the magnetic free layer to the magnetic fixed layer. In other words, the direction of the read current through the antiparallel-state reference cell is consistent with the direction of the current for writing 1, and the direction of the read current through the parallel-state reference cell is consistent with the direction of the current for writing 0. This ensures that after a long period of read operations, the resistance states of both the antiparallel-state and parallel-state reference cells are less likely to flip, reducing the possibility of the resistance state of the reference cell flipping during read operations. Correspondingly, this provides a more reliable reference resistor for data reading from the data unit, ensuring the reliability of the reference unit and thus improving the data read accuracy and reliability of the MRAM.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 2 to 4 This is a schematic diagram of the structure of an embodiment of the magnetic random access memory of the present invention.

[0025] In this embodiment, the magnetic random access memory (MRAM) 200 includes: a drive signal module 180 for providing read signals; and a storage array 400 including multiple arrayed storage cells, each storage cell including a magnetic tunnel junction (MTJ) 100, the MTJ 100 including a pinned layer 1001 and a free layer 1001 disposed opposite to each other. Layer 1002 defines a storage unit for the data to be read as a data unit 110. The data unit 110 is used to load a read signal and output a data voltage Vdata. A storage unit for use as a data read reference is defined as a reference unit 120. The reference unit 120 includes an anti-parallel (AP state) reference unit 120H and a parallel (P state) reference unit 120L. The magnetic free layer 1002 of the parallel state reference unit 120L is coupled to the magnetic fixed layer 1001 of the anti-parallel state reference unit 120H to form a reference output terminal 120A. The reference unit 120 is used to load a read signal and output a reference voltage Vref through the reference output terminal 120A. A comparison circuit 150 is used to read the data of the data unit 110 according to the relative magnitude of the data voltage Vdata and the reference voltage Vref.

[0026] In this embodiment, "coupling" refers to direct or indirect connection. The meaning of "coupling" will be consistent throughout the following text and will not be explained one by one.

[0027] The drive signal module 180 is used to provide a read signal to the storage array 400 so that the storage array 400 outputs data based on the read signal. In this embodiment, the drive signal module 180 is used to provide a bit line voltage, the reference unit 120 is used to load the bit line voltage and output a reference current through the reference output terminal 120A, and the data unit 110 is used to load the bit line voltage and output a data current.

[0028] In this embodiment, the magnetic random access memory 200 further includes a load circuit 140, which is coupled to the data unit 110 and to the reference output terminal 120A; the load circuit 140 is used to convert the read current of the data unit 110 into a data voltage Vdata, and to convert the read current of the reference unit 120 into a reference voltage Vref.

[0029] In this embodiment, the drive signal module 180 includes: a clamping circuit 160 coupled to the load circuit 140, the clamping circuit 160 being used to clamp the bit line voltages of the data unit 110 and the reference unit 120; and a bit line selection circuit 170, one end of which is coupled to the clamping circuit 160, and the other end of which is coupled to the data unit 110 and the reference output terminal 120A of the reference unit 120, respectively, the bit line selection circuit 170 being adapted to select the data unit 110 to be read and the reference unit 120.

[0030] The clamping circuit 160 is used to provide bit line voltages to the data unit 110 and the reference unit 120, and to clamp the bit line voltages of the data unit 110 and the reference unit 120, thereby limiting the bit line voltages of the data unit 110 and the reference unit 120 to a preset range, so as to prevent the bit line voltages of the data unit 110 and the reference unit 120 from being too large, which would damage the magnetic tunnel junction 100 of the data unit 110 and the reference unit 120, thereby protecting the data unit 110 and the reference unit 120.

[0031] In this embodiment, the clamping circuit 160 includes an NMOS transistor. The drain of the NMOS transistor is coupled to the load circuit 140, the source is coupled to the bit line selection circuit 170, and the gate is used to load the clamping control signal VClamp.

[0032] During a read operation, the voltage applied to the gate of the NMOS transistor is the sum of the threshold voltage of the NMOS transistor and the bit line voltage, thereby ensuring that the bit line voltage applied to the data unit 110 or the reference unit 120 is the preset bit line voltage. When the voltage applied to the gate of the NMOS transistor is greater than the preset bit line voltage, the channel of the NMOS transistor will be turned off, thus protecting the circuit.

[0033] like Figure 3 As shown, in a specific implementation, the clamping circuit 160 may include a first NMOS transistor N1 and a second NMOS transistor N2. The drain of the first NMOS transistor N1 is coupled to the first output terminal of the load circuit 140, and the gate of the first NMOS transistor N1 is coupled to the clamping control signal VClamp. The drain of the second NMOS transistor N2 is coupled to the second output terminal of the load circuit 140, and the gate of the second NMOS transistor N2 is adapted to be coupled to the clamping control signal VClamp. The first NMOS transistor N1 and the second NMOS transistor N2 are adapted to clamp the bit line voltages of the data unit 110 and the reference unit 120 under the control of the same clamping control signal VClamp, so as to avoid damage caused by excessive bit line voltages of the data unit 110 and the reference unit 120 due to factors such as misoperation.

[0034] In a specific implementation, the bit line selection circuit 170 may include a first bit line selection switch MUX. data and the second bit selection switch MUX ref The first line selector switch MUX data The first connection terminal is coupled to the source of the first NMOS transistor N1, and the first line selection switch MUX is used. data The second connection terminal is coupled to the data unit 110, and the first line selection switch MUX data Used to select the data unit 110 to be read.

[0035] In practical implementation, the second bit line selection switch MUX ref The first connection terminal is coupled to the source of the second NMOS transistor N2, and the second bit line selection switch MUX ref The second connection terminal is coupled to the reference unit 120, and the second bit line selection switch MUX ref Used to select the reference cell 120 to be read. Specifically, the second bit line selection switch MUX ref The second connection terminal is coupled to the reference output terminal 120A.

[0036] Storage units are used to store data. For example... Figure 4 As shown, the storage array 400 includes multiple storage cells arranged in a matrix. These multiple storage cells are repeating cells, meaning they have the same structure.

[0037] Therefore, the antiparallel reference unit 120H or the parallel reference unit 120L has the same structure as the data unit 110, which is beneficial to improving the accuracy of the reference unit 120 as a reference for data reading.

[0038] In a specific implementation, the magnetic tunnel junction 100 in the storage cell is used to store data. Specifically, when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are parallel, the storage cell is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low-resistance state (RL); when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are antiparallel, the storage cell is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high-resistance state (RH).

[0039] The magnetization direction of the magnetically fixed layer 1001 is fixed and serves as a reference layer for the magnetization direction of the magnetically free layer 1002. The magnetically free layer 1002 has two stable orientations, parallel or opposite to the magnetization direction of the magnetically fixed layer 1001, thereby enabling the magnetic tunnel junction 100 to be in a low-resistance or high-resistance state. Both the magnetically free layer 1002 and the magnetically fixed layer 1001 are made of ferromagnetic metallic materials, such as CoFeB or CoFe.

[0040] In this embodiment, the magnetic tunnel junction 100 further includes a tunneling barrier layer 1003 located between the magnetically fixed layer 1001 and the magnetically free layer 1002. The tunneling barrier layer 1003 is used to achieve electrical isolation between the magnetically fixed layer 1001 and the magnetically free layer 1002. The material of the tunneling barrier layer 1003 is an insulating material, such as MgO, SrO, BaO, RaO, SiO2, Al2O3, HfO2, NiO, GdO, Ta2O5, MoO2, TiO2, or WO2.

[0041] As an example, the magnetic tunnel junction 100 is bottom-pinned and includes a magnetically fixed layer 1001 and a magnetically free layer 1002 located on the magnetically fixed layer 1001.

[0042] The storage cell also includes a selection transistor N0 connected to the magnetic tunnel junction 100, the gate of which is coupled to the word line WL. The selection transistor N0 is adapted to be turned on or off under the control of a signal connected to the word line WL to read data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor. Figure 4 As shown, in the memory array 400, multiple memory cells are arranged in an array. The gate of the select transistor of each memory cell is connected to the corresponding word line WL. <n>Coupled, where n is an integer greater than or equal to 0.

[0043] In this embodiment, the magnetic tunnel junction 100 is magnetically fixed at the bottom. Correspondingly, in the data unit 110, the drain of the selection transistor N0 is coupled to the magnetic fixing layer 1002 of the magnetic tunnel junction 100, and the source line SL of the selection transistor N0 is grounded to VSS.

[0044] In a specific implementation, the magnetic random access memory 200 uses at least one antiparallel reference cell 120H and at least one parallel reference cell 120L to form a standard resistor. By comparing the data cell 110 with the standard resistor, it is determined whether the data cell 110 is in a high resistance state or a low resistance state, thereby realizing the reading of data from the data cell 110.

[0045] Data unit 110 contains data to be read, and the resistance state of the magnetic tunnel junction 100 in data unit 110 needs to be confirmed.

[0046] Reference unit 120 is adapted to store and output reference data, which is used as a reference for reading data from data unit 110. Reference output terminal 120A is used to output a reference signal for reading data from data unit 110. Specifically, during a read operation, reference unit 120 outputs a reference signal through reference output terminal 120A based on the read signal provided by drive signal module 180.

[0047] Specifically, the reference unit 120 includes at least one antiparallel state (i.e., high resistance state (RH)) reference unit 120H and at least one parallel state (i.e., low resistance state (RL)) reference unit 120L. The magnetic tunnel junction 100 in the at least one antiparallel state reference unit 120H and the at least one parallel state reference unit 120L forms a standard resistor. By comparing the data unit 110 with the standard resistor, it is determined whether the data unit 110 is in a high resistance state or a low resistance state, thereby realizing the data reading of the data unit 110.

[0048] In this embodiment, the antiparallel reference unit 120H refers to the magnetic tunnel junction 100 in the antiparallel reference unit 120H being in an antiparallel (AP) state, with the magnetic direction of the magnetic free layer 1002 being antiparallel to the magnetic direction of the magnetic fixed layer 1001; the parallel reference unit 120L refers to the magnetic tunnel junction 100 in the parallel reference unit 120L being in a parallel (P) state, with the magnetic direction of the magnetic free layer 1002 being parallel to the magnetic direction of the magnetic fixed layer 1001.

[0049] As an example, in reference cell 120, the number of antiparallel reference cells 120H and parallel reference cells 120L is the same, and the number of both antiparallel reference cells 120H and parallel reference cells 120L is y; where y is a positive integer. By making the number of antiparallel reference cells 120H and parallel reference cells 120L the same, it is beneficial to reduce the complexity of circuit design.

[0050] In this embodiment, for ease of illustration and explanation, the reference unit 120 is shown to include one antiparallel reference unit 120H and one parallel reference unit 120L as an example. However, the number of antiparallel reference units 120H and parallel reference units 120L included in the reference unit 120 is not limited to this. In other embodiments, the reference unit may include multiple antiparallel reference units and parallel reference units, and the number of antiparallel reference units and parallel reference units may also be different.

[0051] In MRAM, the direction of the write current (writing "0") that changes the magnetic tunnel junction 100 from a high-resistivity state (i.e., anti-parallel state) to a low-resistivity state (i.e., parallel state) is the same as the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, and the direction of the write current (writing "1") that changes the magnetic tunnel junction 100 from a low-resistivity state to a high-resistivity state is the same as the direction of the magnetic fixed layer 1001 pointing to the magnetic free layer 1002.

[0052] In this embodiment, the magnetic fixed layer 1001 of the antiparallel reference unit 120H and the magnetic free layer 1002 of the parallel reference unit 120L are coupled to form a reference output terminal 120A. The magnetic tunnel junction 100 in the antiparallel reference unit 120H and the parallel reference unit 120L are coupled to the drive signal module 180 in different ways. Therefore, during the read operation, the direction of the read current through the antiparallel reference unit 120H is consistent with the direction of the magnetic fixed layer 1001 pointing to the magnetic free layer 1002, and the direction of the read current through the parallel reference unit 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001. When the direction of the read current through the antiparallel reference unit 120H is consistent with the direction of the write 1 current, the direction of the read current through the parallel reference unit 120L is consistent with the direction of the write 0 current. This ensures that after a long period of read operation, the resistive state of the antiparallel reference unit 120H and the parallel reference unit 120L is not easily flipped.

[0053] As an example, the magnetic tunnel junction 100 is bottom-pinned and includes a magnetically fixed layer 1001 and a magnetically free layer 1002 located on the magnetically fixed layer 1001.

[0054] Accordingly, in this embodiment, the magnetic free layer 1001 of the data unit 110 is coupled to the load circuit 140.

[0055] Specifically, the drain of the selection transistor N0 in the data unit 110 is coupled to the magnetic fixing layer 1001 of the magnetic tunnel junction 100, and the source of the selection transistor N0 in the data unit 110 is grounded to VSS.

[0056] Accordingly, in this embodiment, in the parallel-state reference cell 120L, the drain of the selected transistor N0 is coupled to the magnetic fixing layer 1001 of the magnetic tunnel junction 100, and the source of the selected transistor N0 is REF_SL. <0> Grounded VSS, the magnetic free layer 1002 of the magnetic tunnel junction 100 is used to form the reference output terminal 120A.

[0057] In this embodiment, in the antiparallel reference cell 120H, the drain of the selector transistor N0 is coupled to the magnetic fixing layer 1001 of the magnetic tunnel junction 100, and the source of the selector transistor N0 is REF_SL. <1> The magnetic free layer 1002 is used to form the reference output terminal 120A and the magnetic tunnel junction 100, grounded VSS.

[0058] In this embodiment, during the read operation, the direction of the read current is along the reference output terminal 120A towards the ground terminal VSS. Specifically, in this embodiment, in the parallel state reference cell 120L, the direction of the read current through the magnetic tunnel junction 100 is consistent with the direction of the magnetic free layer 1002 towards the magnetic fixed layer 1001, that is, the same as the current direction that writes the magnetic tunnel junction 100 into a low-resistance state or a parallel state. Since the magnetic tunnel junction 100 in the parallel state reference cell 120L is already in a low-resistance state, it can prevent the resistance state of the parallel state reference cell 120L from flipping.

[0059] In the antiparallel reference cell 120H, the direction of the read current through the magnetic tunnel junction 100 is consistent with the direction of the magnetic fixed layer 1001 pointing to the magnetic free layer 1002, which is the same as the direction of the current that writes the magnetic tunnel junction 100 as a high-resistance state or an antiparallel state. Since the magnetic tunnel junction 100 in the antiparallel reference cell 120H is already in a high-resistance state, the resistance state of the antiparallel reference cell 120H can be prevented from flipping.

[0060] The load circuit 120 is used to convert the read current of the data unit 110 into a data voltage Vdata, and to convert the read current of the reference unit 120 into a reference voltage Vref, so that the comparison circuit 150 can read the information of the data unit 110 by comparing the relative magnitudes of the data voltage Vdata and the reference voltage Vref.

[0061] The load circuit 140 includes an input terminal (not shown), a first output terminal (not shown), and a second output terminal (not shown). The input terminal of the load circuit 140 is coupled to the power supply VDD, the first output terminal is coupled to the data unit 110, and the second output terminal is coupled to the reference output terminal 120A.

[0062] like Figure 2 As shown, when no data is being read, the data voltage Vdata obtained by the load circuit 140 is equal to the reference voltage Vref. When data is being read, if the resistance of the data unit 110 is in a low-resistance state RL, the data voltage Vdata at the connection point between the comparator circuit 150 and the load circuit 140 will be pulled down by the resistance of the low-resistance state RL. Compared with the state when no data is being read, the data voltage Vdata decreases and shows a decreasing trend. The comparator circuit 150 can detect that the data voltage Vdata of the data unit 110 is less than the reference voltage Vref, thereby determining that the data bit stored in the data unit 110 is "0".

[0063] If the resistance of data unit 110 is in a high-resistance state RH, the data voltage Vdata connected to the connection point of comparator circuit 150 and load circuit 140 will be pulled up by the resistance of the high-resistance state RH. Compared with the state where no data is read, the data voltage Vdata increases and shows an increasing trend. Comparator circuit 150 can detect that the data voltage Vdata of data unit 110 is greater than the reference voltage Vref of reference unit 120, thereby determining that the data bit stored in data unit 110 is "1", or vice versa.

[0064] In this embodiment, the load circuit 140 is a current mirror. The current mirror is used to mirror the read current generated by the reference unit 120 into the data unit 110, and to convert the read current of the data unit 110 into a data voltage Vdata.

[0065] In this embodiment, the reference unit 120 includes the same number of antiparallel reference units 120H and parallel reference units 120L, and the number of both antiparallel reference units 120H and parallel reference units 120L is y; where y is a positive integer.

[0066] During a read operation, the bit line voltage applied by the drive signal module 180 to the data unit 110 is the data bit line voltage Vread(BL), and the bit line voltage applied by the drive signal module 180 to the reference unit 120 is the reference bit line voltage Vread(REF_BL). The mirror ratio used from the reference unit 120 to the data unit 110 is 2y:x, where x is the ratio of the data bit line voltage Vread(BL) to the reference bit line voltage Vread(REF_BL). By setting the above mirror ratio, it is ensured that the read current of the data unit 110 is compared with the read current generated by the reference unit 120 under the same bit line voltage.

[0067] In this embodiment, the data bit line voltage Vread(BL) and the reference bit line voltage Vread(REF_BL) are the same, so the mirror ratio compensation factor x = 1. The mirror ratio compensation factor x is an integer, which helps to reduce the complexity of circuit design. Moreover, the drive signal module 180 includes a clamping circuit 160 coupled to the load circuit 140. The clamping circuit 160 is used to clamp the bit line voltages of the data unit 110 and the reference unit 120. By making the data bit line voltage Vread(BL) and the reference bit line voltage Vread(REF_BL) the same, the data unit 110 and the reference unit 120 can use the same clamping voltage module 160, which also helps to reduce the design complexity of the clamping circuit 160.

[0068] As an example, the current mirror includes: a first PMOS transistor group P_Cell and a second PMOS transistor group P_REF, wherein both the first PMOS transistor group P_Cell and the second PMOS transistor group P_REF include one or more PMOS transistors connected in parallel.

[0069] In the first PMOS transistor group P_Cell, the source of the PMOS transistor is coupled to the power supply VDD, the drain of the PMOS transistor is coupled to the gate of the PMOS transistor, and the drain of the PMOS transistor is coupled to the data cell 110. The first PMOS transistor group P_Cell is adapted to convert the read current through the first PMOS transistor group P_Cell into the data voltage Vdata.

[0070] In the second PMOS transistor group P_REF, the source of the PMOS transistor is coupled to the power supply VDD, the drain of the PMOS transistor is coupled to the gate, and the drain of the PMOS transistor is coupled to the reference output terminal 120A. The second PMOS transistor group P_REF is suitable for converting the read current through the second PMOS transistor group into the reference voltage Vref.

[0071] Correspondingly, the drain of the PMOS transistor in the first PMOS transistor group is the first output terminal of the load circuit 140, and the drain of the PMOS transistor in the second PMOS transistor group P_REF is the second output terminal of the load circuit 140.

[0072] In this embodiment, the data bit line voltage Vread(BL) and the reference bit line voltage Vread(REF_BL) are the same, so the mirror ratio compensation factor x = 1, and the first PMOS transistor group P_Cell is a PMOS transistor.

[0073] In this embodiment, the number of antiparallel reference units 120H and parallel reference units 120L is the same, and the number of antiparallel reference units 120H and parallel reference units 120L is y; where y is a positive integer, therefore, the second PMOS transistor group includes 2y parallel PMOS transistors.

[0074] As an example, there is one antiparallel reference cell 120H and one parallel reference cell 120L. Therefore, the second PMOS transistor group P_REF includes two PMOS transistors connected in parallel.

[0075] The comparator circuit 150 is used to read information from the data unit 110 based on the relative magnitudes of the data voltage Vdata and the reference voltage Vref. In this embodiment, the comparator circuit 150 includes a first input terminal 1501, a second input terminal 1502, and an output terminal 1503. The first input terminal 1501 is coupled to the data unit 110, and the second input terminal 1502 is coupled to the reference output terminal 120A. The comparator circuit 150 is used to read information from the data unit 110 based on the relative magnitudes of the data voltage Vdata and the reference voltage Vref, and the output terminal 1503 outputs a comparison result signal.

[0076] In this embodiment, the comparator circuit 150 is a sense amplifier (SA). As an example, the non-inverting input of the sense amplifier is coupled to the data unit 110, and the inverting input of the sense amplifier is coupled to the reference unit 120.

[0077] In specific implementation, if the data voltage Vdata is less than the reference voltage Vref, it can be determined that the data stored in the data unit 110 is "0", and the magnetic tunnel junction 100 of the data unit 110 is in a low-resistance state (i.e., parallel state); if the data voltage Vdata is greater than the reference voltage Vref, it can be determined that the data stored in the data unit 110 is "1", and the magnetic tunnel junction 100 of the data unit 110 is in a high-resistance state (i.e., anti-parallel state); or vice versa.

[0078] Figure 5 This is a schematic diagram of another embodiment of the magnetic random access memory of the present invention. The similarities between the present invention and the previous embodiments will not be repeated here. The difference is that the magnetic tunnel junction 300 is top-pinned, and the magnetic tunnel junction 300 includes a magnetic free layer 3002 and a magnetic fixed layer 3001 located on the magnetic free layer 3002.

[0079] In this embodiment, the magnetic fixing layer 3001 of the data unit 310 is coupled to the load circuit 340.

[0080] In this embodiment, the storage unit further includes a selection transistor N0 connected to the magnetic tunnel junction 300, and the gate of the selection transistor N0 is coupled to the word line WL.

[0081] Accordingly, in this embodiment, in the data unit 310, the drain of the selection transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the selection transistor N0 is grounded.

[0082] In this embodiment, in the parallel state reference cell 320L, the drain of the selective transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, the source of the selective transistor N0 is used to form the reference output terminal 320A, and the magnetic fixed layer 3001 of the magnetic tunnel junction 300 is grounded to VSS.

[0083] In this embodiment, in the antiparallel reference cell 320H, the magnetic fixing layer 3001 of the magnetic tunnel junction 300 is used to form the reference output terminal 320A, the drain of the selective transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the selective transistor N0 is grounded to VSS.

[0084] In MRAM, the direction of the write current (writing "0") that changes the magnetic tunnel junction 300 from a high-resistivity state (i.e., anti-parallel state) to a low-resistivity state (i.e., parallel state) is the same as the direction of the magnetic free layer 3002 pointing towards the magnetic fixed layer 3001, and the direction of the write current (writing "1") that changes the magnetic tunnel junction 300 from a low-resistivity state to a high-resistivity state is the same as the direction of the magnetic fixed layer 3001 pointing towards the magnetic free layer 3002.

[0085] In this embodiment, during the read operation, the direction of the read current is along the reference output terminal 320A towards the ground terminal VSS. Specifically, in this embodiment, in the parallel state reference cell 320L, the direction of the read current through the magnetic tunnel junction 300 is consistent with the direction of the magnetic free layer 3002 towards the magnetic fixed layer 3001, which is the same as the direction of the current that writes the magnetic tunnel junction 300 into a low-resistance state (i.e., parallel state). Since the magnetic tunnel junction 300 in the parallel state reference cell 320L is already in a low-resistance state, it can prevent the resistance state of the parallel state reference cell 320L from flipping.

[0086] In the antiparallel reference cell 320H, the direction of the read current through the magnetic tunnel junction 300 is consistent with the direction of the magnetic fixed layer 3001 pointing to the magnetic free layer 3002, which is the same as the direction of the current that writes the magnetic tunnel junction 300 as a high-resistance state. Since the magnetic tunnel junction 300 in the antiparallel reference cell 320H is already in a high-resistance state, the resistance state of the antiparallel reference cell 320H can be prevented from flipping.

[0087] For a detailed description of the magnetic random access memory in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0088] Accordingly, this embodiment of the invention also provides a storage array. Figure 4 This is a schematic diagram of the structure of a storage array according to an embodiment of the present invention.

[0089] In this embodiment, the storage array 400 is applied to a magnetic random access memory, which includes: a drive signal module for providing a read signal to the storage array; and a comparison circuit for reading data from the storage array based on the relative magnitude of the data voltage output by the storage array 400 and a reference voltage.

[0090] Reference Figure 4 In this embodiment, the storage array 400 includes: a plurality of storage cells arranged in an array, each storage cell including a magnetic tunnel junction 100, the magnetic tunnel junction 100 including a magnetically fixed layer 1001 and a magnetically free layer 1002 disposed opposite to each other; a storage cell for reading data is defined as a data cell 110, the data cell 110 is used to load a read signal and output a data voltage Vdata; a storage cell for use as a data reading reference is defined as a reference cell 120, the reference cell 120 including an antiparallel state (AP state) reference cell 120H and a parallel state (P state) reference cell 120L, the magnetically free layer 1002 of the parallel state reference cell 120L is coupled to the magnetically fixed layer 1001 of the antiparallel state reference cell 120H to form a reference output terminal 120A, the reference cell 120 is used to load a read signal and output a reference voltage Vref through the reference output terminal 120A.

[0091] In this embodiment, the magnetic free layer 1002 of the parallel-state reference unit 120L is coupled to the magnetic fixed layer 1001 of the anti-parallel-state reference unit 120H to form a reference output terminal 120A. The reference unit 120 is used to load the read signal and outputs a reference voltage Vref through the reference output terminal 120A. Therefore, during the read operation, the direction of the read current through the anti-parallel-state reference unit 120H is consistent with the direction from the magnetic fixed layer 1001 to the magnetic free layer 1002, and the direction of the read current through the parallel-state reference unit 120L is consistent with the direction from the magnetic free layer 1002 to the magnetic fixed layer 1001. In other words, the direction of the read current through the parallel-state reference unit 120L is consistent with the direction from the magnetic free layer 1002 to the magnetic fixed layer 1001. The read current direction through the anti-parallel reference cell 120H is consistent with the write current direction of 1, and the read current direction through the parallel reference cell 120L is consistent with the write current direction of 0. This ensures that after a long read operation, the resistance states of the anti-parallel reference cell 120H and the parallel reference cell 120L are not prone to flipping. This reduces the possibility of the resistance state of the reference cell 120 flipping during the read operation, and provides a more reliable reference resistor for the data reading of the data cell, ensuring the reliability of the reference cell, thereby improving the data reading accuracy of the MRAM and the reliability of the MRAM.

[0092] The storage unit is used to store data. Multiple storage units are duplicate units, meaning multiple storage units have the same structure. Therefore, the antiparallel reference unit 120H or the parallel reference unit 120L has the same structure as the data unit 110, which helps to improve the accuracy of the reference unit 120 as a data reading reference.

[0093] In a specific implementation, the magnetic tunnel junction 100 in the storage cell is used to store data. Specifically, when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are parallel, the storage cell is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low-resistance state (RL); when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are antiparallel, the storage cell is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high-resistance state (RH).

[0094] The magnetization direction of the magnetically fixed layer 1001 is fixed and serves as a reference layer for the magnetization direction of the magnetically free layer 1002. The magnetization direction of the magnetically free layer 1002 has two stable orientations, parallel or opposite to the magnetization direction of the magnetically fixed layer 1001, thereby enabling the magnetic tunnel junction 100 to be in a low-resistance state (i.e., parallel state) or a high-resistance state (anti-parallel state). The materials of the magnetically free layer 1002 and the magnetically fixed layer 1001 are ferromagnetic metallic materials.

[0095] In this embodiment, the magnetic tunnel junction 100 further includes a tunneling barrier layer 1003 located between the magnetically fixed layer 1001 and the magnetically free layer 1002. The tunneling barrier layer 1003 is used to achieve electrical isolation between the magnetically fixed layer 1001 and the magnetically free layer 1002. The material of the tunneling barrier layer 1003 is an insulating material.

[0096] As an example, the magnetic tunnel junction 100 is bottom-pinned and includes a magnetically fixed layer 1001 and a magnetically free layer 1002 located on the magnetically fixed layer 1001.

[0097] The storage cell also includes a selection transistor N0 connected to the magnetic tunnel junction 100, the gate of which is coupled to the word line WL. The selection transistor N0 is adapted to be turned on or off under the control of a signal connected to the word line WL to read data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor.

[0098] In this embodiment, the magnetic tunnel junction 100 is magnetically fixed at the bottom. The magnetic tunnel junction 100 includes a magnetically fixed layer 1001 and a magnetically free layer 1002 located on the magnetically fixed layer 1001. Correspondingly, in the data unit 110, the drain of the selection transistor N0 is coupled to the magnetically fixed layer 1002 of the magnetic tunnel junction 100, and the source of the selection transistor N0 is grounded to VSS.

[0099] In a specific implementation, the magnetic random access memory 200 uses at least one antiparallel reference cell 120H and at least one parallel reference cell 120L to form a standard resistor. By comparing the data cell 110 with the standard resistor, it is determined whether the data cell 110 is in a high resistance state or a low resistance state, thereby realizing the reading of data from the data cell 110.

[0100] Data unit 110 contains data to be read, and the resistance state of the magnetic tunnel junction 100 in data unit 110 needs to be confirmed. Reference unit 120 is adapted to store and output reference data, which is used as a reference for reading data from data unit 110.

[0101] The reference output terminal 120A is used to output a reference signal for reading data from the data unit 110. Specifically, during a read operation, the reference unit 120 outputs a reference signal through the reference output terminal 120A based on the read signal provided by the drive signal module 180.

[0102] Specifically, the reference unit 120 includes at least one antiparallel state (i.e., high resistance state (RH)) reference unit 120H and at least one parallel state (i.e., low resistance state (RL)) reference unit 120L. The magnetic tunnel junction 100 in the at least one antiparallel state reference unit 120H and the at least one parallel state reference unit 120L forms a standard resistor. By comparing the data unit 110 with the standard resistor, it is determined whether the data unit 110 is in a high resistance state or a low resistance state, thereby realizing the data reading of the data unit 110.

[0103] In this embodiment, the antiparallel reference unit 120H refers to the magnetic tunnel junction 100 in the antiparallel reference unit 120H being in an antiparallel (AP) state, with the magnetic direction of the magnetic free layer 1002 being antiparallel to the magnetic direction of the magnetic fixed layer 1001; the parallel reference unit 120L refers to the magnetic tunnel junction 100 in the parallel reference unit 120L being in a parallel (P) state, with the magnetic direction of the magnetic free layer 1002 being parallel to the magnetic direction of the magnetic fixed layer 1001.

[0104] As an example, in reference cell 120, the number of antiparallel reference cells 120H and parallel reference cells 120L is the same, and the number of both antiparallel reference cells 120H and parallel reference cells 120L is y; where y is a positive integer. By making the number of antiparallel reference cells 120H and parallel reference cells 120L the same, it is beneficial to reduce the complexity of circuit design.

[0105] In this embodiment, for ease of illustration and explanation, the reference unit 120 is shown to include one antiparallel reference unit 120H and one parallel reference unit 120L as an example. However, the number of antiparallel reference units 120H and parallel reference units 120L included in the reference unit 120 is not limited to this. In other embodiments, the reference unit may include multiple antiparallel reference units and parallel reference units, and the number of antiparallel reference units and parallel reference units may also be different.

[0106] As an example, the magnetic tunnel junction 100 is magnetically fixed at the bottom and includes a magnetically fixed layer 1001 and a magnetically free layer 1002 located on the magnetically fixed layer 1001. Specifically, the drain of the selection transistor N0 in the data unit 110 is coupled to the magnetically fixed layer 1001 of the magnetic tunnel junction 100, and the source of the selection transistor N0 in the data unit 110 is grounded to VSS.

[0107] Accordingly, in this embodiment, in the parallel state reference cell 120L, the drain of the selective transistor N0 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100, the source of the selective transistor N0 is grounded to VSS, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is used to form the reference output terminal 120A.

[0108] In this embodiment, in the antiparallel reference cell 120H, the drain of the selective transistor N0 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100, the source of the selective transistor N0 is used to form the reference output terminal 120A, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is grounded to VSS.

[0109] In this embodiment, during the read operation, the direction of the read current is along the reference output terminal 120A and points towards the ground terminal VSS.

[0110] Specifically, in the parallel state reference cell 120L, the direction of the read current through the magnetic tunnel junction 100 is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, which is the same as the direction of the current that writes the magnetic tunnel junction 100 as a low-resistance state or a parallel state. Since the magnetic tunnel junction 100 in the parallel state reference cell 120L is already in a low-resistance state, it can prevent the resistance state of the parallel state reference cell 120L from flipping.

[0111] In the antiparallel reference cell 120H, the direction of the read current through the magnetic tunnel junction 100 is consistent with the direction of the magnetic fixed layer 1001 pointing to the magnetic free layer 1002, which is the same as the direction of the current that writes the magnetic tunnel junction 100 as a high-resistance state or an antiparallel state. Since the magnetic tunnel junction 100 in the antiparallel reference cell 120H is already in a high-resistance state, the resistance state of the antiparallel reference cell 120H can be prevented from flipping.

[0112] Accordingly, the present invention also provides a storage array according to another embodiment. The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that the magnetic tunnel junction is top-pinned, and the magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer.

[0113] In this embodiment, the memory cell further includes a selection transistor connected to a magnetic tunnel junction, with the gate of the selection transistor coupled to the word line. Correspondingly, in this embodiment, in the data cell, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

[0114] In this embodiment, in the parallel-state reference cell, the drain of the selected transistor is coupled to the magnetic free layer of the magnetic tunnel junction, the source of the selected transistor is used to form the reference output terminal, and the magnetic fixed layer of the magnetic tunnel junction is grounded.

[0115] In this embodiment, in the antiparallel reference cell, the magnetic fixing layer of the magnetic tunnel junction is used to form the reference output terminal, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

[0116] In MRAM, the direction of the write current (writing "0") for writing the magnetic tunnel junction from a high-resistivity state (i.e., anti-parallel state) to a low-resistivity state (i.e., parallel state) is the same as the direction from the magnetic free layer to the magnetic fixed layer, and the direction of the write current (writing "1") for writing the magnetic tunnel junction from a low-resistivity state to a high-resistivity state is the same as the direction from the magnetic fixed layer to the magnetic free layer.

[0117] In this embodiment, during the read operation, the direction of the read current is along the direction from the reference output terminal to the ground terminal. Specifically, in this embodiment, in the parallel state reference cell, the direction of the read current through the magnetic tunnel junction is consistent with the direction from the magnetic free layer to the magnetic fixed layer, that is, the same as the direction of the current that writes the magnetic tunnel junction into a low-resistance state (i.e., parallel state). Since the magnetic tunnel junction in the parallel state reference cell is already in a low-resistance state, it can prevent the resistance state of the parallel state reference cell from flipping.

[0118] In the antiparallel reference cell, the direction of the read current through the magnetic tunnel junction is the same as the direction from the magnetic fixed layer to the magnetic free layer, which is the same as the direction of the current that writes the magnetic tunnel junction as a high-resistivity state. Since the magnetic tunnel junction in the antiparallel reference cell is already in a high-resistivity state, the resistance state of the antiparallel reference cell can be prevented from flipping.

[0119] For a detailed description of the storage array described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0120] Accordingly, embodiments of the present invention also provide an electronic device. The electronic device includes: a magnetic random access memory provided in embodiments of the present invention.

[0121] As described above, the magnetic random access memory (MRAM) provided in this embodiment of the invention has a low probability of the resistance state of the reference cell flipping during a read operation. This provides a more reliable reference resistor for data reading of the data cell, ensuring the reliability of the reference cell and thus improving the data reading accuracy of the MRAM. Consequently, the performance of the electronic device provided in this embodiment of the invention is also improved. For example, improving the data reading accuracy is beneficial for optimizing the user experience and perception.

[0122] In this embodiment, the electronic device can be an electronic device capable of data storage and retrieval, such as a chip, mobile phone, computer, or in-vehicle electronic product.

[0123] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.< / n>

Claims

1. A magnetic random access memory, characterized in that, include: The drive signal module is used to provide read signals; The drive signal module is used to provide bit line voltage; A storage array includes multiple storage cells arranged in an array, each storage cell including a magnetic tunnel junction, the magnetic tunnel junction including a magnetically fixed layer and a magnetically free layer disposed opposite to each other; The storage unit for the data to be read is defined as a data unit, which is used to load the data voltage output by the read signal; the data unit is also used to load the bit line voltage to output data current; A storage unit used as a reference for data reading is defined as a reference unit. The reference unit includes a parallel state reference unit and an antiparallel state reference unit. The magnetic free layer of the parallel state reference unit is coupled to the magnetic fixed layer of the antiparallel state reference unit to form a reference output terminal. The reference unit is used to load the reading signal and output a reference voltage through the reference output terminal. The reference unit is also used to load the bit line voltage and output a reference current through the reference output terminal. A comparator circuit is used to read data from the data unit based on the relative magnitudes of the data voltage and the reference voltage; A load circuit is coupled to the data unit and to the reference output terminal; the load circuit is used to convert the data current of the data unit into a data voltage and to convert the reference current of the reference unit into a reference voltage.

2. The magnetic random access memory as described in claim 1, characterized in that, The magnetic tunnel junction includes a magnetically fixed layer and a magnetically free layer located on the magnetically fixed layer; Alternatively, the magnetic tunnel junction may include a magnetic free layer and a magnetic fixation layer located on the magnetic free layer.

3. The magnetic random access memory as described in claim 2, characterized in that, The magnetic tunnel junction includes a magnetically fixed layer and a magnetically free layer located on the magnetically fixed layer; the memory cell also includes a selection transistor connected to the magnetic tunnel junction, the gate of the selection transistor being coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic fixing layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the parallel-state reference cell, the drain of the selection transistor is coupled to the magnetic fixing layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the antiparallel reference cell, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, the source of the selection transistor is used to form the reference output terminal, and the magnetic free layer of the magnetic tunnel junction is grounded.

4. The magnetic random access memory as described in claim 2, characterized in that, The magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer; the memory cell also includes a selection transistor connected to the magnetic tunnel junction, the gate of the selection transistor being coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the parallel-state reference cell, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, the source of the selection transistor is used to form the reference output terminal, and the magnetic fixed layer of the magnetic tunnel junction is grounded. In the antiparallel reference cell, the magnetic fixing layer of the magnetic tunnel junction is used to form the reference output terminal, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

5. The magnetic random access memory as described in claim 1, characterized in that, The drive signal module includes: A clamping circuit, coupled to the load circuit, is used to provide bit line voltages to the data unit and the reference unit, and to clamp the bit line voltages of the data unit and the reference unit. The bit line selection circuit has one end coupled to the clamping circuit and the other end coupled to the data unit and the reference output terminal respectively. The bit line selection circuit is adapted to select the data unit to be read and the reference unit.

6. The magnetic random access memory as described in claim 5, characterized in that, The clamping circuit includes an NMOS transistor, the drain of which is coupled to the load circuit, the source of which is coupled to the bit line selection circuit, and the gate of which is used to load the clamping control signal. During a read operation, the voltage applied to the gate of the NMOS transistor is the sum of the threshold voltage and the bit line voltage of the NMOS transistor.

7. The magnetic random access memory as described in claim 1, characterized in that, The load circuit is a current mirror.

8. The magnetic random access memory as described in claim 7, characterized in that, The number of antiparallel state reference units and parallel state reference units is the same, and the number of both antiparallel state reference units and parallel state reference units is y; where y is a positive integer; During a read operation, the bit line voltage applied by the drive signal module to the data unit is the data bit line voltage, and the bit line voltage applied by the drive signal module to the reference unit is the reference bit line voltage. The mirror ratio used from the reference cell to the data cell is 2y:x; where x is the ratio of the data bit line voltage to the reference bit line voltage.

9. The magnetic random access memory as described in claim 8, characterized in that, The data bit line voltage and the reference bit line voltage are the same.

10. The magnetic random access memory as claimed in claim 7, characterized in that, The current mirror includes: a first PMOS transistor group and a second PMOS transistor group, wherein the first PMOS transistor group and the second PMOS transistor group each include one PMOS transistor or multiple PMOS transistors connected in parallel. In the first PMOS transistor group, the source of the PMOS transistor is coupled to the power supply, the drain of the PMOS transistor is coupled to the gate of the PMOS transistor, and the drain of the PMOS transistor is coupled to the data unit. The first PMOS transistor group is adapted to convert the read current through the first PMOS transistor group into a data voltage. In the second PMOS transistor group, the source of the PMOS transistor is coupled to the power supply, the drain of the PMOS transistor is coupled to the gate, and the drain of the PMOS transistor is coupled to the reference output terminal. The second PMOS transistor group is adapted to convert the read current through the second PMOS transistor group into a reference voltage.

11. The magnetic random access memory as claimed in claim 1, characterized in that, The comparison circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the data unit, the second input terminal is coupled to the reference output terminal, and the output terminal is used to output a comparison result signal.

12. The magnetic random access memory as claimed in claim 1, characterized in that, The comparison circuit is a sensitive amplifier.

13. A storage array applied to a magnetic random access memory, the magnetic random access memory comprising: A drive signal module is used to provide read signals to the memory array, and the drive signal module is used to provide bit line voltage; A comparator circuit is used to read data from the memory array based on the relative magnitude of the data voltage output by the memory array and a reference voltage. The storage array is characterized in that it comprises: A storage cell with multiple arrays arranged in an array, the storage cell including a magnetic tunnel junction, the magnetic tunnel junction including a magnetically fixed layer and a magnetically free layer disposed opposite to each other; The storage unit for the data to be read is defined as a data unit. The data unit is used to load the read signal and output the data voltage; the data unit is also used to load the bit line voltage and output the data current. A reference cell is defined as a storage unit used as a data reading reference. The reference cell includes a parallel-state reference cell and an anti-parallel-state reference cell. The magnetically free layer of the parallel-state reference cell is coupled to the magnetically fixed layer of the anti-parallel-state reference cell to form a reference output terminal. The reference cell is used to load the read signal and output the reference voltage through the reference output terminal. The reference cell is also used to load the bit line voltage and output a reference current through the reference output terminal. A load circuit is coupled to the data unit and to the reference output terminal; the load circuit is used to convert the data current of the data unit into a data voltage and to convert the reference current of the reference unit into a reference voltage.

14. The storage array as claimed in claim 13, characterized in that, The magnetic tunnel junction includes a magnetically fixed layer and a magnetically free layer located on the magnetically fixed layer; Alternatively, the magnetic tunnel junction may include a magnetic free layer and a magnetic fixation layer located on the magnetic free layer.

15. The storage array as claimed in claim 14, characterized in that, The magnetic tunnel junction includes a magnetically fixed layer and a magnetically free layer located on the magnetically fixed layer; the memory cell also includes a selection transistor connected to the magnetic tunnel junction, the gate of the selection transistor being coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic fixing layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the parallel-state reference cell, the drain of the selection transistor is coupled to the magnetic fixing layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the antiparallel reference cell, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, the source of the selection transistor is used to form the reference output terminal, and the magnetic free layer of the magnetic tunnel junction is grounded.

16. The storage array as claimed in claim 14, characterized in that, The magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer; the memory cell also includes a selection transistor connected to the magnetic tunnel junction, the gate of the selection transistor being coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In the parallel-state reference cell, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, the source of the selection transistor is used to form the reference output terminal, and the magnetic fixed layer of the magnetic tunnel junction is grounded. In the antiparallel reference cell, the magnetic fixing layer of the magnetic tunnel junction is used to form the reference output terminal, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

17. An electronic device, characterized in that, It includes the magnetic random access memory as described in any one of claims 1 to 12.

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