Methods for forming semiconductor structures

Abstract

This invention provides a method for forming a semiconductor structure. The method includes providing an initial substrate, which includes a plateau region and a fin region. A patterned fin mask layer is formed on the initial substrate, comprising a first mask layer for forming fins and a second mask layer for covering the plateau region. Using the fin mask layer as a mask, a portion of the initial substrate thickness in the fin region is removed to form multiple parallel fins. The remaining thickness of the initial substrate is used as the substrate, the initial substrate protruding from the substrate within the fin region is defined as the fin, and the initial substrate protruding from the substrate within the plateau region is defined as the plateau. The second mask layer is removed to expose the first mask layer in the plateau region. An isolation material layer is formed covering the fins and the plateau, exposing the first mask layer. The first mask layer exposed by the isolation material layer is removed. A portion of the isolation material layer is removed to form an isolation layer between the fins. This invention improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the unique electrical properties of semiconductor materials to perform specific functions, such as generating, controlling, receiving, converting, and amplifying signals, and performing energy conversion. Commonly used semiconductor devices include field-effect transistors (FETs), bipolar transistors (BPTZs), and diodes. Among these, laterally diffused metal-oxide-semiconductor (LDMOS) is particularly widely used in power integrated circuits due to its greater compatibility with complementary metal-oxide-semiconductor (CMOS) logic processes.

[0003] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of transistors is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes the subthreshold leakage phenomenon, also known as the short-channel effect (SCE), more likely to occur.

[0004] Therefore, in order to better adapt to the reduction of feature size, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as LDMOS fin field-effect transistors. In this device structure, the gate structure can control the ultra-thin body (fin) from at least both sides. Compared with planar LDMOS, the gate structure has stronger control over the channel and can effectively suppress short-channel effects; and compared with other devices, it has better compatibility with existing integrated circuit manufacturing.

[0005] However, the semiconductor devices formed by existing technologies have complex manufacturing processes and high costs. Summary of the Invention

[0006] The problem addressed by this invention is to provide a method for forming a semiconductor structure to improve the electrical performance of the device.

[0007] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0008] An initial substrate is provided, the initial substrate including a plateau region and a fin region;

[0009] A patterned fin mask layer is formed on the initial substrate, the fin mask layer including a first mask layer for forming fins and a second mask layer for covering the platform region;

[0010] Using the fin mask layer as a mask, a portion of the initial substrate thickness in the fin region is removed to form multiple parallel fins, wherein the remaining thickness of the initial substrate is used as the substrate, the initial substrate protruding from the substrate in the fin region is used as the fin, and the initial substrate protruding from the substrate in the platform region is used as the platform.

[0011] Remove the second mask layer to expose the first mask layer of the platform region;

[0012] An insulating material layer is formed covering the fin and the platform, the insulating material layer exposing the first mask layer;

[0013] Remove the first mask layer exposed by the isolation material layer;

[0014] A portion of the insulating material layer is removed to form an insulating layer between the fins.

[0015] As can be seen, in this embodiment of the invention, after the fin is formed, the fin and the platform are covered by an isolation material layer, and the first mask layer is exposed. This allows the fin, substrate, and platform to remove the first mask layer used for forming the fin under the protection of the isolation material layer. Furthermore, by removing a portion of the isolation material layer, an isolation layer is formed between the fins. This integrates the step of forming the isolation layer with the step of removing the first mask layer, avoiding the steps of forming and removing the sacrificial layer, simplifying the process, and reducing the process cost. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure.

[0017] Figures 2 to 19 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0018] Currently, the fabrication process for devices is complex and costly.

[0019] refer to Figure 1The diagram illustrates a semiconductor structure for forming an LDMOS device, including a source 190, a drain 191, and a gate 170, wherein, to improve the breakdown voltage of the drain 191, the drain 191 is formed on a platform, and the gate 170 and the source 191 are formed on a fin.

[0020] However, during the formation of the fins and platform, a sidewall hard mask layer is required to form the fin pattern. When removing the sidewall hard mask layer, due to the extremely small size of the fins, a sacrificial layer is needed to fill the gaps between the fins to avoid damage before the sidewall hard mask layer is removed. This means that after removing the sidewall hard mask layer, the sacrificial layer filled between the fins also needs to be removed, making the process complex and costly.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing an initial substrate, the initial substrate including a plateau region and a fin region; forming a patterned fin mask layer on the initial substrate, the fin mask layer including a first mask layer for forming fins and a second mask layer for covering the plateau region; using the fin mask layer as a mask, removing a portion of the initial substrate thickness in the fin region to form a plurality of parallel fins, wherein the remaining thickness of the initial substrate is used as the substrate, the initial substrate protruding from the substrate within the fin region is used as the fin, and the initial substrate protruding from the substrate within the plateau region is used as the platform; removing the second mask layer to expose the first mask layer in the plateau region; forming an isolation material layer covering the fins and the platform, the isolation material layer exposing the first mask layer; removing the first mask layer exposed by the isolation material layer; removing a portion of the isolation material layer to form an isolation layer between the fins.

[0022] As can be seen, in this embodiment of the invention, after the fin is formed, the fin and the platform are covered by an isolation material layer, and the first mask layer is exposed. This allows the fin, substrate, and platform to remove the first mask layer used for forming the fin under the protection of the isolation material layer. Furthermore, by removing a portion of the isolation material layer, an isolation layer is formed between the fins. This integrates the step of forming the isolation layer with the step of removing the first mask layer, avoiding the steps of forming and removing the sacrificial layer, simplifying the process, and reducing the process cost.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figures 2 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0025] refer to Figures 2-3,in, Figure 2 This is a top view. Figure 3 for Figure 2 Cross-sectional view along the AA' direction. An initial substrate 200 is provided, the initial substrate including a plateau region II and a fin region I.

[0026] The initial substrate 200 is used to provide a process basis for the subsequent formation of substrates, fins, and platforms adjacent to the fins. The initial substrate is also used to provide a process basis for the subsequent formation of semiconductor structures.

[0027] In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The initial substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the initial substrate may be suitable for process requirements or easy to integrate.

[0028] The initial substrate surface includes adjacent well regions 20A and drift regions 20B. Optionally, the well regions 20A and drift regions 20B are connected. The well region 20A can be used as the well region of an LDMOS device, and the drift region 20B can be used as the drift region of an LDMOS device. In subsequent processes, corresponding device structures are formed on the well regions 20A and drift regions 20B, thereby forming the corresponding LDMOS device.

[0029] The well region 20A and drift region 20B are doped with dopants of different conductivity types. For example, when N-type ions are doped in the well region, P-type ions are doped in the drift region; when P-type ions are doped in the well region, N-type ions are doped in the drift region. The different conductivity types of dopants can be related to the conductivity type of the final device to be formed, which will not be elaborated here.

[0030] The well region 20A and drift region 20B can be formed by epitaxial processes. For example, during epitaxial growth, corresponding ions are doped to form a layer structure of the corresponding conductivity type; or, the well region 20A and drift region 20B can be formed by ion implantation of corresponding ions in the corresponding regions of the initial substrate. Wherein, when the doping ion is an N-type ion, the N-type ion can be a P ion, an As ion, or an Sb ion; when the doping ion is a P-type ion, the P-type ion can be a B ion, a Ga ion, or an In ion.

[0031] The fin region I is the area used to form the fins in subsequent processes, and the platform region II is the area used to form the platform in subsequent processes. Optionally, the fin region I is defined as the portion of the well region 20A and the portion of the drift region 20B facing the well region 20A, and the platform region II is defined as the portion of the drift region 20B facing away from the well region 20A.

[0032] Optionally, the initial substrate may further include a planarization layer 210, a hard mask material layer 220, and a hard mask cap layer 221.

[0033] The initial substrate further includes a planarization layer 210, which alleviates surface unevenness and provides a process foundation for subsequent processes. The hard mask material layer 220, after patterning, forms a patterned hard mask layer to serve as a mask for forming fins in subsequent steps. The hard mask cap layer 221 accurately transfers the pattern to the patterned hard mask layer. The planarization layer 210, hard mask material layer 220, and hard mask cap layer 221 can be made of one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxynitride, silicon oxynitride, boron nitride, and boron carbonitride, with adjacent layers made of different materials. In this embodiment, the planarization layer 210 can be made of silicon oxide, the hard mask material layer 220 can be made of silicon nitride, and the hard mask cap layer 221 can be made of silicon oxide.

[0034] It should be noted that the thermal expansion coefficients of the hard mask material layer and the fin material differ significantly. If the hard mask material layer is formed directly on the initial substrate, it is prone to cracking or even falling off, thus failing to perform its masking function. Therefore, a planarization layer is formed between the hard mask material layer and the initial substrate. This planarization layer not only alleviates the problem of unevenness on the surface of the initial substrate but also acts as a buffer for the hard mask material layer.

[0035] refer to Figures 4-5 A patterned fin mask layer is formed on the initial substrate, the fin mask layer including a first mask layer for forming fins and a second mask layer for covering the platform region.

[0036] The first mask layer is a sidewall hard mask layer used to form the fin; the second mask layer is a photoresist layer used as a mask for the platform area so that subsequent processes can pattern only the fin area.

[0037] Specifically, the steps for forming the fin mask layer may include:

[0038] refer to Figure 4A first mask layer 230 is formed on the initial substrate. The first mask layer 230 includes a plurality of fin pattern structures that extend from the fin region to the platform region.

[0039] It should be noted that the first mask layer is used to expose a portion of the initial substrate of the fin region and the plateau region after patterning. The first mask layer 230 includes a plurality of fin patterned structures that extend from the fin region to the plateau region.

[0040] In this embodiment of the invention, the first mask layer can be a sidewall hard mask layer, which can meet the requirements for accuracy and stability of pattern transfer under relatively small critical dimensions. Specifically, the sidewall hard mask layer can be formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), or other processes in the art.

[0041] In this embodiment, the material of the first mask layer can be silicon nitride. Silicon nitride has high hardness and density, which is beneficial for improving the masking effect of the first mask layer in subsequent patterning. Furthermore, silicon nitride is a commonly used dielectric material in semiconductor processes and has high process compatibility. In other embodiments, the material of the first mask layer can also be amorphous carbon. In other embodiments, the material of the first mask layer can also be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

[0042] In this embodiment of the invention, in order to ensure the uniformity of the fin size, multiple pseudo-fins parallel to the fin are formed at the same time as the fin. Correspondingly, the first mask layer is used to form both the fin and the pseudo-fin (not shown in the figure).

[0043] refer to Figure 5 A second mask layer 240 is formed on the first mask layer 230, and the second mask layer 240 covers the initial substrate of the platform region II and the first mask layer 230.

[0044] Optionally, the second mask layer is used to cover the initial substrate and the first mask layer of the platform region. The second mask layer serves as a mask for the first mask layer of the platform region, thereby exposing the first mask layer of the fin region so that subsequent processes can perform corresponding processing on the fin region.

[0045] In this embodiment, the first mask layer is a sidewall hard mask layer, and the second mask layer is a photolithography mask layer. The material of the corresponding photolithography mask layer can be photoresist, which can be formed through spin coating and curing processes. The exposure and development can be achieved using appropriate process parameters. The photoresist can be positive or negative; this invention does not impose a specific limitation.

[0046] refer to Figures 6-7 ,in, Figure 6 This is a top view. Figure 7 for Figure 6 A cross-sectional view along the BB' direction shows that, using the fin mask layer as a mask, a portion of the initial substrate thickness in the fin region is removed to form multiple parallel fins 202. The remaining thickness of the initial substrate is used as substrate 201, the initial substrate protruding from the substrate in the fin region is used as fin 202, and the initial substrate protruding from the substrate in the platform region is used as a platform.

[0047] As described above, the fin mask layer includes a first mask layer for forming the fins and a second mask layer for covering the platform region. That is, by using the first mask layer for forming the fins and the second mask layer for covering the platform region, a portion of the initial substrate thickness of the fin region is removed to form multiple parallel fins.

[0048] Specifically, during the etching process, the hard mask cap layer 221 can be etched first using the first mask layer and the second mask layer 240 as masks to transfer the fin pattern to the hard mask cap layer 221. Then, using the hard mask cap layer 221 as a mask, the hard mask material layer 220 is etched to form a patterned hard mask layer 222. Further, using the patterned hard mask layer 222 as a mask, the planarization layer 210 and the initial substrate are etched to form the fin 202. It should be noted that in this embodiment, since the patterned hard mask layer 222 and the first mask layer (sidewall hard mask layer) 230 are made of the same material, while patterning the hard mask material layer 220, the first mask layer 230 exposed in the fin area is removed or partially removed. The illustration in the figure uses the removal of the first mask layer 230 exposed in the fin area as an example.

[0049] In this embodiment, the initial substrate is etched using a wet etching process, a dry etching process, or a combination of wet and dry etching processes to form the corresponding structure.

[0050] Optionally, the initial substrate can be etched by wet etching. Accordingly, the etching solution for wet etching can be an acid mixture, such as hydrochloric acid, phosphoric acid, nitric acid, etc., mixed in a certain proportion.

[0051] It should be noted that, based on the embodiments of the present invention, the first mask layer is also used to form a pseudo fin. Accordingly, in the etching process of this step, while forming the fin, a pseudo fin (not shown in the figure) parallel to the fin is also formed.

[0052] Next, refer to Figure 8 Remove the second mask layer to expose the first mask layer 230 of the platform region II.

[0053] The second mask layer is a mask layer covering the platform area. By removing the second mask layer, the first mask layer of the platform area is exposed, thereby facilitating the removal of the first mask layer in subsequent steps.

[0054] In this embodiment of the invention, the second mask layer is a photoresist layer, and correspondingly, the second mask layer can be removed by a stripping process.

[0055] In this embodiment of the invention, isolation trenches can be further formed, thereby simultaneously forming an isolation layer between the fins and an isolation structure within the isolation trenches. Specifically, the process of forming the isolation trenches may include:

[0056] In this embodiment, reference Figure 9 The fin region includes an isolation region 20C, which is located on the side of the fin region I opposite to the platform region II. After removing the second mask layer, it may further include:

[0057] First, the fins within the isolation zone 20C are removed to form an isolation trench N.

[0058] The isolation trench is used to provide process space for the subsequent formation of the isolation structure, thereby forming an isolation structure for the isolation device structure within the isolation trench.

[0059] Specifically, at least a portion of the fin height within the isolation zone can be removed using dry etching, wet etching, or a combination of both.

[0060] In embodiments of the present invention, when a pseudo-fin is also formed, the pseudo-fin can be removed simultaneously during the step of removing at least a portion of the height of the fin within the isolation zone, thereby simplifying the process and reducing process costs.

[0061] Next, refer to Figures 10-11 An isolation material layer 251 is formed covering the fin and the platform, the isolation material layer exposing the first mask layer.

[0062] The isolation material layer provides a process basis for the subsequent formation of the isolation layer and isolation structure. At the same time, it fills between and covers the fins, thereby avoiding damage to the fins during the subsequent removal of the first mask layer. This integrates the step of forming the isolation layer with the step of removing the first mask layer, avoiding the steps of forming and removing the sacrificial layer, simplifying the process and reducing the process cost.

[0063] For details, please refer to Figure 10 An initial isolation material layer 250 is formed that completely covers the side of the substrate having the first mask layer.

[0064] Optionally, the initial insulating material layer is used to form the insulating material layer.

[0065] In this embodiment, the initial insulating material layer is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps reduce the difficulty and cost of forming the insulating material layer. Furthermore, silicon oxide has a low dielectric constant, which also helps improve the insulating effect of the initial insulating material layer. In other embodiments, the initial insulating material layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.

[0066] In this embodiment, a flowable chemical vapor deposition (FCVD) process is used to form the initial isolation material layer. The FCVD process has excellent filling capabilities and is suitable for filling openings with high aspect ratios, which helps reduce the probability of voids and other defects forming within the initial isolation material layer, thereby improving the quality of the isolation material layer.

[0067] refer to Figure 11 The initial isolation material layer is planarized until the remaining initial isolation material layer exposes the top of the first mask layer 230, wherein the remaining initial isolation material layer is used as the isolation material layer 251.

[0068] The initial isolation material layer completely covers the substrate having the first mask layer. The initial isolation material layer can be planarized through processes such as grinding, and the initial isolation material layer on the platform can be removed until the top of the first mask layer 230 is exposed.

[0069] It should be further noted that the insulating material layer 251 also covers the insulating trench.

[0070] refer to Figure 12 Remove the first mask layer exposed by the isolation material layer 251.

[0071] Since the fin is covered by an insulating material layer, the first mask layer exposed by removing the insulating material layer can protect the fin from the effects of this step, thereby avoiding potential damage.

[0072] Optionally, an appropriate etching process can be selected based on the material of the first mask layer to remove the first mask layer.

[0073] It should be noted that in this embodiment, after removing the first mask layer, the hard mask cap layer 221 beneath the first mask layer is exposed.

[0074] refer to Figure 13 A portion of the insulating material layer is removed to form an insulating layer 252 between the fins.

[0075] In this embodiment, the height of the remaining isolation material layer is higher than the height of the bottom of the isolation trench, wherein the isolation material layer in the isolation zone 20C serves as the isolation structure, forming an isolation layer between the fins.

[0076] Specifically, the step of removing a portion of the insulating material layer may include:

[0077] The isolation material layer 251 is planarized to remove the isolation material layer that protrudes above the platform.

[0078] In this embodiment, after removing the first mask layer, the isolation material layer can be planarized to reduce the thickness of the isolation material layer that needs to be etched subsequently. Specifically, since the hard mask cap layer and the isolation material are made of the same material in this embodiment, the isolation material layer can be removed by grinding with the patterned hard mask layer as the stop layer, thereby removing the hard mask cap layer at the same time.

[0079] After removing the isolation material layer on the platform, this embodiment may further include: removing the planarization layer and the pattern hard mask layer.

[0080] The planarization layer and the pattern hard mask layer can be removed by selecting an appropriate etching process based on their materials.

[0081] refer to Figure 14-15 ,in, Figure 15 for Figure 14 A cross-sectional view along the CC' direction shows the remaining isolation material layer being etched until the remaining isolation material layer exposes the top and part of the sidewalls of the fin, wherein the remaining isolation material layer is used as isolation layer 252.

[0082] The isolation material layer is located between the fins and in the isolation groove. The isolation material layer between the fins serves as the isolation layer, which can achieve isolation between the fins.

[0083] The isolation material layer also covers the isolation trench, and the isolation material layer in the isolation trench serves as the isolation structure 260, which is used to isolate the device structure on the semiconductor structure.

[0084] In this embodiment of the invention, the process may further include the formation of the gate structure, the source, and the drain. Specifically, the formation process of the gate structure, the source, and the drain is as follows:

[0085] refer to Figures 16-17 ,in, Figure 17 for Figure 16 A cross-sectional view along the DD' direction shows a gate structure 270 spanning the fin, the gate structure 270 covering a portion of the drift region 20B and a portion of the well region 20A.

[0086] The gate structure 270 includes a gate dielectric layer 271, a gate 272, and a sidewall 273. The specific formation process of forming the gate structure across the fin may be as follows: forming a gate dielectric material layer that conformally covers the initial substrate having one side of the fin; forming a gate across the fin on the gate dielectric material layer, the gate covering part of the sidewall and part of the top of the fin; forming sidewalls on both sides of the gate; and using the gate and sidewalls as a mask to remove the exposed gate dielectric material layer, leaving the remaining gate dielectric material layer as the gate dielectric layer.

[0087] It should be noted that the gate dielectric material layer is used to form the gate dielectric layer 271. The material of the gate dielectric layer 271 is a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 271 is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0088] The gate 272 serves as an electrode for electrical connection with an external circuit. In this embodiment, the gate 272 can be made of a magnesium-tungsten alloy; in other embodiments, the gate 272 can also be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0089] Optionally, the gate material layer is used to subsequently form the gate. Therefore, the selection of the gate material can be found in the previous section on the selection of the gate material layer, and will not be repeated here.

[0090] The sidewall 273 is used to support and isolate the gate, thereby preventing a short circuit between the gate and the side structure.

[0091] In the step of forming a gate spanning the fin on the gate dielectric material layer, multiple dummy gates (not shown in the figure) parallel to the gate can also be formed simultaneously, thereby improving the dimensional uniformity of the gate. After removing the exposed gate dielectric material layer using the gate and sidewalls as masks, the dummy gates and the sidewalls on both sides of the dummy gates can be removed.

[0092] In this embodiment, the sidewall 273 is made of silicon nitride. In other embodiments, the sidewall may also be made of silicon oxynitride.

[0093] refer to Figure 18 A barrier layer 280 is formed on the side of the gate structure facing the platform, the barrier layer covering at least a portion of the drift region.

[0094] The barrier layer can be a metallized barrier layer, which is used to prevent doped ions in the drift region from diffusing outward.

[0095] It is understandable that when the drift area is a fin, a barrier layer needs to be formed in the groove between the fins. Correspondingly, the formation process of the barrier layer is not easy to control, and the morphology of the formed barrier layer is not good. However, in this embodiment, since most of the drift area is a platform, the process of forming the barrier layer in this embodiment is simpler, and the morphology of the formed barrier layer is good.

[0096] The material of the barrier layer may include amorphous silicon. In other embodiments, the material of the barrier layer may also include silicon nitride or silicon titanide.

[0097] refer to Figure 19 A source electrode 290 is formed in the well region 20A, and a drain electrode 291 is formed in the drift region 20B.

[0098] While forming the source in the well region, a drain can also be formed in the drift region. Alternatively, in other embodiments, the source and drain can be formed before the gate structure. During operation of the semiconductor structure, the source and drain provide stress to the channel, increasing the migration rate of charge carriers in the channel.

[0099] It can be explained in detail that when the semiconductor device is an LDMOS transistor, the LDMOS transistor is a high-voltage device. The parasitic transistor formed by the drain, substrate and source of the LDMOS transistor can discharge electrostatic current. When the drain of the embodiment of the present invention is connected to high voltage, voltage division can be performed based on the aforementioned platform to avoid device breakdown.

[0100] As can be seen, in this embodiment of the invention, after the fin is formed, the fin and the platform are covered by an isolation material layer, and the first mask layer is exposed. This allows the fin, substrate, and platform to remove the first mask layer used for forming the fin under the protection of the isolation material layer. Furthermore, by removing a portion of the isolation material layer, an isolation layer is formed between the fins. This integrates the step of forming the isolation layer with the step of removing the first mask layer, avoiding the steps of forming and removing the sacrificial layer, simplifying the process, and reducing the process cost.

[0101] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing an initial substrate, the initial substrate comprising a platform region and a fin region; forming a patterned fin mask layer on the initial substrate, the fin mask layer comprising a first mask layer for forming fins and a second mask layer for covering the platform region; removing a partial thickness of the initial substrate in the fin region with the fin mask layer as a mask, to form a plurality of parallel fins, wherein the initial substrate with a remaining thickness is used as a substrate, the initial substrate protruding from the substrate in the fin region is used as a fin, and the initial substrate protruding from the substrate in the platform region is used as a platform; removing the second mask layer to expose the first mask layer in the platform region; forming an isolation material layer covering the fins and the platform, the isolation material layer exposing the first mask layer, so that the fins, the substrate and the platform are removed for forming the first mask layer for forming fins under the protection of the isolation material layer; removing the first mask layer exposed by the isolation material layer; removing a partial thickness of the isolation material layer to form an isolation layer between the fins.

2. The method of forming a semiconductor structure of claim 1, wherein, The method of forming a patterned fin mask layer on the initial substrate comprises: forming a first mask layer on the initial substrate, the first mask layer comprising a plurality of fin pattern structures extending from the fin region to the platform region; forming a second mask layer on the first mask layer, the second mask layer covering the initial substrate and the first mask layer in the platform region.

3. The method of forming a semiconductor structure of claim 1, wherein, The first mask layer is a sidewall hard mask layer, and the second mask layer is a photoresist mask layer.

4. The method of forming a semiconductor structure of claim 1, wherein, The method of forming an isolation material layer covering the fins and the platform comprises: forming an initial isolation material layer completely covering the substrate with one side of the first mask layer; planarizing the initial isolation material layer until the remaining initial isolation material layer exposes the top of the first mask layer, wherein the remaining initial isolation material layer is used as the isolation material layer.

5. The method of forming a semiconductor structure of claim 1, wherein, The method of removing a partial thickness of the isolation material layer comprises: planarizing the isolation material layer to remove the isolation material layer above the platform; etching the remaining isolation material layer until the remaining isolation material layer exposes the top and part of the sidewall of the fin, wherein the remaining isolation material layer is used as the isolation layer.

6. The method of forming a semiconductor structure of claim 5, wherein, In the step of providing an initial substrate, a planar layer, a patterned hard mask layer and a hard mask cap layer are sequentially formed on the initial substrate; In the step of planarizing the isolation material layer, the patterned hard mask layer is used as a stop layer to grind and remove the isolation material layer; Before the step of etching the remaining isolation material layer, the planar layer and the patterned hard mask layer are removed.

7. The method of forming a semiconductor structure of claim 1, wherein, The fin region comprises an isolation region on the side of the fin region away from the platform region, and after the step of removing the second mask layer and before the step of forming an isolation material layer covering the fins and the platform, the method further comprises: removing the fins in the isolation region to form an isolation trench; In the step of forming an isolation material layer covering the fins and the platform, the isolation material layer simultaneously covers the isolation trench. In the step of removing part of the thickness of the isolation material layer, the height of the remaining isolation material layer is higher than the height of the bottom of the isolation trench, wherein the isolation material layer in the isolation region is used as an isolation structure. 8.The method of claim 7, wherein: In the step of forming the fin, a plurality of dummy fins parallel to the fin are also formed; In the step of removing at least part of the height of the fin in the isolation region, the dummy fins are also removed.

9. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the initial substrate, the surface of the initial substrate comprises adjacent well regions and drift regions, wherein a region of the well region and a region of the drift region facing the well region are used as a fin region, and a region of the drift region away from the well region is used as a platform region; after the step of forming the isolation layer between the fins, the method further comprises: forming a gate structure across the fins, the gate structure covering part of the drift region and part of the well region; forming a source in the well region and a drain in the drift region.

10. The method of forming a semiconductor structure of claim 9, wherein, The gate structure comprises a gate dielectric layer, a gate electrode, and a sidewall, and the step of forming the gate structure across the fins comprises: forming a gate dielectric material layer conformally covering one side of the initial substrate having the fin; forming a gate electrode across the fin on the gate dielectric material layer, the gate electrode covering part of the sidewall and part of the top of the fin; forming a sidewall on both sides of the gate electrode; using the gate electrode and the sidewall as a mask, removing the exposed gate dielectric material layer, and using the remaining gate dielectric material layer as the gate dielectric layer.

11. The method of forming a semiconductor structure of claim 10, wherein, The step of forming a gate electrode across the fin on the gate dielectric material layer further comprises forming a plurality of dummy gate electrodes parallel to the gate electrode; after the step of using the gate electrode and the sidewall as a mask to remove the exposed gate dielectric material layer, the method further comprises removing the dummy gate electrodes and the sidewalls on both sides of the dummy gate electrodes.

12. The method of forming a semiconductor structure of claim 9, wherein, After the step of forming the gate structure across the fin, the method further comprises, before the step of forming a source in the well region and a drain in the drift region: forming a barrier layer on the side of the gate structure facing the platform, the barrier layer covering at least part of the drift region.

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