GaN Device Interconnection Structure and Its Preparation Method

Abstract

The GaN device interconnection structure and its manufacturing method of the present invention. The manufacturing method includes: providing a semiconductor substrate including a source region, a drain region, and a gate region, with a first direction and a second direction perpendicular to each other defined on the surface of the semiconductor substrate; manufacturing a gate combination structure, including gate fingers and a gate interconnection reserved part, and the connection direction of two adjacent gate fingers is the first direction; manufacturing a first dielectric layer and a first layer of interconnection metal; manufacturing a second dielectric layer and a second layer of interconnection metal. The present invention realizes the electrical lead-out of the gate based on the gate interconnection reserved part, and provides an interconnection wiring scheme through the first source metal interconnection line, the first drain metal interconnection line, the gate metal interconnection line, the second source metal interconnection line, and the second drain metal interconnection line, which is beneficial to the effective control of the gate resistance, is conducive to uniform current distribution, effectively improves the utilization rate of the effective area of the chip, and is suitable for the mass production product design of gallium nitride with low voltage and high power density.

Description

Technical Field

[0001] The present invention belongs to the field of gallium nitride power device design, and particularly relates to a GaN device interconnection structure and a preparation method thereof. Background Art

[0002] In the preparation of traditional GaN devices, it is necessary to electrically lead out the source electrode, drain electrode, and gate (three terminals), and interconnection metals are required for wiring during the preparation of the device structure. However, it is often difficult to achieve effective wiring connections, such as problems like increased resistance and wasted active area. For example, for traditional gallium nitride HEMT devices, all three terminals of the device are on the front side of the wafer, and the primitive cell of the gallium nitride device is a single-finger structure. Therefore, the interconnection layout of the three terminals on the same platform has an important impact on the performance of the gallium nitride device. The interconnection wiring is often achieved by bridging the gate and the source and arranging the pads outside the active area. This also has many problems. The bridging increases the active area. When the active area increases, problems such as an increase in gate resistance, uneven current distribution, and low utilization rate of the effective area of the chip are introduced, thus limiting the improvement of the performance advantages of gallium nitride devices.

[0003] Therefore, it is necessary to provide a GaN device interconnection structure and a preparation method to solve the above-mentioned existing problems or other problems. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a GaN device interconnection structure and a preparation method thereof, which are used to solve the problems in the prior art such as the difficulty in effectively interconnecting and wiring between the gate, drain, and source electrodes, and the low utilization rate of the effective area of the chip, large gate resistance, and uneven current distribution caused by the existing interconnection wiring structure.

[0005] To achieve the above purpose and other related purposes, the present invention provides a preparation method of a GaN device interconnection structure, and the preparation method includes the following steps:

[0006] Provide a semiconductor substrate, and the semiconductor substrate includes a gate region, a source region, and a drain region;

[0007] Prepare at least one gate combination structure, the gate combination structure is located in the gate region, includes at least two gate fingers and at least one gate interconnection reserved part connected to adjacent two gate fingers, the connection direction of the adjacent two gate fingers is the first direction, the source region is located on one side of the gate region, the drain region is located on the other side of the gate region, the connection direction of the source region and the drain region is the second direction, and the second direction is perpendicular to the first direction;

[0008] Form a first dielectric layer, and the first dielectric layer covers the semiconductor substrate and the gate combination structure;

[0009] For the first metallization, at least one first source metal interconnect line, at least one first drain metal interconnect line, and at least one gate metal interconnect line that are parallel to the second direction and alternately spaced from each other are formed on the first dielectric layer. The first source metal interconnect line is electrically connected to the source region below the first source interconnect line through a contact hole penetrating the first dielectric layer. The first drain metal interconnect line is electrically connected to the drain region below the first drain interconnect line through a contact hole penetrating the first dielectric layer. The gate metal interconnect line is electrically connected to the gate interconnect reserved portion below the gate interconnect line through a contact hole penetrating the first dielectric layer;

[0010] A second dielectric layer is formed, covering the first dielectric layer, the first source metal interconnect line, the first drain metal interconnect line, and the gate metal interconnect line;

[0011] For the second metallization, at least one second source metal interconnect line and at least one second drain metal interconnect line that are parallel to the first direction and alternately spaced from each other are formed on the second dielectric layer. The first source metal interconnect line is electrically connected to the first source metal interconnect line below the first source interconnect line through a contact hole penetrating the second dielectric layer. The second drain metal interconnect line is electrically connected to the first drain metal interconnect line below the second drain interconnect line through a contact hole penetrating the second dielectric layer.

[0012] Optionally, at least one first source metal interconnect line and at least one first drain metal interconnect line that are alternately arranged are included between two of the gate metal interconnect lines.

[0013] Optionally, the manufacturing method further includes: preparing a source metal contact and a drain metal contact on the semiconductor substrate, and the source metal contact, the drain metal contact, and the gate combined structure are spaced from each other.

[0014] Optionally, the distance between the first source metal interconnect line and the first drain interconnect line is less than the distance between the first source metal interconnect line or the first drain metal interconnect line and the gate metal interconnect line.

[0015] Optionally, the second source metal interconnect line and the second drain metal interconnect line are alternately spaced and arranged at equal intervals.

[0016] Optionally, the manufacturing method further includes: preparing a source pad electrically connected to the second source metal interconnect line, a drain pad electrically connected to the second drain metal interconnect line, a gate pad electrically connected to the gate metal interconnect line, and a substrate lead-out pad.

[0017] The present invention also provides a GaN device interconnection structure, which is preferably prepared by using the preparation method of the GaN device interconnection structure of the present invention. Of course, other methods can also be used. The GaN device interconnection structure includes:

[0018] A semiconductor substrate, which includes a gate region, a source region, and a drain region;

[0019] At least one gate combination structure, which is located in the gate region and includes at least two gate fingers and at least one gate interconnection reserved part connected to two adjacent gate fingers. The connection direction of the two adjacent gate fingers is the first direction. The source region is located on one side of the gate region, and the drain region is located on the other side of the gate region. The connection direction of the source region and the drain region is the second direction, and the second direction is perpendicular to the first direction;

[0020] A first dielectric layer, which covers the semiconductor substrate and the gate combination structure;

[0021] At least one first source metal interconnection line, at least one first drain metal interconnection line, and at least one gate metal interconnection line, which are located on the first dielectric layer, are parallel to the second direction, and are alternately spaced from each other. The first source metal interconnection line is electrically connected to the source region below the first source interconnection line through a contact hole penetrating the first dielectric layer. The first drain metal interconnection line is electrically connected to the drain region below the first drain interconnection line through a contact hole penetrating the first dielectric layer. The gate metal interconnection line is electrically connected to the gate interconnection reserved part below the gate interconnection line through a contact hole penetrating the first dielectric layer;

[0022] A second dielectric layer, which covers the first dielectric layer, the first source metal interconnection line, the first drain metal interconnection line, and the gate metal interconnection line;

[0023] At least one second source metal interconnection line and at least one second drain metal interconnection line, which are located on the second dielectric layer, are parallel to the first direction, and are alternately spaced from each other. The first source metal interconnection line is electrically connected to the first source metal interconnection line below the first source interconnection line through a contact hole penetrating the second dielectric layer. The second drain metal interconnection line is electrically connected to the first drain metal interconnection line below the second drain interconnection line through a contact hole penetrating the second dielectric layer.

[0024] Optionally, the contact holes penetrating the first dielectric layer include: a first source interconnect contact hole, a first drain interconnect contact hole, and a gate interconnect contact hole. The first source interconnect contact hole is located above the source region, the first drain interconnect contact hole is located above the drain region, the gate interconnect contact hole is located above the gate interconnect reserved portion, and the first source interconnect contact hole and the first drain interconnect contact hole are arranged at intervals in the first direction; the contact holes penetrating the second dielectric layer include: a second source interconnect contact hole and a second drain interconnect contact hole. The second source interconnect contact hole exposes the first source metal interconnect line, and the second drain interconnect contact hole exposes the first drain metal interconnect line.

[0025] Optionally, between two of the gate metal interconnect lines, there are at least one first source metal interconnect line and at least one first drain metal interconnect line arranged alternately.

[0026] Optionally, the line width of the first source metal interconnect line is the same as that of the first drain metal interconnect line and is greater than the line width of the gate metal interconnect line; the line width of the second source metal interconnect line is the same as that of the second drain metal interconnect line.

[0027] As described above, the GaN device interconnect structure and its manufacturing method of the present invention realize the electrical lead-out of the gate based on the gate interconnect reserved portion, and provide an interconnect wiring solution through the first source metal interconnect line, the first drain metal interconnect line, the gate metal interconnect line, the second source metal interconnect line, and the second drain metal interconnect line, which is beneficial to the effective control of the gate resistance, conducive to uniform current distribution, effectively improves the utilization rate of the effective area of the chip, and is applicable to the mass production product design of gallium nitride with low voltage and high power density. Description of the Drawings

[0028] Figure 1 It shows a process flow chart of the manufacturing of the GaN device interconnect structure in an embodiment of the present invention.

[0029] Figure 2 It shows a schematic diagram of providing a semiconductor substrate in the manufacturing of the GaN device interconnect structure in an embodiment of the present invention.

[0030] Figure 3 It shows a top view schematic diagram of the source region, drain region, and gate region defined in the semiconductor substrate in the manufacturing of the GaN device interconnect structure in an embodiment of the present invention.

[0031] Figure 4 It shows Figure 3 a partial enlarged schematic diagram of the source region, drain region, and gate region in

[0032] Figure 5It shows a partial schematic diagram of forming a gate combination structure, a source metal contact, and a drain metal contact in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0033] Figure 6 It shows a partial schematic diagram of forming a gate interconnection contact hole, a first source interconnection contact hole, and a first drain interconnection contact hole in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0034] Figure 7 It shows a partial schematic diagram of forming a gate metal interconnection line, a first source metal interconnection line, and a first drain metal interconnection line in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0035] Figure 8 It shows a partially enlarged top view schematic diagram of forming a second source interconnection contact hole and a second drain interconnection contact hole in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0036] Figure 9 It shows a partially enlarged top view schematic diagram of forming a second source metal interconnection line and a second drain metal interconnection line in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0037] Figure 10 It shows a structural layout schematic diagram of forming a gate pad, a source pad, a drain pad, and a substrate lead-out pad in the preparation of the GaN device interconnection structure according to an embodiment of the present invention.

[0038] Figure 11 It shows a wiring scheme of an existing interconnection wiring implemented by bridging a gate and a source and arranging pads outside an active region in the comparative example of the present invention.

[0039] Element number description

[0040] 100, semiconductor substrate; 201, semiconductor substrate; 202, GaN channel layer; 203, barrier layer; 204, gate dielectric layer; 101, gate region; 102, source region; 103, drain region; 104, gate combination structure; 105, gate finger; 106, gate interconnection reserved part; 107, source metal contact; 108, drain metal contact; 109, gate interconnection contact hole; 110, first source interconnection contact hole; 111, first drain interconnection contact hole; 112, gate metal interconnection line; 113 first source metal interconnection line; 114, first drain metal interconnection line; 115, spacer; 116, source lead-out region; 117, drain lead-out region; 118, second source interconnection contact hole; 119, second drain interconnection contact hole; 120, second source metal interconnection line; 121, second drain metal interconnection line; 122, source pad; 123, drain pad; 124, gate pad; 125, substrate lead-out pad; S1~S6, steps. Detailed implementation manners

[0041] The following describes the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0043] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers. Additionally, "between... and..." used in the present invention includes the two endpoint values.

[0044] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0046] As Figure 1 shown, the present invention provides a method for preparing a GaN device interconnection structure. The preparation method includes steps S1 - S8. The following will describe in detail the method for preparing the GaN device interconnection structure of the present invention with reference to the drawings. Among them, the order of the above steps is not limited in the method for preparing the GaN device interconnection structure provided by the present invention, and can be adjusted according to common knowledge in the art. Figure 1 Only an example of the method for preparing the GaN device interconnection structure of the present invention is provided.

[0047] First, as shown in S1 in Figure 1 and Figures 2-4 , a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a source region 102, a drain region 103, and a gate region 101. In one example, the semiconductor substrate 100 includes an active region and a non-active region. The active region includes the source region 102, the drain region 103, and the gate region 101. Among them, the semiconductor substrate 100 can be any semiconductor structure on which source, drain, gate, and their interconnection wiring layers of a device need to be formed. The semiconductor substrate 100 can be a stacked structure. In one example, as shown in Figure 2 , the semiconductor substrate 100 includes a semiconductor substrate 201, a GaN channel layer 202, a barrier layer 203, and a gate dielectric layer 204 from bottom to top. Among them, a two-dimensional electron gas (2DEG) is formed in the GaN channel layer 202 based on the barrier layer 203. Source and drain ohmic contacts can also be formed in the semiconductor substrate corresponding to the source and drain contacts, so as to obtain a GaN device by combining subsequent processes. This figure can also be shown as the working principle diagram of the device.

[0048] In addition, as shown in Figure 3 and Figure 4 , Figure 3 shows the distribution of the source region 102, the drain region 103, and the gate region 101 in one example, Figure 4 shows a partial enlarged view of a unit cell. The source region 102 is used to prepare a source contact electrode for electrically leading out the source of the device. The drain region 103 is used to prepare a drain contact electrode for electrically leading out the drain of the device. The gate region 101 is used to prepare a gate contact electrode of the device for electrically leading out the gate of the device. In addition, it should be noted that taking the source region 102 as an example, it represents the region for preparing all source contact electrodes of the device. The source region 102 can include several source region units. Source contact electrodes are prepared in the source region units to form multiple source contact electrodes. Among them, the shape and arrangement of the source contact electrodes can be changed according to actual needs. Similarly, the drain region 103 and the gate region 101 can also be designed similarly. In this embodiment, the direction in which the length of the gate region 101 shown in the figure extends is defined as the first direction. That is, the first direction is the extending direction of the gate fingers formed in the gate region, and the direction perpendicular to the first direction is defined as the second direction. Descriptions will be based on this subsequently. In addition, it should be noted that Figure 2Although the dashed-line box has a certain thickness, it does not mean that each region is above the semiconductor substrate. On the one hand, the dashed-line box region schematically represents the positions of the source region 102, the drain region 103, and the gate region 101 in the semiconductor substrate in the cross-sectional view. On the other hand, it can also be regarded as a schematic of forming the bottom metal contacts of each electrode.

[0049] Next, as Figure 1 in S2 and Figure 5 shown, at least one gate combination structure 104 is fabricated on the semiconductor substrate 100 corresponding to the gate region 101. The gate combination structure 104 includes at least two gate fingers 105 and at least one gate interconnection reserved portion 106. The gate interconnection reserved portion 106 is connected to two adjacent gate fingers 105. Among them, the connection direction of the two adjacent gate fingers 105 is the first direction. The source region 102 is located on one side of the gate region 101, the drain region 103 is located on the other side of the gate region 101, the connection direction of the source region 102 and the drain region 103 is the second direction, and the second direction is perpendicular to the first direction.

[0050] In this embodiment, the gate interconnection reserved portion 106 is fabricated while fabricating the gate fingers 105 (as the device gate structure) on the semiconductor substrate 100, so as to facilitate the electrical lead-out of the subsequent device gate by means of re-wiring. Among them, two adjacent gate fingers 105 (in the second direction) can share one gate interconnection reserved portion 106. Of course, four diagonal gate fingers 105 can also share one gate interconnection reserved portion 106. In one example, the gate combination structure 104 includes at least two gate interconnection reserved portions 106, and each gate interconnection reserved portion 106 is connected to four diagonal gate fingers. The design of the gate interconnection reserved portion 106 facilitates the lead-out of the gate fingers, and at the same time is beneficial to saving the area of the active region, and is beneficial to alleviating the wiring limitation brought by the gate finger size. In addition, it is also beneficial to improve the uniformity of current distribution, reduce the introduced gate resistance, and is suitable for the mass production product design of gallium nitride with low voltage and high power density. When arranging the unit cells, since the gate finger size is small and cannot be directly interconnected, a gate bus bar region is reserved in the central region to reduce the gate resistance.

[0051] Continuing, as Figure 5As shown, a plurality of source metal contacts 107 are fabricated on the semiconductor substrate 100 corresponding to the source region 102, and a plurality of drain metal contacts 108 are fabricated on the semiconductor substrate 100 corresponding to the drain region 103. The source metal contacts 107, the drain metal contacts 108, and the gate combination structure 104 are arranged at intervals. Among them, the source metal contacts 107 and the drain metal contacts 108 fabricated in this step S4 and the fabrication of the gate combination structure 104 in step S3 can be fabricated based on the fabrication processes of gate contact metals, source contact metals, and drain contact metals in existing processes. The fabrication sequence can be adjusted according to requirements, and the materials can be selected from existing metal contact materials.

[0052] As an example, the source metal contact 107 includes a contact portion formed on the surface of the semiconductor substrate 100 and a source field plate portion connected to the contact portion and extending above the gate finger 105. There is a spacing between the source field plate portion and the top of the gate finger 105. To simultaneously fabricate a field plate structure in this step. The field plate can be fabricated by existing processes. For example, the above structure can be obtained by depositing a dielectric layer and filling it to form a metal layer.

[0053] As an example, a device arrangement method is provided. Among them, the source metal contacts 107, the drain metal contacts 108, and the gate fingers 105 are arranged in a periodic array. For example, the formed arrangement structure includes a plurality of unit rows arranged in a first direction; in the second direction, for each unit row, it includes a plurality of repeating periods, and each period includes the source contact metal 107, the gate finger 105, the drain contact metal 108, and the gate finger 105 arranged in sequence to achieve a common source connection and a common drain connection structure, that is, a source contact metal 107 - gate finger 105 - drain contact metal 108 - gate finger 105 - source contact metal 107 - gate finger 105 is formed, and so on for the arrangement. Each cell can be connected in common source and in common drain. In one example, the upper and lower (the first direction) relative positions of adjacent unit rows are the electrodes of the same device, that is, the gate fingers correspond to the gate fingers, the source metal contacts correspond to the source metal contacts, and the drain metal contacts correspond to the drain metal contacts. Additionally, as an example, when forming a plurality of unit rows, two adjacent gate fingers 105 in the same unit row and two gate fingers 105 opposite to it in adjacent unit rows are connected to the same gate interconnection reserved portion 106.

[0054] Next, as Figure 1 neutralize S3 and Figure 6As shown, the first contact holes for each electrode of the device are prepared. Specifically, first, a first dielectric layer covering the source metal contact 107, the drain metal contact 108, and the gate combination structure 104 is prepared on the semiconductor substrate 100. In the figure, for the sake of showing the positional relationship between each contact hole and each electrode metal contact, the first dielectric layer is not explicitly shown, but those skilled in the art can know its position according to common sense. The first dielectric layer can be prepared by existing deposition processes, including but not limited to silicon oxide.

[0055] Next, a first source interconnect contact hole 110, a first drain interconnect contact hole 111, and a gate interconnect contact hole 109 are prepared in the first dielectric layer. The first source interconnect contact hole 110 exposes the source metal contact 107, the first drain interconnect contact hole 111 exposes the drain metal contact 108, and the gate interconnect contact hole 109 exposes the gate interconnect reserved portion 106. In one example, the first source interconnect contact hole 110 and the first drain interconnect contact hole 111 are arranged at intervals in the first direction. It should be noted here that since the source metal contact 107 exposed by the first source interconnect contact hole 100 and the drain metal contact 108 exposed by the first drain interconnect contact hole 111 are not on the same straight line, the interval arrangement of the first source interconnect contact hole 110 and the first drain interconnect contact hole 111 in the first direction means that their projections on the straight line extending in the first direction are arranged at intervals, that is, on the straight line extending in the first direction, the projection of the first source interconnect contact hole 100 does not overlap with the projection of the first drain interconnect contact hole 111. Among them, Figure 6 For the sake of clearly showing each positional relationship, transparent lines are used to represent each material layer. In addition, the formation method of each interconnect contact hole in the first dielectric layer includes but is not limited to dry etching, and can be prepared by existing processes, such as being prepared based on photolithography-etching.

[0056] As an example, several first source interconnect contact holes 110 arranged at intervals in the first direction are provided above the same source metal contact 107. In addition, the first source interconnect contact holes 110 on different source metal contacts 107 are correspondingly arranged in the second direction, and the positions are correspondingly the same. That is to say, the arrangements of the first source interconnect contact holes 110 on the source metal contact 107 are the same, and for the projection of the first source interconnect contact hole 100 on the straight line extending in the first direction, the projections of the first source interconnect contact holes 110 on different source metal contacts 107 coincide on this straight line. For example, Figure 6As shown, the arrangement of the first source interconnection contact holes 110 on the left and right source metal contacts 107 is the same. For the first source interconnection contact holes 110 closest to the gate interconnection reserved part 106 on both sides, the projections of the first source interconnection contact holes 110 on both sides coincide on any straight line along the first direction. Similarly, a plurality of first drain interconnection contact holes 111 are arranged at intervals along the first direction corresponding to the same drain metal contact 108, and the first drain interconnection contact holes 111 on different drain contact metals 108 are correspondingly arranged in the second direction, with the positions corresponding identically.

[0057] That is to say, in one example, the first source interconnection contact holes 110 and the first drain interconnection contact holes 111 are arranged at intervals in the direction of the gate finger extension. In one example, they are arranged alternately at intervals. It means that the projections of the first source interconnection contact holes 110 and the first drain interconnection contact holes 111 in the first direction do not overlap, and their projections are arranged at intervals.

[0058] In addition, in one example, a plurality of the first source interconnection contact holes 110 are provided on one source metal contact 107, and the plurality of the first source interconnection contact holes 110 are arranged at intervals along the first direction. A plurality of the first drain interconnection contact holes 111 are provided on one drain metal contact 108, and the plurality of the first drain interconnection contact holes 111 are arranged at intervals along the first direction. At this time, the projections of the first source interconnection contact holes 110 and the first drain interconnection contact holes 111 are arranged alternately at intervals in the first direction. In another example, in the same unit row, all the first source interconnection contact holes 110 are correspondingly arranged, that is, the projections of the first source interconnection contact holes 110 overlap along the first direction. In the same unit row, all the first drain interconnection contact holes 111 are correspondingly arranged, that is, the projections of the first drain interconnection contact holes 111 overlap along the first direction.

[0059] In one example, the first source interconnection contact hole 110 includes a plurality of first source interconnection contact hole units arranged in a strip shape along the first direction, such as Figure 6 the four small holes arranged along the gate finger direction shown in Figure 6 The first drain interconnection contact hole 111 includes a plurality of first drain interconnection contact hole units arranged in a strip shape along the first direction; such as Figure 6 the four small holes arranged along the gate finger direction shown in

[0060] Next, as shown in Figure 1 S4 inFigure 7 As shown, the first metalization is performed to prepare first source metal interconnect lines 113, first drain metal interconnect lines 114, and gate metal interconnect lines 112 arranged at intervals. The first source metal interconnect lines 113 fill the first source interconnect contact holes 108 and extend to the surface of the first dielectric layer and are arranged along the second direction. The first source metal interconnect lines 113 connect the source metal contacts 107 on the same unit row. The first drain metal interconnect lines 114 fill the first drain interconnect contact holes 109 and extend to the surface of the first dielectric layer and are arranged along the second direction. The first drain metal interconnect lines 114 connect the drain metal contacts 108 on the same unit row. The gate metal interconnect lines 112 fill the gate interconnect holes 109 and extend to the surface of the first dielectric layer and are arranged along the second direction. The gate metal interconnect lines 112 connect the gate fingers 105 on the same unit row. Similarly, for showing the positional relationship of each structure, Figure 7 the first source interconnect contact holes 110, the first drain interconnect contact holes 111, and the gate interconnect holes 109 are also shown. In an example, the line width of the first source metal interconnect lines 113 is the same as that of the first drain metal interconnect lines 114 and is greater than the line width of the gate metal interconnect lines 112.

[0061] It can be seen from Figure 7 that the interconnect metals in the first layer are in a strip metal shape, and each interconnect metal is equivalent to a T-shaped structure. Taking the first source metal interconnect line 113 as an example, the exposed part above is the strip metal plate for interconnecting the same source metal contacts 107, and the lower part is the vertically downward metal part corresponding to filling each of the first source interconnect contact holes 110. In addition, in an example, corresponding to the schematic diagram of the contact holes, the same source metal contact 107 can correspond to multiple first source metal interconnect lines 113 arranged at intervals, the same drain metal contact 108 corresponds to multiple first drain metal interconnect lines 114 arranged at intervals, and the first source metal interconnect lines 113 and the first drain metal interconnect lines 114 are alternately arranged at intervals. The first-layer interconnect metal wiring interconnects the gate, source, and drain contact holes along the direction perpendicular to the gate finger wiring, realizing the same-pole interconnect of the side-by-side cells.

[0062] As an example, between two of the gate metal interconnect lines 112, there are at least one first source metal interconnect line 113 and at least one first drain metal interconnect line 114 arranged alternately.

[0063] As an example, the spacing between the first source metal interconnect line 113 and the first drain metal interconnect line 114 is smaller than the spacing between the first source metal interconnect line 113 and the gate metal interconnect line 112; the spacing between the first source metal interconnect line 113 and the first drain metal interconnect line 114 is smaller than the spacing between the first drain metal interconnect line 114 and the gate metal interconnect line 112.

[0064] Next, as Figure 1 in S5 of Figure 8 shown, a second dielectric layer covering the first source metal interconnect line 113, the first drain metal interconnect line 114, and the gate metal interconnect line 112 is prepared on the semiconductor substrate 100. Similarly, Figure 8 as shown in the schematic of the first dielectric layer, for the sake of clearly showing the positional relationship of each structure, a simplified schematic is made, and the material layers corresponding to the gate fingers and the gate interconnect reserved parts are not shown in the figure.

[0065] Among them, source electrode lead-out regions 116 and drain electrode lead-out regions 117 arranged alternately at intervals along the second direction are defined in the second dielectric layer. Optionally, a spacer 115 may also exist therebetween. Among them, a second source interconnect contact hole 118 is prepared in the source electrode lead-out region 116, a second drain interconnect contact hole 119 is prepared in the drain electrode lead-out region 117, and the first source metal interconnect line 113 is exposed by the second source interconnect hole 118, and the first drain metal interconnect line 114 is exposed by the second drain interconnect hole 119.

[0066] Among them, the source electrode lead-out regions 116 and the drain electrode lead-out regions 117 are arranged alternately at intervals, and their sizes may be the same or different, which are set according to actual requirements. That is to say, in this step, the lead-out positions of the source metal contact and the drain metal contact are redistributed through the second source interconnect contact hole 118 and the second drain interconnect contact hole 119, forming lead-out regions arranged alternately at intervals along the second direction. Reference can be made to the subsequent Figure 10As shown by the position of the middle pad. In one example, along the first direction, the source electrode lead-out region 116 covers at least two of the first source electrode metal interconnection lines 113, and the drain electrode lead-out region 117 covers at least two of the first drain electrode metal interconnection lines 114; and along the second direction, the source electrode lead-out region 116 covers at least two of the source electrode contact metals 107, and the drain electrode lead-out region 117 covers at least two of the drain electrode contact metals 108. In a specific embodiment, the source electrode lead-out region 116 covers the first source electrode metal interconnection lines 113 on all the units arranged at intervals along the first direction, and the drain electrode lead-out region 117 covers the first drain electrode metal interconnection lines 114 on all the units arranged at intervals along the first direction, forming source electrode lead-out regions 116 and drain electrode lead-out regions 117 that are alternately and spaced apart along the second direction in the top view layout. Of course, the sizes of the respective lead-out regions along the second direction can be designed according to actual requirements.

[0067] In one example, as shown in Figure 8 the second drain electrode interconnection contact hole 119 is arranged corresponding to the first drain electrode interconnection contact hole 111, that is, the second drain electrode interconnection contact hole 119 exposes the metal layer (the first drain electrode metal interconnection line) above the first drain electrode interconnection contact hole 111; the second source electrode interconnection hole 118 is arranged on the side of the first source electrode interconnection contact hole 110 and corresponds to the position of the first drain electrode interconnection contact hole 111 of the adjacent unit row (the unit row arranged along the first direction), that is, it is formed in the region between two adjacent first source electrode interconnection contact holes 110 along the second direction, and this region corresponds to the first drain electrode interconnection contact hole 111 up and down, wherein the second source electrode interconnection hole 118 corresponds to the first source electrode metal interconnection line in this region and correspondingly exposes this metal layer.

[0068] As an example, the second source electrode interconnection contact hole 118 includes a plurality of second source electrode interconnection contact hole units arranged in a square layout (not shown in the figure and replaced by a square), which can be a square layout, and the second drain electrode interconnection contact hole includes a plurality of second drain electrode interconnection contact hole units arranged in a square layout (not shown in the figure and replaced by a square), which can be a square layout.

[0069] Next, as shown in Figure 1 S6 in Figure 9 and the second source electrode metal interconnection lines 120 and the second drain electrode metal interconnection lines 121 that are parallel to the first direction and alternately and spaced apart from each other are prepared by performing a second metallization. In one example, the second source electrode metal interconnection lines 120 and the second drain electrode metal interconnection lines 121 are alternately and spaced apart and arranged at equal intervals. In one example, the line width of the second source electrode metal interconnection lines 120 is the same as the line width of the second drain electrode metal interconnection lines 121.

[0070] In a specific example, the second source metal interconnect line 120 fills the second source interconnect via 118 and extends to the surface of the second dielectric layer to cover the source lead-out region 116, and the second drain metal interconnect line 121 fills the second drain interconnect via 119 and extends to the surface of the second dielectric layer to cover the drain lead-out region 117. The second-level interconnect metal contact vias are distributed according to the pad positions, and are arranged along the gate finger direction corresponding to the source and drain of the first-level interconnect metal respectively. In this step, the second-level interconnect metal is formed, based on which the source metal contact and the drain metal contact can be electrically led out. Among them, similar to the structure of the first-level interconnect metal, the exposed parts of the respective interconnect metals of the second level are in the shape of strip metals, which is equivalent to a T-shaped structure. The strip metal plate exposed above is for realizing the interconnect of the same metal contact, and the lower part is the vertical downward metal part corresponding to filling each contact via. For example, taking the second source metal interconnect line 120 as an example, the second source interconnect contact vias are electrically connected in the source lead-out region 116. Among them, in one example, the electrical lead-out of the source metal contacts in one row of unit rows in the first direction can be realized based on the source lead-out region 116, or the electrical lead-out of the source metal contacts in multiple rows of unit rows in the first direction can be realized.

[0071] Finally, as Figure 10 shown, a source pad 122 electrically connected to the source metal contact 107, a drain pad 123 electrically connected to the drain metal contact 108, and a gate pad 124 electrically connected to the gate combined structure 104 through the gate interconnect reserved part 106 are prepared to obtain a GaN device interconnect structure. In this step, the source pad 122, the drain pad 123, and the gate pad 124 are prepared based on the layout of the first-level interconnect metal and the second-level interconnect metal, so as to realize the interconnect and re-wiring of each pole of the device. Among them, the source pad 122 and the drain pad 123 can prepare the corresponding pads through the corresponding second-level interconnect metal, and the gate pad 124 can prepare the corresponding pad through the first-level interconnect metal (gate metal interconnect line). For example, based on this metal layer and the dielectric layer above, the gate is led out at the required position. The specific preparation process of each lead-out pad can adopt the existing process. In addition, a substrate lead-out pad 125 electrically connected to the semiconductor body substrate can also be prepared in the interconnect structure, so as to apply an electrical signal to the GaN device through each pad.

[0072] As an example, the gate pad 124 and the substrate lead-out pad 125 are arranged adjacent to each other, and are both arranged on the side parts of the alternately arranged source pads 122 and drain pads 123, as Figure 10As shown in the arrangement mode, the gate pad 124 is electrically led out through the gate metal interconnection line 112, the source pad 122 is electrically led out through the second source metal interconnection line 120, and the drain pad 123 is electrically led out through the second drain metal interconnection line 121.

[0073] Based on the above method of the present invention, a gate interconnection area and a gate metal interconnection line are arranged in the active area, source and drain bus interconnection contact holes are arranged in an alternating manner perpendicular to the gate finger direction, and source and drain bus interconnection contact metals are arranged in an alternating manner. The source and drain pads are arranged in an alternating and cyclic layout, and the source and the substrate are directly connected through the interconnection metal. An interconnection wiring scheme is obtained. The device designed by adopting this design scheme shows great advantages in reducing the gate resistance, improving the output performance, and increasing the proportion of the active area. Table 1 shows the parameter comparison between the structure of the present invention and the traditional finger structure. Among them, the traditional difference structure can be seen in Figure 11 the wiring structure shown.

[0074] Table 1

[0075]

[0076] It can be seen that the proportion of the active area, the area of the pad electrode, chip heat dissipation, and device power density are closely related. The device designed by adopting the scheme of the present invention is significantly improved in terms of chip heat dissipation and device power density.

[0077] In addition, as Figures 9-10 shown, and referring to Figures 1-8 , the present invention also provides a GaN device interconnection structure. The GaN device interconnection structure is preferably prepared by using the preparation method of the GaN device interconnection structure of the present invention. Of course, it can also be prepared by other methods. Among them, the GaN device interconnection structure includes:

[0078] A semiconductor substrate 100, the semiconductor substrate includes a source region 102, a drain region 103, and a gate region 101;

[0079] At least one gate combination structure 104, the gate combination structure 104 is located in the gate region 101, the gate combination structure includes at least two gate fingers 105 and at least one gate interconnection reserved part 106, the gate interconnection reserved part is connected to two adjacent gate fingers, wherein the connection direction of the two adjacent gate fingers is the first direction, the source region 102 is located on one side of the gate region 101, the drain region 103 is located on the other side of the gate region 101, the connection direction of the source region 102 and the drain region 103 is the second direction, and the second direction is perpendicular to the first direction;

[0080] A first dielectric layer that covers the semiconductor substrate and the gate combination structure;

[0081] At least one first source metal interconnect line 113, at least one first drain metal interconnect line 114, and at least one gate metal interconnect line 112 that are located on the first dielectric layer, parallel to the second direction, and alternately spaced from each other. The first source metal interconnect line is electrically connected to the source region below the first source interconnect line through a contact hole penetrating the first dielectric layer. The first drain metal interconnect line is electrically connected to the drain region below the first drain interconnect line through a contact hole penetrating the first dielectric layer. The gate metal interconnect line is electrically connected to the gate interconnect reserved portion below the gate interconnect line through a contact hole penetrating the first dielectric layer;

[0082] A second dielectric layer that covers the first dielectric layer, the first source metal interconnect line, the first drain metal interconnect line, and the gate metal interconnect line;

[0083] At least one second source metal interconnect line 120 and at least one second drain metal interconnect line 121 that are located on the second dielectric layer, parallel to the first direction, and alternately spaced from each other. The first source metal interconnect line is electrically connected to the first source metal interconnect line below the first source interconnect line through a contact hole penetrating the second dielectric layer. The second drain metal interconnect line is electrically connected to the first drain metal interconnect line below the second drain interconnect line through a contact hole penetrating the second dielectric layer.

[0084] As an example, the GaN device interconnect structure further includes a source pad 122, a drain pad 123, and a gate pad 124. The source pad is electrically connected to the source metal contact, the drain pad is electrically connected to the drain metal contact, and the gate pad is electrically connected to the gate interconnect reserved portion.

[0085] As an example, the contact holes penetrating the first dielectric layer include: a first source interconnect contact hole 110, a first drain interconnect contact hole 111, and a gate interconnect contact hole 109. The first source interconnect contact hole is located above the source region, the first drain interconnect contact hole is located above the drain region, the gate interconnect contact hole is located above the gate interconnect reserved portion, and the first source interconnect contact hole and the first drain interconnect contact hole are spaced apart in the first direction.

[0086] As an example, the contact holes penetrating the second dielectric layer include: a second source interconnect contact hole 118 and a second drain interconnect contact hole 119. The second source interconnect contact hole exposes the first source metal interconnect line, and the second drain interconnect contact hole exposes the first drain metal interconnect line.

[0087] As an example, between the two gate metal interconnection lines 112, there are at least one first source metal interconnection line 113 and at least one first drain metal interconnection line 114 arranged alternately.

[0088] As an example, the line width of the first source metal interconnection line 113 is the same as that of the first drain metal interconnection line 114 and is greater than the line width of the gate metal interconnection line 112; the line width of the second source metal interconnection line 120 is the same as that of the second drain metal interconnection line 121.

[0089] In summary, for the GaN device interconnection structure and its manufacturing method of the present invention, the electrical property of the gate is led out based on the gate interconnection reserved part, and an interconnection wiring scheme is provided by the first source metal interconnection line, the first drain metal interconnection line, the gate metal interconnection line, the second source metal interconnection line and the second drain metal interconnection line, which is beneficial to the effective control of the gate resistance, conducive to the uniform current distribution, effectively improves the utilization rate of the effective area of the chip, and is applicable to the mass production product design of gallium nitride with low voltage and high power density. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0090] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing an interconnect structure of a GaN device, characterized in that, The preparation method includes: providing a semiconductor substrate, which includes a gate region, a source region, and a drain region; fabricating at least one gate combination structure located in the gate region, the gate combination structure including at least two gate fingers and at least one gate interconnection reserved portion connecting adjacent two gate fingers, the connection direction of the adjacent two gate fingers being the first direction, the source region being located on one side of the gate region, the drain region being located on the other side of the gate region, the connection direction of the source region and the drain region being the second direction, and the second direction being perpendicular to the first direction; forming a first dielectric layer, which covers the semiconductor substrate and the gate combination structure; performing a first metallization to form at least one first source metal interconnection line, at least one first drain metal interconnection line, and at least one gate metal interconnection line that are parallel to the second direction and alternately arranged at intervals on the first dielectric layer, the first source metal interconnection line being electrically connected to the source region below the first source metal interconnection line through a contact hole penetrating the first dielectric layer, the first drain metal interconnection line being electrically connected to the drain region below the first drain metal interconnection line through a contact hole penetrating the first dielectric layer, and the gate metal interconnection line being electrically connected to the gate interconnection reserved portion below the gate interconnection line through a contact hole penetrating the first dielectric layer; forming a second dielectric layer, which covers the first dielectric layer, the first source metal interconnection line, the first drain metal interconnection line, and the gate metal interconnection line; performing a second metallization to form at least one second source metal interconnection line and at least one second drain metal interconnection line that are parallel to the first direction and alternately arranged at intervals on the second dielectric layer, the second source metal interconnection line being electrically connected to the first source metal interconnection line below the second source metal interconnection line through a contact hole penetrating the second dielectric layer, and the second drain metal interconnection line being electrically connected to the first drain metal interconnection line below the second drain metal interconnection line through a contact hole penetrating the second dielectric layer.

2. The manufacturing method of the GaN device interconnection structure according to claim 1, wherein, Between the two gate metal interconnection lines, there are at least one first source metal interconnection line and at least one first drain metal interconnection line arranged alternately.

3. The manufacturing method of the GaN device interconnection structure according to claim 1, characterized in that, The preparation method further includes: fabricating a source metal contact and a drain metal contact on the semiconductor substrate, and the source metal contact, the drain metal contact, and the gate combination structure are arranged at intervals.

4. The manufacturing method of the GaN device interconnection structure according to claim 1, wherein The distance between the first source metal interconnection line and the first drain metal interconnection line is less than the distance between the first source metal interconnection line or the first drain metal interconnection line and the gate metal interconnection line.

5. The preparation method of the GaN device interconnection structure according to claim 1, wherein, The second source metal interconnection line and the second drain metal interconnection line are alternately arranged at intervals and equally spaced.

6. The manufacturing method of the GaN device interconnection structure according to any one of claims 1-5, characterized in that The preparation method further includes: fabricating a source pad electrically connected to the second source metal interconnection line, a drain pad electrically connected to the second drain metal interconnection line, a gate pad electrically connected to the gate metal interconnection line, and a substrate lead-out pad.

7. A GaN device interconnection structure, characterized in that The GaN device interconnection structure includes: A semiconductor substrate, the semiconductor substrate including a gate region, a source region, and a drain region; At least one gate combination structure, the gate combination structure being located in the gate region and including at least two gate fingers and at least one gate interconnection reserved portion connecting adjacent two gate fingers, the connection direction of the adjacent two gate fingers being a first direction, the source region being located on one side of the gate region, the drain region being located on the other side of the gate region, the connection direction of the source region and the drain region being a second direction, and the second direction being perpendicular to the first direction; A first dielectric layer, the first dielectric layer covering the semiconductor substrate and the gate combination structure; At least one first source metal interconnection line, at least one first drain metal interconnection line, and at least one gate metal interconnection line located on the first dielectric layer and arranged parallel to the second direction and alternately spaced from each other, the first source metal interconnection line being electrically connected to the source region below the first source metal interconnection line through a contact hole penetrating the first dielectric layer, the first drain metal interconnection line being electrically connected to the drain region below the first drain metal interconnection line through a contact hole penetrating the first dielectric layer, and the gate metal interconnection line being electrically connected to the gate interconnection reserved portion below the gate interconnection line through a contact hole penetrating the first dielectric layer; A second dielectric layer, the second dielectric layer covering the first dielectric layer, the first source metal interconnection line, the first drain metal interconnection line, and the gate metal interconnection line; At least one second source metal interconnection line and at least one second drain metal interconnection line located on the second dielectric layer and arranged parallel to the first direction and alternately spaced from each other, the second source metal interconnection line being electrically connected to the first source metal interconnection line below the second source metal interconnection line through a contact hole penetrating the second dielectric layer, and the second drain metal interconnection line being electrically connected to the first drain metal interconnection line below the second drain metal interconnection line through a contact hole penetrating the second dielectric layer.

8. The GaN device interconnection structure according to claim 7, wherein, The contact holes penetrating the first dielectric layer include: a first source interconnection contact hole, a first drain interconnection contact hole, and a gate interconnection contact hole. The first source interconnection contact hole is located above the source region, the first drain interconnection contact hole is located above the drain region, the gate interconnection contact hole is located above the gate interconnection reserved portion, and the first source interconnection contact hole and the first drain interconnection contact hole are arranged at intervals in the first direction; The contact holes penetrating the second dielectric layer include: a second source interconnection contact hole and a second drain interconnection contact hole. The second source interconnection contact hole exposes the first source metal interconnection line, and the second drain interconnection contact hole exposes the first drain metal interconnection line.

9. The GaN device interconnection structure according to claim 7, wherein, Between the two gate metal interconnection lines, at least one first source metal interconnection line and at least one first drain metal interconnection line are alternately arranged.

10. The GaN device interconnection structure according to any one of claims 7-9, characterized in that, The line width of the first source metal interconnect line is the same as that of the first drain metal interconnect line and is greater than the line width of the gate metal interconnect line; the line width of the second source metal interconnect line is the same as that of the second drain metal interconnect line.

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