Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, including a substrate and a channel material layer on the substrate, the substrate including a device region and a buried power rail region; forming a mask sidewall on the substrate of the device region; forming a trench in the substrate of the buried power rail region, the bottom of the trench extending into the substrate; forming a buried power rail structure in the trench, the top of the buried power rail structure being lower than the top of the channel material layer; after forming the buried power rail structure, etching the substrate using the mask sidewall as a mask to pattern the channel material layer into a channel structure layer; after forming the channel structure layer, forming an isolation layer on the substrate to bury the buried power rail structure. This invention first forms the buried power rail structure and then forms the channel structure layer, thereby employing a single isolation layer formation process, simplifying the process steps. Furthermore, since the isolation layer formation process typically includes a thermal annealing step, the thermal budget is correspondingly reduced, thus simplifying the process steps while improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] Modern integrated circuits comprise transistors, capacitors, and other devices formed on a semiconductor substrate. These devices are initially isolated from each other on the substrate and then interconnected via interconnect structures to form a functional circuit. Typical interconnect structures include lateral interconnect structures (e.g., metal interconnects) and vertical interconnect structures (e.g., through-hole interconnects and contacts).

[0004] A buried power rail (BPR) is an interconnect structure embedded in a substrate. The buried power rail is formed during the front end of line (FEOL) process and supplies power to the integrated circuit. Specifically, the buried power rail can be used as either a Vdd or Vss power line. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure that simplifies the process steps while improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a channel material layer located on the substrate, the substrate including a device region and a buried power rail region; forming a mask sidewall on the substrate in the device region; after forming the mask sidewall, forming a trench in the substrate in the buried power rail region, the bottom of the trench extending into the substrate; forming a buried power rail structure in the trench, the top of the buried power rail structure being lower than the top of the channel material layer; after forming the buried power rail structure, etching the substrate using the mask sidewall as a mask to pattern the channel material layer into a channel structure layer; after forming the channel structure layer, forming an isolation layer on the substrate, the isolation layer burying the buried power rail structure therein.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the formation method provided by the embodiments of the present invention, after forming a mask sidewall on the substrate of the device region, a trench is first formed in the substrate of the buried power rail region, and a buried power rail structure is formed in the trench. After forming the buried power rail structure, the substrate is etched using the mask sidewall as a mask to pattern the channel material layer into a channel structure layer. Then, an isolation layer is formed on the substrate, and the isolation layer buries the buried power rail structure. Compared with the scheme of forming the channel structure layer first and then forming the trench, the embodiments of the present invention only use an isolation layer formation process once, thereby simplifying the process steps (e.g., reducing the number of planarization steps). Moreover, the process of forming the isolation layer usually includes a thermal annealing step. Correspondingly, since the embodiments of the present invention only use an isolation layer formation process once, the number of thermal annealing steps is reduced, which can reduce the thermal budget, thereby reducing the impact on device performance and thus helping to improve the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 10 to 24 A schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] The current semiconductor structure fabrication process is relatively complex, and the performance of the semiconductor structures needs improvement. This paper analyzes the reasons for the complex fabrication process and the need to improve the performance of semiconductor structures by examining a semiconductor structure fabrication method.

[0012] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 A substrate is provided, including an initial substrate 10, the initial substrate 10 including a device region 10d and a buried power rail region 10b.

[0014] In this embodiment, the substrate further includes a buffer material layer 11 on the initial substrate 10, a hard mask material layer 12 on the buffer layer 11, and an etch stop material layer 13 on the hard mask material layer 12.

[0015] Continue to refer to Figure 1 A mask sidewall 14 is formed on the substrate of the device region 10d and the buried power rail region 10b.

[0016] As an example, the mask sidewall 14 is formed on the substrate of the buried power rail region 10b using a self-aligned double patterning (SADP) process, and in order to improve the load effect caused by pattern density, the mask sidewall 14 is also formed on the substrate of the buried power rail region 10b.

[0017] Therefore, continue to refer to Figure 1 The forming method further includes forming a first shielding layer 15 covering the mask sidewall 14 on the substrate of the device region 10d.

[0018] After forming the first shielding layer 15, the method further includes: using the first shielding layer 15 as a mask, etching away the mask sidewall 14 located in the buried power rail area 10b.

[0019] In this embodiment, after etching away the mask sidewall 14 located in the buried power rail area 10b, the process further includes removing the first shielding layer 15.

[0020] refer to Figure 2 After removing the masking layer 15, the mask sidewall 14 of the device region 10d is used as a mask to sequentially etch the etching stop material layer 13, the hard mask material layer 12 and the buffer material layer 11 to form a buffer layer 21, a hard mask layer 22 and an etching stop layer 23 stacked from bottom to top.

[0021] refer to Figure 3 A planarization layer 24 covering the top of the etch stop layer 23 is formed on the initial substrate 10; a photoresist layer 25 is formed on a portion of the planarization layer 24 on one side of the etch stop layer 23 in the device region 10d.

[0022] After forming the photoresist layer 25, the method further includes: using the photoresist layer 25 as a mask to etch the planarization layer 24, and retaining the planarization layer 24 below the photoresist layer 25 as a second masking layer (not shown).

[0023] refer to Figure 4 Using the second shielding layer (not shown) and the hard mask layer 22 as masks, a portion of the initial substrate 10 (e.g., ...) is etched. Figure 3 As shown, the initial substrate 10 is patterned as a substrate 30 and a fin 31 located on the substrate 30.

[0024] The position of the fin 31 corresponds to the position of the hard mask layer 22.

[0025] Furthermore, at the location of the second shielding layer, the initial substrate 10 is not etched. Therefore, after the substrate 30 and the fin 31 are formed, a protrusion 32 is also formed on the substrate 30, the position of which corresponds to the position of the second shielding layer.

[0026] After forming the fin portion 31 and the protrusion portion 32, the method further includes: removing the second shielding layer.

[0027] refer to Figure 5 After removing the second masking layer, a first initial isolation layer 40 is formed on the substrate 30, and the top of the first initial isolation layer 40 is flush with the top of the hard mask layer 22.

[0028] The first initial isolation layer 40 is formed using an isolation layer forming process.

[0029] Specifically, the step of forming the first initial isolation layer 40 includes: depositing a first isolation material layer on the substrate 30, the first isolation material layer also covering the top of the etch stop layer 23; and planarizing the first isolation material layer with the top of the hard mask layer 22 as the stop position to form the first initial isolation layer 40.

[0030] Therefore, during the planarization process, the etch stop layer 23 is removed.

[0031] refer to Figure 6 In the buried power rail region 10b, the first initial isolation layer 40 and a portion of the substrate 30 are etched to form a trench 44.

[0032] refer to Figure 7 A buried power rail structure 36 is formed in the trench 44, and the top of the buried power rail structure 36 is lower than the top of the fin 31.

[0033] refer to Figure 8 After the buried power rail structure 36 is formed, a second initial isolation layer 37 is formed in the remaining space of the trench 44, and the top of the second initial isolation layer 37 is flush with the top of the hard mask layer 22.

[0034] The second initial isolation layer 37 is formed using an isolation layer forming process.

[0035] Specifically, the step of forming the second initial isolation layer 37 includes: filling the remaining space of the trench 44 with a second isolation material layer (not shown), the second isolation material layer also covering the top of the hard mask layer 22 and the first initial isolation layer 40; and planarizing the second isolation material layer with the top of the hard mask layer 22 as the stop position to form the second initial isolation layer 37.

[0036] refer to Figure 9 The second initial isolation layer 37 and the first initial isolation layer 40 are etched back to expose part of the sidewall of the fin 31. After the etch back process, the remaining second initial isolation layer 37 and the first initial isolation layer 40 constitute an isolation layer 38, which buries the buried power rail structure 36.

[0037] Therefore, in the current forming method, after the buried power rail structure 36 is introduced, two isolation layer forming processes are required to form the isolation layer 38, which leads to a complicated process.

[0038] Moreover, the process of depositing the isolation material layer usually includes a thermal annealing step. Accordingly, this embodiment requires two isolation layer formation processes, which results in a large thermal budget, which can easily have an adverse effect on device performance and thus reduce the performance of the semiconductor structure.

[0039] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a channel material layer located on the substrate, the substrate including a device region and a buried power rail region; forming a mask sidewall on the substrate in the device region; after forming the mask sidewall, forming a trench in the substrate in the buried power rail region, the bottom of the trench extending into the substrate; forming a buried power rail structure in the trench, the top of the buried power rail structure being lower than the top of the channel material layer; after forming the buried power rail structure, etching the substrate using the mask sidewall as a mask to pattern the channel material layer into a channel structure layer; after forming the channel structure layer, forming an isolation layer on the substrate, the isolation layer burying the buried power rail structure therein.

[0040] In the formation method provided by the embodiments of the present invention, after forming a mask sidewall on the substrate of the device region, a trench is first formed in the substrate of the buried power rail region, and a buried power rail structure is formed in the trench. After forming the buried power rail structure, the substrate is etched using the mask sidewall as a mask to pattern the channel material layer into a channel structure layer. Then, an isolation layer is formed on the substrate, and the isolation layer buries the buried power rail structure. Compared with the scheme of forming the channel structure layer first and then forming the trench, the embodiments of the present invention only use the isolation layer formation process once, thereby simplifying the process steps (e.g., reducing the number of planarization steps). Moreover, the process of forming the isolation layer usually includes a thermal annealing step. Accordingly, since the embodiments of the present invention only use the isolation layer formation process once, the number of thermal annealing steps is reduced, and the thermal budget can be reduced accordingly, thereby reducing the impact on device performance and thus helping to improve the performance of the semiconductor structure.

[0041] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 10 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0043] refer to Figure 10 A substrate (not shown) is provided, including a substrate 400 and a channel material layer 100 on the substrate 400, the substrate 400 including a device region 10d and a buried power rail region 10b.

[0044] The substrate is used to provide a process platform for subsequent manufacturing processes.

[0045] In this embodiment, the formation method is used to form a fin field-effect transistor (FinFET) as an example for illustration.

[0046] In other embodiments, the formation method can also be used to form a fully surrounded gate (GAA) transistor, a nanosheet transistor, a forksheet transistor, or a complementary field-effect transistor (CFET).

[0047] In this embodiment, the channel material layer 100 is a fin material layer used to form the fin.

[0048] In other embodiments, the channel material layer comprises one or more stacked channel material layers, each including a sacrificial material layer and a channel material layer situated on the sacrificial material layer. Specifically, when the formed transistor is an NMOS transistor, the material of the sacrificial material layer is SiGe, and the material of the channel material layer is Si; when the formed transistor is a PMOS transistor, the material of the sacrificial material layer is Si, and the material of the channel material layer is SiGe. In this case, the substrate may further include a fin material layer located between the substrate and the channel material stack.

[0049] In this embodiment, the substrate 400 is a silicon substrate. In other embodiments, the substrate may be a substrate of other material types. For example, the substrate material may be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0050] The channel material layer 100 is used to form a channel structure layer after etching, and the channel structure layer is used to provide a channel for the transistor.

[0051] The material of the fin material layer (i.e., the channel material layer 100) is the same as the material of the substrate 400. In this embodiment, the material of the fin material layer (i.e., the channel material layer 100) is silicon. In other embodiments, the material of the fin material layer (i.e., the channel material layer) may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate.

[0052] As an example, the substrate 400 and the channel material layer 100 are an integral structure.

[0053] In this embodiment, the substrate further includes a hard mask (HM) material layer 120 formed on the channel material layer 100.

[0054] The hard mask material layer 120 is used to form a hard mask layer after a patterning process, and the hard mask layer is used as a mask for subsequent etching of the channel material layer 100.

[0055] Furthermore, in the subsequent planarization process to form the isolation layer, the top surface of the hard mask layer is used to define the stop position of the planarization process.

[0056] The hard mask material layer 120 is made of nitrogen-containing material, which makes the hard mask material layer 120 have high hardness and density, thereby enabling the hard mask layer to play the role of etching mask in the subsequent etching process of the channel material layer 100.

[0057] In this embodiment, the material of the hard mask material layer 120 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. These materials have high density and hardness.

[0058] As an example, the material of the hard mask material layer 120 is silicon nitride.

[0059] It should be noted that the substrate also includes a buffer layer 110 located between the channel material layer 100 and the hard mask material layer 120.

[0060] The buffer layer 110 exhibits good adhesion to the channel material layer 100, and the hard mask material layer 120 also exhibits good adhesion to the substrate 100. Furthermore, the buffer layer 110 serves as a stress buffer layer, providing stress buffering during the formation of the hard mask material layer 120 and mitigating the problem of dislocations generated during its formation.

[0061] In this embodiment, the material of the buffer layer 110 is silicon oxide.

[0062] It should also be noted that the substrate further includes an etch stop layer 130 located on top of the hard mask material layer 120.

[0063] Subsequently, mask sidewalls are formed on the hard mask material layer 120. The process of forming mask sidewalls includes an etching process. During the etching process, the etching stop layer 130 can reduce the damage to the film layer (e.g., hard mask material layer 120) located below it, thereby improving the accuracy of subsequent pattern transfer.

[0064] As an example, the material of the etch stop layer 130 is silicon oxide.

[0065] Continue to refer to Figure 10 A mask sidewall 140 is formed on the substrate (not shown) in the device region 10d.

[0066] The mask sidewall 140 is used as a mask for subsequent etching of the substrate. Specifically, the mask sidewall 140 is used as a mask for the subsequent hard mask material layer 120.

[0067] In this embodiment, the mask sidewall 140 is formed on the hard mask material layer 120. Specifically, the mask sidewall 140 is formed on the etch stop layer 130.

[0068] In this embodiment, the mask sidewall 140 is formed using a self-aligned multiple patterning process to increase the pattern density of the channel structure layer and further reduce the pitch of adjacent channel structure layers, thereby enabling the photolithography process to overcome the limit of photolithography resolution.

[0069] For example, the self-aligned multiple patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0070] Taking the formation of the mask sidewall 140 using the SADP process as an example, the steps for forming the mask sidewall 140 include: forming a core layer (not shown) on the etch stop layer 130; forming a conformally conformal sidewall material layer (not shown) covering the etch stop layer 130 and the core layer; removing the sidewall material layer located on top of the core layer and on the etch stop layer 130, and retaining the remaining sidewall material layer located on the sidewall of the core layer as the mask sidewall 140; and removing the core layer after forming the mask sidewall 140.

[0071] In other embodiments, photolithography and etching processes can be used to directly etch the material layer corresponding to the mask sidewall 140 to form the mask sidewall 140.

[0072] In this embodiment, there is a high etching selectivity between the mask sidewall 140 and the etching stop layer 130, so that the etching stop layer 130 can be etched using the mask sidewall 140 as a mask.

[0073] In this embodiment, the mask sidewall 140 is made of silicon nitride. In other embodiments, the mask sidewall may also be made of silicon oxide, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0074] It should be noted that, in order to improve the load effect caused by pattern density, the mask sidewall 140 is also formed on the substrate of the buried power rail area 10b during the formation of the mask sidewall 140.

[0075] Therefore, in conjunction with the reference Figure 10 and Figure 11 The forming method further includes: forming a first shielding layer 141 covering the mask sidewall 140 on the substrate of the device region 10d; using the first shielding layer 141 as a mask, etching away the mask sidewall 140 located in the buried power rail region 10b.

[0076] By removing the mask sidewall 140 located in the buried power rail area 10b, the formation of a trench structure layer in the buried power rail area 10b is avoided, and preparation is made for the subsequent formation of a buried power rail structure in the buried power rail area 10b.

[0077] As an example, the material of the first shielding layer 141 can be photoresist.

[0078] In this embodiment, after etching away the mask sidewall 140 located in the buried power rail area 10b, the process further includes removing the first shielding layer 141.

[0079] Reference Figure 12 and Figure 13 After forming the mask sidewall 140, a trench 170 is formed in the substrate (not shown) of the buried power rail area 10b (e.g., Figure 13 As shown, the bottom of the trench 170 extends into the substrate 400.

[0080] The trench 170 is used to provide space for the subsequent formation of the buried power rail structure.

[0081] The buried power rail structure has a certain thickness along the normal direction of the substrate surface. By extending the bottom of the trench 170 into the substrate 400, the buried power rail structure is disposed in the substrate 400, which helps to release the wiring resources of the back end of kine (BEOL) interconnect to meet the needs of continuous chip miniaturization. In addition, the buried power rail structure adopts the technique of increasing back end resistance by reducing pitch, which also helps to provide a lower local current distribution with lower resistance.

[0082] Specifically, the step of forming the trench 170 includes: forming a patterned structure layer (not shown) covering the mask sidewall 140 on the etching stop layer 130, wherein a patterned opening 165 is formed in the patterned structure layer; using the patterned structure layer as a mask, etching the channel material layer 100 at the bottom of the patterned opening 165 and a substrate 400 of a certain thickness to form the trench 170; and removing the patterned structure layer after forming the trench 170.

[0083] In this embodiment, the pattern structure layer is a stacked structure, the pattern structure layer includes a first planarization layer 150 and a first photoresist layer 160 located on the first planarization layer 150, and the pattern opening 165 is formed in the first photoresist layer 160.

[0084] The first planarization layer 150 provides a flat surface for the formation of the first photoresist layer 160, thereby improving exposure uniformity and consequently improving the dimensional accuracy and topographic quality of the patterned opening 165. As an example, the material of the first planarization layer 150 is spin-on carbon (SOC).

[0085] In this embodiment, the substrate is etched using an anisotropic etching process to form the trench 170.

[0086] The longitudinal etching rate of anisotropic etching processes is much greater than its transverse etching rate. By selecting anisotropic etching processes, it is beneficial to improve the sidewall morphology quality of the trench 170, for example, to improve the sidewall flatness of the trench 170.

[0087] Specifically, the anisotropic etching process can be a plasma dry etching process.

[0088] It should be noted that the substrate also includes a buffer layer 110 on the channel material layer 100, a hard mask material layer 120 on the buffer layer 110, and an etch stop layer 130 on the hard mask material layer 120. Therefore, before etching the channel material layer 100, the etch stop layer 130, the hard mask material layer 120, and the buffer layer 110 are etched sequentially. That is, the trench 170 penetrates the etch stop layer 130, the hard mask material layer 120, the buffer layer 110, and the channel material layer 100, and extends into the substrate 400 of a certain thickness.

[0089] Reference Figures 14 to 16 In the trench 170 (e.g. Figure 13 A buried power rail structure 230 is formed in the trench (as shown), the top of which is lower than the top of the trench material layer 100.

[0090] The buried power rail structure 230 is used to realize electrical interconnection between devices formed on the substrate 100, thereby forming a functional circuit. The buried power rail structure 230 can be used as a Vdd power line or a Vss power line.

[0091] The buried power rail structure 230 is made of a conductive material. In this embodiment, the buried power rail structure 230 is made of a metallic material, including one or more of Co (cobalt), W (tungsten), Ni (nickel), and Ru (ruthenium). The material of the buried power rail structure 230 has low resistivity, which is beneficial for improving RC delay and increasing the processing speed of the chip.

[0092] As an example, the material of the buried power rail structure 230 is tungsten.

[0093] Specifically, the step of forming the buried power rail structure 230 in the trench 170 includes:

[0094] like Figure 14 As shown, a conductive material layer 210 is filled in the trench 170, and the conductive material layer 210 also covers the top of the mask sidewall 140.

[0095] The conductive material layer 210 provides a process basis for the subsequent formation of the buried power rail structure 230.

[0096] In this embodiment, the conductive material layer 210 is made of tungsten.

[0097] As an example, the conductive material layer 210 is formed using an electroplating process.

[0098] It should be noted that, before forming the conductive material layer 210, the forming method further includes: forming a pad layer 200, the pad layer 200 conformally covering the mask sidewall 140, the etching stop layer 130, and the bottom and sidewalls of the trench 170.

[0099] The padding layer 200 is used to improve the adhesion of the conductive material layer 210 in the trench 170.

[0100] As an example, the material of the liner layer 200 is titanium nitride.

[0101] like Figure 15 As shown, the conductive material layer 210 is planarized.

[0102] By planarizing the conductive material layer 210, the top surface of the remaining conductive material layer 210 becomes a flat surface, thus preparing for the subsequent back etching process of the remaining conductive material layer 210, thereby improving the flatness of the top surface of the buried power rail structure.

[0103] In this embodiment, during the planarization process of the conductive material layer 210, the top surface of the mask sidewall 140 is also planarized to make the top surface of the mask sidewall 140 a flat surface.

[0104] By planarizing the top surface of the mask sidewall 140, making it a flat surface, the problem of different etching gas collection angles can be improved when using the mask sidewall 140 as a mask to etch the underlying film layers (e.g., etching stop layer 130, hard mask material layer 120, and buffer layer 110), thereby improving the accuracy of image transmission.

[0105] Correspondingly, during the planarization process, the padding layer 200 is also planarized. Therefore, after the planarization process, the remaining conductive material layer 210 is exposed on the top surface of the mask sidewall 140.

[0106] Specifically, the remaining conductive material layer 210 is flush with the top surface of the mask sidewall 140.

[0107] In this embodiment, the planarization process is performed using chemical mechanical polishing (CMP). CMP facilitates planarization of the top of the film layer and allows for the planarization of multiple film layers.

[0108] like Figure 16As shown, after the planarization process, the conductive material layer 210 is etched back so that the top of the remaining conductive material layer 210 is lower than the top of the channel material layer 100. The remaining conductive material layer 210 in the trench 170 serves as a buried power rail structure 230.

[0109] In this embodiment, an anisotropic etching process is used to perform a back-etching process on the conductive material layer 210.

[0110] The longitudinal etching rate of the anisotropic etching process is much greater than its lateral etching rate, thereby enabling the conductive material layer 210 to be etched in a direction perpendicular to the substrate surface. By controlling the longitudinal etching amount of the conductive material layer 210, the thickness of the remaining conductive material layer 210 in the trench 170 can meet the actual requirements, and the flatness of the top surface of the buried power rail structure 230 is improved.

[0111] Specifically, the anisotropic etching process can be a plasma dry etching process.

[0112] During the etching process, the padding layer 200 is also etched so that the top of the remaining padding layer 200 is flush with the top of the buried power rail structure 230.

[0113] In this embodiment, the top of the buried power rail structure 230 is lower than the top of the channel material layer 100 so that after an isolation layer is formed on the substrate 400, the isolation layer can bury the buried power rail structure 230.

[0114] In this embodiment, the top of the buried power rail structure 230 is higher than the top of the substrate 400.

[0115] Subsequently, conductive plugs (i.e., Via-BPR) are typically used to connect the buried power rail structure 230 to the outside. The conductive plugs are in contact with the top of the buried power rail structure 230. Therefore, by making the top of the buried power rail structure 230 higher than the top of the substrate 400, it is beneficial to reduce the difficulty of forming the conductive plugs. For example, the etching depth can be reduced during the etching process for forming the conductive plugs.

[0116] Reference Figures 17 to 21 After the buried power rail structure 230 is formed, the mask sidewall 140 (such as...) Figure 16 As shown, the substrate (not shown) is etched using a mask to pattern the channel material layer 100 into a channel structure layer 410.

[0117] The channel structure layer 410 is used to provide the channel for the transistor.

[0118] In this embodiment, after forming the buried power rail structure 230, the channel material layer 100 is patterned into a channel structure layer 410, and subsequently an isolation layer is formed on the substrate 400. The isolation layer buries the buried power rail structure 230 within it. Compared with the scheme of forming the channel structure layer first and then forming the trench, in this embodiment, the isolation layer can be formed in only one isolation layer forming process, thereby simplifying the process steps (e.g., reducing the number of planarization steps). Moreover, the process of forming the isolation layer usually includes a thermal annealing step. Since this embodiment only uses the isolation layer forming process in one step, the thermal budget can be reduced accordingly, thus reducing the number of thermal annealing steps, thereby reducing the impact on device performance and thus helping to improve the performance of the semiconductor structure.

[0119] In this embodiment, the channel material layer 100 is a fin material layer, and correspondingly, the channel structure layer 410 is a fin.

[0120] In other embodiments, when the channel material layer comprises one or more stacked channel material stacks, the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer, the channel structure layer correspondingly comprises one or more stacked channel stacks, the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer. Correspondingly, when the substrate may further include a fin material layer located between the substrate and the channel material stacks, the fin material layer is also patterned as a fin.

[0121] like Figure 17 As shown, specifically, the step of etching the substrate using the mask sidewall 140 as a mask includes: etching the hard mask material layer 120 (e.g., using the mask sidewall 140 as a mask) using the mask sidewall 140 as a mask. Figure 15 As shown), a hard mask layer 125 is formed.

[0122] The hard mask layer 125 is used as a mask for etching the channel material layer 100.

[0123] The hard mask material layer 120 is further provided with an etching stop layer 130 on top, and a buffer layer 110 is further provided between the hard mask material layer 120 and the channel material layer 100. Therefore, in the step of etching the substrate using the mask sidewall 140 as a mask, the etching stop layer 130, the hard mask material layer 120 and the buffer layer 110 are etched in sequence.

[0124] In this embodiment, after forming the hard mask layer 125, the method further includes: removing the mask sidewalls 140.

[0125] It should be noted that in this embodiment, after the buried power rail structure 230 is formed, the substrate is etched to avoid the process of forming the trench 170 from causing damage to the hard mask material layer 120, thereby avoiding the impact on the thickness of the hard mask material layer 120, and correspondingly avoiding the impact on the height of the hard mask layer 125, which is beneficial to improving the accuracy of pattern transfer.

[0126] refer to Figure 18 After removing the mask sidewall 140, the forming method further includes forming a linewidth compensation sidewall 245 on the sidewall of the hard mask layer 125.

[0127] During the subsequent etching of the channel material layer 100 using the hard mask layer 125 as a mask, the sidewalls of the hard mask layer 125 are easily affected by lateral etching, which leads to a reduction in the width of the hard mask layer 125 and thus affects the width of the channel structure layer. Therefore, by forming linewidth compensation sidewalls 245 on the sidewalls of the hard mask layer 125, the influence of lateral etching is compensated, thereby enabling the width of the channel structure layer to reach the target width.

[0128] Specifically, the step of forming the linewidth compensation sidewall 245 includes: forming a linewidth compensation material layer 240, which conformally covers the hard mask layer 125, the trench material layer 100, the buried power rail structure 230, and the sidewall of the trench 170 exposed by the buried power rail structure 230, wherein the linewidth compensation material layer 240 located on the sidewall of the hard mask layer 125 serves as the linewidth compensation sidewall 245.

[0129] In this embodiment, the linewidth compensation material layer 240 is formed using atomic layer deposition (ALD). The linewidth compensation material layer 240 formed using ALD has good thickness uniformity and good step coverage capability.

[0130] In other embodiments, chemical vapor deposition can also be used to form the linewidth compensation material layer.

[0131] In this embodiment, the material of the linewidth compensation sidewall 245 is silicon nitride. In other embodiments, the material of the linewidth compensation sidewall may also be silicon oxide, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0132] It should be noted that, in other embodiments, after forming the linewidth compensation material layer, the linewidth compensation material layer may be longitudinally etched in a direction perpendicular to the surface of the substrate, thereby retaining the remaining linewidth compensation material layer located on the sidewall of the hard mask layer as a linewidth compensation sidewall.

[0133] Reference Figure 19 and Figure 20 After forming the linewidth compensation sidewall 245, the forming method further includes: forming a shielding layer 255 (e.g., in the device region 10d, on a portion of the substrate on one side of the hard mask layer 125) on the substrate. Figure 20 (As shown).

[0134] In this embodiment, the shielding layer 255 is defined as the second shielding layer 255.

[0135] The second masking layer 255 also serves as a mask for subsequent etching of the channel material layer 100, thereby allowing a portion of the channel material layer 100 to be retained to meet actual process requirements. For example, by retaining a portion of the channel material layer 100, preparation is made for subsequent measurement processes.

[0136] Specifically, the step of forming the second shielding layer 255 includes: forming a second planarization layer 250 on the substrate that covers the hard mask layer 125 and the linewidth compensation sidewall 245; forming a second photoresist layer 260 on a portion of the second planarization layer 250 on one side of the hard mask layer 125 in the device region 10d; and etching the second planarization layer 250 using the second photoresist layer 260 as a mask to form the second shielding layer 255.

[0137] As an example, the material of the second planarization layer 250 is a SOC material.

[0138] In this embodiment, the second shielding layer 255 is formed on the line width compensation material layer 240. During the formation of the second shielding layer 255, the line width compensation material layer 240 can protect the channel material layer 100, thereby reducing the probability of damage to the channel material layer 100.

[0139] It should be noted that, since the top of the buried power rail structure 230 is lower than the top of the trench material layer 100, during the etching of the second planarization layer 250, a portion of the thickness of the second planarization layer 250 is retained in the trench 170, forming a residual shielding material layer 256 located on top of the buried power rail structure 230.

[0140] Specifically, the top of the residual shielding material layer 256 is lower than the top of the channel material layer 100.

[0141] It should also be noted that the second photoresist layer 260 is consumed during the etching of the second planarization layer 250. As an example, the second photoresist layer 260 is removed after the second masking layer 255 is formed. In other embodiments, the second photoresist layer may be retained on top of the second photoresist layer.

[0142] refer to Figure 21 Using the hard mask layer 125 as a mask, the channel material layer 100 is etched (e.g., ...). Figure 19 As shown, the channel material layer 100 is patterned as a channel structure layer 410.

[0143] Specifically, in the step of etching the channel material layer 100, the linewidth compensation sidewall 245 is also used as a mask.

[0144] In this embodiment, a linewidth compensation material layer 240 is formed on the top of the channel material layer 100. Therefore, before etching the channel material layer 100, the linewidth compensation material layer 240 is longitudinally etched along a direction perpendicular to the surface of the substrate to remove the linewidth compensation material layer 240 located on the top of the channel material layer 100 and the top of the hard mask layer 125. After exposing the channel material layer 100, the channel material layer 100 is etched to form the channel structure layer 410.

[0145] It should be noted that during the etching of the linewidth compensation material layer 240 and the channel material layer 100, the linewidth compensation material layer 240 located on the sidewall of the hard mask layer 125 and the sidewall of the trench 170 is easily affected by lateral etching, resulting in loss.

[0146] As an example, after the trench structure layer 410 is formed, the linewidth compensation material layer 240 (i.e., linewidth compensation sidewall 245) located on the sidewall of the hard mask layer 125 and the linewidth compensation material layer 240 located on the sidewall of the trench 170 are removed.

[0147] As an example, in the trench 170, under the protection of the residual shielding material layer 256, the linewidth compensation material layer 240 covered by the residual shielding material layer 256 is retained, forming a residual compensation material layer 242.

[0148] The buried power rail structure 230 is subsequently connected using conductive plugs (i.e., Via-BPR). During the formation of the conductive plugs, the residual compensation material layer 242 located on top of the buried power rail structure 230 can act as an etching stop layer during the etching process, thereby allowing the conductive plugs to contact the top of the buried power rail structure 230 and reducing the probability of over-etching problems in the buried power rail structure 230.

[0149] It should also be noted that a second shielding layer 255 is formed on a portion of the substrate on one side of the hard mask layer 125. Therefore, during the etching of the channel material layer 100, the second shielding layer 255 is also used as a mask for etching. Correspondingly, after etching the channel material layer 100, a protrusion 420 is formed at the position corresponding to the second shielding layer 255.

[0150] In this embodiment, after the channel structure layer 410 and the protrusion 420 are formed, the second shielding layer 255 and the residual shielding material layer 256 are removed.

[0151] Reference Figures 22 to 24 After forming the channel structure layer 410, an isolation layer 430 (e.g., ...) is formed on the substrate 400. Figure 24 As shown, the isolation layer 430 buries the buried power rail structure 230 within it.

[0152] The isolation layer 430 serves as a shallow trench isolation structure (STI) to isolate adjacent devices.

[0153] In this embodiment, the isolation layer 430 covers a portion of the sidewall of the channel structure layer 410. The channel structure 410 is a fin, and the portion of the fin exposed outside the isolation layer 430 serves as an active fin, which provides a conductive channel for the device during operation.

[0154] In other embodiments, when the channel structure layer includes one or more stacked channel stacks, the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer, and a fin is formed between the substrate and the channel structure layer, the isolation layer correspondingly covers the sidewall of the fin and exposes the channel structure layer.

[0155] In this embodiment, the material of the insulating layer 430 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0156] Specifically, the steps for forming the isolation layer 430 include: Figure 22 As shown, an isolation material layer 431 is formed on the substrate 400, the isolation material layer 431 covering the top of the etch stop layer 130; as Figure 23 As shown, with the top of the hard mask layer 125 as the stop position, the isolation material layer 431 is planarized to form the initial isolation layer 432; as Figure 24 As shown, the initial isolation layer 432 is etched back to achieve a preset thickness, and the remaining initial isolation layer 432 after the etch-back process is used as the isolation layer 430.

[0157] In this embodiment, a fluidic chemical vapor deposition (FCVD) process is used to form the isolation material layer 431. The FCVD process has good gap-filling ability, which helps to reduce the probability of voids and other defects forming in the isolation material layer 431, and thus helps to improve the isolation effect of the isolation layer 430.

[0158] The FCVD process includes the following steps: depositing a thin film precursor on the substrate 400; and performing a vapor annealing treatment on the thin film precursor to form a precursor isolation film. The elements contained in the thin film precursor are determined according to the material of the isolation layer 430.

[0159] In this embodiment, the step of forming the isolation material layer 431 further includes: annealing the precursor isolation film to transform the precursor isolation film into an isolation material layer.

[0160] In other embodiments, a high aspect ratio (HARP) chemical vapor deposition process can also be used to form the isolation material layer. HARP can meet the filling requirements of openings with high aspect ratios, thus improving the gap-filling effect of the isolation material layer.

[0161] In this embodiment, a chemical mechanical polishing (CMP) process is used to planarize the insulating material layer 431. By employing CMP, the stop position of the planarization process can be easily controlled.

[0162] It should be noted that during the planarization process of the isolation material layer 431, the etch stop layer 130 located on top of the hard mask layer 125 is also removed. The etch stop layer 130 and the isolation material layer 431 are made of the same material, therefore, the etch stop layer 130 is easy to remove.

[0163] Moreover, even if a residual compensation material layer 242 is formed on the top of the buried power rail structure 230, the exposed residual compensation material layer 242 can be removed during the planarization process of the isolation material layer 431.

[0164] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, which comprises a substrate and a channel material layer on the substrate, the substrate comprising a device region and a buried power rail region; forming a mask sidewall on the substrate in the device region; after forming the mask sidewall, forming a trench in the substrate in the buried power rail region, the bottom of the trench extending into the substrate; forming a buried power rail structure in the trench, the top of the buried power rail structure being lower than the top of the channel material layer; after forming the buried power rail structure, patterning the channel material layer into a channel structure layer by etching the substrate with the mask sidewall as a mask; after forming the channel structure layer, forming an isolation layer on the substrate, the isolation layer burying the buried power rail structure.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming a buried power rail structure in the trench, the top of the buried power rail structure is higher than the top of the substrate.

3. The method of forming a semiconductor structure of claim 1, wherein, The substrate further comprises a hard mask material layer formed on the channel material layer; In the step of forming a mask sidewall on the substrate in the device region, the mask sidewall is formed on the hard mask material layer; The step of etching the substrate with the mask sidewall as a mask comprises etching the hard mask material layer with the mask sidewall as a mask to form a hard mask layer; After forming the hard mask layer, before patterning the channel material layer into a channel structure layer, the method further comprises removing the mask sidewall; The step of patterning the channel material layer into a channel structure layer comprises etching the channel material layer with the hard mask layer as a mask after removing the mask sidewall.

4. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a buried power rail structure in the trench comprises filling a conductive material layer in the trench, the conductive material layer also covering the top of the mask sidewall; performing a planarization treatment on the conductive material layer; after the planarization treatment, performing a back etching treatment on the conductive material layer, so that the top of the remaining conductive material layer is lower than the top of the channel material layer, and the remaining conductive material layer in the trench serves as a buried power rail structure.

5. The method of forming a semiconductor structure of claim 4, wherein, During the planarization treatment on the conductive material layer, the top surface of the mask sidewall is also planarized, so that the top surface of the mask sidewall is a planar surface.

6. The method of forming a semiconductor structure according to claim 4 or 5, wherein The planarization treatment is performed by using a chemical mechanical polishing process.

7. The method of forming a semiconductor structure of claim 4, wherein, The back etching treatment on the conductive material layer is performed by using an anisotropic etching process.

8. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a trench in the substrate in the buried power rail region comprises forming a pattern structure layer on the substrate, the pattern structure layer covering the mask sidewall, and the pattern structure layer having a pattern opening formed therein; etching the channel material layer at the bottom of the pattern opening and part of the thickness of the substrate with the pattern structure layer as a mask to form a trench; after forming the trench, removing the pattern structure layer.

9. The method of forming a semiconductor structure of claim 1, wherein, The trench is formed by etching the substrate by using an anisotropic etching process.

10. The method of forming a semiconductor structure of claim 3, wherein, Before etching the channel material layer with the hard mask layer as a mask after removing the mask sidewall, the forming method further comprises forming a line width compensation sidewall on the sidewall of the hard mask layer; In the step of etching the channel material layer using the hard mask layer as a mask, the line width compensation side wall is also used as a mask.

11. The method of forming a semiconductor structure of claim 10, wherein, The step of forming the line width compensation side wall on the sidewall of the hard mask layer includes: forming a line width compensation material layer conformally covering the hard mask layer, the channel material layer, the buried power rail structure and the sidewall of the trench exposed by the buried power rail structure, wherein the line width compensation material layer on the sidewall of the hard mask layer is used as the line width compensation side wall.

12. The method of forming a semiconductor structure of claim 11, wherein, The line width compensation material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

13. The method of forming a semiconductor structure according to claim 10 or 11, wherein After the line width compensation side wall is formed and before the channel material layer is etched, the forming method further includes: forming a shielding layer on part of the substrate on one side of the hard mask layer; In the step of etching the channel material layer using the hard mask layer as a mask, the shielding layer is also used as a mask.

14. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the isolation layer includes: forming an isolation material layer on the substrate by a deposition process; The isolation material layer is subjected to a planarization treatment to form an initial isolation layer; The initial isolation layer is subjected to a back etching treatment, and the remaining initial isolation layer is used as the isolation layer.

15. The method of forming a semiconductor structure of claim 14, wherein, The deposition process includes a fluid chemical vapor deposition process.

16. The method of forming a semiconductor structure of claim 1, wherein, The material of the buried power rail structure includes one or two of Co, W, Ni and Ru.

17. The method of forming a semiconductor structure of claim 1, wherein, The channel material layer is a fin material layer. Alternatively, the channel material layer includes one or more stacked channel material layers, and each channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer.

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