Semiconductor structure, manufacturing method thereof, chip packaging structure, and electronic device

Abstract

The present disclosure relates to the technical field of electronic devices, and specifically to a semiconductor structure, a manufacturing method thereof, a chip packaging structure, and an electronic device. The semiconductor structure includes: a substrate, an IPD capacitor, and a first wiring board. The substrate is used to carry a chip, and a receiving groove is provided on a first surface of the substrate; the IPD capacitor is disposed in the receiving groove; the first wiring board is disposed on the first surface of the substrate, and a first connection wiring is provided in the first wiring board, and the first connection wiring is connected to the IPD capacitor. The IPD capacitor can denoise a power signal and improve the stability of the power supply, thereby reducing the power consumption of the chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic devices, and more particularly, to a semiconductor structure, a manufacturing method thereof, a chip packaging structure, and an electronic device. Background Art

[0002] With the evolution of semiconductor process nodes, the size of transistors is getting smaller and the operating speed of chips is getting higher. At the same time, the power consumption of chips is also increasing continuously. Excessive power consumption is not conducive to the battery life of electronic devices on the one hand, and on the other hand, excessive power consumption will cause the chip to heat up, affecting the performance of the chip.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a semiconductor structure, a manufacturing method thereof, a chip packaging structure, and an electronic device, so as to reduce the power consumption of the chip to a certain extent.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising:

[0006] A substrate for carrying a chip, and a receiving groove is provided on a first surface of the substrate;

[0007] An IPD (Integrated passive device) capacitor disposed in the receiving groove;

[0008] A first wiring board disposed on the first surface of the substrate, and a first connection wiring is provided in the first wiring board, and the first connection wiring is connected to the IPD capacitor.

[0009] According to a second aspect of the present disclosure, there is provided a manufacturing method of a semiconductor structure, the manufacturing method comprising:

[0010] Forming a receiving groove on a first surface of a substrate;

[0011] Forming an IPD capacitor in the receiving groove;

[0012] Forming a first wiring board on the substrate, such that a first connection wiring in the first wiring board is connected to the IPD capacitor.

[0013] According to a third aspect of the present disclosure, there is provided a chip packaging structure, the chip packaging structure comprising the above semiconductor structure.

[0014] According to a fourth aspect of the present disclosure, there is provided an electronic device, which includes the above chip package structure.

[0015] In the semiconductor structure provided by the embodiments of the present disclosure, an IPD capacitor is disposed on a substrate. The IPD capacitor is embedded in the substrate. Through the IPD capacitor, power signals can be denoised and the stability of the power supply can be improved, thereby reducing the power consumption of the chip. And since the IPD capacitor is embedded in the substrate, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in the electronic device. Moreover, the routing path between the IPD capacitor and the chip is short, so that parasitic inductance and parasitic capacitance can be reduced, and the performance of the IPD capacitor can be improved.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 Schematic diagram of a first semiconductor structure provided by an exemplary embodiment of the present disclosure;

[0019] Figure 2 Schematic diagram of a second semiconductor structure provided by an exemplary embodiment of the present disclosure;

[0020] Figure 3 Schematic diagram of a first chip package structure provided by an exemplary embodiment of the present disclosure;

[0021] Figure 4 Schematic diagram of a second chip package structure provided by an exemplary embodiment of the present disclosure;

[0022] Figure 5 Schematic diagram of an IPD capacitor provided by an exemplary embodiment of the present disclosure;

[0023] Figure 6 Flowchart of a manufacturing method of a first semiconductor structure provided by an exemplary embodiment of the present disclosure;

[0024] Figure 7 Flowchart of a manufacturing method of a second semiconductor structure provided by an exemplary embodiment of the present disclosure;

[0025] Figure 8Flow chart of the manufacturing method of the third semiconductor structure provided by the exemplary embodiment of the present disclosure;

[0026] Figures 9 - 13 Process diagram of the manufacturing method of a semiconductor structure provided by the exemplary embodiment of the present disclosure;

[0027] Figure 14 Schematic diagram of an electronic device provided by the embodiment of the present disclosure. Detailed implementation manners

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted.

[0029] In this example embodiment, a semiconductor structure is first provided. As Figure 1 shown, the semiconductor structure includes: a substrate 110, an IPD capacitor 120, and a first wiring board 130. The substrate 110 is used to carry a chip. A receiving groove 111 is provided on the first surface of the substrate 110; the IPD capacitor 120 is disposed in the receiving groove 111; the first wiring board 130 is disposed on the first surface of the substrate 110. A first connection trace 131 is provided in the first wiring board 130, and the first connection trace 131 is connected to the IPD capacitor 120.

[0030] For the semiconductor structure provided by the embodiment of the present disclosure, the IPD capacitor 120 is disposed on the substrate 110 and is embedded in the substrate 110. The IPD capacitor 120 can denoise the power signal and improve the stability of the power supply, thereby reducing the power consumption of the chip. Moreover, since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in the electronic device. And the wiring path between the IPD capacitor and the chip is short, thereby reducing the parasitic inductance and parasitic capacitance and improving the performance of the IPD capacitor 120.

[0031] Furthermore, as Figure 3 shown, the semiconductor structure provided by the embodiment of the present disclosure may further include a second wiring board 140. A chip groove 112 is provided on the second surface of the substrate 110. The chip groove 112 is used to receive a first chip 210. The second wiring board 140 is disposed on the second surface of the substrate 110. A second connection trace is provided in the second wiring board 140, and the second connection trace is used to connect the first chip 210. The first surface and the second surface of the substrate 110 face away from each other.

[0032] On one side of the first wiring board 130 away from the substrate 110, a second chip 220 may be provided, and the first chip 210 is disposed in the chip slot 112. The first connection trace 131 in the first wiring board 130 connects the second chip 220. The second wiring board 140 is disposed on the second surface of the substrate 110, and the second wiring board 140 covers the first chip 210. A second connection trace is provided in the second wiring board 140, and the second connection trace connects the first chip 210.

[0033] The following will detail each device of the semiconductor structure provided by the embodiments of the present disclosure:

[0034] The substrate 110 may be a silicon substrate, and a receiving groove 111 is provided on the silicon substrate. The silicon substrate may be obtained by cutting a silicon ingot. The silicon substrate may be a circular substrate or a rectangular substrate, etc. Among them, a plurality of receiving grooves 111 may be provided on the silicon substrate, and IPD capacitors are respectively provided in the plurality of receiving grooves 111. Of course, in practical applications, the substrate 110 may also be a resin substrate, a ceramic substrate, or a glass substrate, etc., and the embodiments of the present disclosure are not limited thereto.

[0035] The receiving groove 111 on the substrate 110 may be formed by etching. Exemplarily, the receiving groove 111 may be implemented through the following steps: applying a photoresist on the first surface of the substrate 110 to form a first photoresist layer; patterning the first photoresist layer; etching the substrate 110 to form the receiving groove 111.

[0036] Among them, the photoresist may be applied on the first surface of the substrate 110 by a photoresist coater so that the photoresist completely covers the first surface of the substrate 110 to form a first photoresist layer. Patterning may be achieved through a mask plate, and holes are provided at positions corresponding to the receiving groove 111 on the mask plate. The mask plate is placed on the side of the first photoresist layer away from the substrate 110, and then exposure is performed to achieve patterning of the first photoresist layer. The portions corresponding to the receiving groove 111 on the patterned first photoresist layer are removed, and the portions on the substrate 110 where the receiving groove 111 is to be formed are exposed to the first photoresist layer. When etching the substrate 110, the receiving groove 111 may be formed on the substrate 110 by dry etching or wet etching.

[0037] The receiving groove 111 may be a round hole, a square hole, or a special-shaped hole, etc. on the substrate 110. And the receiving groove 111 may also be formed by a plurality of holes on the substrate 110. For example, a receiving area is provided on the substrate 110, and a plurality of coaxially arranged annular holes are provided in the receiving area, and the plurality of annular holes form the receiving groove 111. Or a plurality of parallel holes are provided in the receiving area, and the plurality of parallel holes form the receiving groove 111.

[0038] Exemplarily, a receiving area is provided on the substrate 110. A receiving round hole and a receiving annular groove surrounding the receiving round hole are provided in the receiving area. The receiving round hole and the receiving annular groove form a receiving groove 111. Alternatively, a first groove, a second groove, and a third groove are arranged in parallel in the receiving area, and the first groove, the second groove, and the third groove form the receiving groove 111.

[0039] It should be noted that, for the convenience of processing in the embodiments of the present disclosure, the receiving groove 111 may be a recessed structure provided on the substrate 110. When forming the IPD capacitor 120, a support structure may be formed in the receiving groove 111. For example, a support structure is provided between the receiving round hole and the receiving annular groove. That is, the receiving groove 111 is separated into a receiving round hole and a receiving annular groove by the support structure.

[0040] As Figure 5 shown, the IPD capacitor 120 is disposed in the receiving groove 111 on the substrate 110. The IPD capacitor 120 may include a first electrode plate 121, a dielectric layer, and a second electrode plate 123. The first electrode plate 121 may cover the inner wall of the receiving groove 111. The second electrode plate 123 is opposite to the second electrode plate 123, and the dielectric layer is disposed between the first electrode plate 121 and the second electrode plate 123.

[0041] Of course, in practical applications, in order to increase the capacitance value of the IPD capacitor 120, a plurality of capacitors may be provided in the receiving groove 111, and the plurality of capacitors are connected in parallel to increase the capacitance value of the IPD capacitor 120. Exemplarily, four electrode plates may be provided in the receiving groove 111, an insulating dielectric layer is provided between adjacent electrode plates, each two electrode plates form a capacitor, and the two capacitors are connected in parallel.

[0042] Exemplarily, when the receiving groove 111 includes a receiving round hole and a receiving annular groove, the first electrode plate 121 is formed on the inner walls of the receiving round hole and the receiving annular groove, and the portion of the first electrode plate 121 located in the receiving round hole is connected to the portion of the first electrode plate 121 located in the receiving annular groove. That is, the first electrode plate 121 straddles the partition between the receiving round hole and the receiving annular groove. The second electrode plate 123 is disposed opposite to the first electrode plate 121, and a first dielectric layer 122 is provided between the first electrode plate 121 and the second electrode plate 123. The first dielectric layer 122 adheres to the surface of the first electrode plate 121, and the second electrode plate 123 adheres to the side of the first dielectric layer 122 away from the first electrode plate 121. The first electrode plate 121, the first dielectric layer 122, and the second electrode plate 123 form a first capacitor.

[0043] An insulating layer 124 is provided on a side of the second electrode plate 123 away from the first dielectric layer 122. A third electrode plate 125 is provided on a side of the insulating layer 124 away from the second electrode plate 123. A fourth electrode plate 127 is opposite to the third electrode plate 125. A second dielectric layer 126 is provided between the third electrode plate 125 and the fourth electrode plate 127. The third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 form a second capacitor, and the first capacitor and the second capacitor are connected in parallel.

[0044] In the embodiments of the present disclosure, the material of the electrode plate may be a conductive material such as metal, metal oxide, or metal nitride. For example, the material of the electrode plate may be copper, aluminum, silver, titanium nitride, titanium, or tungsten, etc. Among them, the materials of the first electrode plate 121, the second electrode plate 123, the third electrode plate 125, and the fourth electrode plate 127 may be the same or different, and the embodiments of the present disclosure do not make specific limitations on this.

[0045] The material of the dielectric layer may be an insulating material. For example, the material of the dielectric layer may be one or more of alumina, silicon oxide, zirconium oxide, and silicon nitride. The materials of the first dielectric layer 122 and the second dielectric layer 126 may be the same or different, and the embodiments of the present disclosure do not make specific limitations on this.

[0046] When forming the IPD capacitor 120 in the accommodation groove 111, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 may be sequentially formed in the accommodation groove 111 by deposition. For example, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 are sequentially formed in the accommodation groove 111 by physical vapor deposition. Of course, in practical applications, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 may also be formed by printing or spin coating, etc., and the embodiments of the present disclosure are not limited thereto.

[0047] The first wiring board 130 is provided on the first surface of the substrate 110. A first connection wiring 131 is provided in the first wiring board 130, and the first connection wiring 131 is connected to the IPD capacitor 120. The IPD capacitor 120 is embedded in the substrate 110, and the IPD capacitor 120 needs to be connected to the chip. The connection between the IPD capacitor 120 and the chip can be realized through the first connection wiring 131 on the first wiring board 130.

[0048] Among them, the first wiring board 130 may include a first board body and a first connection wiring 131, and the first connection wiring 131 is embedded in the first board body. The material of the first board body may be an organic insulating material, such as polyimide, etc. Or, the material of the first board body may be an inorganic insulating material, such as silicon nitride or silicon oxide, etc. The material of the first connection wiring 131 may be a conductive material such as metal, metal oxide or metal nitride, etc. For example, the material of the first connection wiring 131 may be copper, aluminum, silver, titanium nitride, titanium or tungsten, etc.

[0049] As Figure 2 As shown, the first wiring board 130 may include a first wiring layer 301 and a second wiring layer 302. The first wiring layer 301 is disposed on the first surface of the substrate 110. A first wiring is provided in the first wiring layer 301, and the first wiring is connected to the electrode plate of the IPD capacitor 120; the second wiring layer 302 is disposed on the side of the first wiring layer 301 away from the substrate 110. A second wiring is provided in the second wiring layer 302, and the second wiring is connected to the first wiring.

[0050] The first wiring in the first wiring layer 301 is used to lead out the electrode plate of the IPD capacitor 120, and multiple capacitors in the IPD capacitor 120 can be connected in parallel by using the first wiring in the first wiring layer 301. In the first wiring layer, the first wiring has a contact end, and the contact end is located on the side of the first wiring layer 301 away from the substrate 110. The contact end is used to electrically connect the second wiring in the second wiring layer 302.

[0051] The second wiring in the second wiring layer 302 connects the chip and the contact end in the first wiring layer 301. A pad is provided in the second wiring layer 302. The pad is connected to the second wiring, and the pad is exposed on the side of the second wiring layer 302 away from the first wiring layer 301. The pad is used to connect the chip.

[0052] In the embodiment of the present disclosure, the first wiring layer 301 and the second wiring layer 302 together form the first wiring board 130, and the first wiring and the second wiring form the first connection wiring 131. The materials of the first wiring layer 301 and the second wiring layer 302 may be the same. In the manufacturing process, the first wiring layer 301 and the second wiring layer 302 are formed by two processes. For example, the board body material can be coated on the substrate 110, and the first wiring is formed in the board body material to form the first wiring layer 301. Then, the board body material is coated on the side of the first wiring layer 301 away from the substrate 110, and the second wiring is formed in the board body material.

[0053] A chip slot 112 may be provided on the second surface of the substrate 110. The chip slot 112 is used to accommodate the first chip 210. The first chip 210 may be connected to the IPD capacitor 120 and the second chip 220 provided on the substrate 110.

[0054] Among them, the chip slot 112 on the substrate 110 can be formed by etching. For example, the chip slot 112 can be realized through the following steps: coating a photoresist on the second surface of the substrate 110 to form a second photoresist layer; patterning the second photoresist layer; etching the substrate 110 to form the chip slot 112.

[0055] Among them, the photoresist can be coated on the second surface of the substrate 110 by a photoresist coater so that the photoresist completely covers the second surface of the substrate 110 to form a second photoresist layer. Patterning can be achieved through a mask plate, and holes are provided at positions corresponding to the chip slot 112 on the mask plate. The mask plate is placed on the side of the second photoresist layer away from the substrate 110, and then exposure is performed to pattern the second photoresist layer. The parts corresponding to the chip slot 112 on the patterned second photoresist layer are removed, and the parts on the substrate 110 where the chip slot 112 is to be formed are exposed to the second photoresist layer. When etching the substrate 110, the chip slot 112 can be formed on the substrate 110 by dry etching or wet etching.

[0056] The second wiring board 140 is provided on the second surface of the substrate 110. Second connection wirings are provided in the second wiring board 140, and the second connection wirings are used to connect the first chip 210, and the first surface and the second surface of the substrate 110 face away from each other.

[0057] Among them, the second wiring board 140 can include a second board body and second connection wirings, and the second connection wirings are embedded in the second board body. The material of the second board body can be an organic insulating material, such as polyimide, etc. Or, the material of the second board body can be an inorganic insulating material, such as silicon nitride or silicon oxide, etc. The material of the second connection wirings can be a conductive material such as metal, metal oxide or metal nitride, etc. For example, the material of the second connection wirings can be copper, aluminum, silver, titanium nitride, titanium or tungsten, etc.

[0058] On one side of the second wiring board 140 close to the first chip 210, a plurality of pads can be provided. The plurality of pads can be connected to the second connection wirings and are used to connect the first chip. A metal microsphere array is provided on the side of the second wiring board 140 away from the first chip 210, and the metal microsphere array is used to connect to other devices on the main board.

[0059] As Figure 4 shown, a second chip 220 can be provided on the side of the first wiring board 130 away from the substrate 110, and a first chip 210 is provided in the chip slot 112 on the substrate 110. For example, the first chip 210 can be a SOC chip, and the second chip 220 can be a DRAM chip.

[0060] In an embodiment of the present disclosure, vias 150 may be provided on a substrate 110. The vias 150 connect a first wiring board 130 and a second wiring board 140. The vias 150 may be respectively connected to a first connection trace 131 and a second connection trace to realize electrical connection of devices on both sides of the substrate 110.

[0061] The IPD capacitor 120 is disposed on a first surface of the substrate 110, and the first chip 210 is disposed on a second surface of the substrate 110. Therefore, vias 150 may be provided on the substrate 110 to connect the IPD capacitor 120 and the first chip 210 through the vias 150. Of course, in actual applications, the vias 150 on the substrate 110 may also be used to realize functions such as connection between the first chip 210 and the second chip 220.

[0062] In an embodiment of the present disclosure, power pins may be provided on the substrate 110. The power pins are used to connect to an external power supply and transmit an external power supply signal to the first chip 210 and the second chip 220. The IPD capacitor 120 may be connected to the power pins to denoise the power signal.

[0063] Exemplarily, a first power pin and a second power pin may be provided on the substrate 110. The first power pin and the second power pin are disposed on a second wiring layer 302. The first power pin is used to transmit a power signal to the first chip 210, and the second power pin is used to transmit a power signal to the second chip 220. The second chip 220 is located on the surface of the second wiring layer 302. Therefore, the power signal enters the second chip 220 through the second power pin, the second wiring layer 302, and the pad. The second trace is connected to the IPD capacitor 120 to denoise the power signal input to the second chip 220. The first chip 210 is located on the second surface of the substrate 110. The power signal enters the first chip 210 through the first power pin, the second wiring layer 302, the vias 150, and the second wiring board 140. The second trace in the second wiring layer 302 for connecting the vias 150 may be connected to the IPD capacitor 120 to denoise the power signal entering the first chip 210.

[0064] Of course, in actual applications, the IPD capacitor 120 may also be used to denoise signals other than the power signal. For example, the IPD capacitor 120 may be used to denoise a control signal or a scan signal, etc. The embodiment of the present disclosure is not limited thereto.

[0065] It should be noted that in an embodiment of the present disclosure, a plurality of IPD capacitors and a plurality of vias may be provided on the substrate. For example, a plurality of IPD capacitors are distributed in an array on the substrate, and a plurality of vias are also distributed in an array.

[0066] The semiconductor structure provided by the embodiments of the present disclosure has an IPD capacitor 120 disposed on a substrate 110. The IPD capacitor 120 is embedded in the substrate 110. The IPD capacitor 120 can denoise power signals and improve the stability of the power supply, thereby reducing the power consumption of the chip. Moreover, since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in an electronic device. In addition, the wiring path between the IPD capacitor and the chip is short, so parasitic inductance and parasitic capacitance can be reduced, improving the performance of the IPD capacitor 120.

[0067] The exemplary embodiments of the present disclosure further provide a manufacturing method of a semiconductor structure. As Figure 6 shown, the manufacturing method of the semiconductor structure may include the following steps:

[0068] Step S610, forming a receiving groove on a first surface of the substrate;

[0069] Step S620, forming an IPD capacitor in the receiving groove;

[0070] Step S630, forming a first wiring board on the substrate, and connecting a first connection wiring in the first wiring board to the IPD capacitor.

[0071] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure forms an IPD capacitor 120 on a substrate 110. The IPD capacitor 120 is embedded in the substrate 110. The IPD capacitor 120 can denoise power signals and improve the stability of the power supply, thereby reducing the power consumption of the chip. Moreover, since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in an electronic device. In addition, the wiring path between the IPD capacitor and the chip is short, so parasitic inductance and parasitic capacitance can be reduced, improving the performance of the IPD capacitor 120.

[0072] Further, as Figure 7 shown, the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure may further include:

[0073] Step S640, forming a chip groove on a second surface of the substrate, where the chip groove is used to accommodate a first chip.

[0074] As Figure 8 shown, the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure may further include:

[0075] Step S650, forming a via hole on the substrate, where the via hole is used to connect the first connection wiring in the first wiring board.

[0076] Next, each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure will be described in detail:

[0077] In step S610, a receiving groove 111 is formed on the first surface of the substrate 110.

[0078] Among them, as Figure 10 shown, the substrate 110 may be a silicon substrate 110, and a receiving groove 111 is provided on the silicon substrate 110. The silicon substrate 110 may be obtained by cutting a silicon ingot. The silicon substrate 110 may be a circular substrate 110 or a rectangular substrate 110, etc. Among them, a plurality of receiving grooves 111 may be provided on the silicon substrate 110, and IPD capacitors are respectively provided in the plurality of receiving grooves 111. Of course, in practical applications, the substrate 110 may also be a resin substrate 110, a ceramic substrate 110, or a glass substrate 110, etc., and the embodiments of the present disclosure are not limited thereto.

[0079] The receiving groove 111 on the substrate 110 may be formed by etching. Exemplarily, the receiving groove 111 may be realized through the following steps: coating a photoresist on the first surface of the substrate 110 to form a first photoresist layer; patterning the first photoresist layer; etching the substrate 110 to form the receiving groove 111.

[0080] Among them, the photoresist may be coated on the first surface of the substrate 110 by a photoresist coater so that the photoresist completely covers the first surface of the substrate 110 to form a first photoresist layer. The patterning may be realized through a mask plate, and holes are provided at positions corresponding to the receiving groove 111 on the mask plate. The mask plate is placed on the side of the first photoresist layer away from the substrate 110, and then exposure is performed to realize the patterning of the first photoresist layer. The parts corresponding to the receiving groove 111 on the patterned first photoresist layer are removed, and the part of the substrate 110 where the receiving groove 111 is to be formed is exposed to the first photoresist layer. When etching the substrate 110, the receiving groove 111 may be formed on the substrate 110 by dry etching or wet etching.

[0081] The receiving groove 111 may be a round hole, a square hole, or a special-shaped hole, etc. on the substrate 110. And the receiving groove 111 may also be formed by a plurality of holes on the substrate 110. For example, a receiving area is provided on the substrate 110, and a plurality of coaxially arranged annular holes are provided in the receiving area, and the plurality of annular holes form the receiving groove 111. Or a plurality of parallel holes are provided in the receiving area, and the plurality of parallel holes form the receiving groove 111.

[0082] Exemplarily, a receiving area is provided on the substrate 110, a receiving round hole and a receiving annular groove surrounding the receiving round hole are provided in the receiving area, and the receiving round hole and the receiving annular groove form the receiving groove 111. Or a first groove, a second groove, and a third groove are arranged in parallel in the receiving area, and the first groove, the second groove, and the third groove form the receiving groove 111.

[0083] It should be noted that, for convenience of processing in the embodiments of the present disclosure, the accommodating groove 111 may be a recessed structure provided on the substrate 110. When forming the IPD capacitor 120, a support structure may be formed in the accommodating groove 111. For example, a support structure is provided between the accommodating circular hole and the accommodating annular groove. That is, the accommodating groove 111 is separated into the accommodating circular hole and the accommodating annular groove by the support structure.

[0084] In step S620, the IPD capacitor 120 is formed in the accommodating groove 111.

[0085] Among them, as Figure 11 shown, the IPD capacitor 120 is disposed in the accommodating groove 111 on the substrate 110. The IPD capacitor 120 may include a first electrode plate 121, a dielectric layer, and a second electrode plate 123. The first electrode plate 121 may cover the inner wall of the accommodating groove 111. The second electrode plate 123 is opposite to the second electrode plate 123, and the dielectric layer is disposed between the first electrode plate 121 and the second electrode plate 123.

[0086] Of course, in practical applications, in order to increase the capacitance value of the IPD capacitor 120, a plurality of capacitors may be provided in the accommodating groove 111, and the plurality of capacitors are connected in parallel to increase the capacitance value of the IPD capacitor 120. By way of example, four electrode plates may be provided in the accommodating groove 111, an insulating dielectric layer is provided between adjacent electrode plates, and each two electrode plates form a capacitor, and the two capacitors are connected in parallel.

[0087] By way of example, when the accommodating groove 111 includes an accommodating circular hole and an accommodating annular groove, the first electrode plate 121 is formed on the inner walls of the accommodating circular hole and the accommodating annular groove, and the portion of the first electrode plate 121 located in the accommodating circular hole is connected to the portion of the first electrode plate 121 located in the accommodating annular groove. That is, the first electrode plate 121 straddles the partition between the accommodating circular hole and the accommodating annular groove. The second electrode plate 123 is disposed opposite to the first electrode plate 121, and a first dielectric layer 122 is provided between the first electrode plate 121 and the second electrode plate 123. The first dielectric layer 122 adheres to the surface of the first electrode plate 121, and the second electrode plate 123 adheres to the side of the first dielectric layer 122 away from the first electrode plate 121. The first electrode plate 121, the first dielectric layer 122, and the second electrode plate 123 form a first capacitor.

[0088] An insulating layer 124 is provided on the side of the second electrode plate 123 away from the first dielectric layer 122. A third electrode plate 125 is provided on the side of the insulating layer 124 away from the second electrode plate 123. A fourth electrode plate 127 is opposite to the third electrode plate 125, and a second dielectric layer 126 is provided between the third electrode plate 125 and the fourth electrode plate 127. The third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 form a second capacitor, and the first capacitor and the second capacitor are connected in parallel.

[0089] In the embodiments of the present disclosure, the material of the electrode plate may be a conductive material such as metal, metal oxide, or metal nitride. For example, the material of the electrode plate may be copper, aluminum, silver, titanium nitride, titanium, or tungsten, etc. Among them, the materials of the first electrode plate 121, the second electrode plate 123, the third electrode plate 125, and the fourth electrode plate 127 may be the same or different, and the embodiments of the present disclosure do not make specific limitations in this regard.

[0090] The material of the dielectric layer may be an insulating material. For example, the material of the dielectric layer may be one or more of alumina, silicon oxide, zirconia, and silicon nitride. The materials of the first dielectric layer 122 and the second dielectric layer 126 may be the same or different, and the embodiments of the present disclosure do not make specific limitations in this regard.

[0091] When forming the IPD capacitor 120 in the accommodation groove 111, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 may be sequentially formed in the accommodation groove 111 by deposition. For example, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 are sequentially formed in the accommodation groove 111 by physical vapor deposition. Of course, in practical applications, the first electrode plate 121, the first dielectric layer 122, the second electrode plate 123, the insulating layer 124, the third electrode plate 125, the second dielectric layer 126, and the fourth electrode plate 127 may also be formed by printing or spin coating, etc., and the embodiments of the present disclosure are not limited thereto.

[0092] In step S630. A first wiring board 130 is formed on the substrate 110, and the first connection wiring 131 in the first wiring board 130 is connected to the IPD capacitor 120.

[0093] Among them, as Figure 12 shown, the first wiring board 130 is disposed on the first surface of the substrate 110. The first connection wiring 131 is provided in the first wiring board 130, and the first connection wiring 131 is connected to the IPD capacitor 120. The IPD capacitor 120 is embedded in the substrate 110, and the IPD capacitor 120 needs to be connected to the chip. The connection between the IPD capacitor 120 and the chip can be realized through the first connection wiring 131 on the first wiring board 130.

[0094] Among them, the first wiring board 130 may include a first board body and a first connection wiring 131, and the first connection wiring 131 is embedded in the first board body. The material of the first board body may be an organic insulating material, such as polyimide, etc. Alternatively, the material of the first board body may be an inorganic insulating material, such as silicon nitride or silicon oxide, etc. The material of the first connection wiring 131 may be a conductive material such as metal, metal oxide or metal nitride. For example, the material of the first connection wiring 131 may be copper, aluminum, silver, titanium nitride, titanium or tungsten, etc.

[0095] The first wiring board 130 may include a first wiring layer 301 and a second wiring layer 302. The first wiring layer 301 is disposed on the first surface of the substrate 110, and a first wiring is provided in the first wiring layer 301. The first wiring is connected to the electrode plate of the IPD capacitor 120. The second wiring layer 302 is disposed on the side of the first wiring layer 301 away from the substrate 110, and a second wiring is provided in the second wiring layer 302. The second wiring is connected to the first wiring.

[0096] The first wiring in the first wiring layer 301 is used to lead out the electrode plate of the IPD capacitor 120, and multiple capacitors in the IPD capacitor 120 can be connected in parallel by using the first wiring in the first wiring layer 301. In the first wiring layer, the first wiring has a contact end, and the contact end is located on the side of the first wiring layer 301 away from the substrate 110. The contact end is used to electrically connect the second wiring in the second wiring layer 302.

[0097] The second wiring in the second wiring layer 302 connects the chip and the contact end in the first wiring layer 301. A pad is provided in the second wiring layer 302. The pad is connected to the second wiring, and the pad is exposed on the side of the second wiring layer 302 away from the first wiring layer 301. The pad is used to connect the chip.

[0098] In the embodiment of the present disclosure, the first wiring layer 301 and the second wiring layer 302 together form the first wiring board 130, and the first wiring and the second wiring form the first connection wiring 131. The materials of the first wiring layer 301 and the second wiring layer 302 may be the same. In the manufacturing process, the first wiring layer 301 and the second wiring layer 302 are formed by two processes. For example, the board body material can be coated on the substrate 110, and the first wiring is formed in the board body material to form the first wiring layer 301. Then, the board body material is coated on the side of the first wiring layer 301 away from the substrate 110, and the second wiring is formed in the board body material.

[0099] In step S640, a chip slot 112 is formed on the second surface of the substrate 110, and the chip slot 112 is used to accommodate the first chip 210.

[0100] Among them, as Figure 13As shown, the chip slot 112 on the substrate 110 can be formed by etching. Exemplarily, the chip slot 112 can be achieved through the following steps: Coating a photoresist on the second surface of the substrate 110 to form a second photoresist layer; Patterning the second photoresist layer; Etching the substrate 110 to form the chip slot 112.

[0101] Among them, the photoresist can be coated on the second surface of the substrate 110 by a photoresist coater, so that the photoresist completely covers the second surface of the substrate 110 to form a second photoresist layer. The patterning can be achieved through a mask plate, and holes are provided at positions corresponding to the chip slot 112 on the mask plate. The mask plate is placed on the side of the second photoresist layer away from the substrate 110, and then exposure is performed to achieve the patterning of the second photoresist layer. The parts corresponding to the chip slot 112 on the patterned second photoresist layer are removed, and the parts on the substrate 110 where the chip slot 112 is to be formed are exposed to the second photoresist layer. When etching the substrate 110, the chip slot 112 can be formed on the substrate 110 by dry etching or wet etching.

[0102] In step S650, a via hole 150 is formed on the substrate 110, and the via hole 150 is used to connect the first connection trace 131 in the first trace board 130.

[0103] Among them, step S650 is executed before step S620, and the order of step S610 and step S650 can be interchanged. For example, as Figure 9 shown, the via hole 150 can be formed on the substrate 110, and then the receiving slot 111 is formed. Or the receiving slot 111 can be formed on the substrate 110, and then the via hole 150 is formed. The embodiments of the present disclosure do not make specific limitations on this.

[0104] The via hole 150 on the substrate 110 can be achieved in the following way: Etching a through hole on the substrate 110, and then forming a conductive material in the through hole by deposition or other means. Exemplarily, the via hole 150 can be achieved through the following steps: Coating a photoresist on the first surface of the substrate 110 to form a third photoresist layer; Patterning the third photoresist layer; Etching the substrate 110 to form a through hole; Filling a conductive material in the through hole to form the via hole 150.

[0105] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure forms an IPD capacitor 120 on a substrate 110. The IPD capacitor 120 is embedded in the substrate 110. Through the IPD capacitor 120, power signals can be denoised and the stability of the power supply can be improved, thereby reducing the power consumption of the chip. And since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in an electronic device. Also, the routing path between the IPD capacitor and the chip is short, so parasitic inductance and parasitic capacitance can be reduced, improving the performance of the IPD capacitor 120.

[0106] Furthermore, the embodiments of the present disclosure also provide a chip packaging structure 10, and the chip packaging structure 10 includes the above-mentioned semiconductor structure.

[0107] Among them, the semiconductor structure includes: a substrate 110, an IPD capacitor 120, and a first wiring board 130. The substrate 110 is used to carry a chip, and a receiving groove 111 is provided on the first surface of the substrate 110; the IPD capacitor 120 is disposed in the receiving groove 111; the first wiring board 130 is disposed on the first surface of the substrate 110, and a first connection wiring 131 is provided in the first wiring board 130, and the first connection wiring 131 is connected to the IPD capacitor 120.

[0108] In the chip packaging structure 10 provided by the embodiments of the present disclosure, an IPD capacitor 120 is provided on the substrate 110. The IPD capacitor 120 is embedded in the substrate 110. Through the IPD capacitor 120, power signals can be denoised and the stability of the power supply can be improved, thereby reducing the power consumption of the chip. And since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in an electronic device. Also, the routing path between the IPD capacitor and the chip is short, so parasitic inductance and parasitic capacitance can be reduced, improving the performance of the IPD capacitor 120.

[0109] Furthermore, the chip packaging structure 10 provided by the embodiments of the present disclosure may further include: a first chip 210 and a second chip 220. The first chip 210 is disposed in a chip slot 112, and the chip slot 112 is disposed on the second surface of the substrate 110; the second chip 220 is disposed on a surface of the first wiring board 130 away from the substrate 110.

[0110] Exemplarily, the first chip 210 may be a SOC chip, and the second chip 220 may be a DRAM chip. Of course, in actual applications, the first chip 210 and the second chip 220 may also be other chips, and the embodiments of the present disclosure are not limited thereto.

[0111] It should be noted that the specific implementation manners of the semiconductor structure in the embodiments of the present disclosure have been described in detail in the above embodiments and will not be repeated here.

[0112] Furthermore, an embodiment of the present disclosure also provides an electronic device, which includes the above-mentioned chip packaging structure 10.

[0113] The electronic device provided in the embodiments of the present disclosure may be a mobile phone, a tablet computer, an e-reader, a smart watch, smart glasses, a head-mounted device, a laptop computer, an all-in-one desktop computer, a car computer or a navigator, etc.

[0114] The electronic device provided by the embodiment of the present disclosure is described below by taking a mobile phone as an example:

[0115] The electronic device provided by the embodiment of the present disclosure may further include: a display screen 20, a frame 30, a back cover 40, a battery 50 and a mainboard 60. The display screen 20 is disposed on the front side of the frame 30 and connected to the frame 30, and the back cover 40 is disposed on the rear side of the frame 30 and connected to the frame 30. The display screen 20, the frame 30 and the back cover 40 form a receiving cavity, and the mainboard 60 and the battery 50 are disposed in the receiving cavity.

[0116] The display screen 20 is used to display images and text information, and the display screen 20 can be an OLED display screen 20 or an LCD display screen 20. The display screen 20 can be a flat display screen 20 or a curved display screen 20. The display screen 20 can be provided with a hole-punch area or an under-screen camera area, and the hole-punch area and the under-screen display area are used to allow external light to enter under the display screen 20. A front camera can be provided on the back of the display screen 20, and light enters the front camera from the hole-punch area or the under-screen camera area. A fingerprint recognition area can also be provided on the display screen 20, and a fingerprint recognition sensor is provided at a position corresponding to the fingerprint recognition area.

[0117] The rear cover 40 is used to form the rear profile of the electronic device. A rear camera area may be provided on the rear cover 40, and the rear camera area is used to arrange devices such as a rear camera and a flash. The rear camera area may be covered with a lens decoration, which is used to seal the camera hole on the rear camera area and can also increase the arrangement space of the lens.

[0118] The battery 50 is disposed in the accommodating cavity, and the battery 50 is used to provide electrical energy to various components inside the electronic device. The battery 50 may be connected to a charging circuit and a discharging circuit, the charging circuit is connected to the battery 50 and the charging interface, and the charging interface is used to connect to the adapter. The discharging circuit is connected to the power management circuit, and the discharging circuit transmits the electrical energy in the battery 50 to the power management circuit.

[0119] The mainboard 60 can be connected to the frame 30 or the back cover 40. The mainboard 60 is used to arrange electrical components such as sensor processors. The chip packaging structure 10 provided in the embodiment of the present disclosure is arranged on the mainboard 60 and connected to the power management circuit on the mainboard 60.

[0120] The electronic device provided by the embodiments of the present disclosure includes a chip packaging structure 10. In the chip packaging structure 10, an IPD capacitor 120 is disposed on a substrate 110. The IPD capacitor 120 is embedded in the substrate 110. The IPD capacitor 120 can denoise a power signal and improve the stability of the power supply, thereby reducing the power consumption of the chip. Moreover, since the IPD capacitor is embedded in the substrate 110, the size of the packaged chip in the stacking direction can be reduced, which is beneficial to reducing the difficulty of arranging chips in the electronic device. In addition, the routing path between the IPD capacitor and the chip is short, so that parasitic inductance and parasitic capacitance can be reduced, and the performance of the IPD capacitor 120 can be improved.

[0121] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A semiconductor structure, characterized in that, the semiconductor structure includes: a substrate for carrying a chip, and a receiving groove is provided on a first surface of the substrate; an IPD capacitor disposed in the receiving groove; a first wiring board disposed on the first surface of the substrate, a first connection wiring is provided in the first wiring board, and the first connection wiring is connected to the IPD capacitor; a chip groove is provided on a second surface of the substrate for receiving a first chip, and the semiconductor structure further includes: a second wiring board disposed on the second surface of the substrate and covering the first chip, a second connection wiring is provided in the second wiring board for connecting the first chip, and the first surface and the second surface of the substrate face away from each other; a second chip is provided on a side of the first wiring board away from the substrate; the first connection wiring in the first wiring board is connected to the second chip.

2. The semiconductor structure according to claim 1, characterized in that, a via hole is provided on the substrate, and the via hole connects the first wiring board and the second wiring board respectively.

3. The semiconductor structure according to claim 1, characterized in that, the first wiring board includes: a first wiring layer disposed on the first surface of the substrate, a first wiring is provided in the first wiring layer, and the first wiring is connected to an electrode plate of the IPD capacitor; a second wiring layer disposed on a side of the first wiring layer away from the substrate, a second wiring is provided in the second wiring layer, and the second wiring is connected to the first wiring.

4. The semiconductor structure according to claim 3, characterized in that, a pad is provided in the second wiring layer, the pad is connected to the second wiring, and the pad is exposed on a side of the second wiring layer away from the first wiring layer, and the pad is used for connecting a chip.

5. The semiconductor structure according to claim 1, characterized in that, the IPD capacitor is connected to a power supply and a chip, the IPD capacitor is used for denoising a power signal, and the chip is disposed on the substrate.

6. A manufacturing method of a semiconductor structure for manufacturing the semiconductor structure according to claim 1, characterized in that, the manufacturing method includes: forming a receiving groove on a first surface of the substrate; forming an IPD capacitor in the receiving groove; forming a first wiring board on the substrate so that a first connection wiring in the first wiring board is connected to the IPD capacitor; the manufacturing method further includes: forming a chip groove on the second surface of the substrate for receiving a first chip, and the first surface and the second surface of the substrate face away from each other.

7. The manufacturing method according to claim 6, characterized in that, the manufacturing method further includes: forming a via hole on the substrate, and the via hole is used for connecting a first connection wiring in the first wiring board.

8. A chip packaging structure, characterized in that, the chip packaging structure includes the semiconductor structure according to any one of claims 1-5.

9. The chip packaging structure according to claim 8, characterized in that, The chip package structure further includes: A first chip, which is disposed in a chip slot, and the chip slot is disposed on the second surface of the substrate; A second chip, which is disposed on a surface of the first wiring board away from the substrate.

10. An electronic device, characterized in that, The electronic device includes the chip package structure according to claim 8 or 9.

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