Semiconductor memory structure and method of fabrication

Abstract

The application discloses a semiconductor memory structure and a preparation method thereof, which can reduce the probability of electrical damage of the semiconductor memory structure caused by the charge of the bit line gate. The preparation method of the semiconductor memory structure comprises the following steps: providing a substrate, a plurality of contact windows are formed on the surface of the substrate, a stack structure is formed in the contact window, and the upper surface of the stack structure is higher than the upper surface of the substrate; performing a nitriding treatment on the sidewall surface of the stack structure; forming a first sidewall on the sidewall surface of the stack structure; and performing an oxidation treatment on the first sidewall.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor memory structure, in particular to a semiconductor memory structure and a preparation method thereof. BACKGROUND

[0002] In a semiconductor memory structure, there is a bit line structure and a bit line gate, the bit line structure connects the bit line gates in the same row in series to realize the storage function. In the prior art, when the semiconductor memory structure is used, the sidewall surface of the bit line gate is insulated by an insulating layer, but the insulating layer formed in the prior art is prone to uniformity problems, and a very thick insulating layer needs to be formed to achieve a certain insulation effect, so a new semiconductor memory structure is needed to overcome the above problems. SUMMARY

[0003] Therefore, the present application provides a semiconductor memory structure and a preparation method thereof, which can improve the uniformity of the insulating layer of the bit line gate and can thin the thickness of the insulating layer.

[0004] The present application provides a preparation method of a semiconductor memory structure, comprising the following steps: providing a substrate, a plurality of contact windows are formed on the surface of the substrate, a stack structure is formed in the contact window, and the upper surface of the stack structure is higher than the upper surface of the substrate; performing nitridation treatment on the sidewall surface of the stack structure; forming a first side wall on the sidewall surface of the stack structure; and performing oxidation treatment on the first side wall.

[0005] Optionally, before the nitridation treatment on the sidewall surface of the stack structure, at least the following step is included: forming a second side wall on the sidewall surface of the stack structure.

[0006] Optionally, the method for forming a second side wall on the sidewall surface of the stack structure at least includes the following step: forming at least one sub-side wall on the sidewall surface of the stack structure.

[0007] Optionally, the method for nitridation treatment on the sidewall surface of the stack structure at least includes the following step: before forming at least one sub-side wall on the sidewall surface of the stack structure, performing the nitridation treatment on the surface of the stack structure.

[0008] Optionally, the method for nitridation treatment on the sidewall surface of the stack structure at least includes the following step: performing nitridation treatment on the outermost sub-side wall.

[0009] Optionally, the sub-side wall comprises at least one of a silicon layer and a silicon oxide layer.

[0010] Optionally, the first side wall is prepared by a selective epitaxial growth method.

[0011] Optionally, the nitridation process includes a plasma nitridation process, and a depth of the plasma nitridation process is 0.5nm-2nm.

[0012] Optionally, a working temperature during the plasma nitridation process is 500-600℃.

[0013] Optionally, the first sidewall includes a silicon nitride layer.

[0014] The present application provides a semiconductor memory structure, including: a substrate; a contact window on a surface of the substrate, the contact window exposing an inside of the substrate; a stack structure in the contact window and protruding from a top surface of the substrate; a second sidewall on a sidewall surface of the stack structure, the second sidewall including at least: a first sub-sidewall on the sidewall surface of the stack structure; a nitrided sub-sidewall on a surface of the first sub-sidewall, the nitrided sub-sidewall being obtained by nitridation of the first sub-sidewall; and a first sidewall on a surface of the nitrided sub-sidewall, the first sidewall including at least: a third sub-sidewall on a surface of the nitrided sub-sidewall; and a fourth sub-sidewall on a surface of the third sub-sidewall, the fourth sub-sidewall being obtained by oxidation of the third sub-sidewall.

[0015] Optionally, the first sub-sidewall and the third sub-sidewall are made of the same material.

[0016] Optionally, the nitrided sub-sidewall is partially discontinuous.

[0017] Optionally, a thickness of the nitrided sub-sidewall is 1 / 5-1 / 3 of a thickness of the first sub-sidewall.

[0018] Optionally, the substrate has a plurality of isolation structures and a plurality of active regions formed therein, and each active region is separated by the isolation structures.

[0019] Optionally, the stack structure, the first sidewall and the second sidewall are formed above the isolation structures; and / or: the first sidewall and the second sidewall are deeper in the inside of the isolation structures as they are closer to edges of the isolation structures.

[0020] Optionally, the first sub-sidewall includes at least one of a silicon layer and a silicon nitride layer, and the third sub-sidewall includes a silicon nitride layer.

[0021] Optionally, the first sidewall is partially above the isolation structures and partially above the active regions.

[0022] Optionally, the second side wall further comprises a second sub-side wall formed on a sidewall surface of the first sub-side wall, and the nitrided sub-side wall is formed on a surface of the second sub-side wall, and the second sub-side wall is partially above the isolation structure and partially above the active region.

[0023] The semiconductor memory structure and the preparation method thereof can at least enhance the insulation strength of the first side wall, and when the semiconductor memory structure is used, the charge change in the stack structure can be isolated by the first side wall, so that the breakdown of the semiconductor memory structure caused by the escape of the charge can be effectively prevented, and the possibility of electrical damage can be reduced. In addition, the nitriding treatment of the sidewall surface of the stack structure can improve the uniformity of the film layer subsequently formed on the sidewall surface of the stack structure, and can reduce the required thickness of the first side wall, and has sufficient charge blocking function. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 The preparation method of the semiconductor memory structure in an embodiment of the present application is shown in the step flow chart.

[0026] Figures 2 to 5 The structure of the semiconductor memory structure corresponding to each step of the preparation method of the semiconductor memory structure in an embodiment of the present application is shown in the structure diagram.

[0027] Figure 6 The structure of the semiconductor memory structure in an embodiment of the present application is shown in the structure diagram.

[0028] Figures 7 to 10 The structure of the semiconductor memory structure corresponding to each step of the preparation method of the semiconductor memory structure in another embodiment of the present application is shown in the structure diagram.

[0029] Figure 11 The structure of the semiconductor memory structure in an embodiment of the present application is shown in the structure diagram. DETAILED DESCRIPTION

[0030] The semiconductor memory structure and the preparation method thereof will be further described below in combination with the drawings and embodiments.

[0031] Please refer to Figures 1 to 5wherein Figure 1 is a schematic diagram of a step flow of a method of fabricating a semiconductor memory structure in an embodiment of the present application, Figures 2 to 5 is a schematic diagram of a structure of a semiconductor memory structure corresponding to each step of a method of fabricating a semiconductor memory structure in an embodiment of the present application.

[0032] In this embodiment, the method of fabricating a semiconductor memory structure includes the following steps: step S1 : providing a substrate 101, the substrate 101 having a plurality of contact windows formed on a surface thereof, a stack structure 132a being formed in each of the contact windows, and an upper surface of the stack structure 132a being higher than an upper surface of the substrate 101 ; step S2: performing a nitridation process on a sidewall surface of the stack structure 132a; step S3: forming a first sidewall 161 on the sidewall surface of the stack structure 132a; and step S4: performing an oxidation process on the first sidewall 161.

[0033] In this embodiment, the method of fabricating a semiconductor memory structure performs an oxidation process on the first sidewall of the sidewall surface of the stack structure 132a, thereby at least enhancing the insulation strength of the first sidewall. When the semiconductor memory structure is used, a change in electric charge in the stack structure 132a can be isolated by the first sidewall 161, thereby effectively preventing breakdown of the semiconductor memory structure caused by escape of electric charge, and reducing the likelihood of occurrence of electrical damage. Furthermore, the nitridation process on the sidewall surface of the stack structure can improve uniformity of a film layer subsequently formed on the sidewall surface of the stack structure 132a, and can reduce a required thickness of the first sidewall while having sufficient electric charge blocking function.

[0034] Referring to Figure 2 The substrate 101 is provided, and includes a semiconductor base. The semiconductor base can include silicon (Si), such as crystalline Si, polysilicon, or amorphous Si. In some embodiments, the semiconductor base can include a semiconductor material, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0035] In some embodiments, a conductive region, such as a well doped with impurities, or other structure doped with impurities, can be formed in the substrate 101.

[0036] The substrate 101 is provided with an isolation structure 102, which divides the substrate 101 into a plurality of active regions 1021, and the active regions 1021 can be arranged at equal intervals. The isolation structure 102 can include a shallow trench isolation structure (STI). When the shallow trench isolation structure is formed, the surface of the substrate 101 is etched to form a shallow trench, and then an insulating material is filled in the shallow trench to form the isolation structure 102. The insulating material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and other insulating dielectric materials.

[0037] The active region 1021 can have a regular shape, for example, a long strip shape, and be arranged in a regular arrangement. The active region 1021 is provided with a gate structure.

[0038] The substrate 101 is also provided with word lines and bit lines. The word lines intersect the active regions 1021, the bit lines are distributed perpendicular to the word lines, and the bit lines intersect the active regions 1021. The gate structure is located at the intersection of the bit line and the active region 1021, and is connected to the bit line. The bit line is partially located on the gate structure and partially located on the surface of other regions of the substrate 101.

[0039] In some embodiments, the stack structure 132a includes a bit line structure. In Figure 2 In the illustrated embodiment, the bit line structure includes at least a metal layer 151, and the metal layer 151 includes a single layer of conductive metal material or multiple layers of conductive metal material.

[0040] In Figure 3 In the illustrated embodiment, the metal layer 151 includes only a tungsten layer. In fact, in other embodiments, the metal layer 151 can further include a titanium nitride layer, a copper layer, an aluminum layer, and the like. In some embodiments, the metal layer 151 includes a titanium nitride layer and a tungsten layer stacked in a direction perpendicular to the upper surface of the substrate 101.

[0041] In Figure 3 In the illustrated embodiment, the bit line structure further includes a pad 130 disposed below the metal layer 151. The pad 130 includes at least one of an amorphous silicon layer and a phosphorus-doped silicon layer. In fact, in other embodiments, the specific material of the pad 130 can be provided as needed.

[0042] Please refer to Figure 6 , which is a schematic diagram of the structure of a semiconductor memory junction in another embodiment of the present application.

[0043] In this embodiment, the stack structure 132b can further include, at other positions of the semiconductor memory structure, a first insulating layer 103, a second insulating layer 104, and a third insulating layer 105, which are sequentially arranged upward along the surface of the substrate 101 below the metal layer 151, and a first conductive layer 106.

[0044] The materials of the first insulating layer 103 and the third insulating layer 105 can include insulating materials such as silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxynitride, but are not limited thereto. The first insulating layer 103 and the third insulating layer 105 can be a single-layer structure or a multi-layer structure.

[0045] The material of the second insulating layer 104 can also include insulating materials such as silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxynitride, but is not limited thereto. The material of the second insulating layer 104 is different from the materials of the first insulating layer 103 and the third insulating layer 105, and is used as an etching stop layer in the subsequent process, thereby having different etching selectivity from the first insulating layer 103 and the third insulating layer 105.

[0046] In some embodiments, after the sidewall surface of the stack structure 132a is subjected to a nitridation process, a nitrided layer 170 is formed on the sidewall surface of the stack structure 132a. The nitrided layer 170 is denser than the sidewall surface of the stack structure 132a without the nitridation process, and has higher smoothness and uniformity. Therefore, the first sidewall 161 formed based on the surface of the nitrided layer 170 has better uniformity, and the corresponding structure is as shown in Figure 4 .

[0047] In some embodiments, the first sidewall 161 includes a silicon nitride layer. In fact, the specific material of the first sidewall 161 can be set as needed, and materials that have insulating properties and can be subjected to oxidation treatment are preferred.

[0048] In some embodiments, the first sidewall 161 is prepared by a selective epitaxial growth method. The selective epitaxial growth method can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The specific method of the selective epitaxial growth can be selected as needed by those skilled in the art.

[0049] In some embodiments, after the first sidewall 161 is subjected to an oxidation process, a corresponding semiconductor memory structure or Figure 5 a corresponding semiconductor memory structure is obtained. Figure 10 Figure 5 and Figure 10 ​In the embodiment shown, the first sidewall 161 is formed with an oxide layer 162 formed by oxidation, which can at least enhance the insulation strength of the first sidewall 161. In use of the semiconductor memory structure, the charge variation in the stack structure 132a can be isolated by the first sidewall 161, thus effectively preventing the semiconductor memory structure from breakdown caused by charge escape, and reducing the possibility of electrical damage.

[0050] In some embodiments, the oxidation process includes thermal oxidation, i.e. placing the semiconductor memory structure in a high-temperature environment in an oxygen atmosphere to achieve surface oxidation of the first sidewall 161. The specific processing mode of the oxidation process can also be set as required.

[0051] In some embodiments, before the sidewall surface of the stack structure 132a is subjected to the nitridation process, at least the following step is included: forming a second sidewall 166 on the sidewall surface of the stack structure 132a. For details, please refer to Figure 7 、 Figure 8 .

[0052] In the embodiments shown in Figure 7 、 Figure 8 , the second sidewall 166 can include a plurality of sub-sidewalls, thus facilitating individual processing of single-layer sub-sidewalls as required by the user. In some embodiments, the method of forming a second sidewall 166 on the sidewall surface of the stack structure 132a at least includes the following step: forming at least one sub-sidewall on the sidewall surface of the stack structure 132a.

[0053] In the embodiments shown in Figure 7 、 Figure 8 , the second sidewall 166 includes two sub-sidewalls, i.e. a first sub-sidewall 164 and a second sub-sidewall 163. In some embodiments, the sub-sidewall includes at least one of a silicon layer and a silicon oxide layer. The sub-sidewall should be made of a material layer with insulating properties. In some other embodiments, SiNx, SiOx, SiONx, etc. can also be selected for the preparation of the sub-sidewall.

[0054] In some embodiments, the method of nitriding the sidewall surface of the stack structure 132a at least includes the following step: before at least one sub-sidewall is formed on the sidewall surface of the stack structure 132a, the surface of the stack structure 132a is subjected to the nitridation process. As can be seen in the embodiments shown in Figure 7 、 Figure 8 , the surface of the stack structure 132a is subjected to the nitridation process before the first sub-sidewall and the second sub-sidewall are formed.

[0055] Therefore, the sub-sidewall formed on the surface of the stack structure 132a can be formed on a uniform nitride surface, thereby having better uniformity.

[0056] In some embodiments, the sidewall surface of the stack structure 132a is the surface of the second sidewall 166, and the first sidewall 161 is formed on the surface of the second sidewall 166. Therefore, before the first sidewall 161 is formed, the surface of the second sidewall 166 needs to be subjected to a nitridation process to obtain a second sidewall 166 surface with better smoothness, uniformity and compactness, thereby forming a first sidewall 161 with higher uniformity.

[0057] In some embodiments, the method of nitriding the sidewall surface of the stack structure 132a at least includes the following step: nitriding the outermost sub-sidewall to at least enhance the smoothness of the outermost sub-sidewall, so that the first sidewall 161 formed on the surface of the outermost sub-sidewall has better uniformity.

[0058] In Figure 7 , Figure 8 In the embodiment shown in FIG. 7, the second sidewall 166 includes two sub-sidewalls, and the outer second sub-sidewall is subjected to a nitridation process to obtain a nitrided sub-sidewall 167. The nitrided sub-sidewall 167 is located on the surface of the second sub-sidewall and is formed by nitriding the outermost surface of the second sub-sidewall. The nitrided sub-sidewall 167 can enhance the smoothness of the second sub-sidewall, so that the first sidewall 161 formed on the surface of the outermost first sub-sidewall has better uniformity.

[0059] In some embodiments, the second sidewall 166 includes a first sub-sidewall, and the first sub-sidewall is subjected to a nitridation process to obtain a nitrided sub-sidewall 167. The nitrided sub-sidewall 167 can enhance the smoothness of the outermost sub-sidewall, so that the first sidewall 161 formed on the surface of the outermost first sub-sidewall has better uniformity.

[0060] Please refer to Figure 9 , after the first sidewall 161 is formed on the surface of the nitrided sub-sidewall 167, a structure diagram of the semiconductor memory structure is shown in Figure 8 .

[0061] In one embodiment, the first sidewall 161 is subjected to an oxidation process to form a semiconductor memory structure as shown in Figure 10 .

[0062] In some embodiments, since the depth that can be achieved by nitridation is related to temperature, pressure and the like, in some embodiments, to reduce the difficulty of nitridation and lower the requirements for temperature and pressure during the nitridation process, only the outermost sub-sidewall can be subjected to a nitridation process.

[0063] The nitriding treatment refers to a chemical heat treatment process of making nitrogen atoms penetrate into a target object in a certain medium at a certain temperature. The target object after the nitriding treatment has at least a surface with excellent wear resistance, fatigue resistance, corrosion resistance and high temperature resistance. When the target object is an insulating object, the nitriding treatment can further enhance the insulation strength of the target object.

[0064] In some embodiments, the nitriding treatment includes a plasma nitriding treatment with a nitriding depth of 0.5nm-2nm. It is found that when the thickness of the nitrided surface is 0.5nm-2nm, the nitrided surface can have better insulation performance.

[0065] In some embodiments, the plasma nitriding treatment includes using a nitrogen-containing plasma to bombard the sidewall surface of the stack structure 132a.

[0066] In some embodiments, the working temperature during the plasma nitriding treatment is 500-600℃. It is found that when the working temperature is 500-600℃, better nitriding effect can be achieved, and excessive energy consumption can be avoided. In fact, the working temperature can also be set as needed.

[0067] In fact, a specific nitriding method can also be selected as needed, such as a thermal nitriding method or a plasma anodic nitriding method.

[0068] In some other embodiments, the nitriding treatment also includes a nitriding treatment, and the nitriding depth is related to the thickness of the finally formed nitrided surface. Generally, the nitriding depth is 0.5nm-2nm, so as to form a nitrided surface with a production thickness of 0.5nm-2nm on the sidewall surface of the stack structure.

[0069] In some embodiments, before the sidewall surface of the stack structure 132a is subjected to the nitriding treatment, the following step is further included: pre-cleaning the stack structure 132a. The pre-cleaning includes at least one of a dry cleaning method and a wet cleaning method, so as to remove particulate impurities and the like on the surface of the stack structure 132a, and reduce the influence of the particulate impurities and the like on the subsequent processing results.

[0070] In a second aspect, the present application also provides a semiconductor memory structure.

[0071] Please refer to Figure 11In this embodiment, the semiconductor memory structure includes: a substrate 101; a contact window on the surface of the substrate 101, the contact window exposes the inside of the substrate 101; a stack structure 132a in the contact window and protruding from the upper surface of the substrate 101; a second side wall 166 on the sidewall surface of the stack structure 132a, the second side wall 166 at least includes: a first sub-side wall 164 on the sidewall surface of the stack structure 132a; a nitrided sub-side wall 167 on the surface of the first sub-side wall 164, and the nitrided sub-side wall 167 is obtained by nitriding the first sub-side wall 164; a first side wall 161 on the surface of the second sub-side wall 163, and the first side wall 161 at least includes: a third sub-side wall on the surface of the second sub-side wall 163; a fourth sub-side wall corresponding to the oxide layer 162 on the surface of the third sub-side wall, and the fourth sub-side wall is obtained by oxidizing the third sub-side wall.

[0072] In this embodiment, the semiconductor memory structure performs oxidation treatment on the first side wall of the sidewall surface of the stack structure 132a, thereby at least enhancing the insulation strength of the first side wall. When the semiconductor memory structure is used, the charge change in the stack structure 132a can be isolated by the first side wall 161, thereby effectively preventing the semiconductor memory structure from being broken down due to charge escape and reducing the possibility of electrical damage.

[0073] In this embodiment, the third sub-side wall corresponds to the region of the first side wall 161 that is not subjected to oxidation treatment. The second side wall 166 includes the first sub-side wall 164, and after the first sub-side wall 164 is subjected to nitriding treatment, the nitrided sub-side wall 167 is obtained, which can enhance the smoothness and uniformity of the outermost surface of the first sub-side wall 164, so that the first side wall 161 formed on the surface of the first sub-side wall 164 in the outermost layer has better uniformity.

[0074] In some embodiments, the substrate 101 has a plurality of isolation structures 102 and a plurality of active regions formed therein, and each active region is separated by the isolation structure 102.

[0075] In some embodiments, the stack structure and the first side wall 161 and the second side wall are formed above the isolation structure 102; and / or: the closer the first side wall 161 and the second side wall are to the edge of the isolation structure 102, the deeper the bottom extends into the inside of the isolation structure 102.

[0076] In some embodiments, the first sub-sidewall 164 and the third sub-sidewall are made of the same material. In some embodiments, the first sub-sidewall 164 and the third sub-sidewall are made of silicon nitride.

[0077] In some embodiments, the nitrided sub-sidewall 167 is partially discontinuous to achieve the effect of protecting the sidewall without causing excessive parasitic capacitance value increase.

[0078] In some embodiments, the thickness of the nitrided sub-sidewall 167 is one fifth to one third of the thickness of the first sub-sidewall 164, so as to ensure that the total thickness of the first sidewall 161 is within a reasonable range and to meet the needs of subsequent nitridation processing.

[0079] In some embodiments, the first sub-sidewall 164 includes at least one of a silicon layer and a silicon nitride layer, and the third sub-sidewall includes a silicon nitride layer.

[0080] In some embodiments, the first sidewall 161 is partially located above the isolation structure and partially located above the active region. This is because the periphery of the first sidewall 161 also forms a metal plug, and forming half of the first sidewall 161 above the active region and half of the first sidewall 161 above the active region can make the stack structure have better insulation with respect to the metal plug.

[0081] In some embodiments, the second sidewall further includes a second sub-sidewall formed on the sidewall surface of the first sub-sidewall 164, and the nitrided sub-sidewall 167 is formed on the surface of the second sub-sidewall, and the second sub-sidewall is partially located above the isolation structure and partially located above the active region.

[0082] The above description is only some embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method for fabricating a semiconductor memory structure, characterized in that, Includes the following steps: A substrate is provided, wherein a plurality of contact windows are formed on the surface of the substrate, a stacked structure is formed within the contact windows, and the upper surface of the stacked structure is higher than the upper surface of the substrate, the stacked structure including a metal layer and a pad located below the metal layer; The metal layer and the sidewall surfaces of the gasket are subjected to nitriding treatment; A first sidewall is formed on the sidewall surface of the stacked structure; The first sidewall is subjected to oxidation treatment.

2. The preparation method according to claim 1, characterized in that, Before nitriding the metal layer and the sidewall surfaces of the gasket, at least the following steps are included: A second sidewall is formed on the sidewall surface of the stacked structure.

3. The preparation method according to claim 2, characterized in that, The method for forming a second sidewall on the sidewall surface of the stacked structure includes at least the following steps: At least one sub-sidewall is formed on the sidewall surface of the stacked structure.

4. The preparation method according to claim 3, characterized in that, The method for nitriding the metal layer and the sidewall surface of the gasket includes at least the following steps: Before forming at least one sub-sidewall on the sidewall surface of the stacked structure, the metal layer and the gasket surface are subjected to the nitriding treatment.

5. The preparation method according to claim 3, characterized in that, The method for nitriding the metal layer and the sidewall surface of the gasket includes at least the following steps: The outermost sub-sidewalls are nitrided.

6. The preparation method according to claim 3, characterized in that, The sub-sidewall includes at least one of a silicon layer and a silicon oxide layer.

7. The preparation method according to claim 1, characterized in that, The first sidewall was prepared using a selective epitaxial growth method.

8. The preparation method according to claim 1, characterized in that, The nitriding treatment includes plasma nitriding treatment, wherein the nitriding depth of the plasma nitriding treatment is 0.5 nm to 2 nm.

9. The preparation method according to claim 8, characterized in that, The operating temperature for the plasma nitriding treatment is 500°C to 600°C.

10. The preparation method according to claim 1, characterized in that, The first sidewall includes a silicon nitride layer.

11. A semiconductor memory structure, characterized in that, include: Substrate; A contact window located on the surface of the substrate, the contact window exposing the interior of the substrate; A stacked structure located within the contact window and protruding from the upper surface of the substrate, the stacked structure including a metal layer and a pad located below the metal layer, wherein the sidewall surfaces of the metal layer and the pad are nitrided. A second sidewall located on the sidewall surface of the stacked structure, the second sidewall comprising at least: The first sub-sidewall is located on the sidewall surface of the stacked structure; Nitride sub-sidewalls are located on the surface of the first sub-sidewalls, and the nitride sub-sidewalls are obtained by nitriding the first sub-sidewalls; A first sidewall located on the surface of the nitride sub-sidewall, and the first sidewall includes at least: The third sub-sidewall is located on the surface of the nitride sub-sidewall; The fourth sub-sidewall is located on the surface of the third sub-sidewall, and the fourth sub-sidewall is obtained by oxidation treatment of the third sub-sidewall.

12. The semiconductor memory structure according to claim 11, characterized in that, The first sub-sidewall and the third sub-sidewall have the same composition.

13. The semiconductor memory structure according to claim 11, characterized in that, The nitride sidewall portion is discontinuous.

14. The semiconductor memory structure according to claim 11, characterized in that, The thickness of the nitride sub-sidewall is one-fifth to one-third of the thickness of the first sub-sidewall.

15. The semiconductor memory structure according to claim 11, characterized in that, The substrate has multiple isolation structures and multiple active regions formed inside it, and each active region is separated by the isolation structures.

16. The semiconductor memory structure according to claim 15, characterized in that, The stacked structure, as well as the first and second sidewalls, are formed above the isolation structure; and / or: The closer the first and second sidewalls are to the edge of the isolation structure, the deeper their bottoms extend into the interior of the isolation structure.

17. The semiconductor memory structure according to claim 11, characterized in that, The first sub-sidewall includes at least one of a silicon layer and a silicon nitride layer, and the third sub-sidewall includes a silicon nitride layer.

18. The semiconductor memory structure according to claim 15, characterized in that, The first sidewall is partially located above the isolation structure and partially located above the active area.

19. The semiconductor memory structure according to claim 15, characterized in that, The second sidewall also includes a second sub-sidewall formed on the sidewall surface of the first sub-sidewall, and the nitrided sub-sidewall is formed on the surface of the second sub-sidewall by nitriding the second sub-sidewall, and the second sub-sidewall is partially located above the isolation structure and partially located above the active region.

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